1 ;; Constraint definitions for IA-32 and x86-64.
2 ;; Copyright (C) 2006-2024 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
24 ;; Integer register constraints.
25 ;; It is not necessary to define 'r' here.
26 (define_register_constraint "R" "LEGACY_GENERAL_REGS"
27 "Legacy register---the eight integer registers available on all
28 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
29 @code{si}, @code{di}, @code{bp}, @code{sp}).")
31 (define_register_constraint "q" "TARGET_64BIT ? GENERAL_REGS : Q_REGS"
32 "Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
33 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.")
35 (define_register_constraint "Q" "Q_REGS"
36 "Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
37 @code{c}, and @code{d}.")
39 (define_register_constraint "l" "INDEX_REGS"
40 "@internal Any register that can be used as the index in a base+index
41 memory access: that is, any general register except the stack pointer.")
43 (define_register_constraint "a" "AREG"
44 "The @code{a} register.")
46 (define_register_constraint "b" "BREG"
47 "The @code{b} register.")
49 (define_register_constraint "c" "CREG"
50 "The @code{c} register.")
52 (define_register_constraint "d" "DREG"
53 "The @code{d} register.")
55 (define_register_constraint "S" "SIREG"
56 "The @code{si} register.")
58 (define_register_constraint "D" "DIREG"
59 "The @code{di} register.")
61 (define_register_constraint "A" "AD_REGS"
62 "The @code{a} and @code{d} registers, as a pair (for instructions
63 that return half the result in one and half in the other).")
65 (define_register_constraint "U" "CLOBBERED_REGS"
66 "The call-clobbered integer registers.")
68 ;; Floating-point register constraints.
69 (define_register_constraint "f"
70 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FLOAT_REGS : NO_REGS"
71 "Any 80387 floating-point (stack) register.")
73 (define_register_constraint "t"
74 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_TOP_REG : NO_REGS"
75 "Top of 80387 floating-point stack (@code{%st(0)}).")
77 (define_register_constraint "u"
78 "TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_SECOND_REG : NO_REGS"
79 "Second from top of 80387 floating-point stack (@code{%st(1)}).")
81 (define_register_constraint "Yk" "TARGET_AVX512F ? MASK_REGS : NO_REGS"
82 "@internal Any mask register that can be used as predicate, i.e. k1-k7.")
84 (define_register_constraint "k" "TARGET_AVX512F ? ALL_MASK_REGS : NO_REGS"
85 "@internal Any mask register.")
87 ;; Vector registers (also used for plain floating point nowadays).
88 (define_register_constraint "y" "TARGET_MMX ? MMX_REGS : NO_REGS"
91 (define_register_constraint "x" "TARGET_SSE ? SSE_REGS : NO_REGS"
94 (define_register_constraint "v" "TARGET_SSE ? ALL_SSE_REGS : NO_REGS"
95 "Any EVEX encodable SSE register (@code{%xmm0-%xmm31}).")
97 ;; We use the Y prefix to denote any number of conditional register sets:
98 ;; z First SSE register.
99 ;; d any EVEX encodable SSE register for AVX512DQ target or
100 ;; any SSE register for SSE4_1 target.
101 ;; p Integer register when TARGET_PARTIAL_REG_STALL is disabled
102 ;; a Integer register when zero extensions with AND are disabled
103 ;; b Any register that can be used as the GOT base when calling
104 ;; ___tls_get_addr: that is, any general register except EAX
105 ;; and ESP, for -fno-plt if linker supports it. Otherwise,
107 ;; f x87 register when 80387 floating point arithmetic is enabled
108 ;; r SSE regs not requiring REX prefix when prefixes avoidance is enabled
109 ;; and all SSE regs otherwise
110 ;; v any EVEX encodable SSE register for AVX512VL target,
111 ;; otherwise any SSE register
112 ;; w any EVEX encodable SSE register for AVX512BW with TARGET_AVX512VL
113 ;; target, otherwise any SSE register.
114 ;; W any EVEX encodable SSE register for AVX512BW target,
115 ;; otherwise any SSE register.
117 (define_register_constraint "Yz" "TARGET_SSE ? SSE_FIRST_REG : NO_REGS"
118 "First SSE register (@code{%xmm0}).")
120 (define_register_constraint "Yd"
121 "TARGET_AVX512DQ ? ALL_SSE_REGS : TARGET_SSE4_1 ? SSE_REGS : NO_REGS"
122 "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target.")
124 (define_register_constraint "Yp"
125 "TARGET_PARTIAL_REG_STALL ? NO_REGS : GENERAL_REGS"
126 "@internal Any integer register when TARGET_PARTIAL_REG_STALL is disabled.")
128 (define_register_constraint "Ya"
129 "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)
130 ? NO_REGS : GENERAL_REGS"
131 "@internal Any integer register when zero extensions with AND are disabled.")
133 (define_register_constraint "Yb"
134 "(!flag_plt && HAVE_AS_IX86_TLS_GET_ADDR_GOT) ? TLS_GOTBASE_REGS : BREG"
135 "@internal Any register that can be used as the GOT base when calling
136 ___tls_get_addr: that is, any general register except @code{a} and
137 @code{sp} registers, for -fno-plt if linker supports it. Otherwise,
140 (define_register_constraint "Yf"
141 "(ix86_fpmath & FPMATH_387) ? FLOAT_REGS : NO_REGS"
142 "@internal Any x87 register when 80387 FP arithmetic is enabled.")
144 (define_register_constraint "Yr"
145 "TARGET_SSE ? (TARGET_AVOID_4BYTE_PREFIXES ? NO_REX_SSE_REGS : ALL_SSE_REGS) : NO_REGS"
146 "@internal Lower SSE register when avoiding REX prefix and all SSE registers otherwise.")
148 (define_register_constraint "Yv"
149 "TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS"
150 "@internal For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}), otherwise any SSE register.")
152 (define_register_constraint "Yw"
153 "TARGET_AVX512BW && TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS"
154 "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW with TARGET_AVX512VL target, otherwise any SSE register.")
156 (define_register_constraint "YW"
157 "TARGET_AVX512BW ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS"
158 "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW target, otherwise any SSE register.")
160 ;; We use the B prefix to denote any number of internal operands:
162 ;; g GOT memory operand.
163 ;; m Vector memory operand
164 ;; c Constant memory operand
165 ;; k TLS address that allows insn using non-integer registers
166 ;; n Memory operand without REX prefix
167 ;; r Broadcast memory operand
168 ;; s Sibcall memory operand, not valid for TARGET_X32
169 ;; w Call memory operand, not valid for TARGET_X32
170 ;; z Constant call address operand.
171 ;; C Integer SSE constant with all bits set operand.
172 ;; F Floating-point SSE constant with all bits set operand.
173 ;; H Integer SSE constant that is 128/256bit all ones
174 ;; and zero-extand to 256/512bit, or 128bit all ones
175 ;; and zero-extend to 512bit.
176 ;; M x86-64 memory operand.
178 (define_constraint "Bf"
179 "@internal Flags register operand."
180 (match_operand 0 "flags_reg_operand"))
182 (define_constraint "Bg"
183 "@internal GOT memory operand."
184 (match_operand 0 "GOT_memory_operand"))
186 (define_special_memory_constraint "Bm"
187 "@internal Vector memory operand."
188 (match_operand 0 "vector_memory_operand"))
190 (define_memory_constraint "Bk"
191 "@internal TLS address that allows insn using non-integer registers."
192 (and (match_operand 0 "memory_operand")
193 (not (match_test "ix86_gpr_tls_address_pattern_p (op)"))))
195 (define_special_memory_constraint "Bn"
196 "@internal Memory operand without REX prefix."
197 (and (match_operand 0 "memory_operand")
198 (not (match_test "x86_extended_reg_mentioned_p (op)"))))
200 (define_special_memory_constraint "Br"
201 "@internal bcst memory operand."
202 (match_operand 0 "bcst_mem_operand"))
204 (define_constraint "Bs"
205 "@internal Sibcall memory operand."
206 (ior (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER"))
207 (not (match_test "TARGET_X32"))
208 (match_operand 0 "sibcall_memory_operand"))
209 (and (match_test "TARGET_X32")
210 (match_test "Pmode == DImode")
211 (match_operand 0 "GOT_memory_operand"))))
213 (define_constraint "Bw"
214 "@internal Call memory operand."
215 (ior (and (not (match_test "TARGET_INDIRECT_BRANCH_REGISTER"))
216 (not (match_test "TARGET_X32"))
217 (match_operand 0 "memory_operand"))
218 (and (match_test "TARGET_X32")
219 (match_test "Pmode == DImode")
220 (match_operand 0 "GOT_memory_operand"))))
222 (define_constraint "Bz"
223 "@internal Constant call address operand."
224 (match_operand 0 "constant_call_address_operand"))
226 (define_constraint "BC"
227 "@internal integer SSE constant with all bits set operand."
228 (and (match_test "TARGET_SSE")
229 (ior (match_test "op == constm1_rtx")
230 (match_operand 0 "vector_all_ones_operand"))))
232 (define_constraint "BF"
233 "@internal floating-point SSE constant with all bits set operand."
234 (and (match_test "TARGET_SSE")
235 (match_operand 0 "float_vector_all_ones_operand")))
237 (define_constraint "BH"
238 "@internal integer constant with last half/quarter bits set operand."
239 (ior (match_operand 0 "vector_all_ones_zero_extend_half_operand")
240 (match_operand 0 "vector_all_ones_zero_extend_quarter_operand")))
242 ;; NB: Similar to 'm', but don't use define_memory_constraint on x86-64
243 ;; to prevent LRA from converting the operand to the form '(mem (reg X))'
244 ;; where X is a base register.
245 (define_constraint "BM"
246 "@internal x86-64 memory operand."
247 (and (match_code "mem")
248 (match_test "memory_address_addr_space_p (GET_MODE (op), XEXP (op, 0),
249 MEM_ADDR_SPACE (op))")))
251 ;; Integer constant constraints.
252 (define_constraint "Wb"
253 "Integer constant in the range 0 @dots{} 7, for 8-bit shifts."
254 (and (match_code "const_int")
255 (match_test "IN_RANGE (ival, 0, 7)")))
257 (define_constraint "Ww"
258 "Integer constant in the range 0 @dots{} 15, for 16-bit shifts."
259 (and (match_code "const_int")
260 (match_test "IN_RANGE (ival, 0, 15)")))
262 (define_constraint "I"
263 "Integer constant in the range 0 @dots{} 31, for 32-bit shifts."
264 (and (match_code "const_int")
265 (match_test "IN_RANGE (ival, 0, 31)")))
267 (define_constraint "J"
268 "Integer constant in the range 0 @dots{} 63, for 64-bit shifts."
269 (and (match_code "const_int")
270 (match_test "IN_RANGE (ival, 0, 63)")))
272 (define_constraint "K"
273 "Signed 8-bit integer constant."
274 (and (match_code "const_int")
275 (match_test "IN_RANGE (ival, -128, 127)")))
277 (define_constraint "L"
278 "@code{0xFF}, @code{0xFFFF} or @code{0xFFFFFFFF}
279 for AND as a zero-extending move."
280 (and (match_code "const_int")
281 (ior (match_test "ival == 0xff")
282 (match_test "ival == 0xffff")
283 (match_test "ival == HOST_WIDE_INT_C (0xffffffff)"))))
285 (define_constraint "M"
286 "0, 1, 2, or 3 (shifts for the @code{lea} instruction)."
287 (and (match_code "const_int")
288 (match_test "IN_RANGE (ival, 0, 3)")))
290 (define_constraint "N"
291 "Unsigned 8-bit integer constant (for @code{in} and @code{out}
293 (and (match_code "const_int")
294 (match_test "IN_RANGE (ival, 0, 255)")))
296 (define_constraint "O"
297 "@internal Integer constant in the range 0 @dots{} 127, for 128-bit shifts."
298 (and (match_code "const_int")
299 (match_test "IN_RANGE (ival, 0, 127)")))
301 ;; Floating-point constant constraints.
302 ;; We allow constants even if TARGET_80387 isn't set, because the
303 ;; stack register converter may need to load 0.0 into the function
304 ;; value register (top of stack).
305 (define_constraint "G"
306 "Standard 80387 floating point constant."
307 (and (match_code "const_double")
308 (match_test "standard_80387_constant_p (op) > 0")))
310 ;; This can theoretically be any mode's CONST0_RTX.
311 (define_constraint "C"
312 "Constant zero operand."
313 (ior (match_test "op == const0_rtx")
314 (match_operand 0 "const0_operand")))
316 ;; Constant-or-symbol-reference constraints.
318 (define_constraint "e"
319 "32-bit signed integer constant, or a symbolic reference known
320 to fit that range (for immediate operands in sign-extending x86-64
322 (match_operand 0 "x86_64_immediate_operand"))
324 ;; We use W prefix to denote any number of
325 ;; constant-or-symbol-reference constraints
327 (define_constraint "We"
328 "32-bit signed integer constant, or a symbolic reference known
329 to fit that range (for sign-extending conversion operations that
330 require non-VOIDmode immediate operands)."
331 (and (match_operand 0 "x86_64_immediate_operand")
332 (match_test "mode != VOIDmode")))
334 (define_constraint "Wz"
335 "32-bit unsigned integer constant, or a symbolic reference known
336 to fit that range (for zero-extending conversion operations that
337 require non-VOIDmode immediate operands)."
338 (and (match_operand 0 "x86_64_zext_immediate_operand")
339 (match_test "mode != VOIDmode")))
341 (define_constraint "Wd"
342 "128-bit integer constant where both the high and low 64-bit word
343 of it satisfies the e constraint."
344 (match_operand 0 "x86_64_hilo_int_operand"))
346 (define_constraint "Wf"
347 "32-bit signed integer constant zero extended from word size
348 to double word size."
349 (match_operand 0 "x86_64_dwzext_immediate_operand"))
351 (define_constraint "Ws"
352 "A symbolic reference or label reference."
353 (match_code "const,symbol_ref,label_ref"))
355 (define_constraint "Z"
356 "32-bit unsigned integer constant, or a symbolic reference known
357 to fit that range (for immediate operands in zero-extending x86-64
359 (match_operand 0 "x86_64_zext_immediate_operand"))
361 ;; T prefix is used for different address constraints
363 ;; s - address with no segment register
364 ;; i - address with no index and no rip
365 ;; b - address with no base and no rip
367 (define_address_constraint "Tv"
368 "VSIB address operand"
369 (match_operand 0 "vsib_address_operand"))
371 (define_address_constraint "Ts"
372 "Address operand without segment register"
373 (match_operand 0 "address_no_seg_operand"))
375 ;; j prefix is used for APX operand constraints.
376 ;; < Auto-dec memory operand without GPR32.
377 ;; > Auto-inc memory operand without GPR32.
378 ;; a Vector memory operand without GPR32.
379 ;; b VSIB address operand without EGPR.
380 ;; c Integer register. GENERAL_GPR16 for TARGET_APX_EGPR and
381 ;; !TARGET_AVX, otherwise GENERAL_REGS.
382 ;; e Memory operand for APX NDD ADD.
383 ;; j Integer register. GENERAL_GPR16 for TARGET_APX_EGPR, otherwise
385 ;; o Offsetable memory operand without GPR32.
386 ;; p General address operand without GPR32.
387 ;; m Memory operand without GPR32.
388 ;; M Memory operand, with APX NDD check.
389 ;; R Integer register. GENERAL_REGS.
390 ;; O Offsettable memory operand, with APX NDD check.
391 ;; V Non-offsetable memory operand without GPR32.
393 ;; Constraint that force to use EGPR, can only adopt to register class.
394 (define_register_constraint "jR" "GENERAL_REGS")
396 (define_register_constraint "jr"
397 "TARGET_APX_EGPR ? GENERAL_GPR16 : GENERAL_REGS")
399 (define_memory_constraint "jm"
400 "@internal memory operand without GPR32."
401 (and (match_operand 0 "memory_operand")
402 (not (and (match_test "TARGET_APX_EGPR")
403 (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
405 (define_constraint "j<"
406 "@internal auto-dec memory operand without GPR32."
407 (and (and (match_code "mem")
408 (ior (match_test "GET_CODE (XEXP (op, 0)) == PRE_DEC")
409 (match_test "GET_CODE (XEXP (op, 0)) == POST_DEC")))
410 (not (and (match_test "TARGET_APX_EGPR")
411 (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
413 (define_constraint "j>"
414 "@internal auto-inc memory operand without GPR32."
415 (and (and (match_code "mem")
416 (ior (match_test "GET_CODE (XEXP (op, 0)) == PRE_INC")
417 (match_test "GET_CODE (XEXP (op, 0)) == POST_INC")))
418 (not (and (match_test "TARGET_APX_EGPR")
419 (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
421 (define_memory_constraint "jo"
422 "@internal offsetable memory operand without GPR32."
423 (and (and (match_code "mem")
424 (match_test "offsettable_nonstrict_memref_p (op)"))
425 (not (and (match_test "TARGET_APX_EGPR")
426 (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
428 (define_constraint "jV"
429 "@internal non-offsetable memory operand without GPR32."
430 (and (and (match_code "mem")
431 (match_test "memory_address_addr_space_p (GET_MODE (op),
433 MEM_ADDR_SPACE (op))")
434 (not (match_test "offsettable_nonstrict_memref_p (op)")))
435 (not (and (match_test "TARGET_APX_EGPR")
436 (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
438 (define_address_constraint "jp"
439 "@internal general address operand without GPR32"
440 (and (match_test "address_operand (op, VOIDmode)")
441 (not (and (match_test "TARGET_APX_EGPR")
442 (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
444 (define_special_memory_constraint "ja"
445 "@internal vector memory operand without GPR32."
446 (and (match_operand 0 "vector_memory_operand")
447 (not (and (match_test "TARGET_APX_EGPR")
448 (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
450 (define_address_constraint "jb"
451 "VSIB address operand without EGPR"
452 (and (match_operand 0 "vsib_address_operand")
453 (not (and (match_test "TARGET_APX_EGPR")
454 (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
456 (define_register_constraint "jc"
457 "TARGET_APX_EGPR && !TARGET_AVX ? GENERAL_GPR16 : GENERAL_REGS")
459 (define_memory_constraint "je"
460 "@internal Memory operand for APX NDD ADD."
461 (match_operand 0 "apx_ndd_add_memory_operand"))
463 (define_memory_constraint "jM"
464 "@internal Memory operand, with APX NDD check."
465 (match_operand 0 "apx_ndd_memory_operand"))
467 (define_memory_constraint "jO"
468 "@internal Offsettable memory operand, with APX NDD check."
469 (and (match_operand 0 "apx_ndd_memory_operand")
470 (match_test "offsettable_nonstrict_memref_p (op)")))