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* c-common.c (catenate_strings): New.
[official-gcc.git] / gcc / config / mips / mips.h
blob974817f8518886dbd9604a2099d77dcdf2817fbd
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
8
9 This file is part of GCC.
10
11 GCC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GCC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GCC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
25
26
27 /* Standard GCC variables that we reference. */
28
29 extern int target_flags;
30
31 /* MIPS external variables defined in mips.c. */
32
33 /* Which processor to schedule for. Since there is no difference between
34 a R2000 and R3000 in terms of the scheduler, we collapse them into
35 just an R3000. The elements of the enumeration must match exactly
36 the cpu attribute in the mips.md machine description. */
37
38 enum processor_type {
39 PROCESSOR_DEFAULT,
40 PROCESSOR_4KC,
41 PROCESSOR_5KC,
42 PROCESSOR_20KC,
43 PROCESSOR_M4K,
44 PROCESSOR_R3000,
45 PROCESSOR_R3900,
46 PROCESSOR_R6000,
47 PROCESSOR_R4000,
48 PROCESSOR_R4100,
49 PROCESSOR_R4111,
50 PROCESSOR_R4120,
51 PROCESSOR_R4130,
52 PROCESSOR_R4300,
53 PROCESSOR_R4600,
54 PROCESSOR_R4650,
55 PROCESSOR_R5000,
56 PROCESSOR_R5400,
57 PROCESSOR_R5500,
58 PROCESSOR_R7000,
59 PROCESSOR_R8000,
60 PROCESSOR_R9000,
61 PROCESSOR_SB1,
62 PROCESSOR_SR71000
63 };
64
65 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
66 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
67 to work on a 64 bit machine. */
68
69 #define ABI_32 0
70 #define ABI_N32 1
71 #define ABI_64 2
72 #define ABI_EABI 3
73 #define ABI_O64 4
74
75 /* Information about one recognized processor. Defined here for the
76 benefit of TARGET_CPU_CPP_BUILTINS. */
77 struct mips_cpu_info {
78 /* The 'canonical' name of the processor as far as GCC is concerned.
79 It's typically a manufacturer's prefix followed by a numerical
80 designation. It should be lower case. */
81 const char *name;
82
83 /* The internal processor number that most closely matches this
84 entry. Several processors can have the same value, if there's no
85 difference between them from GCC's point of view. */
86 enum processor_type cpu;
87
88 /* The ISA level that the processor implements. */
89 int isa;
90 };
91
92 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
93 extern const char *current_function_file; /* filename current function is in */
94 extern int num_source_filenames; /* current .file # */
95 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
96 extern int sym_lineno; /* sgi next label # for each stmt */
97 extern int set_noreorder; /* # of nested .set noreorder's */
98 extern int set_nomacro; /* # of nested .set nomacro's */
99 extern int set_noat; /* # of nested .set noat's */
100 extern int set_volatile; /* # of nested .set volatile's */
101 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
102 extern int mips_dbx_regno[]; /* Map register # to debug register # */
103 extern GTY(()) rtx cmp_operands[2];
104 extern enum processor_type mips_arch; /* which cpu to codegen for */
105 extern enum processor_type mips_tune; /* which cpu to schedule for */
106 extern int mips_isa; /* architectural level */
107 extern int mips_abi; /* which ABI to use */
108 extern int mips16_hard_float; /* mips16 without -msoft-float */
109 extern const char *mips_arch_string; /* for -march=<xxx> */
110 extern const char *mips_tune_string; /* for -mtune=<xxx> */
111 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
112 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
113 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
114 extern const struct mips_cpu_info mips_cpu_info_table[];
115 extern const struct mips_cpu_info *mips_arch_info;
116 extern const struct mips_cpu_info *mips_tune_info;
117
118 /* Macros to silence warnings about numbers being signed in traditional
119 C and unsigned in ISO C when compiled on 32-bit hosts. */
120
121 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
122 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
123 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
124
125 \f
126 /* Run-time compilation parameters selecting different hardware subsets. */
127
128 /* Macros used in the machine description to test the flags. */
129
130 /* Bits for real switches */
131 #define MASK_INT64 0x00000001 /* ints are 64 bits */
132 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
133 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
134 #define MASK_NO_FUSED_MADD 0x00000008 /* Don't generate floating point
135 multiply-add operations. */
136 #define MASK_EXPLICIT_RELOCS 0x00000010 /* Use relocation operators. */
137 #define MASK_MEMCPY 0x00000020 /* call memcpy instead of inline code*/
138 #define MASK_SOFT_FLOAT 0x00000040 /* software floating point */
139 #define MASK_FLOAT64 0x00000080 /* fp registers are 64 bits */
140 #define MASK_ABICALLS 0x00000100 /* emit .abicalls/.cprestore/.cpload */
141 #define MASK_XGOT 0x00000200 /* emit big-got PIC */
142 #define MASK_LONG_CALLS 0x00000400 /* Always call through a register */
143 #define MASK_64BIT 0x00000800 /* Use 64 bit GP registers and insns */
144 #define MASK_EMBEDDED_DATA 0x00001000 /* Reduce RAM usage, not fast code */
145 #define MASK_BIG_ENDIAN 0x00002000 /* Generate big endian code */
146 #define MASK_SINGLE_FLOAT 0x00004000 /* Only single precision FPU. */
147 #define MASK_MAD 0x00008000 /* Generate mad/madu as on 4650. */
148 #define MASK_4300_MUL_FIX 0x00010000 /* Work-around early Vr4300 CPU bug */
149 #define MASK_MIPS16 0x00020000 /* Generate mips16 code */
150 #define MASK_NO_CHECK_ZERO_DIV \
151 0x00040000 /* divide by zero checking */
152 #define MASK_BRANCHLIKELY 0x00080000 /* Generate Branch Likely
153 instructions. */
154 #define MASK_UNINIT_CONST_IN_RODATA \
155 0x00100000 /* Store uninitialized
156 consts in rodata */
157 #define MASK_FIX_R4000 0x00200000 /* Work around R4000 errata. */
158 #define MASK_FIX_R4400 0x00400000 /* Work around R4400 errata. */
159 #define MASK_FIX_SB1 0x00800000 /* Work around SB-1 errata. */
160 #define MASK_FIX_VR4120 0x01000000 /* Work around VR4120 errata. */
161 #define MASK_VR4130_ALIGN 0x02000000 /* Perform VR4130 alignment opts. */
162 #define MASK_FP_EXCEPTIONS 0x04000000 /* FP exceptions are enabled. */
163 #define MASK_DIVIDE_BREAKS 0x08000000 /* Divide by zero check uses
164 break instead of trap. */
165 #define MASK_PAIRED_SINGLE 0x10000000 /* Support paired-single FPU. */
166 #define MASK_MIPS3D 0x20000000 /* Support MIPS-3D instructions. */
167
168 /* Debug switches, not documented */
169 #define MASK_DEBUG 0 /* unused */
170 #define MASK_DEBUG_D 0 /* don't do define_split's */
171
172 /* Dummy switches used only in specs */
173 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
174
175 /* r4000 64 bit sizes */
176 #define TARGET_INT64 ((target_flags & MASK_INT64) != 0)
177 #define TARGET_LONG64 ((target_flags & MASK_LONG64) != 0)
178 #define TARGET_FLOAT64 ((target_flags & MASK_FLOAT64) != 0)
179 #define TARGET_64BIT ((target_flags & MASK_64BIT) != 0)
180
181 /* Mips vs. GNU linker */
182 #define TARGET_SPLIT_ADDRESSES ((target_flags & MASK_SPLIT_ADDR) != 0)
183
184 /* Debug Modes */
185 #define TARGET_DEBUG_MODE ((target_flags & MASK_DEBUG) != 0)
186 #define TARGET_DEBUG_D_MODE ((target_flags & MASK_DEBUG_D) != 0)
187
188 /* call memcpy instead of inline code */
189 #define TARGET_MEMCPY ((target_flags & MASK_MEMCPY) != 0)
190
191 /* .abicalls, etc from Pyramid V.4 */
192 #define TARGET_ABICALLS ((target_flags & MASK_ABICALLS) != 0)
193 #define TARGET_XGOT ((target_flags & MASK_XGOT) != 0)
194
195 /* software floating point */
196 #define TARGET_SOFT_FLOAT ((target_flags & MASK_SOFT_FLOAT) != 0)
197 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
198
199 /* always call through a register */
200 #define TARGET_LONG_CALLS ((target_flags & MASK_LONG_CALLS) != 0)
201
202 /* for embedded systems, optimize for
203 reduced RAM space instead of for
204 fastest code. */
205 #define TARGET_EMBEDDED_DATA ((target_flags & MASK_EMBEDDED_DATA) != 0)
206
207 /* always store uninitialized const
208 variables in rodata, requires
209 TARGET_EMBEDDED_DATA. */
210 #define TARGET_UNINIT_CONST_IN_RODATA \
211 ((target_flags & MASK_UNINIT_CONST_IN_RODATA) != 0)
212
213 /* generate big endian code. */
214 #define TARGET_BIG_ENDIAN ((target_flags & MASK_BIG_ENDIAN) != 0)
215
216 #define TARGET_SINGLE_FLOAT ((target_flags & MASK_SINGLE_FLOAT) != 0)
217 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
218
219 #define TARGET_MAD ((target_flags & MASK_MAD) != 0)
220
221 #define TARGET_FUSED_MADD ((target_flags & MASK_NO_FUSED_MADD) == 0)
222
223 #define TARGET_4300_MUL_FIX ((target_flags & MASK_4300_MUL_FIX) != 0)
224
225 #define TARGET_CHECK_ZERO_DIV ((target_flags & MASK_NO_CHECK_ZERO_DIV) == 0)
226 #define TARGET_DIVIDE_TRAPS ((target_flags & MASK_DIVIDE_BREAKS) == 0)
227
228 #define TARGET_BRANCHLIKELY ((target_flags & MASK_BRANCHLIKELY) != 0)
229
230 #define TARGET_FIX_SB1 ((target_flags & MASK_FIX_SB1) != 0)
231
232 /* Work around R4000 errata. */
233 #define TARGET_FIX_R4000 ((target_flags & MASK_FIX_R4000) != 0)
234
235 /* Work around R4400 errata. */
236 #define TARGET_FIX_R4400 ((target_flags & MASK_FIX_R4400) != 0)
237 #define TARGET_FIX_VR4120 ((target_flags & MASK_FIX_VR4120) != 0)
238 #define TARGET_VR4130_ALIGN ((target_flags & MASK_VR4130_ALIGN) != 0)
239
240 #define TARGET_FP_EXCEPTIONS ((target_flags & MASK_FP_EXCEPTIONS) != 0)
241
242 #define TARGET_PAIRED_SINGLE_FLOAT \
243 ((target_flags & MASK_PAIRED_SINGLE) != 0)
244 #define TARGET_MIPS3D ((target_flags & MASK_MIPS3D) != 0)
245
246 /* True if we should use NewABI-style relocation operators for
247 symbolic addresses. This is never true for mips16 code,
248 which has its own conventions. */
249
250 #define TARGET_EXPLICIT_RELOCS ((target_flags & MASK_EXPLICIT_RELOCS) != 0)
251
252
253 /* True if the call patterns should be split into a jalr followed by
254 an instruction to restore $gp. This is only ever true for SVR4 PIC,
255 in which $gp is call-clobbered. It is only safe to split the load
256 from the call when every use of $gp is explicit. */
257
258 #define TARGET_SPLIT_CALLS \
259 (TARGET_EXPLICIT_RELOCS && TARGET_ABICALLS && !TARGET_NEWABI)
260
261 /* True if we can optimize sibling calls. For simplicity, we only
262 handle cases in which call_insn_operand will reject invalid
263 sibcall addresses. There are two cases in which this isn't true:
264
265 - TARGET_MIPS16. call_insn_operand accepts constant addresses
266 but there is no direct jump instruction. It isn't worth
267 using sibling calls in this case anyway; they would usually
268 be longer than normal calls.
269
270 - TARGET_ABICALLS && !TARGET_EXPLICIT_RELOCS. call_insn_operand
271 accepts global constants, but "jr $25" is the only allowed
272 sibcall. */
273
274 #define TARGET_SIBCALLS \
275 (!TARGET_MIPS16 && (!TARGET_ABICALLS || TARGET_EXPLICIT_RELOCS))
276
277 /* True if .gpword or .gpdword should be used for switch tables.
278
279 Although GAS does understand .gpdword, the SGI linker mishandles
280 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
281 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
282 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
283
284 /* Generate mips16 code */
285 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
286
287 /* Generic ISA defines. */
288 #define ISA_MIPS1 (mips_isa == 1)
289 #define ISA_MIPS2 (mips_isa == 2)
290 #define ISA_MIPS3 (mips_isa == 3)
291 #define ISA_MIPS4 (mips_isa == 4)
292 #define ISA_MIPS32 (mips_isa == 32)
293 #define ISA_MIPS32R2 (mips_isa == 33)
294 #define ISA_MIPS64 (mips_isa == 64)
295
296 /* Architecture target defines. */
297 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
298 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
299 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
300 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
301 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
302 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
303 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
304 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
305 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
306 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
307
308 /* Scheduling target defines. */
309 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
310 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
311 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
312 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
313 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
314 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
315 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
316 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
317 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
318 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
319 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
320 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
321
322 /* True if the pre-reload scheduler should try to create chains of
323 multiply-add or multiply-subtract instructions. For example,
324 suppose we have:
325
326 t1 = a * b
327 t2 = t1 + c * d
328 t3 = e * f
329 t4 = t3 - g * h
330
331 t1 will have a higher priority than t2 and t3 will have a higher
332 priority than t4. However, before reload, there is no dependence
333 between t1 and t3, and they can often have similar priorities.
334 The scheduler will then tend to prefer:
335
336 t1 = a * b
337 t3 = e * f
338 t2 = t1 + c * d
339 t4 = t3 - g * h
340
341 which stops us from making full use of macc/madd-style instructions.
342 This sort of situation occurs frequently in Fourier transforms and
343 in unrolled loops.
344
345 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
346 queue so that chained multiply-add and multiply-subtract instructions
347 appear ahead of any other instruction that is likely to clobber lo.
348 In the example above, if t2 and t3 become ready at the same time,
349 the code ensures that t2 is scheduled first.
350
351 Multiply-accumulate instructions are a bigger win for some targets
352 than others, so this macro is defined on an opt-in basis. */
353 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
354 || TUNE_MIPS4120 \
355 || TUNE_MIPS4130)
356
357 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
358 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
359
360 /* IRIX specific stuff. */
361 #define TARGET_IRIX 0
362 #define TARGET_IRIX6 0
363
364 /* Define preprocessor macros for the -march and -mtune options.
365 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
366 processor. If INFO's canonical name is "foo", define PREFIX to
367 be "foo", and define an additional macro PREFIX_FOO. */
368 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
369 do \
370 { \
371 char *macro, *p; \
372 \
373 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
374 for (p = macro; *p != 0; p++) \
375 *p = TOUPPER (*p); \
376 \
377 builtin_define (macro); \
378 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
379 free (macro); \
380 } \
381 while (0)
382
383 /* Target CPU builtins. */
384 #define TARGET_CPU_CPP_BUILTINS() \
385 do \
386 { \
387 builtin_assert ("cpu=mips"); \
388 builtin_define ("__mips__"); \
389 builtin_define ("_mips"); \
390 \
391 /* We do this here because __mips is defined below \
392 and so we can't use builtin_define_std. */ \
393 if (!flag_iso) \
394 builtin_define ("mips"); \
395 \
396 /* Treat _R3000 and _R4000 like register-size defines, \
397 which is how they've historically been used. */ \
398 if (TARGET_64BIT) \
399 { \
400 builtin_define ("__mips64"); \
401 builtin_define_std ("R4000"); \
402 builtin_define ("_R4000"); \
403 } \
404 else \
405 { \
406 builtin_define_std ("R3000"); \
407 builtin_define ("_R3000"); \
408 } \
409 if (TARGET_FLOAT64) \
410 builtin_define ("__mips_fpr=64"); \
411 else \
412 builtin_define ("__mips_fpr=32"); \
413 \
414 if (TARGET_MIPS16) \
415 builtin_define ("__mips16"); \
416 \
417 if (TARGET_MIPS3D) \
418 builtin_define ("__mips3d"); \
419 \
420 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
421 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
422 \
423 if (ISA_MIPS1) \
424 { \
425 builtin_define ("__mips=1"); \
426 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
427 } \
428 else if (ISA_MIPS2) \
429 { \
430 builtin_define ("__mips=2"); \
431 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
432 } \
433 else if (ISA_MIPS3) \
434 { \
435 builtin_define ("__mips=3"); \
436 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
437 } \
438 else if (ISA_MIPS4) \
439 { \
440 builtin_define ("__mips=4"); \
441 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
442 } \
443 else if (ISA_MIPS32) \
444 { \
445 builtin_define ("__mips=32"); \
446 builtin_define ("__mips_isa_rev=1"); \
447 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
448 } \
449 else if (ISA_MIPS32R2) \
450 { \
451 builtin_define ("__mips=32"); \
452 builtin_define ("__mips_isa_rev=2"); \
453 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
454 } \
455 else if (ISA_MIPS64) \
456 { \
457 builtin_define ("__mips=64"); \
458 builtin_define ("__mips_isa_rev=1"); \
459 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
460 } \
461 \
462 if (TARGET_HARD_FLOAT) \
463 builtin_define ("__mips_hard_float"); \
464 else if (TARGET_SOFT_FLOAT) \
465 builtin_define ("__mips_soft_float"); \
466 \
467 if (TARGET_SINGLE_FLOAT) \
468 builtin_define ("__mips_single_float"); \
469 \
470 if (TARGET_PAIRED_SINGLE_FLOAT) \
471 builtin_define ("__mips_paired_single_float"); \
472 \
473 if (TARGET_BIG_ENDIAN) \
474 { \
475 builtin_define_std ("MIPSEB"); \
476 builtin_define ("_MIPSEB"); \
477 } \
478 else \
479 { \
480 builtin_define_std ("MIPSEL"); \
481 builtin_define ("_MIPSEL"); \
482 } \
483 \
484 /* Macros dependent on the C dialect. */ \
485 if (preprocessing_asm_p ()) \
486 { \
487 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
488 builtin_define ("_LANGUAGE_ASSEMBLY"); \
489 } \
490 else if (c_dialect_cxx ()) \
491 { \
492 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
493 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
494 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
495 } \
496 else \
497 { \
498 builtin_define_std ("LANGUAGE_C"); \
499 builtin_define ("_LANGUAGE_C"); \
500 } \
501 if (c_dialect_objc ()) \
502 { \
503 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
504 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
505 /* Bizarre, but needed at least for Irix. */ \
506 builtin_define_std ("LANGUAGE_C"); \
507 builtin_define ("_LANGUAGE_C"); \
508 } \
509 \
510 if (mips_abi == ABI_EABI) \
511 builtin_define ("__mips_eabi"); \
512 \
513 } while (0)
514
515
516
517 /* Macro to define tables used to set the flags.
518 This is a list in braces of pairs in braces,
519 each pair being { "NAME", VALUE }
520 where VALUE is the bits to set or minus the bits to clear.
521 An empty string NAME is used to identify the default VALUE. */
522
523 #define TARGET_SWITCHES \
524 { \
525 SUBTARGET_TARGET_SWITCHES \
526 {"int64", MASK_INT64 | MASK_LONG64, \
527 N_("Use 64-bit int type")}, \
528 {"long64", MASK_LONG64, \
529 N_("Use 64-bit long type")}, \
530 {"long32", -(MASK_LONG64 | MASK_INT64), \
531 N_("Use 32-bit long type")}, \
532 {"split-addresses", MASK_SPLIT_ADDR, \
533 N_("Optimize lui/addiu address loads")}, \
534 {"no-split-addresses", -MASK_SPLIT_ADDR, \
535 N_("Don't optimize lui/addiu address loads")}, \
536 {"gas", 0, \
537 N_("Use GNU as (now ignored)")}, \
538 {"gpOPT", 0, \
539 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
540 {"gpopt", 0, \
541 N_("Use GP relative sdata/sbss sections (now ignored)")}, \
542 {"no-gpOPT", 0, \
543 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
544 {"no-gpopt", 0, \
545 N_("Don't use GP relative sdata/sbss sections (now ignored)")}, \
546 {"stats", 0, \
547 N_("Output compiler statistics (now ignored)")}, \
548 {"no-stats", 0, \
549 N_("Don't output compiler statistics")}, \
550 {"memcpy", MASK_MEMCPY, \
551 N_("Don't optimize block moves")}, \
552 {"no-memcpy", -MASK_MEMCPY, \
553 N_("Optimize block moves")}, \
554 {"mips-tfile", MASK_MIPS_TFILE, \
555 N_("Use mips-tfile asm postpass")}, \
556 {"no-mips-tfile", -MASK_MIPS_TFILE, \
557 N_("Don't use mips-tfile asm postpass")}, \
558 {"soft-float", MASK_SOFT_FLOAT, \
559 N_("Use software floating point")}, \
560 {"hard-float", -MASK_SOFT_FLOAT, \
561 N_("Use hardware floating point")}, \
562 {"fp64", MASK_FLOAT64, \
563 N_("Use 64-bit FP registers")}, \
564 {"fp32", -MASK_FLOAT64, \
565 N_("Use 32-bit FP registers")}, \
566 {"gp64", MASK_64BIT, \
567 N_("Use 64-bit general registers")}, \
568 {"gp32", -MASK_64BIT, \
569 N_("Use 32-bit general registers")}, \
570 {"abicalls", MASK_ABICALLS, \
571 N_("Use Irix PIC")}, \
572 {"no-abicalls", -MASK_ABICALLS, \
573 N_("Don't use Irix PIC")}, \
574 {"long-calls", MASK_LONG_CALLS, \
575 N_("Use indirect calls")}, \
576 {"no-long-calls", -MASK_LONG_CALLS, \
577 N_("Don't use indirect calls")}, \
578 {"embedded-data", MASK_EMBEDDED_DATA, \
579 N_("Use ROM instead of RAM")}, \
580 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
581 N_("Don't use ROM instead of RAM")}, \
582 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
583 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
584 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
585 N_("Don't put uninitialized constants in ROM")}, \
586 {"eb", MASK_BIG_ENDIAN, \
587 N_("Use big-endian byte order")}, \
588 {"el", -MASK_BIG_ENDIAN, \
589 N_("Use little-endian byte order")}, \
590 {"single-float", MASK_SINGLE_FLOAT, \
591 N_("Use single (32-bit) FP only")}, \
592 {"double-float", -MASK_SINGLE_FLOAT, \
593 N_("Don't use single (32-bit) FP only")}, \
594 {"paired-single", MASK_PAIRED_SINGLE, \
595 N_("Use paired-single floating point instructions")}, \
596 {"no-paired-single", -MASK_PAIRED_SINGLE, \
597 N_("Use paired-single floating point instructions")}, \
598 {"ips3d", MASK_MIPS3D, \
599 N_("Use MIPS-3D instructions")}, \
600 {"no-mips3d", -MASK_MIPS3D, \
601 N_("Use MIPS-3D instructions")}, \
602 {"mad", MASK_MAD, \
603 N_("Use multiply accumulate")}, \
604 {"no-mad", -MASK_MAD, \
605 N_("Don't use multiply accumulate")}, \
606 {"no-fused-madd", MASK_NO_FUSED_MADD, \
607 N_("Don't generate fused multiply/add instructions")}, \
608 {"fused-madd", -MASK_NO_FUSED_MADD, \
609 N_("Generate fused multiply/add instructions")}, \
610 {"vr4130-align", MASK_VR4130_ALIGN, \
611 N_("Perform VR4130-specific alignment optimizations")}, \
612 {"no-vr4130-align", -MASK_VR4130_ALIGN, \
613 N_("Don't perform VR4130-specific alignment optimizations")}, \
614 {"fix4300", MASK_4300_MUL_FIX, \
615 N_("Work around early 4300 hardware bug")}, \
616 {"no-fix4300", -MASK_4300_MUL_FIX, \
617 N_("Don't work around early 4300 hardware bug")}, \
618 {"fix-sb1", MASK_FIX_SB1, \
619 N_("Work around errata for early SB-1 revision 2 cores")}, \
620 {"no-fix-sb1", -MASK_FIX_SB1, \
621 N_("Don't work around errata for early SB-1 revision 2 cores")}, \
622 {"fix-r4000", MASK_FIX_R4000, \
623 N_("Work around R4000 errata")}, \
624 {"no-fix-r4000", -MASK_FIX_R4000, \
625 N_("Don't work around R4000 errata")}, \
626 {"fix-r4400", MASK_FIX_R4400, \
627 N_("Work around R4400 errata")}, \
628 {"no-fix-r4400", -MASK_FIX_R4400, \
629 N_("Don't work around R4400 errata")}, \
630 {"fix-vr4120", MASK_FIX_VR4120, \
631 N_("Work around certain VR4120 errata")}, \
632 {"no-fix-vr4120", -MASK_FIX_VR4120, \
633 N_("Don't work around certain VR4120 errata")}, \
634 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
635 N_("Trap on integer divide by zero")}, \
636 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
637 N_("Don't trap on integer divide by zero")}, \
638 {"divide-traps", -MASK_DIVIDE_BREAKS, \
639 N_("Use trap to check for integer divide by zero")}, \
640 {"divide-breaks", MASK_DIVIDE_BREAKS, \
641 N_("Use break to check for integer divide by zero")}, \
642 { "branch-likely", MASK_BRANCHLIKELY, \
643 N_("Use Branch Likely instructions, overriding default for arch")}, \
644 { "no-branch-likely", -MASK_BRANCHLIKELY, \
645 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
646 {"explicit-relocs", MASK_EXPLICIT_RELOCS, \
647 N_("Use NewABI-style %reloc() assembly operators")}, \
648 {"no-explicit-relocs", -MASK_EXPLICIT_RELOCS, \
649 N_("Use assembler macros instead of relocation operators")}, \
650 {"ips16", MASK_MIPS16, \
651 N_("Generate mips16 code") }, \
652 {"no-mips16", -MASK_MIPS16, \
653 N_("Generate normal-mode code") }, \
654 {"xgot", MASK_XGOT, \
655 N_("Lift restrictions on GOT size") }, \
656 {"no-xgot", -MASK_XGOT, \
657 N_("Do not lift restrictions on GOT size") }, \
658 {"fp-exceptions", MASK_FP_EXCEPTIONS, \
659 N_("FP exceptions are enabled") }, \
660 {"no-fp-exceptions", -MASK_FP_EXCEPTIONS, \
661 N_("FP exceptions are not enabled") }, \
662 {"debug", MASK_DEBUG, \
663 NULL}, \
664 {"debugd", MASK_DEBUG_D, \
665 NULL}, \
666 {"", (TARGET_DEFAULT \
667 | TARGET_CPU_DEFAULT \
668 | TARGET_ENDIAN_DEFAULT \
669 | TARGET_FP_EXCEPTIONS_DEFAULT), \
670 NULL}, \
671 }
672
673 /* Default target_flags if no switches are specified */
674
675 #ifndef TARGET_DEFAULT
676 #define TARGET_DEFAULT 0
677 #endif
678
679 #ifndef TARGET_CPU_DEFAULT
680 #define TARGET_CPU_DEFAULT 0
681 #endif
682
683 #ifndef TARGET_ENDIAN_DEFAULT
684 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
685 #endif
686
687 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
688 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
689 #endif
690
691 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
692 #ifndef MIPS_ISA_DEFAULT
693 #ifndef MIPS_CPU_STRING_DEFAULT
694 #define MIPS_CPU_STRING_DEFAULT "from-abi"
695 #endif
696 #endif
697
698 #ifdef IN_LIBGCC2
699 #undef TARGET_64BIT
700 /* Make this compile time constant for libgcc2 */
701 #ifdef __mips64
702 #define TARGET_64BIT 1
703 #else
704 #define TARGET_64BIT 0
705 #endif
706 #endif /* IN_LIBGCC2 */
707
708 #ifndef MULTILIB_ENDIAN_DEFAULT
709 #if TARGET_ENDIAN_DEFAULT == 0
710 #define MULTILIB_ENDIAN_DEFAULT "EL"
711 #else
712 #define MULTILIB_ENDIAN_DEFAULT "EB"
713 #endif
714 #endif
715
716 #ifndef MULTILIB_ISA_DEFAULT
717 # if MIPS_ISA_DEFAULT == 1
718 # define MULTILIB_ISA_DEFAULT "mips1"
719 # else
720 # if MIPS_ISA_DEFAULT == 2
721 # define MULTILIB_ISA_DEFAULT "mips2"
722 # else
723 # if MIPS_ISA_DEFAULT == 3
724 # define MULTILIB_ISA_DEFAULT "mips3"
725 # else
726 # if MIPS_ISA_DEFAULT == 4
727 # define MULTILIB_ISA_DEFAULT "mips4"
728 # else
729 # if MIPS_ISA_DEFAULT == 32
730 # define MULTILIB_ISA_DEFAULT "mips32"
731 # else
732 # if MIPS_ISA_DEFAULT == 33
733 # define MULTILIB_ISA_DEFAULT "mips32r2"
734 # else
735 # if MIPS_ISA_DEFAULT == 64
736 # define MULTILIB_ISA_DEFAULT "mips64"
737 # else
738 # define MULTILIB_ISA_DEFAULT "mips1"
739 # endif
740 # endif
741 # endif
742 # endif
743 # endif
744 # endif
745 # endif
746 #endif
747
748 #ifndef MULTILIB_DEFAULTS
749 #define MULTILIB_DEFAULTS \
750 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
751 #endif
752
753 /* We must pass -EL to the linker by default for little endian embedded
754 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
755 linker will default to using big-endian output files. The OUTPUT_FORMAT
756 line must be in the linker script, otherwise -EB/-EL will not work. */
757
758 #ifndef ENDIAN_SPEC
759 #if TARGET_ENDIAN_DEFAULT == 0
760 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
761 #else
762 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
763 #endif
764 #endif
765
766 #define TARGET_OPTIONS \
767 { \
768 SUBTARGET_TARGET_OPTIONS \
769 { "tune=", &mips_tune_string, \
770 N_("Specify CPU for scheduling purposes"), 0}, \
771 { "arch=", &mips_arch_string, \
772 N_("Specify CPU for code generation purposes"), 0}, \
773 { "abi=", &mips_abi_string, \
774 N_("Specify an ABI"), 0}, \
775 { "ips", &mips_isa_string, \
776 N_("Specify a Standard MIPS ISA"), 0}, \
777 { "no-flush-func", &mips_cache_flush_func, \
778 N_("Don't call any cache flush functions"), 0}, \
779 { "flush-func=", &mips_cache_flush_func, \
780 N_("Specify cache flush function"), 0}, \
781 }
782
783 /* This is meant to be redefined in the host dependent files. */
784 #define SUBTARGET_TARGET_OPTIONS
785
786 /* Support for a compile-time default CPU, et cetera. The rules are:
787 --with-arch is ignored if -march is specified or a -mips is specified
788 (other than -mips16).
789 --with-tune is ignored if -mtune is specified.
790 --with-abi is ignored if -mabi is specified.
791 --with-float is ignored if -mhard-float or -msoft-float are
792 specified.
793 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
794 specified. */
795 #define OPTION_DEFAULT_SPECS \
796 {"arch", "%{!march=*:%{mips16:-march=%(VALUE)}%{!mips*:-march=%(VALUE)}}" }, \
797 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
798 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
799 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
800 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }
801
802
803 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
804 && ISA_HAS_COND_TRAP)
805
806 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
807 && !TARGET_SR71K \
808 && !TARGET_MIPS16)
809
810 /* Generate three-operand multiply instructions for SImode. */
811 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
812 || TARGET_MIPS5400 \
813 || TARGET_MIPS5500 \
814 || TARGET_MIPS7000 \
815 || TARGET_MIPS9000 \
816 || TARGET_MAD \
817 || ISA_MIPS32 \
818 || ISA_MIPS32R2 \
819 || ISA_MIPS64) \
820 && !TARGET_MIPS16)
821
822 /* Generate three-operand multiply instructions for DImode. */
823 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
824 && !TARGET_MIPS16)
825
826 /* True if the ABI can only work with 64-bit integer registers. We
827 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
828 otherwise floating-point registers must also be 64-bit. */
829 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
830
831 /* Likewise for 32-bit regs. */
832 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
833
834 /* True if symbols are 64 bits wide. At present, n64 is the only
835 ABI for which this is true. */
836 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64)
837
838 /* ISA has instructions for managing 64 bit fp and gp regs (e.g. mips3). */
839 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
840 || ISA_MIPS4 \
841 || ISA_MIPS64)
842
843 /* ISA has branch likely instructions (e.g. mips2). */
844 /* Disable branchlikely for tx39 until compare rewrite. They haven't
845 been generated up to this point. */
846 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
847
848 /* ISA has the conditional move instructions introduced in mips4. */
849 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
850 || ISA_MIPS32 \
851 || ISA_MIPS32R2 \
852 || ISA_MIPS64) \
853 && !TARGET_MIPS5500 \
854 && !TARGET_MIPS16)
855
856 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
857 branch on CC, and move (both FP and non-FP) on CC. */
858 #define ISA_HAS_8CC (ISA_MIPS4 \
859 || ISA_MIPS32 \
860 || ISA_MIPS32R2 \
861 || ISA_MIPS64)
862
863 /* This is a catch all for other mips4 instructions: indexed load, the
864 FP madd and msub instructions, and the FP recip and recip sqrt
865 instructions. */
866 #define ISA_HAS_FP4 ((ISA_MIPS4 \
867 || ISA_MIPS64) \
868 && !TARGET_MIPS16)
869
870 /* ISA has conditional trap instructions. */
871 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
872 && !TARGET_MIPS16)
873
874 /* ISA has integer multiply-accumulate instructions, madd and msub. */
875 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
876 || ISA_MIPS32R2 \
877 || ISA_MIPS64 \
878 ) && !TARGET_MIPS16)
879
880 /* ISA has floating-point nmadd and nmsub instructions. */
881 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
882 || ISA_MIPS64) \
883 && (!TARGET_MIPS5400 || TARGET_MAD) \
884 && ! TARGET_MIPS16)
885
886 /* ISA has count leading zeroes/ones instruction (not implemented). */
887 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
888 || ISA_MIPS32R2 \
889 || ISA_MIPS64 \
890 ) && !TARGET_MIPS16)
891
892 /* ISA has double-word count leading zeroes/ones instruction (not
893 implemented). */
894 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
895 && !TARGET_MIPS16)
896
897 /* ISA has three operand multiply instructions that put
898 the high part in an accumulator: mulhi or mulhiu. */
899 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
900 || TARGET_MIPS5500 \
901 || TARGET_SR71K \
902 )
903
904 /* ISA has three operand multiply instructions that
905 negates the result and puts the result in an accumulator. */
906 #define ISA_HAS_MULS (TARGET_MIPS5400 \
907 || TARGET_MIPS5500 \
908 || TARGET_SR71K \
909 )
910
911 /* ISA has three operand multiply instructions that subtracts the
912 result from a 4th operand and puts the result in an accumulator. */
913 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
914 || TARGET_MIPS5500 \
915 || TARGET_SR71K \
916 )
917 /* ISA has three operand multiply instructions that the result
918 from a 4th operand and puts the result in an accumulator. */
919 #define ISA_HAS_MACC ((TARGET_MIPS4120 && !TARGET_MIPS16) \
920 || (TARGET_MIPS4130 && !TARGET_MIPS16) \
921 || TARGET_MIPS5400 \
922 || TARGET_MIPS5500 \
923 || TARGET_SR71K \
924 )
925
926 /* ISA has 32-bit rotate right instruction. */
927 #define ISA_HAS_ROTR_SI (!TARGET_MIPS16 \
928 && (ISA_MIPS32R2 \
929 || TARGET_MIPS5400 \
930 || TARGET_MIPS5500 \
931 || TARGET_SR71K \
932 ))
933
934 /* ISA has 64-bit rotate right instruction. */
935 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
936 && !TARGET_MIPS16 \
937 && (TARGET_MIPS5400 \
938 || TARGET_MIPS5500 \
939 || TARGET_SR71K \
940 ))
941
942 /* ISA has data prefetch instructions. This controls use of 'pref'. */
943 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
944 || ISA_MIPS32 \
945 || ISA_MIPS32R2 \
946 || ISA_MIPS64) \
947 && !TARGET_MIPS16)
948
949 /* ISA has data indexed prefetch instructions. This controls use of
950 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
951 (prefx is a cop1x instruction, so can only be used if FP is
952 enabled.) */
953 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
954 || ISA_MIPS64) \
955 && !TARGET_MIPS16)
956
957 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
958 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
959 also requires TARGET_DOUBLE_FLOAT. */
960 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
961
962 /* ISA includes the MIPS32r2 seb and seh instructions. */
963 #define ISA_HAS_SEB_SEH (!TARGET_MIPS16 \
964 && (ISA_MIPS32R2 \
965 ))
966
967 /* True if the result of a load is not available to the next instruction.
968 A nop will then be needed between instructions like "lw $4,..."
969 and "addiu $4,$4,1". */
970 #define ISA_HAS_LOAD_DELAY (mips_isa == 1 \
971 && !TARGET_MIPS3900 \
972 && !TARGET_MIPS16)
973
974 /* Likewise mtc1 and mfc1. */
975 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
976
977 /* Likewise floating-point comparisons. */
978 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
979
980 /* True if mflo and mfhi can be immediately followed by instructions
981 which write to the HI and LO registers.
982
983 According to MIPS specifications, MIPS ISAs I, II, and III need
984 (at least) two instructions between the reads of HI/LO and
985 instructions which write them, and later ISAs do not. Contradicting
986 the MIPS specifications, some MIPS IV processor user manuals (e.g.
987 the UM for the NEC Vr5000) document needing the instructions between
988 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
989 MIPS64 and later ISAs to have the interlocks, plus any specific
990 earlier-ISA CPUs for which CPU documentation declares that the
991 instructions are really interlocked. */
992 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
993 || ISA_MIPS32R2 \
994 || ISA_MIPS64 \
995 || TARGET_MIPS5500)
996 \f
997 /* Add -G xx support. */
998
999 #undef SWITCH_TAKES_ARG
1000 #define SWITCH_TAKES_ARG(CHAR) \
1001 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
1002
1003 #define OVERRIDE_OPTIONS override_options ()
1004
1005 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
1006
1007 /* Show we can debug even without a frame pointer. */
1008 #define CAN_DEBUG_WITHOUT_FP
1009 \f
1010 /* Tell collect what flags to pass to nm. */
1011 #ifndef NM_FLAGS
1012 #define NM_FLAGS "-Bn"
1013 #endif
1014
1015 \f
1016 #define SUBTARGET_TARGET_SWITCHES
1017
1018 #ifndef MIPS_ABI_DEFAULT
1019 #define MIPS_ABI_DEFAULT ABI_32
1020 #endif
1021
1022 /* Use the most portable ABI flag for the ASM specs. */
1023
1024 #if MIPS_ABI_DEFAULT == ABI_32
1025 #define MULTILIB_ABI_DEFAULT "mabi=32"
1026 #endif
1027
1028 #if MIPS_ABI_DEFAULT == ABI_O64
1029 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1030 #endif
1031
1032 #if MIPS_ABI_DEFAULT == ABI_N32
1033 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1034 #endif
1035
1036 #if MIPS_ABI_DEFAULT == ABI_64
1037 #define MULTILIB_ABI_DEFAULT "mabi=64"
1038 #endif
1039
1040 #if MIPS_ABI_DEFAULT == ABI_EABI
1041 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1042 #endif
1043
1044 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1045 to the assembler. It may be overridden by subtargets. */
1046 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1047 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1048 %{noasmopt:-O0} \
1049 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1050 #endif
1051
1052 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1053 the assembler. It may be overridden by subtargets.
1054
1055 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1056 COFF debugging info. */
1057
1058 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1059 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1060 %{g} %{g0} %{g1} %{g2} %{g3} \
1061 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1062 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1063 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1064 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1065 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1066 #endif
1067
1068 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1069 overridden by subtargets. */
1070
1071 #ifndef SUBTARGET_ASM_SPEC
1072 #define SUBTARGET_ASM_SPEC ""
1073 #endif
1074
1075 #undef ASM_SPEC
1076 #define ASM_SPEC "\
1077 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1078 %{mips32} %{mips32r2} %{mips64} \
1079 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1080 %{mips3d:-mips3d} \
1081 %{mfix-vr4120} \
1082 %(subtarget_asm_optimizing_spec) \
1083 %(subtarget_asm_debugging_spec) \
1084 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
1085 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1086 %{mtune=*} %{v} \
1087 %(subtarget_asm_spec)"
1088
1089 /* Extra switches sometimes passed to the linker. */
1090 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1091 will interpret it as a -b option. */
1092
1093 #ifndef LINK_SPEC
1094 #define LINK_SPEC "\
1095 %(endian_spec) \
1096 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1097 %{bestGnum} %{shared} %{non_shared}"
1098 #endif /* LINK_SPEC defined */
1099
1100
1101 /* Specs for the compiler proper */
1102
1103 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1104 overridden by subtargets. */
1105 #ifndef SUBTARGET_CC1_SPEC
1106 #define SUBTARGET_CC1_SPEC ""
1107 #endif
1108
1109 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1110
1111 #ifndef CC1_SPEC
1112 #define CC1_SPEC "\
1113 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1114 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1115 %{save-temps: } \
1116 %(subtarget_cc1_spec)"
1117 #endif
1118
1119 /* Preprocessor specs. */
1120
1121 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1122 overridden by subtargets. */
1123 #ifndef SUBTARGET_CPP_SPEC
1124 #define SUBTARGET_CPP_SPEC ""
1125 #endif
1126
1127 #define CPP_SPEC "%(subtarget_cpp_spec)"
1128
1129 /* This macro defines names of additional specifications to put in the specs
1130 that can be used in various specifications like CC1_SPEC. Its definition
1131 is an initializer with a subgrouping for each command option.
1132
1133 Each subgrouping contains a string constant, that defines the
1134 specification name, and a string constant that used by the GCC driver
1135 program.
1136
1137 Do not define this macro if it does not need to do anything. */
1138
1139 #define EXTRA_SPECS \
1140 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1141 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1142 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1143 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1144 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1145 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1146 { "endian_spec", ENDIAN_SPEC }, \
1147 SUBTARGET_EXTRA_SPECS
1148
1149 #ifndef SUBTARGET_EXTRA_SPECS
1150 #define SUBTARGET_EXTRA_SPECS
1151 #endif
1152 \f
1153 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1154 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1155 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1156
1157 #ifndef PREFERRED_DEBUGGING_TYPE
1158 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1159 #endif
1160
1161 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
1162
1163 /* By default, turn on GDB extensions. */
1164 #define DEFAULT_GDB_EXTENSIONS 1
1165
1166 /* Local compiler-generated symbols must have a prefix that the assembler
1167 understands. By default, this is $, although some targets (e.g.,
1168 NetBSD-ELF) need to override this. */
1169
1170 #ifndef LOCAL_LABEL_PREFIX
1171 #define LOCAL_LABEL_PREFIX "$"
1172 #endif
1173
1174 /* By default on the mips, external symbols do not have an underscore
1175 prepended, but some targets (e.g., NetBSD) require this. */
1176
1177 #ifndef USER_LABEL_PREFIX
1178 #define USER_LABEL_PREFIX ""
1179 #endif
1180
1181 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1182 since the length can run past this up to a continuation point. */
1183 #undef DBX_CONTIN_LENGTH
1184 #define DBX_CONTIN_LENGTH 1500
1185
1186 /* How to renumber registers for dbx and gdb. */
1187 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1188
1189 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1190 #define DWARF_FRAME_REGNUM(REG) (REG)
1191
1192 /* The DWARF 2 CFA column which tracks the return address. */
1193 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1194
1195 /* The DWARF 2 CFA column which tracks the return address from a
1196 signal handler context. */
1197 #define SIGNAL_UNWIND_RETURN_COLUMN (FP_REG_LAST + 1)
1198
1199 /* Before the prologue, RA lives in r31. */
1200 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1201
1202 /* Describe how we implement __builtin_eh_return. */
1203 #define EH_RETURN_DATA_REGNO(N) \
1204 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1205
1206 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1207
1208 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1209 The default for this in 64-bit mode is 8, which causes problems with
1210 SFmode register saves. */
1211 #define DWARF_CIE_DATA_ALIGNMENT 4
1212
1213 /* Correct the offset of automatic variables and arguments. Note that
1214 the MIPS debug format wants all automatic variables and arguments
1215 to be in terms of the virtual frame pointer (stack pointer before
1216 any adjustment in the function), while the MIPS 3.0 linker wants
1217 the frame pointer to be the stack pointer after the initial
1218 adjustment. */
1219
1220 #define DEBUGGER_AUTO_OFFSET(X) \
1221 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1222 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1223 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1224 \f
1225 /* Target machine storage layout */
1226
1227 #define BITS_BIG_ENDIAN 0
1228 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1229 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1230
1231 /* Define this to set the endianness to use in libgcc2.c, which can
1232 not depend on target_flags. */
1233 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1234 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1235 #else
1236 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1237 #endif
1238
1239 #define MAX_BITS_PER_WORD 64
1240
1241 /* Width of a word, in units (bytes). */
1242 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1243 #define MIN_UNITS_PER_WORD 4
1244
1245 /* For MIPS, width of a floating point register. */
1246 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1247
1248 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1249 the next available register. */
1250 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1251
1252 /* The largest size of value that can be held in floating-point
1253 registers and moved with a single instruction. */
1254 #define UNITS_PER_HWFPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1255
1256 /* The largest size of value that can be held in floating-point
1257 registers. */
1258 #define UNITS_PER_FPVALUE \
1259 (TARGET_SOFT_FLOAT ? 0 \
1260 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1261 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1262
1263 /* The number of bytes in a double. */
1264 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1265
1266 #define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : 0)
1267
1268 /* Set the sizes of the core types. */
1269 #define SHORT_TYPE_SIZE 16
1270 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1271 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1272 #define LONG_LONG_TYPE_SIZE 64
1273
1274 #define FLOAT_TYPE_SIZE 32
1275 #define DOUBLE_TYPE_SIZE 64
1276 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1277
1278 /* long double is not a fixed mode, but the idea is that, if we
1279 support long double, we also want a 128-bit integer type. */
1280 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1281
1282 #ifdef IN_LIBGCC2
1283 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1284 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1285 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1286 # else
1287 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1288 # endif
1289 #endif
1290
1291 /* Width in bits of a pointer. */
1292 #ifndef POINTER_SIZE
1293 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1294 #endif
1295
1296 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1297 #define PARM_BOUNDARY ((mips_abi == ABI_O64 \
1298 || TARGET_NEWABI \
1299 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1300
1301
1302 /* Allocation boundary (in *bits*) for the code of a function. */
1303 #define FUNCTION_BOUNDARY 32
1304
1305 /* Alignment of field after `int : 0' in a structure. */
1306 #define EMPTY_FIELD_BOUNDARY 32
1307
1308 /* Every structure's size must be a multiple of this. */
1309 /* 8 is observed right on a DECstation and on riscos 4.02. */
1310 #define STRUCTURE_SIZE_BOUNDARY 8
1311
1312 /* There is no point aligning anything to a rounder boundary than this. */
1313 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1314
1315 /* All accesses must be aligned. */
1316 #define STRICT_ALIGNMENT 1
1317
1318 /* Define this if you wish to imitate the way many other C compilers
1319 handle alignment of bitfields and the structures that contain
1320 them.
1321
1322 The behavior is that the type written for a bit-field (`int',
1323 `short', or other integer type) imposes an alignment for the
1324 entire structure, as if the structure really did contain an
1325 ordinary field of that type. In addition, the bit-field is placed
1326 within the structure so that it would fit within such a field,
1327 not crossing a boundary for it.
1328
1329 Thus, on most machines, a bit-field whose type is written as `int'
1330 would not cross a four-byte boundary, and would force four-byte
1331 alignment for the whole structure. (The alignment used may not
1332 be four bytes; it is controlled by the other alignment
1333 parameters.)
1334
1335 If the macro is defined, its definition should be a C expression;
1336 a nonzero value for the expression enables this behavior. */
1337
1338 #define PCC_BITFIELD_TYPE_MATTERS 1
1339
1340 /* If defined, a C expression to compute the alignment given to a
1341 constant that is being placed in memory. CONSTANT is the constant
1342 and ALIGN is the alignment that the object would ordinarily have.
1343 The value of this macro is used instead of that alignment to align
1344 the object.
1345
1346 If this macro is not defined, then ALIGN is used.
1347
1348 The typical use of this macro is to increase alignment for string
1349 constants to be word aligned so that `strcpy' calls that copy
1350 constants can be done inline. */
1351
1352 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1353 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1354 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1355
1356 /* If defined, a C expression to compute the alignment for a static
1357 variable. TYPE is the data type, and ALIGN is the alignment that
1358 the object would ordinarily have. The value of this macro is used
1359 instead of that alignment to align the object.
1360
1361 If this macro is not defined, then ALIGN is used.
1362
1363 One use of this macro is to increase alignment of medium-size
1364 data to make it all fit in fewer cache lines. Another is to
1365 cause character arrays to be word-aligned so that `strcpy' calls
1366 that copy constants to character arrays can be done inline. */
1367
1368 #undef DATA_ALIGNMENT
1369 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1370 ((((ALIGN) < BITS_PER_WORD) \
1371 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1372 || TREE_CODE (TYPE) == UNION_TYPE \
1373 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1374
1375
1376 #define PAD_VARARGS_DOWN \
1377 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1378
1379 /* Define if operations between registers always perform the operation
1380 on the full register even if a narrower mode is specified. */
1381 #define WORD_REGISTER_OPERATIONS
1382
1383 /* When in 64 bit mode, move insns will sign extend SImode and CCmode
1384 moves. All other references are zero extended. */
1385 #define LOAD_EXTEND_OP(MODE) \
1386 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1387 ? SIGN_EXTEND : ZERO_EXTEND)
1388
1389 /* Define this macro if it is advisable to hold scalars in registers
1390 in a wider mode than that declared by the program. In such cases,
1391 the value is constrained to be within the bounds of the declared
1392 type, but kept valid in the wider mode. The signedness of the
1393 extension may differ from that of the type. */
1394
1395 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1396 if (GET_MODE_CLASS (MODE) == MODE_INT \
1397 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1398 { \
1399 if ((MODE) == SImode) \
1400 (UNSIGNEDP) = 0; \
1401 (MODE) = Pmode; \
1402 }
1403
1404 /* Define if loading short immediate values into registers sign extends. */
1405 #define SHORT_IMMEDIATES_SIGN_EXTEND
1406 \f
1407 /* Standard register usage. */
1408
1409 /* Number of hardware registers. We have:
1410
1411 - 32 integer registers
1412 - 32 floating point registers
1413 - 8 condition code registers
1414 - 2 accumulator registers (hi and lo)
1415 - 32 registers each for coprocessors 0, 2 and 3
1416 - 3 fake registers:
1417 - ARG_POINTER_REGNUM
1418 - FRAME_POINTER_REGNUM
1419 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1420 - 3 dummy entries that were used at various times in the past. */
1421
1422 #define FIRST_PSEUDO_REGISTER 176
1423
1424 /* By default, fix the kernel registers ($26 and $27), the global
1425 pointer ($28) and the stack pointer ($29). This can change
1426 depending on the command-line options.
1427
1428 Regarding coprocessor registers: without evidence to the contrary,
1429 it's best to assume that each coprocessor register has a unique
1430 use. This can be overridden, in, e.g., override_options() or
1431 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1432 for a particular target. */
1433
1434 #define FIXED_REGISTERS \
1435 { \
1436 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1437 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1438 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1439 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1440 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1441 /* COP0 registers */ \
1442 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1443 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1444 /* COP2 registers */ \
1445 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1446 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1447 /* COP3 registers */ \
1448 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1449 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1450 }
1451
1452
1453 /* Set up this array for o32 by default.
1454
1455 Note that we don't mark $31 as a call-clobbered register. The idea is
1456 that it's really the call instructions themselves which clobber $31.
1457 We don't care what the called function does with it afterwards.
1458
1459 This approach makes it easier to implement sibcalls. Unlike normal
1460 calls, sibcalls don't clobber $31, so the register reaches the
1461 called function in tact. EPILOGUE_USES says that $31 is useful
1462 to the called function. */
1463
1464 #define CALL_USED_REGISTERS \
1465 { \
1466 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1467 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1468 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1469 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1470 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1471 /* COP0 registers */ \
1472 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1473 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1474 /* COP2 registers */ \
1475 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1476 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1477 /* COP3 registers */ \
1478 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1479 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1480 }
1481
1482
1483 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1484
1485 #define CALL_REALLY_USED_REGISTERS \
1486 { /* General registers. */ \
1487 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1488 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1489 /* Floating-point registers. */ \
1490 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1491 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1492 /* Others. */ \
1493 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1494 /* COP0 registers */ \
1495 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1496 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1497 /* COP2 registers */ \
1498 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1499 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1500 /* COP3 registers */ \
1501 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1502 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1503 }
1504
1505 /* Internal macros to classify a register number as to whether it's a
1506 general purpose register, a floating point register, a
1507 multiply/divide register, or a status register. */
1508
1509 #define GP_REG_FIRST 0
1510 #define GP_REG_LAST 31
1511 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1512 #define GP_DBX_FIRST 0
1513
1514 #define FP_REG_FIRST 32
1515 #define FP_REG_LAST 63
1516 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1517 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1518
1519 #define MD_REG_FIRST 64
1520 #define MD_REG_LAST 65
1521 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1522 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1523
1524 #define ST_REG_FIRST 67
1525 #define ST_REG_LAST 74
1526 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1527
1528
1529 /* FIXME: renumber. */
1530 #define COP0_REG_FIRST 80
1531 #define COP0_REG_LAST 111
1532 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1533
1534 #define COP2_REG_FIRST 112
1535 #define COP2_REG_LAST 143
1536 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1537
1538 #define COP3_REG_FIRST 144
1539 #define COP3_REG_LAST 175
1540 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1541 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1542 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1543
1544 #define AT_REGNUM (GP_REG_FIRST + 1)
1545 #define HI_REGNUM (MD_REG_FIRST + 0)
1546 #define LO_REGNUM (MD_REG_FIRST + 1)
1547
1548 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1549 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1550 should be used instead. */
1551 #define FPSW_REGNUM ST_REG_FIRST
1552
1553 #define GP_REG_P(REGNO) \
1554 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1555 #define M16_REG_P(REGNO) \
1556 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1557 #define FP_REG_P(REGNO) \
1558 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1559 #define MD_REG_P(REGNO) \
1560 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1561 #define ST_REG_P(REGNO) \
1562 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1563 #define COP0_REG_P(REGNO) \
1564 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1565 #define COP2_REG_P(REGNO) \
1566 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1567 #define COP3_REG_P(REGNO) \
1568 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1569 #define ALL_COP_REG_P(REGNO) \
1570 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1571
1572 #define FP_REG_RTX_P(X) (GET_CODE (X) == REG && FP_REG_P (REGNO (X)))
1573
1574 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1575 to initialize the mips16 gp pseudo register. */
1576 #define CONST_GP_P(X) \
1577 (GET_CODE (X) == CONST \
1578 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1579 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1580
1581 /* Return coprocessor number from register number. */
1582
1583 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1584 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1585 : COP3_REG_P (REGNO) ? '3' : '?')
1586
1587
1588 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1589
1590 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1591 array built in override_options. Because machmodes.h is not yet
1592 included before this file is processed, the MODE bound can't be
1593 expressed here. */
1594
1595 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1596
1597 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1598 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1599
1600 /* Value is 1 if it is a good idea to tie two pseudo registers
1601 when one has mode MODE1 and one has mode MODE2.
1602 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1603 for any hard reg, then this must be 0 for correct output. */
1604 #define MODES_TIEABLE_P(MODE1, MODE2) \
1605 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1606 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1607 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1608 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1609
1610 /* Register to use for pushing function arguments. */
1611 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1612
1613 /* These two registers don't really exist: they get eliminated to either
1614 the stack or hard frame pointer. */
1615 #define ARG_POINTER_REGNUM 77
1616 #define FRAME_POINTER_REGNUM 78
1617
1618 /* $30 is not available on the mips16, so we use $17 as the frame
1619 pointer. */
1620 #define HARD_FRAME_POINTER_REGNUM \
1621 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1622
1623 /* Value should be nonzero if functions must have frame pointers.
1624 Zero means the frame pointer need not be set up (and parms
1625 may be accessed via the stack pointer) in functions that seem suitable.
1626 This is computed in `reload', in reload1.c. */
1627 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1628
1629 /* Register in which static-chain is passed to a function. */
1630 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1631
1632 /* Registers used as temporaries in prologue/epilogue code. If we're
1633 generating mips16 code, these registers must come from the core set
1634 of 8. The prologue register mustn't conflict with any incoming
1635 arguments, the static chain pointer, or the frame pointer. The
1636 epilogue temporary mustn't conflict with the return registers, the
1637 frame pointer, the EH stack adjustment, or the EH data registers. */
1638
1639 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1640 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1641
1642 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1643 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1644
1645 /* Define this macro if it is as good or better to call a constant
1646 function address than to call an address kept in a register. */
1647 #define NO_FUNCTION_CSE 1
1648
1649 /* The ABI-defined global pointer. Sometimes we use a different
1650 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1651 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1652
1653 /* We normally use $28 as the global pointer. However, when generating
1654 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1655 register instead. They can then avoid saving and restoring $28
1656 and perhaps avoid using a frame at all.
1657
1658 When a leaf function uses something other than $28, mips_expand_prologue
1659 will modify pic_offset_table_rtx in place. Take the register number
1660 from there after reload. */
1661 #define PIC_OFFSET_TABLE_REGNUM \
1662 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1663
1664 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1665 \f
1666 /* Define the classes of registers for register constraints in the
1667 machine description. Also define ranges of constants.
1668
1669 One of the classes must always be named ALL_REGS and include all hard regs.
1670 If there is more than one class, another class must be named NO_REGS
1671 and contain no registers.
1672
1673 The name GENERAL_REGS must be the name of a class (or an alias for
1674 another name such as ALL_REGS). This is the class of registers
1675 that is allowed by "g" or "r" in a register constraint.
1676 Also, registers outside this class are allocated only when
1677 instructions express preferences for them.
1678
1679 The classes must be numbered in nondecreasing order; that is,
1680 a larger-numbered class must never be contained completely
1681 in a smaller-numbered class.
1682
1683 For any two classes, it is very desirable that there be another
1684 class that represents their union. */
1685
1686 enum reg_class
1687 {
1688 NO_REGS, /* no registers in set */
1689 M16_NA_REGS, /* mips16 regs not used to pass args */
1690 M16_REGS, /* mips16 directly accessible registers */
1691 T_REG, /* mips16 T register ($24) */
1692 M16_T_REGS, /* mips16 registers plus T register */
1693 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1694 LEA_REGS, /* Every GPR except $25 */
1695 GR_REGS, /* integer registers */
1696 FP_REGS, /* floating point registers */
1697 HI_REG, /* hi register */
1698 LO_REG, /* lo register */
1699 MD_REGS, /* multiply/divide registers (hi/lo) */
1700 COP0_REGS, /* generic coprocessor classes */
1701 COP2_REGS,
1702 COP3_REGS,
1703 HI_AND_GR_REGS, /* union classes */
1704 LO_AND_GR_REGS,
1705 HI_AND_FP_REGS,
1706 COP0_AND_GR_REGS,
1707 COP2_AND_GR_REGS,
1708 COP3_AND_GR_REGS,
1709 ALL_COP_REGS,
1710 ALL_COP_AND_GR_REGS,
1711 ST_REGS, /* status registers (fp status) */
1712 ALL_REGS, /* all registers */
1713 LIM_REG_CLASSES /* max value + 1 */
1714 };
1715
1716 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1717
1718 #define GENERAL_REGS GR_REGS
1719
1720 /* An initializer containing the names of the register classes as C
1721 string constants. These names are used in writing some of the
1722 debugging dumps. */
1723
1724 #define REG_CLASS_NAMES \
1725 { \
1726 "NO_REGS", \
1727 "M16_NA_REGS", \
1728 "M16_REGS", \
1729 "T_REG", \
1730 "M16_T_REGS", \
1731 "PIC_FN_ADDR_REG", \
1732 "LEA_REGS", \
1733 "GR_REGS", \
1734 "FP_REGS", \
1735 "HI_REG", \
1736 "LO_REG", \
1737 "MD_REGS", \
1738 /* coprocessor registers */ \
1739 "COP0_REGS", \
1740 "COP2_REGS", \
1741 "COP3_REGS", \
1742 "HI_AND_GR_REGS", \
1743 "LO_AND_GR_REGS", \
1744 "HI_AND_FP_REGS", \
1745 "COP0_AND_GR_REGS", \
1746 "COP2_AND_GR_REGS", \
1747 "COP3_AND_GR_REGS", \
1748 "ALL_COP_REGS", \
1749 "ALL_COP_AND_GR_REGS", \
1750 "ST_REGS", \
1751 "ALL_REGS" \
1752 }
1753
1754 /* An initializer containing the contents of the register classes,
1755 as integers which are bit masks. The Nth integer specifies the
1756 contents of class N. The way the integer MASK is interpreted is
1757 that register R is in the class if `MASK & (1 << R)' is 1.
1758
1759 When the machine has more than 32 registers, an integer does not
1760 suffice. Then the integers are replaced by sub-initializers,
1761 braced groupings containing several integers. Each
1762 sub-initializer must be suitable as an initializer for the type
1763 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1764
1765 #define REG_CLASS_CONTENTS \
1766 { \
1767 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1768 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1769 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1770 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1771 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1772 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1773 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR */ \
1774 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1775 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1776 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1777 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1778 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1779 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1780 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1781 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1782 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1783 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1784 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1785 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1786 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1787 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1788 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1789 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1790 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1791 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
1792 }
1793
1794
1795 /* A C expression whose value is a register class containing hard
1796 register REGNO. In general there is more that one such class;
1797 choose a class which is "minimal", meaning that no smaller class
1798 also contains the register. */
1799
1800 extern const enum reg_class mips_regno_to_class[];
1801
1802 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1803
1804 /* A macro whose definition is the name of the class to which a
1805 valid base register must belong. A base register is one used in
1806 an address which is the register value plus a displacement. */
1807
1808 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1809
1810 /* A macro whose definition is the name of the class to which a
1811 valid index register must belong. An index register is one used
1812 in an address where its value is either multiplied by a scale
1813 factor or added to another register (as well as added to a
1814 displacement). */
1815
1816 #define INDEX_REG_CLASS NO_REGS
1817
1818 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1819 registers explicitly used in the rtl to be used as spill registers
1820 but prevents the compiler from extending the lifetime of these
1821 registers. */
1822
1823 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1824
1825 /* This macro is used later on in the file. */
1826 #define GR_REG_CLASS_P(CLASS) \
1827 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
1828 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS \
1829 || (CLASS) == PIC_FN_ADDR_REG || (CLASS) == LEA_REGS)
1830
1831 /* This macro is also used later on in the file. */
1832 #define COP_REG_CLASS_P(CLASS) \
1833 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
1834
1835 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1836 is the default value (allocate the registers in numeric order). We
1837 define it just so that we can override it for the mips16 target in
1838 ORDER_REGS_FOR_LOCAL_ALLOC. */
1839
1840 #define REG_ALLOC_ORDER \
1841 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1842 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1843 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1844 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1845 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1846 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1847 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1848 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1849 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1850 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1851 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
1852 }
1853
1854 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1855 to be rearranged based on a particular function. On the mips16, we
1856 want to allocate $24 (T_REG) before other registers for
1857 instructions for which it is possible. */
1858
1859 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1860
1861 /* REGISTER AND CONSTANT CLASSES */
1862
1863 /* Get reg_class from a letter such as appears in the machine
1864 description.
1865
1866 DEFINED REGISTER CLASSES:
1867
1868 'd' General (aka integer) registers
1869 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
1870 'y' General registers (in both mips16 and non mips16 mode)
1871 'e' Effective address registers (general registers except $25)
1872 't' mips16 temporary register ($24)
1873 'f' Floating point registers
1874 'h' Hi register
1875 'l' Lo register
1876 'x' Multiply/divide registers
1877 'z' FP Status register
1878 'B' Cop0 register
1879 'C' Cop2 register
1880 'D' Cop3 register
1881 'b' All registers */
1882
1883 extern enum reg_class mips_char_to_class[256];
1884
1885 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
1886
1887 /* True if VALUE is a signed 16-bit number. */
1888
1889 #define SMALL_OPERAND(VALUE) \
1890 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1891
1892 /* True if VALUE is an unsigned 16-bit number. */
1893
1894 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1895 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1896
1897 /* True if VALUE can be loaded into a register using LUI. */
1898
1899 #define LUI_OPERAND(VALUE) \
1900 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1901 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1902
1903 /* Return a value X with the low 16 bits clear, and such that
1904 VALUE - X is a signed 16-bit value. */
1905
1906 #define CONST_HIGH_PART(VALUE) \
1907 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1908
1909 #define CONST_LOW_PART(VALUE) \
1910 ((VALUE) - CONST_HIGH_PART (VALUE))
1911
1912 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1913 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1914 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1915
1916 /* The letters I, J, K, L, M, N, O, and P in a register constraint
1917 string can be used to stand for particular ranges of immediate
1918 operands. This macro defines what the ranges are. C is the
1919 letter, and VALUE is a constant value. Return 1 if VALUE is
1920 in the range specified by C. */
1921
1922 /* For MIPS:
1923
1924 `I' is used for the range of constants an arithmetic insn can
1925 actually contain (16 bits signed integers).
1926
1927 `J' is used for the range which is just zero (i.e., $r0).
1928
1929 `K' is used for the range of constants a logical insn can actually
1930 contain (16 bit zero-extended integers).
1931
1932 `L' is used for the range of constants that be loaded with lui
1933 (i.e., the bottom 16 bits are zero).
1934
1935 `M' is used for the range of constants that take two words to load
1936 (i.e., not matched by `I', `K', and `L').
1937
1938 `N' is used for negative 16 bit constants other than -65536.
1939
1940 `O' is a 15 bit signed integer.
1941
1942 `P' is used for positive 16 bit constants. */
1943
1944 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1945 ((C) == 'I' ? SMALL_OPERAND (VALUE) \
1946 : (C) == 'J' ? ((VALUE) == 0) \
1947 : (C) == 'K' ? SMALL_OPERAND_UNSIGNED (VALUE) \
1948 : (C) == 'L' ? LUI_OPERAND (VALUE) \
1949 : (C) == 'M' ? (!SMALL_OPERAND (VALUE) \
1950 && !SMALL_OPERAND_UNSIGNED (VALUE) \
1951 && !LUI_OPERAND (VALUE)) \
1952 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
1953 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
1954 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
1955 : 0)
1956
1957 /* Similar, but for floating constants, and defining letters G and H.
1958 Here VALUE is the CONST_DOUBLE rtx itself. */
1959
1960 /* For Mips
1961
1962 'G' : Floating point 0 */
1963
1964 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1965 ((C) == 'G' \
1966 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
1967
1968 /* Letters in the range `Q' through `U' may be defined in a
1969 machine-dependent fashion to stand for arbitrary operand types.
1970 The machine description macro `EXTRA_CONSTRAINT' is passed the
1971 operand as its first argument and the constraint letter as its
1972 second operand.
1973
1974 `Q' is for signed 16-bit constants.
1975 `R' is for single-instruction memory references. Note that this
1976 constraint has often been used in linux and glibc code.
1977 `S' is for legitimate constant call addresses.
1978 `T' is for constant move_operands that cannot be safely loaded into $25.
1979 `U' is for constant move_operands that can be safely loaded into $25.
1980 `W' is for memory references that are based on a member of BASE_REG_CLASS.
1981 This is true for all non-mips16 references (although it can sometimes
1982 be indirect if !TARGET_EXPLICIT_RELOCS). For mips16, it excludes
1983 stack and constant-pool references.
1984 `YG' is for 0 valued vector constants. */
1985
1986 #define EXTRA_CONSTRAINT_Y(OP,STR) \
1987 (((STR)[1] == 'G') ? (GET_CODE (OP) == CONST_VECTOR \
1988 && (OP) == CONST0_RTX (GET_MODE (OP))) \
1989 : FALSE)
1990
1991
1992 #define EXTRA_CONSTRAINT_STR(OP,CODE,STR) \
1993 (((CODE) == 'Q') ? const_arith_operand (OP, VOIDmode) \
1994 : ((CODE) == 'R') ? (GET_CODE (OP) == MEM \
1995 && mips_fetch_insns (OP) == 1) \
1996 : ((CODE) == 'S') ? (CONSTANT_P (OP) \
1997 && call_insn_operand (OP, VOIDmode)) \
1998 : ((CODE) == 'T') ? (CONSTANT_P (OP) \
1999 && move_operand (OP, VOIDmode) \
2000 && mips_dangerous_for_la25_p (OP)) \
2001 : ((CODE) == 'U') ? (CONSTANT_P (OP) \
2002 && move_operand (OP, VOIDmode) \
2003 && !mips_dangerous_for_la25_p (OP)) \
2004 : ((CODE) == 'W') ? (GET_CODE (OP) == MEM \
2005 && memory_operand (OP, VOIDmode) \
2006 && (!TARGET_MIPS16 \
2007 || (!stack_operand (OP, VOIDmode) \
2008 && !CONSTANT_P (XEXP (OP, 0))))) \
2009 : ((CODE) == 'Y') ? EXTRA_CONSTRAINT_Y (OP, STR) \
2010 : FALSE)
2011
2012 /* Y is the only multi-letter constraint, and has length 2. */
2013
2014 #define CONSTRAINT_LEN(C,STR) \
2015 (((C) == 'Y') ? 2 \
2016 : DEFAULT_CONSTRAINT_LEN (C, STR))
2017
2018 /* Say which of the above are memory constraints. */
2019 #define EXTRA_MEMORY_CONSTRAINT(C, STR) ((C) == 'R' || (C) == 'W')
2020
2021 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2022 mips_preferred_reload_class (X, CLASS)
2023
2024 /* Certain machines have the property that some registers cannot be
2025 copied to some other registers without using memory. Define this
2026 macro on those machines to be a C expression that is nonzero if
2027 objects of mode MODE in registers of CLASS1 can only be copied to
2028 registers of class CLASS2 by storing a register of CLASS1 into
2029 memory and loading that memory location into a register of CLASS2.
2030
2031 Do not define this macro if its value would always be zero. */
2032 #if 0
2033 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2034 ((!TARGET_DEBUG_H_MODE \
2035 && GET_MODE_CLASS (MODE) == MODE_INT \
2036 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2037 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2038 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2039 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2040 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2041 #endif
2042 /* The HI and LO registers can only be reloaded via the general
2043 registers. Condition code registers can only be loaded to the
2044 general registers, and from the floating point registers. */
2045
2046 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2047 mips_secondary_reload_class (CLASS, MODE, X, 1)
2048 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2049 mips_secondary_reload_class (CLASS, MODE, X, 0)
2050
2051 /* Return the maximum number of consecutive registers
2052 needed to represent mode MODE in a register of class CLASS. */
2053
2054 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2055
2056 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
2057 mips_cannot_change_mode_class (FROM, TO, CLASS)
2058 \f
2059 /* Stack layout; function entry, exit and calling. */
2060
2061 #define STACK_GROWS_DOWNWARD
2062
2063 /* The offset of the first local variable from the beginning of the frame.
2064 See compute_frame_size for details about the frame layout.
2065
2066 ??? If flag_profile_values is true, and we are generating 32-bit code, then
2067 we assume that we will need 16 bytes of argument space. This is because
2068 the value profiling code may emit calls to cmpdi2 in leaf functions.
2069 Without this hack, the local variables will start at sp+8 and the gp save
2070 area will be at sp+16, and thus they will overlap. compute_frame_size is
2071 OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which
2072 will end up as 24 instead of 8. This won't be needed if profiling code is
2073 inserted before virtual register instantiation. */
2074
2075 #define STARTING_FRAME_OFFSET \
2076 ((flag_profile_values && ! TARGET_64BIT \
2077 ? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \
2078 : current_function_outgoing_args_size) \
2079 + (TARGET_ABICALLS && !TARGET_NEWABI \
2080 ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2081
2082 #define RETURN_ADDR_RTX mips_return_addr
2083
2084 /* Since the mips16 ISA mode is encoded in the least-significant bit
2085 of the address, mask it off return addresses for purposes of
2086 finding exception handling regions. */
2087
2088 #define MASK_RETURN_ADDR GEN_INT (-2)
2089
2090
2091 /* Similarly, don't use the least-significant bit to tell pointers to
2092 code from vtable index. */
2093
2094 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2095
2096 /* The eliminations to $17 are only used for mips16 code. See the
2097 definition of HARD_FRAME_POINTER_REGNUM. */
2098
2099 #define ELIMINABLE_REGS \
2100 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2101 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2102 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2103 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2104 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2105 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2106
2107 /* We can always eliminate to the hard frame pointer. We can eliminate
2108 to the stack pointer unless a frame pointer is needed.
2109
2110 In mips16 mode, we need a frame pointer for a large frame; otherwise,
2111 reload may be unable to compute the address of a local variable,
2112 since there is no way to add a large constant to the stack pointer
2113 without using a temporary register. */
2114 #define CAN_ELIMINATE(FROM, TO) \
2115 ((TO) == HARD_FRAME_POINTER_REGNUM \
2116 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
2117 && (!TARGET_MIPS16 \
2118 || compute_frame_size (get_frame_size ()) < 32768)))
2119
2120 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2121 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2122
2123 /* Allocate stack space for arguments at the beginning of each function. */
2124 #define ACCUMULATE_OUTGOING_ARGS 1
2125
2126 /* The argument pointer always points to the first argument. */
2127 #define FIRST_PARM_OFFSET(FNDECL) 0
2128
2129 /* o32 and o64 reserve stack space for all argument registers. */
2130 #define REG_PARM_STACK_SPACE(FNDECL) \
2131 (TARGET_OLDABI \
2132 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2133 : 0)
2134
2135 /* Define this if it is the responsibility of the caller to
2136 allocate the area reserved for arguments passed in registers.
2137 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2138 of this macro is to determine whether the space is included in
2139 `current_function_outgoing_args_size'. */
2140 #define OUTGOING_REG_PARM_STACK_SPACE
2141
2142 #define STACK_BOUNDARY ((TARGET_OLDABI || mips_abi == ABI_EABI) ? 64 : 128)
2143 \f
2144 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2145
2146 /* Symbolic macros for the registers used to return integer and floating
2147 point values. */
2148
2149 #define GP_RETURN (GP_REG_FIRST + 2)
2150 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2151
2152 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2153
2154 /* Symbolic macros for the first/last argument registers. */
2155
2156 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2157 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2158 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2159 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2160
2161 #define LIBCALL_VALUE(MODE) \
2162 mips_function_value (NULL_TREE, NULL, (MODE))
2163
2164 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2165 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2166
2167 /* 1 if N is a possible register number for a function value.
2168 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2169 Currently, R2 and F0 are only implemented here (C has no complex type) */
2170
2171 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2172 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2173 && (N) == FP_RETURN + 2))
2174
2175 /* 1 if N is a possible register number for function argument passing.
2176 We have no FP argument registers when soft-float. When FP registers
2177 are 32 bits, we can't directly reference the odd numbered ones. */
2178
2179 #define FUNCTION_ARG_REGNO_P(N) \
2180 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2181 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2182 && !fixed_regs[N])
2183 \f
2184 /* This structure has to cope with two different argument allocation
2185 schemes. Most MIPS ABIs view the arguments as a structure, of which
2186 the first N words go in registers and the rest go on the stack. If I
2187 < N, the Ith word might go in Ith integer argument register or in a
2188 floating-point register. For these ABIs, we only need to remember
2189 the offset of the current argument into the structure.
2190
2191 The EABI instead allocates the integer and floating-point arguments
2192 separately. The first N words of FP arguments go in FP registers,
2193 the rest go on the stack. Likewise, the first N words of the other
2194 arguments go in integer registers, and the rest go on the stack. We
2195 need to maintain three counts: the number of integer registers used,
2196 the number of floating-point registers used, and the number of words
2197 passed on the stack.
2198
2199 We could keep separate information for the two ABIs (a word count for
2200 the standard ABIs, and three separate counts for the EABI). But it
2201 seems simpler to view the standard ABIs as forms of EABI that do not
2202 allocate floating-point registers.
2203
2204 So for the standard ABIs, the first N words are allocated to integer
2205 registers, and function_arg decides on an argument-by-argument basis
2206 whether that argument should really go in an integer register, or in
2207 a floating-point one. */
2208
2209 typedef struct mips_args {
2210 /* Always true for varargs functions. Otherwise true if at least
2211 one argument has been passed in an integer register. */
2212 int gp_reg_found;
2213
2214 /* The number of arguments seen so far. */
2215 unsigned int arg_number;
2216
2217 /* The number of integer registers used so far. For all ABIs except
2218 EABI, this is the number of words that have been added to the
2219 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2220 unsigned int num_gprs;
2221
2222 /* For EABI, the number of floating-point registers used so far. */
2223 unsigned int num_fprs;
2224
2225 /* The number of words passed on the stack. */
2226 unsigned int stack_words;
2227
2228 /* On the mips16, we need to keep track of which floating point
2229 arguments were passed in general registers, but would have been
2230 passed in the FP regs if this were a 32 bit function, so that we
2231 can move them to the FP regs if we wind up calling a 32 bit
2232 function. We record this information in fp_code, encoded in base
2233 four. A zero digit means no floating point argument, a one digit
2234 means an SFmode argument, and a two digit means a DFmode argument,
2235 and a three digit is not used. The low order digit is the first
2236 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2237 an SFmode argument. ??? A more sophisticated approach will be
2238 needed if MIPS_ABI != ABI_32. */
2239 int fp_code;
2240
2241 /* True if the function has a prototype. */
2242 int prototype;
2243 } CUMULATIVE_ARGS;
2244
2245 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2246 for a call to a function whose data type is FNTYPE.
2247 For a library call, FNTYPE is 0. */
2248
2249 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2250 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2251
2252 /* Update the data in CUM to advance over an argument
2253 of mode MODE and data type TYPE.
2254 (TYPE is null for libcalls where that information may not be available.) */
2255
2256 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2257 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2258
2259 /* Determine where to put an argument to a function.
2260 Value is zero to push the argument on the stack,
2261 or a hard register in which to store the argument.
2262
2263 MODE is the argument's machine mode.
2264 TYPE is the data type of the argument (as a tree).
2265 This is null for libcalls where that information may
2266 not be available.
2267 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2268 the preceding args and about the function being called.
2269 NAMED is nonzero if this argument is a named parameter
2270 (otherwise it is an extra parameter matching an ellipsis). */
2271
2272 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2273 function_arg( &CUM, MODE, TYPE, NAMED)
2274
2275 /* For an arg passed partly in registers and partly in memory,
2276 this is the number of registers used.
2277 For args passed entirely in registers or entirely in memory, zero. */
2278
2279 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2280 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2281
2282 /* If defined, a C expression that gives the alignment boundary, in
2283 bits, of an argument with the specified mode and type. If it is
2284 not defined, `PARM_BOUNDARY' is used for all arguments. */
2285
2286 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2287 (((TYPE) != 0) \
2288 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2289 ? PARM_BOUNDARY \
2290 : TYPE_ALIGN(TYPE)) \
2291 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2292 ? PARM_BOUNDARY \
2293 : GET_MODE_ALIGNMENT(MODE)))
2294
2295 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2296 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2297
2298 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2299 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2300
2301 /* True if using EABI and varargs can be passed in floating-point
2302 registers. Under these conditions, we need a more complex form
2303 of va_list, which tracks GPR, FPR and stack arguments separately. */
2304 #define EABI_FLOAT_VARARGS_P \
2305 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2306
2307 \f
2308 /* Say that the epilogue uses the return address register. Note that
2309 in the case of sibcalls, the values "used by the epilogue" are
2310 considered live at the start of the called function. */
2311 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2312
2313 /* Treat LOC as a byte offset from the stack pointer and round it up
2314 to the next fully-aligned offset. */
2315 #define MIPS_STACK_ALIGN(LOC) \
2316 ((TARGET_OLDABI || mips_abi == ABI_EABI) \
2317 ? ((LOC) + 7) & ~7 \
2318 : ((LOC) + 15) & ~15)
2319
2320 \f
2321 /* Implement `va_start' for varargs and stdarg. */
2322 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2323 mips_va_start (valist, nextarg)
2324 \f
2325 /* Output assembler code to FILE to increment profiler label # LABELNO
2326 for profiling a function entry. */
2327
2328 #define FUNCTION_PROFILER(FILE, LABELNO) \
2329 { \
2330 if (TARGET_MIPS16) \
2331 sorry ("mips16 function profiling"); \
2332 fprintf (FILE, "\t.set\tnoat\n"); \
2333 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2334 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2335 if (!TARGET_NEWABI) \
2336 { \
2337 fprintf (FILE, \
2338 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2339 TARGET_64BIT ? "dsubu" : "subu", \
2340 reg_names[STACK_POINTER_REGNUM], \
2341 reg_names[STACK_POINTER_REGNUM], \
2342 Pmode == DImode ? 16 : 8); \
2343 } \
2344 fprintf (FILE, "\tjal\t_mcount\n"); \
2345 fprintf (FILE, "\t.set\tat\n"); \
2346 }
2347
2348 /* Define this macro if the code for function profiling should come
2349 before the function prologue. Normally, the profiling code comes
2350 after. */
2351
2352 /* #define PROFILE_BEFORE_PROLOGUE */
2353
2354 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2355 the stack pointer does not matter. The value is tested only in
2356 functions that have frame pointers.
2357 No definition is equivalent to always zero. */
2358
2359 #define EXIT_IGNORE_STACK 1
2360
2361 \f
2362 /* A C statement to output, on the stream FILE, assembler code for a
2363 block of data that contains the constant parts of a trampoline.
2364 This code should not include a label--the label is taken care of
2365 automatically. */
2366
2367 #define TRAMPOLINE_TEMPLATE(STREAM) \
2368 { \
2369 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2370 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2371 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2372 if (ptr_mode == DImode) \
2373 { \
2374 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2375 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2376 } \
2377 else \
2378 { \
2379 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2380 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2381 } \
2382 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2383 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2384 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2385 if (ptr_mode == DImode) \
2386 { \
2387 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2388 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2389 } \
2390 else \
2391 { \
2392 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2393 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2394 } \
2395 }
2396
2397 /* A C expression for the size in bytes of the trampoline, as an
2398 integer. */
2399
2400 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2401
2402 /* Alignment required for trampolines, in bits. */
2403
2404 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2405
2406 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2407 program and data caches. */
2408
2409 #ifndef CACHE_FLUSH_FUNC
2410 #define CACHE_FLUSH_FUNC "_flush_cache"
2411 #endif
2412
2413 /* A C statement to initialize the variable parts of a trampoline.
2414 ADDR is an RTX for the address of the trampoline; FNADDR is an
2415 RTX for the address of the nested function; STATIC_CHAIN is an
2416 RTX for the static chain value that should be passed to the
2417 function when it is called. */
2418
2419 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2420 { \
2421 rtx func_addr, chain_addr; \
2422 \
2423 func_addr = plus_constant (ADDR, 32); \
2424 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2425 emit_move_insn (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2426 emit_move_insn (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2427 \
2428 /* Flush both caches. We need to flush the data cache in case \
2429 the system has a write-back cache. */ \
2430 /* ??? Should check the return value for errors. */ \
2431 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2432 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2433 0, VOIDmode, 3, ADDR, Pmode, \
2434 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
2435 GEN_INT (3), TYPE_MODE (integer_type_node)); \
2436 }
2437 \f
2438 /* Addressing modes, and classification of registers for them. */
2439
2440 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2441 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2442 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2443
2444 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2445 and check its validity for a certain class.
2446 We have two alternate definitions for each of them.
2447 The usual definition accepts all pseudo regs; the other rejects them all.
2448 The symbol REG_OK_STRICT causes the latter definition to be used.
2449
2450 Most source files want to accept pseudo regs in the hope that
2451 they will get allocated to the class that the insn wants them to be in.
2452 Some source files that are used after register allocation
2453 need to be strict. */
2454
2455 #ifndef REG_OK_STRICT
2456 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2457 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2458 #else
2459 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2460 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2461 #endif
2462
2463 #define REG_OK_FOR_INDEX_P(X) 0
2464
2465 \f
2466 /* Maximum number of registers that can appear in a valid memory address. */
2467
2468 #define MAX_REGS_PER_ADDRESS 1
2469
2470 #ifdef REG_OK_STRICT
2471 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2472 { \
2473 if (mips_legitimate_address_p (MODE, X, 1)) \
2474 goto ADDR; \
2475 }
2476 #else
2477 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2478 { \
2479 if (mips_legitimate_address_p (MODE, X, 0)) \
2480 goto ADDR; \
2481 }
2482 #endif
2483
2484 /* Check for constness inline but use mips_legitimate_address_p
2485 to check whether a constant really is an address. */
2486
2487 #define CONSTANT_ADDRESS_P(X) \
2488 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2489
2490 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2491
2492 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2493 do { \
2494 if (mips_legitimize_address (&(X), MODE)) \
2495 goto WIN; \
2496 } while (0)
2497
2498
2499 /* A C statement or compound statement with a conditional `goto
2500 LABEL;' executed if memory address X (an RTX) can have different
2501 meanings depending on the machine mode of the memory reference it
2502 is used for.
2503
2504 Autoincrement and autodecrement addresses typically have
2505 mode-dependent effects because the amount of the increment or
2506 decrement is the size of the operand being addressed. Some
2507 machines have other mode-dependent addresses. Many RISC machines
2508 have no mode-dependent addresses.
2509
2510 You may assume that ADDR is a valid address for the machine. */
2511
2512 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2513
2514 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2515 'the start of the function that this code is output in'. */
2516
2517 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2518 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2519 asm_fprintf ((FILE), "%U%s", \
2520 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2521 else \
2522 asm_fprintf ((FILE), "%U%s", (NAME))
2523 \f
2524 /* Specify the machine mode that this machine uses
2525 for the index in the tablejump instruction.
2526 ??? Using HImode in mips16 mode can cause overflow. */
2527 #define CASE_VECTOR_MODE \
2528 (TARGET_MIPS16 ? HImode : ptr_mode)
2529
2530 /* Define as C expression which evaluates to nonzero if the tablejump
2531 instruction expects the table to contain offsets from the address of the
2532 table.
2533 Do not define this if the table should contain absolute addresses. */
2534 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
2535
2536 /* Define this as 1 if `char' should by default be signed; else as 0. */
2537 #ifndef DEFAULT_SIGNED_CHAR
2538 #define DEFAULT_SIGNED_CHAR 1
2539 #endif
2540
2541 /* Max number of bytes we can move from memory to memory
2542 in one reasonably fast instruction. */
2543 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2544 #define MAX_MOVE_MAX 8
2545
2546 /* Define this macro as a C expression which is nonzero if
2547 accessing less than a word of memory (i.e. a `char' or a
2548 `short') is no faster than accessing a word of memory, i.e., if
2549 such access require more than one instruction or if there is no
2550 difference in cost between byte and (aligned) word loads.
2551
2552 On RISC machines, it tends to generate better code to define
2553 this as 1, since it avoids making a QI or HI mode register. */
2554 #define SLOW_BYTE_ACCESS 1
2555
2556 /* Define this to be nonzero if shift instructions ignore all but the low-order
2557 few bits. */
2558 #define SHIFT_COUNT_TRUNCATED 1
2559
2560 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2561 is done just by pretending it is already truncated. */
2562 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2563 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2564
2565
2566 /* Specify the machine mode that pointers have.
2567 After generation of rtl, the compiler makes no further distinction
2568 between pointers and any other objects of this machine mode. */
2569
2570 #ifndef Pmode
2571 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2572 #endif
2573
2574 /* Give call MEMs SImode since it is the "most permissive" mode
2575 for both 32-bit and 64-bit targets. */
2576
2577 #define FUNCTION_MODE SImode
2578
2579 \f
2580 /* The cost of loading values from the constant pool. It should be
2581 larger than the cost of any constant we want to synthesize in-line. */
2582
2583 #define CONSTANT_POOL_COST COSTS_N_INSNS (8)
2584
2585 /* A C expression for the cost of moving data from a register in
2586 class FROM to one in class TO. The classes are expressed using
2587 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2588 the default; other values are interpreted relative to that.
2589
2590 It is not required that the cost always equal 2 when FROM is the
2591 same as TO; on some machines it is expensive to move between
2592 registers if they are not general registers.
2593
2594 If reload sees an insn consisting of a single `set' between two
2595 hard registers, and if `REGISTER_MOVE_COST' applied to their
2596 classes returns a value of 2, reload does not check to ensure
2597 that the constraints of the insn are met. Setting a cost of
2598 other than 2 will allow reload to verify that the constraints are
2599 met. You should do this if the `movM' pattern's constraints do
2600 not allow such copying. */
2601
2602 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2603 mips_register_move_cost (MODE, FROM, TO)
2604
2605 /* ??? Fix this to be right for the R8000. */
2606 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2607 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
2608 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2609
2610 /* Define if copies to/from condition code registers should be avoided.
2611
2612 This is needed for the MIPS because reload_outcc is not complete;
2613 it needs to handle cases where the source is a general or another
2614 condition code register. */
2615 #define AVOID_CCMODE_COPIES
2616
2617 /* A C expression for the cost of a branch instruction. A value of
2618 1 is the default; other values are interpreted relative to that. */
2619
2620 /* ??? Fix this to be right for the R8000. */
2621 #define BRANCH_COST \
2622 ((! TARGET_MIPS16 \
2623 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
2624 ? 2 : 1)
2625
2626 /* If defined, modifies the length assigned to instruction INSN as a
2627 function of the context in which it is used. LENGTH is an lvalue
2628 that contains the initially computed length of the insn and should
2629 be updated with the correct length of the insn. */
2630 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2631 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2632 \f
2633 /* Control the assembler format that we output. */
2634
2635 /* Output to assembler file text saying following lines
2636 may contain character constants, extra white space, comments, etc. */
2637
2638 #ifndef ASM_APP_ON
2639 #define ASM_APP_ON " #APP\n"
2640 #endif
2641
2642 /* Output to assembler file text saying following lines
2643 no longer contain unusual constructs. */
2644
2645 #ifndef ASM_APP_OFF
2646 #define ASM_APP_OFF " #NO_APP\n"
2647 #endif
2648
2649 #define REGISTER_NAMES \
2650 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2651 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2652 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2653 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2654 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2655 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2656 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2657 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2658 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2659 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2660 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2661 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2662 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2663 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2664 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2665 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2666 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2667 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2668 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2669 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2670 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2671 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31" }
2672
2673 /* List the "software" names for each register. Also list the numerical
2674 names for $fp and $sp. */
2675
2676 #define ADDITIONAL_REGISTER_NAMES \
2677 { \
2678 { "$29", 29 + GP_REG_FIRST }, \
2679 { "$30", 30 + GP_REG_FIRST }, \
2680 { "at", 1 + GP_REG_FIRST }, \
2681 { "v0", 2 + GP_REG_FIRST }, \
2682 { "v1", 3 + GP_REG_FIRST }, \
2683 { "a0", 4 + GP_REG_FIRST }, \
2684 { "a1", 5 + GP_REG_FIRST }, \
2685 { "a2", 6 + GP_REG_FIRST }, \
2686 { "a3", 7 + GP_REG_FIRST }, \
2687 { "t0", 8 + GP_REG_FIRST }, \
2688 { "t1", 9 + GP_REG_FIRST }, \
2689 { "t2", 10 + GP_REG_FIRST }, \
2690 { "t3", 11 + GP_REG_FIRST }, \
2691 { "t4", 12 + GP_REG_FIRST }, \
2692 { "t5", 13 + GP_REG_FIRST }, \
2693 { "t6", 14 + GP_REG_FIRST }, \
2694 { "t7", 15 + GP_REG_FIRST }, \
2695 { "s0", 16 + GP_REG_FIRST }, \
2696 { "s1", 17 + GP_REG_FIRST }, \
2697 { "s2", 18 + GP_REG_FIRST }, \
2698 { "s3", 19 + GP_REG_FIRST }, \
2699 { "s4", 20 + GP_REG_FIRST }, \
2700 { "s5", 21 + GP_REG_FIRST }, \
2701 { "s6", 22 + GP_REG_FIRST }, \
2702 { "s7", 23 + GP_REG_FIRST }, \
2703 { "t8", 24 + GP_REG_FIRST }, \
2704 { "t9", 25 + GP_REG_FIRST }, \
2705 { "k0", 26 + GP_REG_FIRST }, \
2706 { "k1", 27 + GP_REG_FIRST }, \
2707 { "gp", 28 + GP_REG_FIRST }, \
2708 { "sp", 29 + GP_REG_FIRST }, \
2709 { "fp", 30 + GP_REG_FIRST }, \
2710 { "ra", 31 + GP_REG_FIRST }, \
2711 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2712 }
2713
2714 /* This is meant to be redefined in the host dependent files. It is a
2715 set of alternative names and regnums for mips coprocessors. */
2716
2717 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2718
2719 /* A C compound statement to output to stdio stream STREAM the
2720 assembler syntax for an instruction operand X. X is an RTL
2721 expression.
2722
2723 CODE is a value that can be used to specify one of several ways
2724 of printing the operand. It is used when identical operands
2725 must be printed differently depending on the context. CODE
2726 comes from the `%' specification that was used to request
2727 printing of the operand. If the specification was just `%DIGIT'
2728 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2729 is the ASCII code for LTR.
2730
2731 If X is a register, this macro should print the register's name.
2732 The names can be found in an array `reg_names' whose type is
2733 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2734
2735 When the machine description has a specification `%PUNCT' (a `%'
2736 followed by a punctuation character), this macro is called with
2737 a null pointer for X and the punctuation character for CODE.
2738
2739 See mips.c for the MIPS specific codes. */
2740
2741 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2742
2743 /* A C expression which evaluates to true if CODE is a valid
2744 punctuation character for use in the `PRINT_OPERAND' macro. If
2745 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
2746 punctuation characters (except for the standard one, `%') are
2747 used in this way. */
2748
2749 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2750
2751 /* A C compound statement to output to stdio stream STREAM the
2752 assembler syntax for an instruction operand that is a memory
2753 reference whose address is ADDR. ADDR is an RTL expression. */
2754
2755 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2756
2757
2758 /* A C statement, to be executed after all slot-filler instructions
2759 have been output. If necessary, call `dbr_sequence_length' to
2760 determine the number of slots filled in a sequence (zero if not
2761 currently outputting a sequence), to decide how many no-ops to
2762 output, or whatever.
2763
2764 Don't define this macro if it has nothing to do, but it is
2765 helpful in reading assembly output if the extent of the delay
2766 sequence is made explicit (e.g. with white space).
2767
2768 Note that output routines for instructions with delay slots must
2769 be prepared to deal with not being output as part of a sequence
2770 (i.e. when the scheduling pass is not run, or when no slot
2771 fillers could be found.) The variable `final_sequence' is null
2772 when not processing a sequence, otherwise it contains the
2773 `sequence' rtx being output. */
2774
2775 #define DBR_OUTPUT_SEQEND(STREAM) \
2776 do \
2777 { \
2778 if (set_nomacro > 0 && --set_nomacro == 0) \
2779 fputs ("\t.set\tmacro\n", STREAM); \
2780 \
2781 if (set_noreorder > 0 && --set_noreorder == 0) \
2782 fputs ("\t.set\treorder\n", STREAM); \
2783 \
2784 fputs ("\n", STREAM); \
2785 } \
2786 while (0)
2787
2788
2789 /* How to tell the debugger about changes of source files. */
2790 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2791 mips_output_filename (STREAM, NAME)
2792
2793 /* mips-tfile does not understand .stabd directives. */
2794 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2795 dbxout_begin_stabn_sline (LINE); \
2796 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2797 } while (0)
2798
2799 /* Use .loc directives for SDB line numbers. */
2800 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2801 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2802
2803 /* The MIPS implementation uses some labels for its own purpose. The
2804 following lists what labels are created, and are all formed by the
2805 pattern $L[a-z].*. The machine independent portion of GCC creates
2806 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2807
2808 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2809 $Lb[0-9]+ Begin blocks for MIPS debug support
2810 $Lc[0-9]+ Label for use in s<xx> operation.
2811 $Le[0-9]+ End blocks for MIPS debug support */
2812
2813 #undef ASM_DECLARE_OBJECT_NAME
2814 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2815 mips_declare_object (STREAM, NAME, "", ":\n", 0)
2816
2817 /* Globalizing directive for a label. */
2818 #define GLOBAL_ASM_OP "\t.globl\t"
2819
2820 /* This says how to define a global common symbol. */
2821
2822 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2823
2824 /* This says how to define a local common symbol (i.e., not visible to
2825 linker). */
2826
2827 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2828 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2829 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2830 #endif
2831
2832 /* This says how to output an external. It would be possible not to
2833 output anything and let undefined symbol become external. However
2834 the assembler uses length information on externals to allocate in
2835 data/sdata bss/sbss, thereby saving exec time. */
2836
2837 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2838 mips_output_external(STREAM,DECL,NAME)
2839
2840 /* This is how to declare a function name. The actual work of
2841 emitting the label is moved to function_prologue, so that we can
2842 get the line number correctly emitted before the .ent directive,
2843 and after any .file directives. Define as empty so that the function
2844 is not declared before the .ent directive elsewhere. */
2845
2846 #undef ASM_DECLARE_FUNCTION_NAME
2847 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2848
2849 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2850 #define FUNCTION_NAME_ALREADY_DECLARED 0
2851 #endif
2852
2853 /* This is how to store into the string LABEL
2854 the symbol_ref name of an internal numbered label where
2855 PREFIX is the class of label and NUM is the number within the class.
2856 This is suitable for output with `assemble_name'. */
2857
2858 #undef ASM_GENERATE_INTERNAL_LABEL
2859 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2860 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2861
2862 /* This is how to output an element of a case-vector that is absolute. */
2863
2864 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2865 fprintf (STREAM, "\t%s\t%sL%d\n", \
2866 ptr_mode == DImode ? ".dword" : ".word", \
2867 LOCAL_LABEL_PREFIX, \
2868 VALUE)
2869
2870 /* This is how to output an element of a case-vector. We can make the
2871 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2872 is supported. */
2873
2874 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2875 do { \
2876 if (TARGET_MIPS16) \
2877 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2878 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2879 else if (TARGET_GPWORD) \
2880 fprintf (STREAM, "\t%s\t%sL%d\n", \
2881 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2882 LOCAL_LABEL_PREFIX, VALUE); \
2883 else \
2884 fprintf (STREAM, "\t%s\t%sL%d\n", \
2885 ptr_mode == DImode ? ".dword" : ".word", \
2886 LOCAL_LABEL_PREFIX, VALUE); \
2887 } while (0)
2888
2889 /* When generating mips16 code we want to put the jump table in the .text
2890 section. In all other cases, we want to put the jump table in the .rdata
2891 section. Unfortunately, we can't use JUMP_TABLES_IN_TEXT_SECTION, because
2892 it is not conditional. Instead, we use ASM_OUTPUT_CASE_LABEL to switch back
2893 to the .text section if appropriate. */
2894 #undef ASM_OUTPUT_CASE_LABEL
2895 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
2896 do { \
2897 if (TARGET_MIPS16) \
2898 function_section (current_function_decl); \
2899 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \
2900 } while (0)
2901
2902 /* This is how to output an assembler line
2903 that says to advance the location counter
2904 to a multiple of 2**LOG bytes. */
2905
2906 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2907 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2908
2909 /* This is how to output an assembler line to advance the location
2910 counter by SIZE bytes. */
2911
2912 #undef ASM_OUTPUT_SKIP
2913 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2914 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2915
2916 /* This is how to output a string. */
2917 #undef ASM_OUTPUT_ASCII
2918 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
2919 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
2920
2921 /* Output #ident as a in the read-only data section. */
2922 #undef ASM_OUTPUT_IDENT
2923 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2924 { \
2925 const char *p = STRING; \
2926 int size = strlen (p) + 1; \
2927 readonly_data_section (); \
2928 assemble_string (p, size); \
2929 }
2930 \f
2931 /* Default to -G 8 */
2932 #ifndef MIPS_DEFAULT_GVALUE
2933 #define MIPS_DEFAULT_GVALUE 8
2934 #endif
2935
2936 /* Define the strings to put out for each section in the object file. */
2937 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2938 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2939 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
2940
2941 #undef READONLY_DATA_SECTION_ASM_OP
2942 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2943 \f
2944 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2945 do \
2946 { \
2947 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
2948 TARGET_64BIT ? "dsubu" : "subu", \
2949 reg_names[STACK_POINTER_REGNUM], \
2950 reg_names[STACK_POINTER_REGNUM], \
2951 TARGET_64BIT ? "sd" : "sw", \
2952 reg_names[REGNO], \
2953 reg_names[STACK_POINTER_REGNUM]); \
2954 } \
2955 while (0)
2956
2957 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2958 do \
2959 { \
2960 if (! set_noreorder) \
2961 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2962 \
2963 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2964 TARGET_64BIT ? "ld" : "lw", \
2965 reg_names[REGNO], \
2966 reg_names[STACK_POINTER_REGNUM], \
2967 TARGET_64BIT ? "daddu" : "addu", \
2968 reg_names[STACK_POINTER_REGNUM], \
2969 reg_names[STACK_POINTER_REGNUM]); \
2970 \
2971 if (! set_noreorder) \
2972 fprintf (STREAM, "\t.set\treorder\n"); \
2973 } \
2974 while (0)
2975
2976 /* How to start an assembler comment.
2977 The leading space is important (the mips native assembler requires it). */
2978 #ifndef ASM_COMMENT_START
2979 #define ASM_COMMENT_START " #"
2980 #endif
2981 \f
2982 /* Default definitions for size_t and ptrdiff_t. We must override the
2983 definitions from ../svr4.h on mips-*-linux-gnu. */
2984
2985 #undef SIZE_TYPE
2986 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2987
2988 #undef PTRDIFF_TYPE
2989 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2990
2991 /* See mips_expand_prologue's use of loadgp for when this should be
2992 true. */
2993
2994 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS && !TARGET_OLDABI)
2995 \f
2996 #ifndef __mips16
2997 /* Since the bits of the _init and _fini function is spread across
2998 many object files, each potentially with its own GP, we must assume
2999 we need to load our GP. We don't preserve $gp or $ra, since each
3000 init/fini chunk is supposed to initialize $gp, and crti/crtn
3001 already take care of preserving $ra and, when appropriate, $gp. */
3002 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3003 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3004 asm (SECTION_OP "\n\
3005 .set noreorder\n\
3006 bal 1f\n\
3007 nop\n\
3008 1: .cpload $31\n\
3009 .set reorder\n\
3010 jal " USER_LABEL_PREFIX #FUNC "\n\
3011 " TEXT_SECTION_ASM_OP);
3012 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3013 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3014 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3015 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3016 asm (SECTION_OP "\n\
3017 .set noreorder\n\
3018 bal 1f\n\
3019 nop\n\
3020 1: .set reorder\n\
3021 .cpsetup $31, $2, 1b\n\
3022 jal " USER_LABEL_PREFIX #FUNC "\n\
3023 " TEXT_SECTION_ASM_OP);
3024 #endif
3025 #endif
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