gcc/config/riscv/riscv.h

   1 /* Definition of RISC-V target for GNU compiler.
   2    Copyright (C) 2011-2018 Free Software Foundation, Inc.
   3    Contributed by Andrew Waterman (andrew@sifive.com).
   4    Based on MIPS target for GNU compiler.
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 3, or (at your option)
  11 any later version.
  12
  13 GCC is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_RISCV_H
  23 #define GCC_RISCV_H
  24
  25 #include "config/riscv/riscv-opts.h"
  26
  27 /* Target CPU builtins.  */
  28 #define TARGET_CPU_CPP_BUILTINS() riscv_cpu_cpp_builtins (pfile)
  29
  30 /* Default target_flags if no switches are specified  */
  31
  32 #ifndef TARGET_DEFAULT
  33 #define TARGET_DEFAULT 0
  34 #endif
  35
  36 #ifndef RISCV_TUNE_STRING_DEFAULT
  37 #define RISCV_TUNE_STRING_DEFAULT "rocket"
  38 #endif
  39
  40 /* Support for a compile-time default CPU, et cetera.  The rules are:
  41    --with-arch is ignored if -march is specified.
  42    --with-abi is ignored if -mabi is specified.
  43    --with-tune is ignored if -mtune is specified.  */
  44 #define OPTION_DEFAULT_SPECS \
  45   {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
  46   {"arch", "%{!march=*:-march=%(VALUE)}" }, \
  47   {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
  48
  49 #ifdef IN_LIBGCC2
  50 #undef TARGET_64BIT
  51 /* Make this compile time constant for libgcc2 */
  52 #define TARGET_64BIT           (__riscv_xlen == 64)
  53 #endif /* IN_LIBGCC2 */
  54
  55 #undef ASM_SPEC
  56 #define ASM_SPEC "\
  57 %(subtarget_asm_debugging_spec) \
  58 %{" FPIE_OR_FPIC_SPEC ":-fpic} \
  59 %{march=*} \
  60 %{mabi=*} \
  61 %(subtarget_asm_spec)"
  62
  63 #define TARGET_DEFAULT_CMODEL CM_MEDLOW
  64
  65 #define LOCAL_LABEL_PREFIX      "."
  66 #define USER_LABEL_PREFIX       ""
  67
  68 /* Offsets recorded in opcodes are a multiple of this alignment factor.
  69    The default for this in 64-bit mode is 8, which causes problems with
  70    SFmode register saves.  */
  71 #define DWARF_CIE_DATA_ALIGNMENT -4
  72
  73 /* The mapping from gcc register number to DWARF 2 CFA column number.  */
  74 #define DWARF_FRAME_REGNUM(REGNO) \
  75   (GP_REG_P (REGNO) || FP_REG_P (REGNO) ? REGNO : INVALID_REGNUM)
  76
  77 /* The DWARF 2 CFA column which tracks the return address.  */
  78 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
  79 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
  80
  81 /* Describe how we implement __builtin_eh_return.  */
  82 #define EH_RETURN_DATA_REGNO(N) \
  83   ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
  84
  85 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, GP_ARG_FIRST + 4)
  86
  87 /* Target machine storage layout */
  88
  89 #define BITS_BIG_ENDIAN 0
  90 #define BYTES_BIG_ENDIAN 0
  91 #define WORDS_BIG_ENDIAN 0
  92
  93 #define MAX_BITS_PER_WORD 64
  94
  95 /* Width of a word, in units (bytes).  */
  96 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
  97 #ifndef IN_LIBGCC2
  98 #define MIN_UNITS_PER_WORD 4
  99 #endif
 100
 101 /* The `Q' extension is not yet supported.  */
 102 #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4)
 103
 104 /* The largest type that can be passed in floating-point registers.  */
 105 #define UNITS_PER_FP_ARG                                        \
 106   (riscv_abi == ABI_ILP32 || riscv_abi == ABI_LP64 ? 0 :        \
 107    riscv_abi == ABI_ILP32F || riscv_abi == ABI_LP64F ? 4 : 8)   \
 108
 109 /* Set the sizes of the core types.  */
 110 #define SHORT_TYPE_SIZE 16
 111 #define INT_TYPE_SIZE 32
 112 #define LONG_LONG_TYPE_SIZE 64
 113 #define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32)
 114 #define LONG_TYPE_SIZE POINTER_SIZE
 115
 116 #define FLOAT_TYPE_SIZE 32
 117 #define DOUBLE_TYPE_SIZE 64
 118 #define LONG_DOUBLE_TYPE_SIZE 128
 119
 120 /* Allocation boundary (in *bits*) for storing arguments in argument list.  */
 121 #define PARM_BOUNDARY BITS_PER_WORD
 122
 123 /* Allocation boundary (in *bits*) for the code of a function.  */
 124 #define FUNCTION_BOUNDARY (TARGET_RVC ? 16 : 32)
 125
 126 /* The smallest supported stack boundary the calling convention supports.  */
 127 #define MIN_STACK_BOUNDARY (2 * BITS_PER_WORD)
 128
 129 /* The ABI stack alignment.  */
 130 #define ABI_STACK_BOUNDARY 128
 131
 132 /* There is no point aligning anything to a rounder boundary than this.  */
 133 #define BIGGEST_ALIGNMENT STACK_BOUNDARY
 134
 135 /* The user-level ISA permits unaligned accesses, but they are not required
 136    of the privileged architecture.  */
 137 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
 138
 139 /* Define this if you wish to imitate the way many other C compilers
 140    handle alignment of bitfields and the structures that contain
 141    them.
 142
 143    The behavior is that the type written for a bit-field (`int',
 144    `short', or other integer type) imposes an alignment for the
 145    entire structure, as if the structure really did contain an
 146    ordinary field of that type.  In addition, the bit-field is placed
 147    within the structure so that it would fit within such a field,
 148    not crossing a boundary for it.
 149
 150    Thus, on most machines, a bit-field whose type is written as `int'
 151    would not cross a four-byte boundary, and would force four-byte
 152    alignment for the whole structure.  (The alignment used may not
 153    be four bytes; it is controlled by the other alignment
 154    parameters.)
 155
 156    If the macro is defined, its definition should be a C expression;
 157    a nonzero value for the expression enables this behavior.  */
 158
 159 #define PCC_BITFIELD_TYPE_MATTERS 1
 160
 161 /* An integer expression for the size in bits of the largest integer machine
 162    mode that should actually be used.  We allow pairs of registers.  */
 163 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
 164
 165 /* If defined, a C expression to compute the alignment for a static
 166    variable.  TYPE is the data type, and ALIGN is the alignment that
 167    the object would ordinarily have.  The value of this macro is used
 168    instead of that alignment to align the object.
 169
 170    If this macro is not defined, then ALIGN is used.
 171
 172    One use of this macro is to increase alignment of medium-size
 173    data to make it all fit in fewer cache lines.  Another is to
 174    cause character arrays to be word-aligned so that `strcpy' calls
 175    that copy constants to character arrays can be done inline.  */
 176
 177 #define DATA_ALIGNMENT(TYPE, ALIGN)                                     \
 178   ((((ALIGN) < BITS_PER_WORD)                                           \
 179     && (TREE_CODE (TYPE) == ARRAY_TYPE                                  \
 180         || TREE_CODE (TYPE) == UNION_TYPE                               \
 181         || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
 182
 183 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
 184    character arrays to be word-aligned so that `strcpy' calls that copy
 185    constants to character arrays can be done inline, and 'strcmp' can be
 186    optimised to use word loads. */
 187 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
 188   DATA_ALIGNMENT (TYPE, ALIGN)
 189
 190 /* Define if operations between registers always perform the operation
 191    on the full register even if a narrower mode is specified.  */
 192 #define WORD_REGISTER_OPERATIONS 1
 193
 194 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
 195    moves.  All other references are zero extended.  */
 196 #define LOAD_EXTEND_OP(MODE) \
 197   (TARGET_64BIT && (MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
 198
 199 /* Define this macro if it is advisable to hold scalars in registers
 200    in a wider mode than that declared by the program.  In such cases,
 201    the value is constrained to be within the bounds of the declared
 202    type, but kept valid in the wider mode.  The signedness of the
 203    extension may differ from that of the type.  */
 204
 205 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
 206   if (GET_MODE_CLASS (MODE) == MODE_INT         \
 207       && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
 208     {                                           \
 209       if ((MODE) == SImode)                     \
 210         (UNSIGNEDP) = 0;                        \
 211       (MODE) = word_mode;                       \
 212     }
 213
 214 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
 215    Extensions of pointers to word_mode must be signed.  */
 216 #define POINTERS_EXTEND_UNSIGNED false
 217
 218 /* Define if loading short immediate values into registers sign extends.  */
 219 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
 220
 221 /* Standard register usage.  */
 222
 223 /* Number of hardware registers.  We have:
 224
 225    - 32 integer registers
 226    - 32 floating point registers
 227    - 2 fake registers:
 228         - ARG_POINTER_REGNUM
 229         - FRAME_POINTER_REGNUM */
 230
 231 #define FIRST_PSEUDO_REGISTER 66
 232
 233 /* x0, sp, gp, and tp are fixed.  */
 234
 235 #define FIXED_REGISTERS                                                 \
 236 { /* General registers.  */                                             \
 237   1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 238   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 239   /* Floating-point registers.  */                                      \
 240   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 241   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 242   /* Others.  */                                                        \
 243   1, 1                                                                  \
 244 }
 245
 246 /* a0-a7, t0-t6, fa0-fa7, and ft0-ft11 are volatile across calls.
 247    The call RTLs themselves clobber ra.  */
 248
 249 #define CALL_USED_REGISTERS                                             \
 250 { /* General registers.  */                                             \
 251   1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1,                       \
 252   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,                       \
 253   /* Floating-point registers.  */                                      \
 254   1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1,                       \
 255   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,                       \
 256   /* Others.  */                                                        \
 257   1, 1                                                                  \
 258 }
 259
 260 /* Internal macros to classify an ISA register's type.  */
 261
 262 #define GP_REG_FIRST 0
 263 #define GP_REG_LAST  31
 264 #define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
 265
 266 #define FP_REG_FIRST 32
 267 #define FP_REG_LAST  63
 268 #define FP_REG_NUM   (FP_REG_LAST - FP_REG_FIRST + 1)
 269
 270 /* The DWARF 2 CFA column which tracks the return address from a
 271    signal handler context.  This means that to maintain backwards
 272    compatibility, no hard register can be assigned this column if it
 273    would need to be handled by the DWARF unwinder.  */
 274 #define DWARF_ALT_FRAME_RETURN_COLUMN 64
 275
 276 #define GP_REG_P(REGNO) \
 277   ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
 278 #define FP_REG_P(REGNO)  \
 279   ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
 280
 281 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
 282
 283 /* Use s0 as the frame pointer if it is so requested.  */
 284 #define HARD_FRAME_POINTER_REGNUM 8
 285 #define STACK_POINTER_REGNUM 2
 286 #define THREAD_POINTER_REGNUM 4
 287
 288 /* These two registers don't really exist: they get eliminated to either
 289    the stack or hard frame pointer.  */
 290 #define ARG_POINTER_REGNUM 64
 291 #define FRAME_POINTER_REGNUM 65
 292
 293 /* Register in which static-chain is passed to a function.  */
 294 #define STATIC_CHAIN_REGNUM (GP_TEMP_FIRST + 2)
 295
 296 /* Registers used as temporaries in prologue/epilogue code.
 297
 298    The prologue registers mustn't conflict with any
 299    incoming arguments, the static chain pointer, or the frame pointer.
 300    The epilogue temporary mustn't conflict with the return registers,
 301    the frame pointer, the EH stack adjustment, or the EH data registers. */
 302
 303 #define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST + 1)
 304 #define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP_REGNUM)
 305
 306 #define MCOUNT_NAME "_mcount"
 307
 308 #define NO_PROFILE_COUNTERS 1
 309
 310 /* Emit rtl for profiling.  Output assembler code to FILE
 311    to call "_mcount" for profiling a function entry.  */
 312 #define PROFILE_HOOK(LABEL)                                             \
 313   {                                                                     \
 314     rtx fun, ra;                                                        \
 315     ra = get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);          \
 316     fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME);                      \
 317     emit_library_call (fun, LCT_NORMAL, VOIDmode, ra, Pmode);           \
 318   }
 319
 320 /* All the work done in PROFILE_HOOK, but still required.  */
 321 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
 322
 323 /* Define this macro if it is as good or better to call a constant
 324    function address than to call an address kept in a register.  */
 325 #define NO_FUNCTION_CSE 1
 326
 327 /* Define the classes of registers for register constraints in the
 328    machine description.  Also define ranges of constants.
 329
 330    One of the classes must always be named ALL_REGS and include all hard regs.
 331    If there is more than one class, another class must be named NO_REGS
 332    and contain no registers.
 333
 334    The name GENERAL_REGS must be the name of a class (or an alias for
 335    another name such as ALL_REGS).  This is the class of registers
 336    that is allowed by "g" or "r" in a register constraint.
 337    Also, registers outside this class are allocated only when
 338    instructions express preferences for them.
 339
 340    The classes must be numbered in nondecreasing order; that is,
 341    a larger-numbered class must never be contained completely
 342    in a smaller-numbered class.
 343
 344    For any two classes, it is very desirable that there be another
 345    class that represents their union.  */
 346
 347 enum reg_class
 348 {
 349   NO_REGS,                      /* no registers in set */
 350   SIBCALL_REGS,                 /* registers used by indirect sibcalls */
 351   JALR_REGS,                    /* registers used by indirect calls */
 352   GR_REGS,                      /* integer registers */
 353   FP_REGS,                      /* floating-point registers */
 354   FRAME_REGS,                   /* arg pointer and frame pointer */
 355   ALL_REGS,                     /* all registers */
 356   LIM_REG_CLASSES               /* max value + 1 */
 357 };
 358
 359 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 360
 361 #define GENERAL_REGS GR_REGS
 362
 363 /* An initializer containing the names of the register classes as C
 364    string constants.  These names are used in writing some of the
 365    debugging dumps.  */
 366
 367 #define REG_CLASS_NAMES                                                 \
 368 {                                                                       \
 369   "NO_REGS",                                                            \
 370   "SIBCALL_REGS",                                                       \
 371   "JALR_REGS",                                                          \
 372   "GR_REGS",                                                            \
 373   "FP_REGS",                                                            \
 374   "FRAME_REGS",                                                         \
 375   "ALL_REGS"                                                            \
 376 }
 377
 378 /* An initializer containing the contents of the register classes,
 379    as integers which are bit masks.  The Nth integer specifies the
 380    contents of class N.  The way the integer MASK is interpreted is
 381    that register R is in the class if `MASK & (1 << R)' is 1.
 382
 383    When the machine has more than 32 registers, an integer does not
 384    suffice.  Then the integers are replaced by sub-initializers,
 385    braced groupings containing several integers.  Each
 386    sub-initializer must be suitable as an initializer for the type
 387    `HARD_REG_SET' which is defined in `hard-reg-set.h'.  */
 388
 389 #define REG_CLASS_CONTENTS                                              \
 390 {                                                                       \
 391   { 0x00000000, 0x00000000, 0x00000000 },       /* NO_REGS */           \
 392   { 0xf00000c0, 0x00000000, 0x00000000 },       /* SIBCALL_REGS */      \
 393   { 0xffffffc0, 0x00000000, 0x00000000 },       /* JALR_REGS */         \
 394   { 0xffffffff, 0x00000000, 0x00000000 },       /* GR_REGS */           \
 395   { 0x00000000, 0xffffffff, 0x00000000 },       /* FP_REGS */           \
 396   { 0x00000000, 0x00000000, 0x00000003 },       /* FRAME_REGS */        \
 397   { 0xffffffff, 0xffffffff, 0x00000003 }        /* ALL_REGS */          \
 398 }
 399
 400 /* A C expression whose value is a register class containing hard
 401    register REGNO.  In general there is more that one such class;
 402    choose a class which is "minimal", meaning that no smaller class
 403    also contains the register.  */
 404
 405 #define REGNO_REG_CLASS(REGNO) riscv_regno_to_class[ (REGNO) ]
 406
 407 /* A macro whose definition is the name of the class to which a
 408    valid base register must belong.  A base register is one used in
 409    an address which is the register value plus a displacement.  */
 410
 411 #define BASE_REG_CLASS GR_REGS
 412
 413 /* A macro whose definition is the name of the class to which a
 414    valid index register must belong.  An index register is one used
 415    in an address where its value is either multiplied by a scale
 416    factor or added to another register (as well as added to a
 417    displacement).  */
 418
 419 #define INDEX_REG_CLASS NO_REGS
 420
 421 /* We generally want to put call-clobbered registers ahead of
 422    call-saved ones.  (IRA expects this.)  */
 423
 424 #define REG_ALLOC_ORDER                                                 \
 425 { \
 426   /* Call-clobbered GPRs.  */                                           \
 427   15, 14, 13, 12, 11, 10, 16, 17, 6, 28, 29, 30, 31, 5, 7, 1,           \
 428   /* Call-saved GPRs.  */                                               \
 429   8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,                         \
 430   /* GPRs that can never be exposed to the register allocator.  */      \
 431   0, 2, 3, 4,                                                           \
 432   /* Call-clobbered FPRs.  */                                           \
 433   47, 46, 45, 44, 43, 42, 32, 33, 34, 35, 36, 37, 38, 39, 48, 49,       \
 434   60, 61, 62, 63,                                                       \
 435   /* Call-saved FPRs.  */                                               \
 436   40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,                       \
 437   /* None of the remaining classes have defined call-saved              \
 438      registers.  */                                                     \
 439   64, 65                                                                \
 440 }
 441
 442 /* True if VALUE is a signed 12-bit number.  */
 443
 444 #define SMALL_OPERAND(VALUE) \
 445   ((unsigned HOST_WIDE_INT) (VALUE) + IMM_REACH/2 < IMM_REACH)
 446
 447 /* True if VALUE can be loaded into a register using LUI.  */
 448
 449 #define LUI_OPERAND(VALUE)                                              \
 450   (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH)       \
 451    || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0)
 452
 453 /* Stack layout; function entry, exit and calling.  */
 454
 455 #define STACK_GROWS_DOWNWARD 1
 456
 457 #define FRAME_GROWS_DOWNWARD 1
 458
 459 #define RETURN_ADDR_RTX riscv_return_addr
 460
 461 #define ELIMINABLE_REGS                                                 \
 462 {{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
 463  { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},                    \
 464  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
 465  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}                            \
 466
 467 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 468   (OFFSET) = riscv_initial_elimination_offset (FROM, TO)
 469
 470 /* Allocate stack space for arguments at the beginning of each function.  */
 471 #define ACCUMULATE_OUTGOING_ARGS 1
 472
 473 /* The argument pointer always points to the first argument.  */
 474 #define FIRST_PARM_OFFSET(FNDECL) 0
 475
 476 #define REG_PARM_STACK_SPACE(FNDECL) 0
 477
 478 /* Define this if it is the responsibility of the caller to
 479    allocate the area reserved for arguments passed in registers.
 480    If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
 481    of this macro is to determine whether the space is included in
 482    `crtl->outgoing_args_size'.  */
 483 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
 484
 485 #define STACK_BOUNDARY riscv_stack_boundary
 486
 487 /* Symbolic macros for the registers used to return integer and floating
 488    point values.  */
 489
 490 #define GP_RETURN GP_ARG_FIRST
 491 #define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST)
 492
 493 #define MAX_ARGS_IN_REGISTERS 8
 494
 495 /* Symbolic macros for the first/last argument registers.  */
 496
 497 #define GP_ARG_FIRST (GP_REG_FIRST + 10)
 498 #define GP_ARG_LAST  (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
 499 #define GP_TEMP_FIRST (GP_REG_FIRST + 5)
 500 #define FP_ARG_FIRST (FP_REG_FIRST + 10)
 501 #define FP_ARG_LAST  (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
 502
 503 #define CALLEE_SAVED_REG_NUMBER(REGNO)                  \
 504   ((REGNO) >= 8 && (REGNO) <= 9 ? (REGNO) - 8 :         \
 505    (REGNO) >= 18 && (REGNO) <= 27 ? (REGNO) - 16 : -1)
 506
 507 #define LIBCALL_VALUE(MODE) \
 508   riscv_function_value (NULL_TREE, NULL_TREE, MODE)
 509
 510 #define FUNCTION_VALUE(VALTYPE, FUNC) \
 511   riscv_function_value (VALTYPE, FUNC, VOIDmode)
 512
 513 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
 514
 515 /* 1 if N is a possible register number for function argument passing.
 516    We have no FP argument registers when soft-float.  When FP registers
 517    are 32 bits, we can't directly reference the odd numbered ones.  */
 518
 519 /* Accept arguments in a0-a7, and in fa0-fa7 if permitted by the ABI.  */
 520 #define FUNCTION_ARG_REGNO_P(N)                                         \
 521   (IN_RANGE ((N), GP_ARG_FIRST, GP_ARG_LAST)                            \
 522    || (UNITS_PER_FP_ARG && IN_RANGE ((N), FP_ARG_FIRST, FP_ARG_LAST)))
 523
 524 typedef struct {
 525   /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */
 526   unsigned int num_gprs;
 527
 528   /* Number of floating-point registers used so far, likewise.  */
 529   unsigned int num_fprs;
 530 } CUMULATIVE_ARGS;
 531
 532 /* Initialize a variable CUM of type CUMULATIVE_ARGS
 533    for a call to a function whose data type is FNTYPE.
 534    For a library call, FNTYPE is 0.  */
 535
 536 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 537   memset (&(CUM), 0, sizeof (CUM))
 538
 539 #define EPILOGUE_USES(REGNO)    ((REGNO) == RETURN_ADDR_REGNUM)
 540
 541 /* Align based on stack boundary, which might have been set by the user.  */
 542 #define RISCV_STACK_ALIGN(LOC) \
 543   (((LOC) + ((STACK_BOUNDARY/8)-1)) & -(STACK_BOUNDARY/8))
 544
 545 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
 546    the stack pointer does not matter.  The value is tested only in
 547    functions that have frame pointers.
 548    No definition is equivalent to always zero.  */
 549
 550 #define EXIT_IGNORE_STACK 1
 551
 552
 553 /* Trampolines are a block of code followed by two pointers.  */
 554
 555 #define TRAMPOLINE_CODE_SIZE 16
 556 #define TRAMPOLINE_SIZE         \
 557   ((Pmode == SImode)            \
 558    ? TRAMPOLINE_CODE_SIZE       \
 559    : (TRAMPOLINE_CODE_SIZE + POINTER_SIZE * 2))
 560 #define TRAMPOLINE_ALIGNMENT POINTER_SIZE
 561
 562 /* Addressing modes, and classification of registers for them.  */
 563
 564 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
 565 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
 566   riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1)
 567
 568 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
 569    and check its validity for a certain class.
 570    We have two alternate definitions for each of them.
 571    The usual definition accepts all pseudo regs; the other rejects them all.
 572    The symbol REG_OK_STRICT causes the latter definition to be used.
 573
 574    Most source files want to accept pseudo regs in the hope that
 575    they will get allocated to the class that the insn wants them to be in.
 576    Some source files that are used after register allocation
 577    need to be strict.  */
 578
 579 #ifndef REG_OK_STRICT
 580 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 581   riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
 582 #else
 583 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 584   riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
 585 #endif
 586
 587 #define REG_OK_FOR_INDEX_P(X) 0
 588
 589 /* Maximum number of registers that can appear in a valid memory address.  */
 590
 591 #define MAX_REGS_PER_ADDRESS 1
 592
 593 #define CONSTANT_ADDRESS_P(X) \
 594   (CONSTANT_P (X) && memory_address_p (SImode, X))
 595
 596 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
 597    'the start of the function that this code is output in'.  */
 598
 599 #define ASM_OUTPUT_LABELREF(FILE,NAME)                                  \
 600   do {                                                                  \
 601     if (strcmp (NAME, "..CURRENT_FUNCTION") == 0)                       \
 602       asm_fprintf ((FILE), "%U%s",                                      \
 603                    XSTR (XEXP (DECL_RTL (current_function_decl),        \
 604                                0), 0));                                 \
 605     else                                                                \
 606       asm_fprintf ((FILE), "%U%s", (NAME));                             \
 607   } while (0)
 608
 609 #define JUMP_TABLES_IN_TEXT_SECTION 0
 610 #define CASE_VECTOR_MODE SImode
 611 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
 612
 613 /* The load-address macro is used for PC-relative addressing of symbols
 614    that bind locally.  Don't use it for symbols that should be addressed
 615    via the GOT.  Also, avoid it for CM_MEDLOW, where LUI addressing
 616    currently results in more opportunities for linker relaxation.  */
 617 #define USE_LOAD_ADDRESS_MACRO(sym)                                     \
 618   (!TARGET_EXPLICIT_RELOCS &&                                           \
 619    ((flag_pic                                                           \
 620      && ((SYMBOL_REF_P (sym) && SYMBOL_REF_LOCAL_P (sym))               \
 621          || ((GET_CODE (sym) == CONST)                                  \
 622              && SYMBOL_REF_P (XEXP (XEXP (sym, 0),0))                   \
 623              && SYMBOL_REF_LOCAL_P (XEXP (XEXP (sym, 0),0)))))          \
 624      || riscv_cmodel == CM_MEDANY))
 625
 626 /* Define this as 1 if `char' should by default be signed; else as 0.  */
 627 #define DEFAULT_SIGNED_CHAR 0
 628
 629 #define MOVE_MAX UNITS_PER_WORD
 630 #define MAX_MOVE_MAX 8
 631
 632 /* The SPARC port says:
 633    Nonzero if access to memory by bytes is slow and undesirable.
 634    For RISC chips, it means that access to memory by bytes is no
 635    better than access by words when possible, so grab a whole word
 636    and maybe make use of that.  */
 637 #define SLOW_BYTE_ACCESS 1
 638
 639 #define SHIFT_COUNT_TRUNCATED 1
 640
 641 /* Specify the machine mode that pointers have.
 642    After generation of rtl, the compiler makes no further distinction
 643    between pointers and any other objects of this machine mode.  */
 644
 645 #define Pmode word_mode
 646
 647 /* Give call MEMs SImode since it is the "most permissive" mode
 648    for both 32-bit and 64-bit targets.  */
 649
 650 #define FUNCTION_MODE SImode
 651
 652 /* A C expression for the cost of a branch instruction.  A value of 2
 653    seems to minimize code size.  */
 654
 655 #define BRANCH_COST(speed_p, predictable_p) \
 656   ((!(speed_p) || (predictable_p)) ? 2 : riscv_branch_cost)
 657
 658 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
 659
 660 /* Control the assembler format that we output.  */
 661
 662 /* Output to assembler file text saying following lines
 663    may contain character constants, extra white space, comments, etc.  */
 664
 665 #ifndef ASM_APP_ON
 666 #define ASM_APP_ON " #APP\n"
 667 #endif
 668
 669 /* Output to assembler file text saying following lines
 670    no longer contain unusual constructs.  */
 671
 672 #ifndef ASM_APP_OFF
 673 #define ASM_APP_OFF " #NO_APP\n"
 674 #endif
 675
 676 #define REGISTER_NAMES                                          \
 677 { "zero","ra",  "sp",  "gp",  "tp",  "t0",  "t1",  "t2",        \
 678   "s0",  "s1",  "a0",  "a1",  "a2",  "a3",  "a4",  "a5",        \
 679   "a6",  "a7",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",        \
 680   "s8",  "s9",  "s10", "s11", "t3",  "t4",  "t5",  "t6",        \
 681   "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",       \
 682   "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",       \
 683   "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",       \
 684   "fs8", "fs9", "fs10","fs11","ft8", "ft9", "ft10","ft11",      \
 685   "arg", "frame", }
 686
 687 #define ADDITIONAL_REGISTER_NAMES                                       \
 688 {                                                                       \
 689   { "x0",        0 + GP_REG_FIRST },                                    \
 690   { "x1",        1 + GP_REG_FIRST },                                    \
 691   { "x2",        2 + GP_REG_FIRST },                                    \
 692   { "x3",        3 + GP_REG_FIRST },                                    \
 693   { "x4",        4 + GP_REG_FIRST },                                    \
 694   { "x5",        5 + GP_REG_FIRST },                                    \
 695   { "x6",        6 + GP_REG_FIRST },                                    \
 696   { "x7",        7 + GP_REG_FIRST },                                    \
 697   { "x8",        8 + GP_REG_FIRST },                                    \
 698   { "x9",        9 + GP_REG_FIRST },                                    \
 699   { "x10",      10 + GP_REG_FIRST },                                    \
 700   { "x11",      11 + GP_REG_FIRST },                                    \
 701   { "x12",      12 + GP_REG_FIRST },                                    \
 702   { "x13",      13 + GP_REG_FIRST },                                    \
 703   { "x14",      14 + GP_REG_FIRST },                                    \
 704   { "x15",      15 + GP_REG_FIRST },                                    \
 705   { "x16",      16 + GP_REG_FIRST },                                    \
 706   { "x17",      17 + GP_REG_FIRST },                                    \
 707   { "x18",      18 + GP_REG_FIRST },                                    \
 708   { "x19",      19 + GP_REG_FIRST },                                    \
 709   { "x20",      20 + GP_REG_FIRST },                                    \
 710   { "x21",      21 + GP_REG_FIRST },                                    \
 711   { "x22",      22 + GP_REG_FIRST },                                    \
 712   { "x23",      23 + GP_REG_FIRST },                                    \
 713   { "x24",      24 + GP_REG_FIRST },                                    \
 714   { "x25",      25 + GP_REG_FIRST },                                    \
 715   { "x26",      26 + GP_REG_FIRST },                                    \
 716   { "x27",      27 + GP_REG_FIRST },                                    \
 717   { "x28",      28 + GP_REG_FIRST },                                    \
 718   { "x29",      29 + GP_REG_FIRST },                                    \
 719   { "x30",      30 + GP_REG_FIRST },                                    \
 720   { "x31",      31 + GP_REG_FIRST },                                    \
 721   { "f0",        0 + FP_REG_FIRST },                                    \
 722   { "f1",        1 + FP_REG_FIRST },                                    \
 723   { "f2",        2 + FP_REG_FIRST },                                    \
 724   { "f3",        3 + FP_REG_FIRST },                                    \
 725   { "f4",        4 + FP_REG_FIRST },                                    \
 726   { "f5",        5 + FP_REG_FIRST },                                    \
 727   { "f6",        6 + FP_REG_FIRST },                                    \
 728   { "f7",        7 + FP_REG_FIRST },                                    \
 729   { "f8",        8 + FP_REG_FIRST },                                    \
 730   { "f9",        9 + FP_REG_FIRST },                                    \
 731   { "f10",      10 + FP_REG_FIRST },                                    \
 732   { "f11",      11 + FP_REG_FIRST },                                    \
 733   { "f12",      12 + FP_REG_FIRST },                                    \
 734   { "f13",      13 + FP_REG_FIRST },                                    \
 735   { "f14",      14 + FP_REG_FIRST },                                    \
 736   { "f15",      15 + FP_REG_FIRST },                                    \
 737   { "f16",      16 + FP_REG_FIRST },                                    \
 738   { "f17",      17 + FP_REG_FIRST },                                    \
 739   { "f18",      18 + FP_REG_FIRST },                                    \
 740   { "f19",      19 + FP_REG_FIRST },                                    \
 741   { "f20",      20 + FP_REG_FIRST },                                    \
 742   { "f21",      21 + FP_REG_FIRST },                                    \
 743   { "f22",      22 + FP_REG_FIRST },                                    \
 744   { "f23",      23 + FP_REG_FIRST },                                    \
 745   { "f24",      24 + FP_REG_FIRST },                                    \
 746   { "f25",      25 + FP_REG_FIRST },                                    \
 747   { "f26",      26 + FP_REG_FIRST },                                    \
 748   { "f27",      27 + FP_REG_FIRST },                                    \
 749   { "f28",      28 + FP_REG_FIRST },                                    \
 750   { "f29",      29 + FP_REG_FIRST },                                    \
 751   { "f30",      30 + FP_REG_FIRST },                                    \
 752   { "f31",      31 + FP_REG_FIRST },                                    \
 753 }
 754
 755 /* Globalizing directive for a label.  */
 756 #define GLOBAL_ASM_OP "\t.globl\t"
 757
 758 /* This is how to store into the string LABEL
 759    the symbol_ref name of an internal numbered label where
 760    PREFIX is the class of label and NUM is the number within the class.
 761    This is suitable for output with `assemble_name'.  */
 762
 763 #undef ASM_GENERATE_INTERNAL_LABEL
 764 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)                   \
 765   sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
 766
 767 /* This is how to output an element of a case-vector that is absolute.  */
 768
 769 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)                          \
 770   fprintf (STREAM, "\t.word\t%sL%d\n", LOCAL_LABEL_PREFIX, VALUE)
 771
 772 /* This is how to output an element of a PIC case-vector. */
 773
 774 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)              \
 775   fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n",                            \
 776            LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL)
 777
 778 /* This is how to output an assembler line
 779    that says to advance the location counter
 780    to a multiple of 2**LOG bytes.  */
 781
 782 #define ASM_OUTPUT_ALIGN(STREAM,LOG)                                    \
 783   fprintf (STREAM, "\t.align\t%d\n", (LOG))
 784
 785 /* Define the strings to put out for each section in the object file.  */
 786 #define TEXT_SECTION_ASM_OP     "\t.text"       /* instructions */
 787 #define DATA_SECTION_ASM_OP     "\t.data"       /* large data */
 788 #define READONLY_DATA_SECTION_ASM_OP    "\t.section\t.rodata"
 789 #define BSS_SECTION_ASM_OP      "\t.bss"
 790 #define SBSS_SECTION_ASM_OP     "\t.section\t.sbss,\"aw\",@nobits"
 791 #define SDATA_SECTION_ASM_OP    "\t.section\t.sdata,\"aw\",@progbits"
 792
 793 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO)                               \
 794 do                                                                      \
 795   {                                                                     \
 796     fprintf (STREAM, "\taddi\t%s,%s,-8\n\t%s\t%s,0(%s)\n",              \
 797              reg_names[STACK_POINTER_REGNUM],                           \
 798              reg_names[STACK_POINTER_REGNUM],                           \
 799              TARGET_64BIT ? "sd" : "sw",                                \
 800              reg_names[REGNO],                                          \
 801              reg_names[STACK_POINTER_REGNUM]);                          \
 802   }                                                                     \
 803 while (0)
 804
 805 #define ASM_OUTPUT_REG_POP(STREAM,REGNO)                                \
 806 do                                                                      \
 807   {                                                                     \
 808     fprintf (STREAM, "\t%s\t%s,0(%s)\n\taddi\t%s,%s,8\n",               \
 809              TARGET_64BIT ? "ld" : "lw",                                \
 810              reg_names[REGNO],                                          \
 811              reg_names[STACK_POINTER_REGNUM],                           \
 812              reg_names[STACK_POINTER_REGNUM],                           \
 813              reg_names[STACK_POINTER_REGNUM]);                          \
 814   }                                                                     \
 815 while (0)
 816
 817 #define ASM_COMMENT_START "#"
 818
 819 #undef SIZE_TYPE
 820 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
 821
 822 #undef PTRDIFF_TYPE
 823 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
 824
 825 /* The maximum number of bytes copied by one iteration of a movmemsi loop.  */
 826
 827 #define RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER (UNITS_PER_WORD * 4)
 828
 829 /* The maximum number of bytes that can be copied by a straight-line
 830    movmemsi implementation.  */
 831
 832 #define RISCV_MAX_MOVE_BYTES_STRAIGHT (RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER * 3)
 833
 834 /* If a memory-to-memory move would take MOVE_RATIO or more simple
 835    move-instruction pairs, we will do a movmem or libcall instead.
 836    Do not use move_by_pieces at all when strict alignment is not
 837    in effect but the target has slow unaligned accesses; in this
 838    case, movmem or libcall is more efficient.  */
 839
 840 #define MOVE_RATIO(speed)                                               \
 841   (!STRICT_ALIGNMENT && riscv_slow_unaligned_access_p ? 1 :             \
 842    (speed) ? RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD :      \
 843    CLEAR_RATIO (speed) / 2)
 844
 845 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
 846    of the length of a memset call, but use the default otherwise.  */
 847
 848 #define CLEAR_RATIO(speed) ((speed) ? 16 : 6)
 849
 850 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
 851    optimizing for size adjust the ratio to account for the overhead of
 852    loading the constant and replicating it across the word.  */
 853
 854 #define SET_RATIO(speed) (CLEAR_RATIO (speed) - ((speed) ? 0 : 2))
 855
 856 #ifndef USED_FOR_TARGET
 857 extern const enum reg_class riscv_regno_to_class[];
 858 extern bool riscv_slow_unaligned_access_p;
 859 extern unsigned riscv_stack_boundary;
 860 #endif
 861
 862 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
 863   (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4)
 864
 865 #define XLEN_SPEC \
 866   "%{march=rv32*:32}" \
 867   "%{march=rv64*:64}" \
 868
 869 #define ABI_SPEC \
 870   "%{mabi=ilp32:ilp32}" \
 871   "%{mabi=ilp32f:ilp32f}" \
 872   "%{mabi=ilp32d:ilp32d}" \
 873   "%{mabi=lp64:lp64}" \
 874   "%{mabi=lp64f:lp64f}" \
 875   "%{mabi=lp64d:lp64d}" \
 876
 877 #define STARTFILE_PREFIX_SPEC                   \
 878    "/lib" XLEN_SPEC "/" ABI_SPEC "/ "           \
 879    "/usr/lib" XLEN_SPEC "/" ABI_SPEC "/ "       \
 880    "/lib/ "                                     \
 881    "/usr/lib/ "
 882
 883 /* ISA constants needed for code generation.  */
 884 #define OPCODE_LW    0x2003
 885 #define OPCODE_LD    0x3003
 886 #define OPCODE_AUIPC 0x17
 887 #define OPCODE_JALR  0x67
 888 #define OPCODE_LUI   0x37
 889 #define OPCODE_ADDI  0x13
 890 #define SHIFT_RD  7
 891 #define SHIFT_RS1 15
 892 #define SHIFT_IMM 20
 893 #define IMM_BITS 12
 894 #define C_SxSP_BITS 6
 895
 896 #define IMM_REACH (1LL << IMM_BITS)
 897 #define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH/2)) & ~(IMM_REACH-1))
 898 #define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE))
 899
 900 #define SWSP_REACH (4LL << C_SxSP_BITS)
 901 #define SDSP_REACH (8LL << C_SxSP_BITS)
 902
 903 #endif /* ! GCC_RISCV_H */