gcc/config/riscv/riscv.h

   1 /* Definition of RISC-V target for GNU compiler.
   2    Copyright (C) 2011-2018 Free Software Foundation, Inc.
   3    Contributed by Andrew Waterman (andrew@sifive.com).
   4    Based on MIPS target for GNU compiler.
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 3, or (at your option)
  11 any later version.
  12
  13 GCC is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_RISCV_H
  23 #define GCC_RISCV_H
  24
  25 #include "config/riscv/riscv-opts.h"
  26
  27 /* Target CPU builtins.  */
  28 #define TARGET_CPU_CPP_BUILTINS() riscv_cpu_cpp_builtins (pfile)
  29
  30 /* Target CPU versions for D.  */
  31 #define TARGET_D_CPU_VERSIONS riscv_d_target_versions
  32
  33 /* Default target_flags if no switches are specified  */
  34
  35 #ifndef TARGET_DEFAULT
  36 #define TARGET_DEFAULT 0
  37 #endif
  38
  39 #ifndef RISCV_TUNE_STRING_DEFAULT
  40 #define RISCV_TUNE_STRING_DEFAULT "rocket"
  41 #endif
  42
  43 /* Support for a compile-time default CPU, et cetera.  The rules are:
  44    --with-arch is ignored if -march is specified.
  45    --with-abi is ignored if -mabi is specified.
  46    --with-tune is ignored if -mtune is specified.  */
  47 #define OPTION_DEFAULT_SPECS \
  48   {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
  49   {"arch", "%{!march=*:-march=%(VALUE)}" }, \
  50   {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
  51
  52 #ifdef IN_LIBGCC2
  53 #undef TARGET_64BIT
  54 /* Make this compile time constant for libgcc2 */
  55 #define TARGET_64BIT           (__riscv_xlen == 64)
  56 #endif /* IN_LIBGCC2 */
  57
  58 #undef ASM_SPEC
  59 #define ASM_SPEC "\
  60 %(subtarget_asm_debugging_spec) \
  61 %{" FPIE_OR_FPIC_SPEC ":-fpic} \
  62 %{march=*} \
  63 %{mabi=*} \
  64 %(subtarget_asm_spec)"
  65
  66 #define TARGET_DEFAULT_CMODEL CM_MEDLOW
  67
  68 #define LOCAL_LABEL_PREFIX      "."
  69 #define USER_LABEL_PREFIX       ""
  70
  71 /* Offsets recorded in opcodes are a multiple of this alignment factor.
  72    The default for this in 64-bit mode is 8, which causes problems with
  73    SFmode register saves.  */
  74 #define DWARF_CIE_DATA_ALIGNMENT -4
  75
  76 /* The mapping from gcc register number to DWARF 2 CFA column number.  */
  77 #define DWARF_FRAME_REGNUM(REGNO) \
  78   (GP_REG_P (REGNO) || FP_REG_P (REGNO) ? REGNO : INVALID_REGNUM)
  79
  80 /* The DWARF 2 CFA column which tracks the return address.  */
  81 #define DWARF_FRAME_RETURN_COLUMN RETURN_ADDR_REGNUM
  82 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, RETURN_ADDR_REGNUM)
  83
  84 /* Describe how we implement __builtin_eh_return.  */
  85 #define EH_RETURN_DATA_REGNO(N) \
  86   ((N) < 4 ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
  87
  88 #define EH_RETURN_STACKADJ_RTX  gen_rtx_REG (Pmode, GP_ARG_FIRST + 4)
  89
  90 /* Target machine storage layout */
  91
  92 #define BITS_BIG_ENDIAN 0
  93 #define BYTES_BIG_ENDIAN 0
  94 #define WORDS_BIG_ENDIAN 0
  95
  96 #define MAX_BITS_PER_WORD 64
  97
  98 /* Width of a word, in units (bytes).  */
  99 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
 100 #ifndef IN_LIBGCC2
 101 #define MIN_UNITS_PER_WORD 4
 102 #endif
 103
 104 /* The `Q' extension is not yet supported.  */
 105 #define UNITS_PER_FP_REG (TARGET_DOUBLE_FLOAT ? 8 : 4)
 106
 107 /* The largest type that can be passed in floating-point registers.  */
 108 #define UNITS_PER_FP_ARG                                                \
 109   ((riscv_abi == ABI_ILP32 || riscv_abi == ABI_ILP32E                   \
 110     || riscv_abi == ABI_LP64)                                           \
 111    ? 0                                                                  \
 112    : ((riscv_abi == ABI_ILP32F || riscv_abi == ABI_LP64F) ? 4 : 8))
 113
 114 /* Set the sizes of the core types.  */
 115 #define SHORT_TYPE_SIZE 16
 116 #define INT_TYPE_SIZE 32
 117 #define LONG_LONG_TYPE_SIZE 64
 118 #define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32)
 119 #define LONG_TYPE_SIZE POINTER_SIZE
 120
 121 #define FLOAT_TYPE_SIZE 32
 122 #define DOUBLE_TYPE_SIZE 64
 123 #define LONG_DOUBLE_TYPE_SIZE 128
 124
 125 /* Allocation boundary (in *bits*) for storing arguments in argument list.  */
 126 #define PARM_BOUNDARY BITS_PER_WORD
 127
 128 /* Allocation boundary (in *bits*) for the code of a function.  */
 129 #define FUNCTION_BOUNDARY (TARGET_RVC ? 16 : 32)
 130
 131 /* The smallest supported stack boundary the calling convention supports.  */
 132 #define STACK_BOUNDARY \
 133   (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 2 * BITS_PER_WORD)
 134
 135 /* The ABI stack alignment.  */
 136 #define ABI_STACK_BOUNDARY (riscv_abi == ABI_ILP32E ? BITS_PER_WORD : 128)
 137
 138 /* There is no point aligning anything to a rounder boundary than this.  */
 139 #define BIGGEST_ALIGNMENT 128
 140
 141 /* The user-level ISA permits unaligned accesses, but they are not required
 142    of the privileged architecture.  */
 143 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN
 144
 145 /* Define this if you wish to imitate the way many other C compilers
 146    handle alignment of bitfields and the structures that contain
 147    them.
 148
 149    The behavior is that the type written for a bit-field (`int',
 150    `short', or other integer type) imposes an alignment for the
 151    entire structure, as if the structure really did contain an
 152    ordinary field of that type.  In addition, the bit-field is placed
 153    within the structure so that it would fit within such a field,
 154    not crossing a boundary for it.
 155
 156    Thus, on most machines, a bit-field whose type is written as `int'
 157    would not cross a four-byte boundary, and would force four-byte
 158    alignment for the whole structure.  (The alignment used may not
 159    be four bytes; it is controlled by the other alignment
 160    parameters.)
 161
 162    If the macro is defined, its definition should be a C expression;
 163    a nonzero value for the expression enables this behavior.  */
 164
 165 #define PCC_BITFIELD_TYPE_MATTERS 1
 166
 167 /* An integer expression for the size in bits of the largest integer machine
 168    mode that should actually be used.  We allow pairs of registers.  */
 169 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
 170
 171 /* If defined, a C expression to compute the alignment for a static
 172    variable.  TYPE is the data type, and ALIGN is the alignment that
 173    the object would ordinarily have.  The value of this macro is used
 174    instead of that alignment to align the object.
 175
 176    If this macro is not defined, then ALIGN is used.
 177
 178    One use of this macro is to increase alignment of medium-size
 179    data to make it all fit in fewer cache lines.  Another is to
 180    cause character arrays to be word-aligned so that `strcpy' calls
 181    that copy constants to character arrays can be done inline.  */
 182
 183 #define DATA_ALIGNMENT(TYPE, ALIGN)                                     \
 184   ((((ALIGN) < BITS_PER_WORD)                                           \
 185     && (TREE_CODE (TYPE) == ARRAY_TYPE                                  \
 186         || TREE_CODE (TYPE) == UNION_TYPE                               \
 187         || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
 188
 189 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
 190    character arrays to be word-aligned so that `strcpy' calls that copy
 191    constants to character arrays can be done inline, and 'strcmp' can be
 192    optimised to use word loads. */
 193 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
 194   DATA_ALIGNMENT (TYPE, ALIGN)
 195
 196 /* Define if operations between registers always perform the operation
 197    on the full register even if a narrower mode is specified.  */
 198 #define WORD_REGISTER_OPERATIONS 1
 199
 200 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
 201    moves.  All other references are zero extended.  */
 202 #define LOAD_EXTEND_OP(MODE) \
 203   (TARGET_64BIT && (MODE) == SImode ? SIGN_EXTEND : ZERO_EXTEND)
 204
 205 /* Define this macro if it is advisable to hold scalars in registers
 206    in a wider mode than that declared by the program.  In such cases,
 207    the value is constrained to be within the bounds of the declared
 208    type, but kept valid in the wider mode.  The signedness of the
 209    extension may differ from that of the type.  */
 210
 211 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE)     \
 212   if (GET_MODE_CLASS (MODE) == MODE_INT         \
 213       && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
 214     {                                           \
 215       if ((MODE) == SImode)                     \
 216         (UNSIGNEDP) = 0;                        \
 217       (MODE) = word_mode;                       \
 218     }
 219
 220 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
 221    Extensions of pointers to word_mode must be signed.  */
 222 #define POINTERS_EXTEND_UNSIGNED false
 223
 224 /* Define if loading short immediate values into registers sign extends.  */
 225 #define SHORT_IMMEDIATES_SIGN_EXTEND 1
 226
 227 /* Standard register usage.  */
 228
 229 /* Number of hardware registers.  We have:
 230
 231    - 32 integer registers
 232    - 32 floating point registers
 233    - 2 fake registers:
 234         - ARG_POINTER_REGNUM
 235         - FRAME_POINTER_REGNUM */
 236
 237 #define FIRST_PSEUDO_REGISTER 66
 238
 239 /* x0, sp, gp, and tp are fixed.  */
 240
 241 #define FIXED_REGISTERS                                                 \
 242 { /* General registers.  */                                             \
 243   1, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 244   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 245   /* Floating-point registers.  */                                      \
 246   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 247   0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,                       \
 248   /* Others.  */                                                        \
 249   1, 1                                                                  \
 250 }
 251
 252 /* a0-a7, t0-t6, fa0-fa7, and ft0-ft11 are volatile across calls.
 253    The call RTLs themselves clobber ra.  */
 254
 255 #define CALL_USED_REGISTERS                                             \
 256 { /* General registers.  */                                             \
 257   1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1,                       \
 258   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,                       \
 259   /* Floating-point registers.  */                                      \
 260   1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1,                       \
 261   1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,                       \
 262   /* Others.  */                                                        \
 263   1, 1                                                                  \
 264 }
 265
 266 /* Internal macros to classify an ISA register's type.  */
 267
 268 #define GP_REG_FIRST 0
 269 #define GP_REG_LAST  (TARGET_RVE ? 15 : 31)
 270 #define GP_REG_NUM   (GP_REG_LAST - GP_REG_FIRST + 1)
 271
 272 #define FP_REG_FIRST 32
 273 #define FP_REG_LAST  63
 274 #define FP_REG_NUM   (FP_REG_LAST - FP_REG_FIRST + 1)
 275
 276 /* The DWARF 2 CFA column which tracks the return address from a
 277    signal handler context.  This means that to maintain backwards
 278    compatibility, no hard register can be assigned this column if it
 279    would need to be handled by the DWARF unwinder.  */
 280 #define DWARF_ALT_FRAME_RETURN_COLUMN 64
 281
 282 #define GP_REG_P(REGNO) \
 283   ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
 284 #define FP_REG_P(REGNO)  \
 285   ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
 286
 287 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
 288
 289 /* Use s0 as the frame pointer if it is so requested.  */
 290 #define HARD_FRAME_POINTER_REGNUM 8
 291 #define STACK_POINTER_REGNUM 2
 292 #define THREAD_POINTER_REGNUM 4
 293
 294 /* These two registers don't really exist: they get eliminated to either
 295    the stack or hard frame pointer.  */
 296 #define ARG_POINTER_REGNUM 64
 297 #define FRAME_POINTER_REGNUM 65
 298
 299 /* Register in which static-chain is passed to a function.  */
 300 #define STATIC_CHAIN_REGNUM (GP_TEMP_FIRST + 2)
 301
 302 /* Registers used as temporaries in prologue/epilogue code.
 303
 304    The prologue registers mustn't conflict with any
 305    incoming arguments, the static chain pointer, or the frame pointer.
 306    The epilogue temporary mustn't conflict with the return registers,
 307    the frame pointer, the EH stack adjustment, or the EH data registers. */
 308
 309 #define RISCV_PROLOGUE_TEMP_REGNUM (GP_TEMP_FIRST + 1)
 310 #define RISCV_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, RISCV_PROLOGUE_TEMP_REGNUM)
 311
 312 #define MCOUNT_NAME "_mcount"
 313
 314 #define NO_PROFILE_COUNTERS 1
 315
 316 /* Emit rtl for profiling.  Output assembler code to FILE
 317    to call "_mcount" for profiling a function entry.  */
 318 #define PROFILE_HOOK(LABEL)                                             \
 319   {                                                                     \
 320     rtx fun, ra;                                                        \
 321     ra = get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);          \
 322     fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME);                      \
 323     emit_library_call (fun, LCT_NORMAL, VOIDmode, ra, Pmode);           \
 324   }
 325
 326 /* All the work done in PROFILE_HOOK, but still required.  */
 327 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0)
 328
 329 /* Define this macro if it is as good or better to call a constant
 330    function address than to call an address kept in a register.  */
 331 #define NO_FUNCTION_CSE 1
 332
 333 /* Define the classes of registers for register constraints in the
 334    machine description.  Also define ranges of constants.
 335
 336    One of the classes must always be named ALL_REGS and include all hard regs.
 337    If there is more than one class, another class must be named NO_REGS
 338    and contain no registers.
 339
 340    The name GENERAL_REGS must be the name of a class (or an alias for
 341    another name such as ALL_REGS).  This is the class of registers
 342    that is allowed by "g" or "r" in a register constraint.
 343    Also, registers outside this class are allocated only when
 344    instructions express preferences for them.
 345
 346    The classes must be numbered in nondecreasing order; that is,
 347    a larger-numbered class must never be contained completely
 348    in a smaller-numbered class.
 349
 350    For any two classes, it is very desirable that there be another
 351    class that represents their union.  */
 352
 353 enum reg_class
 354 {
 355   NO_REGS,                      /* no registers in set */
 356   SIBCALL_REGS,                 /* registers used by indirect sibcalls */
 357   JALR_REGS,                    /* registers used by indirect calls */
 358   GR_REGS,                      /* integer registers */
 359   FP_REGS,                      /* floating-point registers */
 360   FRAME_REGS,                   /* arg pointer and frame pointer */
 361   ALL_REGS,                     /* all registers */
 362   LIM_REG_CLASSES               /* max value + 1 */
 363 };
 364
 365 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 366
 367 #define GENERAL_REGS GR_REGS
 368
 369 /* An initializer containing the names of the register classes as C
 370    string constants.  These names are used in writing some of the
 371    debugging dumps.  */
 372
 373 #define REG_CLASS_NAMES                                                 \
 374 {                                                                       \
 375   "NO_REGS",                                                            \
 376   "SIBCALL_REGS",                                                       \
 377   "JALR_REGS",                                                          \
 378   "GR_REGS",                                                            \
 379   "FP_REGS",                                                            \
 380   "FRAME_REGS",                                                         \
 381   "ALL_REGS"                                                            \
 382 }
 383
 384 /* An initializer containing the contents of the register classes,
 385    as integers which are bit masks.  The Nth integer specifies the
 386    contents of class N.  The way the integer MASK is interpreted is
 387    that register R is in the class if `MASK & (1 << R)' is 1.
 388
 389    When the machine has more than 32 registers, an integer does not
 390    suffice.  Then the integers are replaced by sub-initializers,
 391    braced groupings containing several integers.  Each
 392    sub-initializer must be suitable as an initializer for the type
 393    `HARD_REG_SET' which is defined in `hard-reg-set.h'.  */
 394
 395 #define REG_CLASS_CONTENTS                                              \
 396 {                                                                       \
 397   { 0x00000000, 0x00000000, 0x00000000 },       /* NO_REGS */           \
 398   { 0xf00000c0, 0x00000000, 0x00000000 },       /* SIBCALL_REGS */      \
 399   { 0xffffffc0, 0x00000000, 0x00000000 },       /* JALR_REGS */         \
 400   { 0xffffffff, 0x00000000, 0x00000000 },       /* GR_REGS */           \
 401   { 0x00000000, 0xffffffff, 0x00000000 },       /* FP_REGS */           \
 402   { 0x00000000, 0x00000000, 0x00000003 },       /* FRAME_REGS */        \
 403   { 0xffffffff, 0xffffffff, 0x00000003 }        /* ALL_REGS */          \
 404 }
 405
 406 /* A C expression whose value is a register class containing hard
 407    register REGNO.  In general there is more that one such class;
 408    choose a class which is "minimal", meaning that no smaller class
 409    also contains the register.  */
 410
 411 #define REGNO_REG_CLASS(REGNO) riscv_regno_to_class[ (REGNO) ]
 412
 413 /* A macro whose definition is the name of the class to which a
 414    valid base register must belong.  A base register is one used in
 415    an address which is the register value plus a displacement.  */
 416
 417 #define BASE_REG_CLASS GR_REGS
 418
 419 /* A macro whose definition is the name of the class to which a
 420    valid index register must belong.  An index register is one used
 421    in an address where its value is either multiplied by a scale
 422    factor or added to another register (as well as added to a
 423    displacement).  */
 424
 425 #define INDEX_REG_CLASS NO_REGS
 426
 427 /* We generally want to put call-clobbered registers ahead of
 428    call-saved ones.  (IRA expects this.)  */
 429
 430 #define REG_ALLOC_ORDER                                                 \
 431 { \
 432   /* Call-clobbered GPRs.  */                                           \
 433   15, 14, 13, 12, 11, 10, 16, 17, 6, 28, 29, 30, 31, 5, 7, 1,           \
 434   /* Call-saved GPRs.  */                                               \
 435   8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,                         \
 436   /* GPRs that can never be exposed to the register allocator.  */      \
 437   0, 2, 3, 4,                                                           \
 438   /* Call-clobbered FPRs.  */                                           \
 439   47, 46, 45, 44, 43, 42, 32, 33, 34, 35, 36, 37, 38, 39, 48, 49,       \
 440   60, 61, 62, 63,                                                       \
 441   /* Call-saved FPRs.  */                                               \
 442   40, 41, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59,                       \
 443   /* None of the remaining classes have defined call-saved              \
 444      registers.  */                                                     \
 445   64, 65                                                                \
 446 }
 447
 448 /* True if VALUE is a signed 12-bit number.  */
 449
 450 #define SMALL_OPERAND(VALUE) \
 451   ((unsigned HOST_WIDE_INT) (VALUE) + IMM_REACH/2 < IMM_REACH)
 452
 453 /* True if VALUE can be loaded into a register using LUI.  */
 454
 455 #define LUI_OPERAND(VALUE)                                              \
 456   (((VALUE) | ((1UL<<31) - IMM_REACH)) == ((1UL<<31) - IMM_REACH)       \
 457    || ((VALUE) | ((1UL<<31) - IMM_REACH)) + IMM_REACH == 0)
 458
 459 /* Stack layout; function entry, exit and calling.  */
 460
 461 #define STACK_GROWS_DOWNWARD 1
 462
 463 #define FRAME_GROWS_DOWNWARD 1
 464
 465 #define RETURN_ADDR_RTX riscv_return_addr
 466
 467 #define ELIMINABLE_REGS                                                 \
 468 {{ ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM},                         \
 469  { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM},                    \
 470  { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM},                         \
 471  { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}                            \
 472
 473 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
 474   (OFFSET) = riscv_initial_elimination_offset (FROM, TO)
 475
 476 /* Allocate stack space for arguments at the beginning of each function.  */
 477 #define ACCUMULATE_OUTGOING_ARGS 1
 478
 479 /* The argument pointer always points to the first argument.  */
 480 #define FIRST_PARM_OFFSET(FNDECL) 0
 481
 482 #define REG_PARM_STACK_SPACE(FNDECL) 0
 483
 484 /* Define this if it is the responsibility of the caller to
 485    allocate the area reserved for arguments passed in registers.
 486    If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
 487    of this macro is to determine whether the space is included in
 488    `crtl->outgoing_args_size'.  */
 489 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
 490
 491 #define PREFERRED_STACK_BOUNDARY riscv_stack_boundary
 492
 493 /* Symbolic macros for the registers used to return integer and floating
 494    point values.  */
 495
 496 #define GP_RETURN GP_ARG_FIRST
 497 #define FP_RETURN (UNITS_PER_FP_ARG == 0 ? GP_RETURN : FP_ARG_FIRST)
 498
 499 #define MAX_ARGS_IN_REGISTERS (riscv_abi == ABI_ILP32E ? 6 : 8)
 500
 501 /* Symbolic macros for the first/last argument registers.  */
 502
 503 #define GP_ARG_FIRST (GP_REG_FIRST + 10)
 504 #define GP_ARG_LAST  (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
 505 #define GP_TEMP_FIRST (GP_REG_FIRST + 5)
 506 #define FP_ARG_FIRST (FP_REG_FIRST + 10)
 507 #define FP_ARG_LAST  (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
 508
 509 #define CALLEE_SAVED_REG_NUMBER(REGNO)                  \
 510   ((REGNO) >= 8 && (REGNO) <= 9 ? (REGNO) - 8 :         \
 511    (REGNO) >= 18 && (REGNO) <= 27 ? (REGNO) - 16 : -1)
 512
 513 #define LIBCALL_VALUE(MODE) \
 514   riscv_function_value (NULL_TREE, NULL_TREE, MODE)
 515
 516 #define FUNCTION_VALUE(VALTYPE, FUNC) \
 517   riscv_function_value (VALTYPE, FUNC, VOIDmode)
 518
 519 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
 520
 521 /* 1 if N is a possible register number for function argument passing.
 522    We have no FP argument registers when soft-float.  */
 523
 524 /* Accept arguments in a0-a7, and in fa0-fa7 if permitted by the ABI.  */
 525 #define FUNCTION_ARG_REGNO_P(N)                                         \
 526   (IN_RANGE ((N), GP_ARG_FIRST, GP_ARG_LAST)                            \
 527    || (UNITS_PER_FP_ARG && IN_RANGE ((N), FP_ARG_FIRST, FP_ARG_LAST)))
 528
 529 typedef struct {
 530   /* Number of integer registers used so far, up to MAX_ARGS_IN_REGISTERS. */
 531   unsigned int num_gprs;
 532
 533   /* Number of floating-point registers used so far, likewise.  */
 534   unsigned int num_fprs;
 535 } CUMULATIVE_ARGS;
 536
 537 /* Initialize a variable CUM of type CUMULATIVE_ARGS
 538    for a call to a function whose data type is FNTYPE.
 539    For a library call, FNTYPE is 0.  */
 540
 541 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
 542   memset (&(CUM), 0, sizeof (CUM))
 543
 544 #define EPILOGUE_USES(REGNO)    riscv_epilogue_uses (REGNO)
 545
 546 /* Align based on stack boundary, which might have been set by the user.  */
 547 #define RISCV_STACK_ALIGN(LOC) \
 548   (((LOC) + ((PREFERRED_STACK_BOUNDARY/8)-1)) & -(PREFERRED_STACK_BOUNDARY/8))
 549
 550 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
 551    the stack pointer does not matter.  The value is tested only in
 552    functions that have frame pointers.
 553    No definition is equivalent to always zero.  */
 554
 555 #define EXIT_IGNORE_STACK 1
 556
 557
 558 /* Trampolines are a block of code followed by two pointers.  */
 559
 560 #define TRAMPOLINE_CODE_SIZE 16
 561 #define TRAMPOLINE_SIZE         \
 562   ((Pmode == SImode)            \
 563    ? TRAMPOLINE_CODE_SIZE       \
 564    : (TRAMPOLINE_CODE_SIZE + POINTER_SIZE * 2))
 565 #define TRAMPOLINE_ALIGNMENT POINTER_SIZE
 566
 567 /* Addressing modes, and classification of registers for them.  */
 568
 569 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
 570 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
 571   riscv_regno_mode_ok_for_base_p (REGNO, MODE, 1)
 572
 573 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
 574    and check its validity for a certain class.
 575    We have two alternate definitions for each of them.
 576    The usual definition accepts all pseudo regs; the other rejects them all.
 577    The symbol REG_OK_STRICT causes the latter definition to be used.
 578
 579    Most source files want to accept pseudo regs in the hope that
 580    they will get allocated to the class that the insn wants them to be in.
 581    Some source files that are used after register allocation
 582    need to be strict.  */
 583
 584 #ifndef REG_OK_STRICT
 585 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 586   riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
 587 #else
 588 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
 589   riscv_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
 590 #endif
 591
 592 #define REG_OK_FOR_INDEX_P(X) 0
 593
 594 /* Maximum number of registers that can appear in a valid memory address.  */
 595
 596 #define MAX_REGS_PER_ADDRESS 1
 597
 598 #define CONSTANT_ADDRESS_P(X) \
 599   (CONSTANT_P (X) && memory_address_p (SImode, X))
 600
 601 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
 602    'the start of the function that this code is output in'.  */
 603
 604 #define ASM_OUTPUT_LABELREF(FILE,NAME)                                  \
 605   do {                                                                  \
 606     if (strcmp (NAME, "..CURRENT_FUNCTION") == 0)                       \
 607       asm_fprintf ((FILE), "%U%s",                                      \
 608                    XSTR (XEXP (DECL_RTL (current_function_decl),        \
 609                                0), 0));                                 \
 610     else                                                                \
 611       asm_fprintf ((FILE), "%U%s", (NAME));                             \
 612   } while (0)
 613
 614 #define JUMP_TABLES_IN_TEXT_SECTION 0
 615 #define CASE_VECTOR_MODE SImode
 616 #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW)
 617
 618 /* The load-address macro is used for PC-relative addressing of symbols
 619    that bind locally.  Don't use it for symbols that should be addressed
 620    via the GOT.  Also, avoid it for CM_MEDLOW, where LUI addressing
 621    currently results in more opportunities for linker relaxation.  */
 622 #define USE_LOAD_ADDRESS_MACRO(sym)                                     \
 623   (!TARGET_EXPLICIT_RELOCS &&                                           \
 624    ((flag_pic                                                           \
 625      && ((SYMBOL_REF_P (sym) && SYMBOL_REF_LOCAL_P (sym))               \
 626          || ((GET_CODE (sym) == CONST)                                  \
 627              && SYMBOL_REF_P (XEXP (XEXP (sym, 0),0))                   \
 628              && SYMBOL_REF_LOCAL_P (XEXP (XEXP (sym, 0),0)))))          \
 629      || riscv_cmodel == CM_MEDANY))
 630
 631 /* Define this as 1 if `char' should by default be signed; else as 0.  */
 632 #define DEFAULT_SIGNED_CHAR 0
 633
 634 #define MOVE_MAX UNITS_PER_WORD
 635 #define MAX_MOVE_MAX 8
 636
 637 /* The SPARC port says:
 638    Nonzero if access to memory by bytes is slow and undesirable.
 639    For RISC chips, it means that access to memory by bytes is no
 640    better than access by words when possible, so grab a whole word
 641    and maybe make use of that.  */
 642 #define SLOW_BYTE_ACCESS 1
 643
 644 /* Using SHIFT_COUNT_TRUNCATED is discouraged, so we handle this with patterns
 645    in the md file instead.  */
 646 #define SHIFT_COUNT_TRUNCATED 0
 647
 648 /* Specify the machine mode that pointers have.
 649    After generation of rtl, the compiler makes no further distinction
 650    between pointers and any other objects of this machine mode.  */
 651
 652 #define Pmode word_mode
 653
 654 /* Give call MEMs SImode since it is the "most permissive" mode
 655    for both 32-bit and 64-bit targets.  */
 656
 657 #define FUNCTION_MODE SImode
 658
 659 /* A C expression for the cost of a branch instruction.  A value of 2
 660    seems to minimize code size.  */
 661
 662 #define BRANCH_COST(speed_p, predictable_p) \
 663   ((!(speed_p) || (predictable_p)) ? 2 : riscv_branch_cost)
 664
 665 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
 666
 667 /* Control the assembler format that we output.  */
 668
 669 /* Output to assembler file text saying following lines
 670    may contain character constants, extra white space, comments, etc.  */
 671
 672 #ifndef ASM_APP_ON
 673 #define ASM_APP_ON " #APP\n"
 674 #endif
 675
 676 /* Output to assembler file text saying following lines
 677    no longer contain unusual constructs.  */
 678
 679 #ifndef ASM_APP_OFF
 680 #define ASM_APP_OFF " #NO_APP\n"
 681 #endif
 682
 683 #define REGISTER_NAMES                                          \
 684 { "zero","ra",  "sp",  "gp",  "tp",  "t0",  "t1",  "t2",        \
 685   "s0",  "s1",  "a0",  "a1",  "a2",  "a3",  "a4",  "a5",        \
 686   "a6",  "a7",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",        \
 687   "s8",  "s9",  "s10", "s11", "t3",  "t4",  "t5",  "t6",        \
 688   "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",       \
 689   "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",       \
 690   "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",       \
 691   "fs8", "fs9", "fs10","fs11","ft8", "ft9", "ft10","ft11",      \
 692   "arg", "frame", }
 693
 694 #define ADDITIONAL_REGISTER_NAMES                                       \
 695 {                                                                       \
 696   { "x0",        0 + GP_REG_FIRST },                                    \
 697   { "x1",        1 + GP_REG_FIRST },                                    \
 698   { "x2",        2 + GP_REG_FIRST },                                    \
 699   { "x3",        3 + GP_REG_FIRST },                                    \
 700   { "x4",        4 + GP_REG_FIRST },                                    \
 701   { "x5",        5 + GP_REG_FIRST },                                    \
 702   { "x6",        6 + GP_REG_FIRST },                                    \
 703   { "x7",        7 + GP_REG_FIRST },                                    \
 704   { "x8",        8 + GP_REG_FIRST },                                    \
 705   { "x9",        9 + GP_REG_FIRST },                                    \
 706   { "x10",      10 + GP_REG_FIRST },                                    \
 707   { "x11",      11 + GP_REG_FIRST },                                    \
 708   { "x12",      12 + GP_REG_FIRST },                                    \
 709   { "x13",      13 + GP_REG_FIRST },                                    \
 710   { "x14",      14 + GP_REG_FIRST },                                    \
 711   { "x15",      15 + GP_REG_FIRST },                                    \
 712   { "x16",      16 + GP_REG_FIRST },                                    \
 713   { "x17",      17 + GP_REG_FIRST },                                    \
 714   { "x18",      18 + GP_REG_FIRST },                                    \
 715   { "x19",      19 + GP_REG_FIRST },                                    \
 716   { "x20",      20 + GP_REG_FIRST },                                    \
 717   { "x21",      21 + GP_REG_FIRST },                                    \
 718   { "x22",      22 + GP_REG_FIRST },                                    \
 719   { "x23",      23 + GP_REG_FIRST },                                    \
 720   { "x24",      24 + GP_REG_FIRST },                                    \
 721   { "x25",      25 + GP_REG_FIRST },                                    \
 722   { "x26",      26 + GP_REG_FIRST },                                    \
 723   { "x27",      27 + GP_REG_FIRST },                                    \
 724   { "x28",      28 + GP_REG_FIRST },                                    \
 725   { "x29",      29 + GP_REG_FIRST },                                    \
 726   { "x30",      30 + GP_REG_FIRST },                                    \
 727   { "x31",      31 + GP_REG_FIRST },                                    \
 728   { "f0",        0 + FP_REG_FIRST },                                    \
 729   { "f1",        1 + FP_REG_FIRST },                                    \
 730   { "f2",        2 + FP_REG_FIRST },                                    \
 731   { "f3",        3 + FP_REG_FIRST },                                    \
 732   { "f4",        4 + FP_REG_FIRST },                                    \
 733   { "f5",        5 + FP_REG_FIRST },                                    \
 734   { "f6",        6 + FP_REG_FIRST },                                    \
 735   { "f7",        7 + FP_REG_FIRST },                                    \
 736   { "f8",        8 + FP_REG_FIRST },                                    \
 737   { "f9",        9 + FP_REG_FIRST },                                    \
 738   { "f10",      10 + FP_REG_FIRST },                                    \
 739   { "f11",      11 + FP_REG_FIRST },                                    \
 740   { "f12",      12 + FP_REG_FIRST },                                    \
 741   { "f13",      13 + FP_REG_FIRST },                                    \
 742   { "f14",      14 + FP_REG_FIRST },                                    \
 743   { "f15",      15 + FP_REG_FIRST },                                    \
 744   { "f16",      16 + FP_REG_FIRST },                                    \
 745   { "f17",      17 + FP_REG_FIRST },                                    \
 746   { "f18",      18 + FP_REG_FIRST },                                    \
 747   { "f19",      19 + FP_REG_FIRST },                                    \
 748   { "f20",      20 + FP_REG_FIRST },                                    \
 749   { "f21",      21 + FP_REG_FIRST },                                    \
 750   { "f22",      22 + FP_REG_FIRST },                                    \
 751   { "f23",      23 + FP_REG_FIRST },                                    \
 752   { "f24",      24 + FP_REG_FIRST },                                    \
 753   { "f25",      25 + FP_REG_FIRST },                                    \
 754   { "f26",      26 + FP_REG_FIRST },                                    \
 755   { "f27",      27 + FP_REG_FIRST },                                    \
 756   { "f28",      28 + FP_REG_FIRST },                                    \
 757   { "f29",      29 + FP_REG_FIRST },                                    \
 758   { "f30",      30 + FP_REG_FIRST },                                    \
 759   { "f31",      31 + FP_REG_FIRST },                                    \
 760 }
 761
 762 /* Globalizing directive for a label.  */
 763 #define GLOBAL_ASM_OP "\t.globl\t"
 764
 765 /* This is how to store into the string LABEL
 766    the symbol_ref name of an internal numbered label where
 767    PREFIX is the class of label and NUM is the number within the class.
 768    This is suitable for output with `assemble_name'.  */
 769
 770 #undef ASM_GENERATE_INTERNAL_LABEL
 771 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM)                   \
 772   sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
 773
 774 /* This is how to output an element of a case-vector that is absolute.  */
 775
 776 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE)                          \
 777   fprintf (STREAM, "\t.word\t%sL%d\n", LOCAL_LABEL_PREFIX, VALUE)
 778
 779 /* This is how to output an element of a PIC case-vector. */
 780
 781 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL)              \
 782   fprintf (STREAM, "\t.word\t%sL%d-%sL%d\n",                            \
 783            LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL)
 784
 785 /* This is how to output an assembler line
 786    that says to advance the location counter
 787    to a multiple of 2**LOG bytes.  */
 788
 789 #define ASM_OUTPUT_ALIGN(STREAM,LOG)                                    \
 790   fprintf (STREAM, "\t.align\t%d\n", (LOG))
 791
 792 /* Define the strings to put out for each section in the object file.  */
 793 #define TEXT_SECTION_ASM_OP     "\t.text"       /* instructions */
 794 #define DATA_SECTION_ASM_OP     "\t.data"       /* large data */
 795 #define READONLY_DATA_SECTION_ASM_OP    "\t.section\t.rodata"
 796 #define BSS_SECTION_ASM_OP      "\t.bss"
 797 #define SBSS_SECTION_ASM_OP     "\t.section\t.sbss,\"aw\",@nobits"
 798 #define SDATA_SECTION_ASM_OP    "\t.section\t.sdata,\"aw\",@progbits"
 799
 800 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO)                               \
 801 do                                                                      \
 802   {                                                                     \
 803     fprintf (STREAM, "\taddi\t%s,%s,-8\n\t%s\t%s,0(%s)\n",              \
 804              reg_names[STACK_POINTER_REGNUM],                           \
 805              reg_names[STACK_POINTER_REGNUM],                           \
 806              TARGET_64BIT ? "sd" : "sw",                                \
 807              reg_names[REGNO],                                          \
 808              reg_names[STACK_POINTER_REGNUM]);                          \
 809   }                                                                     \
 810 while (0)
 811
 812 #define ASM_OUTPUT_REG_POP(STREAM,REGNO)                                \
 813 do                                                                      \
 814   {                                                                     \
 815     fprintf (STREAM, "\t%s\t%s,0(%s)\n\taddi\t%s,%s,8\n",               \
 816              TARGET_64BIT ? "ld" : "lw",                                \
 817              reg_names[REGNO],                                          \
 818              reg_names[STACK_POINTER_REGNUM],                           \
 819              reg_names[STACK_POINTER_REGNUM],                           \
 820              reg_names[STACK_POINTER_REGNUM]);                          \
 821   }                                                                     \
 822 while (0)
 823
 824 #define ASM_COMMENT_START "#"
 825
 826 #undef SIZE_TYPE
 827 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
 828
 829 #undef PTRDIFF_TYPE
 830 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
 831
 832 /* The maximum number of bytes copied by one iteration of a movmemsi loop.  */
 833
 834 #define RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER (UNITS_PER_WORD * 4)
 835
 836 /* The maximum number of bytes that can be copied by a straight-line
 837    movmemsi implementation.  */
 838
 839 #define RISCV_MAX_MOVE_BYTES_STRAIGHT (RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER * 3)
 840
 841 /* If a memory-to-memory move would take MOVE_RATIO or more simple
 842    move-instruction pairs, we will do a movmem or libcall instead.
 843    Do not use move_by_pieces at all when strict alignment is not
 844    in effect but the target has slow unaligned accesses; in this
 845    case, movmem or libcall is more efficient.  */
 846
 847 #define MOVE_RATIO(speed)                                               \
 848   (!STRICT_ALIGNMENT && riscv_slow_unaligned_access_p ? 1 :             \
 849    (speed) ? RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD :      \
 850    CLEAR_RATIO (speed) / 2)
 851
 852 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
 853    of the length of a memset call, but use the default otherwise.  */
 854
 855 #define CLEAR_RATIO(speed) ((speed) ? 16 : 6)
 856
 857 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
 858    optimizing for size adjust the ratio to account for the overhead of
 859    loading the constant and replicating it across the word.  */
 860
 861 #define SET_RATIO(speed) (CLEAR_RATIO (speed) - ((speed) ? 0 : 2))
 862
 863 #ifndef USED_FOR_TARGET
 864 extern const enum reg_class riscv_regno_to_class[];
 865 extern bool riscv_slow_unaligned_access_p;
 866 extern unsigned riscv_stack_boundary;
 867 #endif
 868
 869 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
 870   (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4)
 871
 872 #define XLEN_SPEC \
 873   "%{march=rv32*:32}" \
 874   "%{march=rv64*:64}" \
 875
 876 #define ABI_SPEC \
 877   "%{mabi=ilp32:ilp32}" \
 878   "%{mabi=ilp32e:ilp32e}" \
 879   "%{mabi=ilp32f:ilp32f}" \
 880   "%{mabi=ilp32d:ilp32d}" \
 881   "%{mabi=lp64:lp64}" \
 882   "%{mabi=lp64f:lp64f}" \
 883   "%{mabi=lp64d:lp64d}" \
 884
 885 #define STARTFILE_PREFIX_SPEC                   \
 886    "/lib" XLEN_SPEC "/" ABI_SPEC "/ "           \
 887    "/usr/lib" XLEN_SPEC "/" ABI_SPEC "/ "       \
 888    "/lib/ "                                     \
 889    "/usr/lib/ "
 890
 891 /* ISA constants needed for code generation.  */
 892 #define OPCODE_LW    0x2003
 893 #define OPCODE_LD    0x3003
 894 #define OPCODE_AUIPC 0x17
 895 #define OPCODE_JALR  0x67
 896 #define OPCODE_LUI   0x37
 897 #define OPCODE_ADDI  0x13
 898 #define SHIFT_RD  7
 899 #define SHIFT_RS1 15
 900 #define SHIFT_IMM 20
 901 #define IMM_BITS 12
 902 #define C_SxSP_BITS 6
 903
 904 #define IMM_REACH (1LL << IMM_BITS)
 905 #define CONST_HIGH_PART(VALUE) (((VALUE) + (IMM_REACH/2)) & ~(IMM_REACH-1))
 906 #define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE))
 907
 908 #define SWSP_REACH (4LL << C_SxSP_BITS)
 909 #define SDSP_REACH (8LL << C_SxSP_BITS)
 910
 911 #endif /* ! GCC_RISCV_H */