RISC-V: Optimze the reverse conditions of rotate shift
[official-gcc.git] / gcc / testsuite / gcc.target / riscv / zbb-rol-ror-06.c
blob70b79abb6ed0d0db2e72a26264d5e6985b0758e5
1 /* { dg-do compile } */
2 /* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */
3 /* { dg-skip-if "" { *-*-* } { "-g" } } */
4 /* { dg-final { check-function-bodies "**" "" } } */
6 /*
7 **foo1:
8 ** roriw a0,a0,14
9 ** ret
11 unsigned int foo1 (unsigned int rs1)
12 { return ((rs1 >> 14) | (rs1 << 18)); }
15 **foo2:
16 ** roriw a0,a0,18
17 ** ret
19 unsigned int foo2 (unsigned int rs1)
20 { return ((rs1 >> 18) | (rs1 << 14)); }
23 **foo3:
24 ** roriw a0,a0,18
25 ** ret
27 unsigned int foo3 (unsigned int rs1)
28 { return ((rs1 << 14) | (rs1 >> 18)); }
31 **foo4:
32 ** roriw a0,a0,14
33 ** ret
35 unsigned int foo4 (unsigned int rs1)
36 { return ((rs1 << 18) | (rs1 >> 14)); }