RISC-V: Optimze the reverse conditions of rotate shift
commit0ccf520d349a82dafca0deb3d307a1080e8589a0
authorFeng Wang <wangfeng@eswincomputing.com>
Sat, 15 Apr 2023 16:11:15 +0000 (15 10:11 -0600)
committerJeff Law <jlaw@ventanamicro>
Mon, 17 Apr 2023 17:52:49 +0000 (17 11:52 -0600)
treee7c642ee9d3b35b20b7fdca84f319de0e1985ce0
parentf46ab321399f9b6b357a9f2bf399b708867cea54
RISC-V: Optimze the reverse conditions of rotate shift

gcc/ChangeLog:

* config/riscv/bitmanip.md (rotrsi3_sext): Support generating
roriw for constant counts.
* rtl.h (reverse_rotate_by_imm_p): Add function declartion
* simplify-rtx.cc (reverse_rotate_by_imm_p): New function.
(simplify_context::simplify_binary_operation_1): Use it.
* expmed.cc (expand_shift_1): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/zbb-rol-ror-04.c: New test.
* gcc.target/riscv/zbb-rol-ror-05.c: New test.
* gcc.target/riscv/zbb-rol-ror-06.c: New test.
* gcc.target/riscv/zbb-rol-ror-07.c: New test.
gcc/config/riscv/bitmanip.md
gcc/expmed.cc
gcc/rtl.h
gcc/simplify-rtx.cc
gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c [new file with mode: 0644]
gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c [new file with mode: 0644]