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* config/mips/mips.h (ISA_HAS_CINS): New macro.
[official-gcc.git] / gcc / config / mips / mips.h
bloba3f47f79dcfed679fcb6cfb0122fa8ec681fc25b
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
16
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26
27 #include "config/vxworks-dummy.h"
28
29 /* MIPS external variables defined in mips.c. */
30
31 /* Which processor to schedule for. Since there is no difference between
32 a R2000 and R3000 in terms of the scheduler, we collapse them into
33 just an R3000. The elements of the enumeration must match exactly
34 the cpu attribute in the mips.md machine description. */
35
36 enum processor_type {
37 PROCESSOR_R3000,
38 PROCESSOR_4KC,
39 PROCESSOR_4KP,
40 PROCESSOR_5KC,
41 PROCESSOR_5KF,
42 PROCESSOR_20KC,
43 PROCESSOR_24KC,
44 PROCESSOR_24KF2_1,
45 PROCESSOR_24KF1_1,
46 PROCESSOR_74KC,
47 PROCESSOR_74KF2_1,
48 PROCESSOR_74KF1_1,
49 PROCESSOR_74KF3_2,
50 PROCESSOR_LOONGSON_2E,
51 PROCESSOR_LOONGSON_2F,
52 PROCESSOR_M4K,
53 PROCESSOR_OCTEON,
54 PROCESSOR_R3900,
55 PROCESSOR_R6000,
56 PROCESSOR_R4000,
57 PROCESSOR_R4100,
58 PROCESSOR_R4111,
59 PROCESSOR_R4120,
60 PROCESSOR_R4130,
61 PROCESSOR_R4300,
62 PROCESSOR_R4600,
63 PROCESSOR_R4650,
64 PROCESSOR_R5000,
65 PROCESSOR_R5400,
66 PROCESSOR_R5500,
67 PROCESSOR_R7000,
68 PROCESSOR_R8000,
69 PROCESSOR_R9000,
70 PROCESSOR_SB1,
71 PROCESSOR_SB1A,
72 PROCESSOR_SR71000,
73 PROCESSOR_XLR,
74 PROCESSOR_MAX
75 };
76
77 /* Costs of various operations on the different architectures. */
78
79 struct mips_rtx_cost_data
80 {
81 unsigned short fp_add;
82 unsigned short fp_mult_sf;
83 unsigned short fp_mult_df;
84 unsigned short fp_div_sf;
85 unsigned short fp_div_df;
86 unsigned short int_mult_si;
87 unsigned short int_mult_di;
88 unsigned short int_div_si;
89 unsigned short int_div_di;
90 unsigned short branch_cost;
91 unsigned short memory_latency;
92 };
93
94 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
95 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
96 to work on a 64-bit machine. */
97
98 #define ABI_32 0
99 #define ABI_N32 1
100 #define ABI_64 2
101 #define ABI_EABI 3
102 #define ABI_O64 4
103
104 /* Masks that affect tuning.
105
106 PTF_AVOID_BRANCHLIKELY
107 Set if it is usually not profitable to use branch-likely instructions
108 for this target, typically because the branches are always predicted
109 taken and so incur a large overhead when not taken. */
110 #define PTF_AVOID_BRANCHLIKELY 0x1
111
112 /* Information about one recognized processor. Defined here for the
113 benefit of TARGET_CPU_CPP_BUILTINS. */
114 struct mips_cpu_info {
115 /* The 'canonical' name of the processor as far as GCC is concerned.
116 It's typically a manufacturer's prefix followed by a numerical
117 designation. It should be lowercase. */
118 const char *name;
119
120 /* The internal processor number that most closely matches this
121 entry. Several processors can have the same value, if there's no
122 difference between them from GCC's point of view. */
123 enum processor_type cpu;
124
125 /* The ISA level that the processor implements. */
126 int isa;
127
128 /* A mask of PTF_* values. */
129 unsigned int tune_flags;
130 };
131
132 /* Enumerates the setting of the -mcode-readable option. */
133 enum mips_code_readable_setting {
134 CODE_READABLE_NO,
135 CODE_READABLE_PCREL,
136 CODE_READABLE_YES
137 };
138
139 /* Macros to silence warnings about numbers being signed in traditional
140 C and unsigned in ISO C when compiled on 32-bit hosts. */
141
142 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
143 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
144 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
145
146 \f
147 /* Run-time compilation parameters selecting different hardware subsets. */
148
149 /* True if we are generating position-independent VxWorks RTP code. */
150 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
151
152 /* True if the output file is marked as ".abicalls; .option pic0"
153 (-call_nonpic). */
154 #define TARGET_ABICALLS_PIC0 \
155 (TARGET_ABSOLUTE_ABICALLS && TARGET_PLT)
156
157 /* True if the output file is marked as ".abicalls; .option pic2" (-KPIC). */
158 #define TARGET_ABICALLS_PIC2 \
159 (TARGET_ABICALLS && !TARGET_ABICALLS_PIC0)
160
161 /* True if the call patterns should be split into a jalr followed by
162 an instruction to restore $gp. It is only safe to split the load
163 from the call when every use of $gp is explicit. */
164
165 #define TARGET_SPLIT_CALLS \
166 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP)
167
168 /* True if we're generating a form of -mabicalls in which we can use
169 operators like %hi and %lo to refer to locally-binding symbols.
170 We can only do this for -mno-shared, and only then if we can use
171 relocation operations instead of assembly macros. It isn't really
172 worth using absolute sequences for 64-bit symbols because GOT
173 accesses are so much shorter. */
174
175 #define TARGET_ABSOLUTE_ABICALLS \
176 (TARGET_ABICALLS \
177 && !TARGET_SHARED \
178 && TARGET_EXPLICIT_RELOCS \
179 && !ABI_HAS_64BIT_SYMBOLS)
180
181 /* True if we can optimize sibling calls. For simplicity, we only
182 handle cases in which call_insn_operand will reject invalid
183 sibcall addresses. There are two cases in which this isn't true:
184
185 - TARGET_MIPS16. call_insn_operand accepts constant addresses
186 but there is no direct jump instruction. It isn't worth
187 using sibling calls in this case anyway; they would usually
188 be longer than normal calls.
189
190 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
191 accepts global constants, but all sibcalls must be indirect. */
192 #define TARGET_SIBCALLS \
193 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
194
195 /* True if we need to use a global offset table to access some symbols. */
196 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
197
198 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
199 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
200
201 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
202 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
203
204 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
205 This is true for both the PIC and non-PIC VxWorks RTP modes. */
206 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
207
208 /* True if .gpword or .gpdword should be used for switch tables.
209
210 Although GAS does understand .gpdword, the SGI linker mishandles
211 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
212 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
213 #define TARGET_GPWORD \
214 (TARGET_ABICALLS \
215 && !TARGET_ABSOLUTE_ABICALLS \
216 && !(mips_abi == ABI_64 && TARGET_IRIX))
217
218 /* Generate mips16 code */
219 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
220 /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */
221 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
222 /* Generate mips16e register save/restore sequences. */
223 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
224
225 /* True if we're generating a form of MIPS16 code in which general
226 text loads are allowed. */
227 #define TARGET_MIPS16_TEXT_LOADS \
228 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
229
230 /* True if we're generating a form of MIPS16 code in which PC-relative
231 loads are allowed. */
232 #define TARGET_MIPS16_PCREL_LOADS \
233 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
234
235 /* Generic ISA defines. */
236 #define ISA_MIPS1 (mips_isa == 1)
237 #define ISA_MIPS2 (mips_isa == 2)
238 #define ISA_MIPS3 (mips_isa == 3)
239 #define ISA_MIPS4 (mips_isa == 4)
240 #define ISA_MIPS32 (mips_isa == 32)
241 #define ISA_MIPS32R2 (mips_isa == 33)
242 #define ISA_MIPS64 (mips_isa == 64)
243 #define ISA_MIPS64R2 (mips_isa == 65)
244
245 /* Architecture target defines. */
246 #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E)
247 #define TARGET_LOONGSON_2F (mips_arch == PROCESSOR_LOONGSON_2F)
248 #define TARGET_LOONGSON_2EF (TARGET_LOONGSON_2E || TARGET_LOONGSON_2F)
249 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
250 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
251 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
252 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
253 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
254 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
255 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
256 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
257 #define TARGET_OCTEON (mips_arch == PROCESSOR_OCTEON)
258 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
259 || mips_arch == PROCESSOR_SB1A)
260 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
261
262 /* Scheduling target defines. */
263 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
264 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
265 || mips_tune == PROCESSOR_24KF2_1 \
266 || mips_tune == PROCESSOR_24KF1_1)
267 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
268 || mips_tune == PROCESSOR_74KF2_1 \
269 || mips_tune == PROCESSOR_74KF1_1 \
270 || mips_tune == PROCESSOR_74KF3_2)
271 #define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
272 || mips_tune == PROCESSOR_LOONGSON_2F)
273 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
274 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
275 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
276 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
277 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
278 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
279 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
280 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
281 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
282 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
283 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
284 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
285 || mips_tune == PROCESSOR_SB1A)
286
287 /* Whether vector modes and intrinsics for ST Microelectronics
288 Loongson-2E/2F processors should be enabled. In o32 pairs of
289 floating-point registers provide 64-bit values. */
290 #define TARGET_LOONGSON_VECTORS (TARGET_HARD_FLOAT_ABI \
291 && TARGET_LOONGSON_2EF)
292
293 /* True if the pre-reload scheduler should try to create chains of
294 multiply-add or multiply-subtract instructions. For example,
295 suppose we have:
296
297 t1 = a * b
298 t2 = t1 + c * d
299 t3 = e * f
300 t4 = t3 - g * h
301
302 t1 will have a higher priority than t2 and t3 will have a higher
303 priority than t4. However, before reload, there is no dependence
304 between t1 and t3, and they can often have similar priorities.
305 The scheduler will then tend to prefer:
306
307 t1 = a * b
308 t3 = e * f
309 t2 = t1 + c * d
310 t4 = t3 - g * h
311
312 which stops us from making full use of macc/madd-style instructions.
313 This sort of situation occurs frequently in Fourier transforms and
314 in unrolled loops.
315
316 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
317 queue so that chained multiply-add and multiply-subtract instructions
318 appear ahead of any other instruction that is likely to clobber lo.
319 In the example above, if t2 and t3 become ready at the same time,
320 the code ensures that t2 is scheduled first.
321
322 Multiply-accumulate instructions are a bigger win for some targets
323 than others, so this macro is defined on an opt-in basis. */
324 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
325 || TUNE_MIPS4120 \
326 || TUNE_MIPS4130 \
327 || TUNE_24K)
328
329 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
330 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
331
332 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
333 directly accessible, while the command-line options select
334 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
335 in use. */
336 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
337 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
338
339 /* IRIX specific stuff. */
340 #define TARGET_IRIX 0
341 #define TARGET_IRIX6 0
342
343 /* Define preprocessor macros for the -march and -mtune options.
344 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
345 processor. If INFO's canonical name is "foo", define PREFIX to
346 be "foo", and define an additional macro PREFIX_FOO. */
347 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
348 do \
349 { \
350 char *macro, *p; \
351 \
352 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
353 for (p = macro; *p != 0; p++) \
354 *p = TOUPPER (*p); \
355 \
356 builtin_define (macro); \
357 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
358 free (macro); \
359 } \
360 while (0)
361
362 /* Target CPU builtins. */
363 #define TARGET_CPU_CPP_BUILTINS() \
364 do \
365 { \
366 /* Everyone but IRIX defines this to mips. */ \
367 if (!TARGET_IRIX) \
368 builtin_assert ("machine=mips"); \
369 \
370 builtin_assert ("cpu=mips"); \
371 builtin_define ("__mips__"); \
372 builtin_define ("_mips"); \
373 \
374 /* We do this here because __mips is defined below and so we \
375 can't use builtin_define_std. We don't ever want to define \
376 "mips" for VxWorks because some of the VxWorks headers \
377 construct include filenames from a root directory macro, \
378 an architecture macro and a filename, where the architecture \
379 macro expands to 'mips'. If we define 'mips' to 1, the \
380 architecture macro expands to 1 as well. */ \
381 if (!flag_iso && !TARGET_VXWORKS) \
382 builtin_define ("mips"); \
383 \
384 if (TARGET_64BIT) \
385 builtin_define ("__mips64"); \
386 \
387 if (!TARGET_IRIX) \
388 { \
389 /* Treat _R3000 and _R4000 like register-size \
390 defines, which is how they've historically \
391 been used. */ \
392 if (TARGET_64BIT) \
393 { \
394 builtin_define_std ("R4000"); \
395 builtin_define ("_R4000"); \
396 } \
397 else \
398 { \
399 builtin_define_std ("R3000"); \
400 builtin_define ("_R3000"); \
401 } \
402 } \
403 if (TARGET_FLOAT64) \
404 builtin_define ("__mips_fpr=64"); \
405 else \
406 builtin_define ("__mips_fpr=32"); \
407 \
408 if (mips_base_mips16) \
409 builtin_define ("__mips16"); \
410 \
411 if (TARGET_MIPS3D) \
412 builtin_define ("__mips3d"); \
413 \
414 if (TARGET_SMARTMIPS) \
415 builtin_define ("__mips_smartmips"); \
416 \
417 if (TARGET_DSP) \
418 { \
419 builtin_define ("__mips_dsp"); \
420 if (TARGET_DSPR2) \
421 { \
422 builtin_define ("__mips_dspr2"); \
423 builtin_define ("__mips_dsp_rev=2"); \
424 } \
425 else \
426 builtin_define ("__mips_dsp_rev=1"); \
427 } \
428 \
429 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
430 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
431 \
432 if (ISA_MIPS1) \
433 { \
434 builtin_define ("__mips=1"); \
435 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
436 } \
437 else if (ISA_MIPS2) \
438 { \
439 builtin_define ("__mips=2"); \
440 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
441 } \
442 else if (ISA_MIPS3) \
443 { \
444 builtin_define ("__mips=3"); \
445 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
446 } \
447 else if (ISA_MIPS4) \
448 { \
449 builtin_define ("__mips=4"); \
450 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
451 } \
452 else if (ISA_MIPS32) \
453 { \
454 builtin_define ("__mips=32"); \
455 builtin_define ("__mips_isa_rev=1"); \
456 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
457 } \
458 else if (ISA_MIPS32R2) \
459 { \
460 builtin_define ("__mips=32"); \
461 builtin_define ("__mips_isa_rev=2"); \
462 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
463 } \
464 else if (ISA_MIPS64) \
465 { \
466 builtin_define ("__mips=64"); \
467 builtin_define ("__mips_isa_rev=1"); \
468 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
469 } \
470 else if (ISA_MIPS64R2) \
471 { \
472 builtin_define ("__mips=64"); \
473 builtin_define ("__mips_isa_rev=2"); \
474 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
475 } \
476 \
477 switch (mips_abi) \
478 { \
479 case ABI_32: \
480 builtin_define ("_ABIO32=1"); \
481 builtin_define ("_MIPS_SIM=_ABIO32"); \
482 break; \
483 \
484 case ABI_N32: \
485 builtin_define ("_ABIN32=2"); \
486 builtin_define ("_MIPS_SIM=_ABIN32"); \
487 break; \
488 \
489 case ABI_64: \
490 builtin_define ("_ABI64=3"); \
491 builtin_define ("_MIPS_SIM=_ABI64"); \
492 break; \
493 \
494 case ABI_O64: \
495 builtin_define ("_ABIO64=4"); \
496 builtin_define ("_MIPS_SIM=_ABIO64"); \
497 break; \
498 } \
499 \
500 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
501 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
502 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
503 builtin_define_with_int_value ("_MIPS_FPSET", \
504 32 / MAX_FPRS_PER_FMT); \
505 \
506 /* These defines reflect the ABI in use, not whether the \
507 FPU is directly accessible. */ \
508 if (TARGET_HARD_FLOAT_ABI) \
509 builtin_define ("__mips_hard_float"); \
510 else \
511 builtin_define ("__mips_soft_float"); \
512 \
513 if (TARGET_SINGLE_FLOAT) \
514 builtin_define ("__mips_single_float"); \
515 \
516 if (TARGET_PAIRED_SINGLE_FLOAT) \
517 builtin_define ("__mips_paired_single_float"); \
518 \
519 if (TARGET_BIG_ENDIAN) \
520 { \
521 builtin_define_std ("MIPSEB"); \
522 builtin_define ("_MIPSEB"); \
523 } \
524 else \
525 { \
526 builtin_define_std ("MIPSEL"); \
527 builtin_define ("_MIPSEL"); \
528 } \
529 \
530 /* Whether Loongson vector modes are enabled. */ \
531 if (TARGET_LOONGSON_VECTORS) \
532 builtin_define ("__mips_loongson_vector_rev"); \
533 \
534 /* Historical Octeon macro. */ \
535 if (TARGET_OCTEON) \
536 builtin_define ("__OCTEON__"); \
537 \
538 /* Macros dependent on the C dialect. */ \
539 if (preprocessing_asm_p ()) \
540 { \
541 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
542 builtin_define ("_LANGUAGE_ASSEMBLY"); \
543 } \
544 else if (c_dialect_cxx ()) \
545 { \
546 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
547 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
548 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
549 } \
550 else \
551 { \
552 builtin_define_std ("LANGUAGE_C"); \
553 builtin_define ("_LANGUAGE_C"); \
554 } \
555 if (c_dialect_objc ()) \
556 { \
557 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
558 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
559 /* Bizarre, but needed at least for Irix. */ \
560 builtin_define_std ("LANGUAGE_C"); \
561 builtin_define ("_LANGUAGE_C"); \
562 } \
563 \
564 if (mips_abi == ABI_EABI) \
565 builtin_define ("__mips_eabi"); \
566 } \
567 while (0)
568
569 /* Default target_flags if no switches are specified */
570
571 #ifndef TARGET_DEFAULT
572 #define TARGET_DEFAULT 0
573 #endif
574
575 #ifndef TARGET_CPU_DEFAULT
576 #define TARGET_CPU_DEFAULT 0
577 #endif
578
579 #ifndef TARGET_ENDIAN_DEFAULT
580 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
581 #endif
582
583 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
584 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
585 #endif
586
587 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
588 #ifndef MIPS_ISA_DEFAULT
589 #ifndef MIPS_CPU_STRING_DEFAULT
590 #define MIPS_CPU_STRING_DEFAULT "from-abi"
591 #endif
592 #endif
593
594 #ifdef IN_LIBGCC2
595 #undef TARGET_64BIT
596 /* Make this compile time constant for libgcc2 */
597 #ifdef __mips64
598 #define TARGET_64BIT 1
599 #else
600 #define TARGET_64BIT 0
601 #endif
602 #endif /* IN_LIBGCC2 */
603
604 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
605 when compiled with hardware floating point. This is because MIPS16
606 code cannot save and restore the floating-point registers, which is
607 important if in a mixed MIPS16/non-MIPS16 environment. */
608
609 #ifdef IN_LIBGCC2
610 #if __mips_hard_float
611 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
612 #endif
613 #endif /* IN_LIBGCC2 */
614
615 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
616
617 #ifndef MULTILIB_ENDIAN_DEFAULT
618 #if TARGET_ENDIAN_DEFAULT == 0
619 #define MULTILIB_ENDIAN_DEFAULT "EL"
620 #else
621 #define MULTILIB_ENDIAN_DEFAULT "EB"
622 #endif
623 #endif
624
625 #ifndef MULTILIB_ISA_DEFAULT
626 # if MIPS_ISA_DEFAULT == 1
627 # define MULTILIB_ISA_DEFAULT "mips1"
628 # else
629 # if MIPS_ISA_DEFAULT == 2
630 # define MULTILIB_ISA_DEFAULT "mips2"
631 # else
632 # if MIPS_ISA_DEFAULT == 3
633 # define MULTILIB_ISA_DEFAULT "mips3"
634 # else
635 # if MIPS_ISA_DEFAULT == 4
636 # define MULTILIB_ISA_DEFAULT "mips4"
637 # else
638 # if MIPS_ISA_DEFAULT == 32
639 # define MULTILIB_ISA_DEFAULT "mips32"
640 # else
641 # if MIPS_ISA_DEFAULT == 33
642 # define MULTILIB_ISA_DEFAULT "mips32r2"
643 # else
644 # if MIPS_ISA_DEFAULT == 64
645 # define MULTILIB_ISA_DEFAULT "mips64"
646 # else
647 # if MIPS_ISA_DEFAULT == 65
648 # define MULTILIB_ISA_DEFAULT "mips64r2"
649 # else
650 # define MULTILIB_ISA_DEFAULT "mips1"
651 # endif
652 # endif
653 # endif
654 # endif
655 # endif
656 # endif
657 # endif
658 # endif
659 #endif
660
661 #ifndef MULTILIB_DEFAULTS
662 #define MULTILIB_DEFAULTS \
663 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
664 #endif
665
666 /* We must pass -EL to the linker by default for little endian embedded
667 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
668 linker will default to using big-endian output files. The OUTPUT_FORMAT
669 line must be in the linker script, otherwise -EB/-EL will not work. */
670
671 #ifndef ENDIAN_SPEC
672 #if TARGET_ENDIAN_DEFAULT == 0
673 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
674 #else
675 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
676 #endif
677 #endif
678
679 /* A spec condition that matches all non-mips16 -mips arguments. */
680
681 #define MIPS_ISA_LEVEL_OPTION_SPEC \
682 "mips1|mips2|mips3|mips4|mips32*|mips64*"
683
684 /* A spec condition that matches all non-mips16 architecture arguments. */
685
686 #define MIPS_ARCH_OPTION_SPEC \
687 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
688
689 /* A spec that infers a -mips argument from an -march argument,
690 or injects the default if no architecture is specified. */
691
692 #define MIPS_ISA_LEVEL_SPEC \
693 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
694 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
695 %{march=mips2|march=r6000:-mips2} \
696 %{march=mips3|march=r4*|march=vr4*|march=orion|march=loongson2*:-mips3} \
697 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000:-mips4} \
698 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
699 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
700 |march=34k*|march=74k*: -mips32r2} \
701 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000: -mips64} \
702 %{march=mips64r2|march=octeon: -mips64r2} \
703 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
704
705 /* A spec that infers a -mhard-float or -msoft-float setting from an
706 -march argument. Note that soft-float and hard-float code are not
707 link-compatible. */
708
709 #define MIPS_ARCH_FLOAT_SPEC \
710 "%{mhard-float|msoft-float|march=mips*:; \
711 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
712 |march=34kc|march=74kc|march=5kc|march=octeon: -msoft-float; \
713 march=*: -mhard-float}"
714
715 /* A spec condition that matches 32-bit options. It only works if
716 MIPS_ISA_LEVEL_SPEC has been applied. */
717
718 #define MIPS_32BIT_OPTION_SPEC \
719 "mips1|mips2|mips32*|mgp32"
720
721 /* Support for a compile-time default CPU, et cetera. The rules are:
722 --with-arch is ignored if -march is specified or a -mips is specified
723 (other than -mips16).
724 --with-tune is ignored if -mtune is specified.
725 --with-abi is ignored if -mabi is specified.
726 --with-float is ignored if -mhard-float or -msoft-float are
727 specified.
728 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
729 specified. */
730 #define OPTION_DEFAULT_SPECS \
731 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
732 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
733 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
734 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
735 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
736 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
737 {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }
738
739
740 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
741 && ISA_HAS_COND_TRAP)
742
743 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY && !TARGET_MIPS16)
744
745 /* True if the ABI can only work with 64-bit integer registers. We
746 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
747 otherwise floating-point registers must also be 64-bit. */
748 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
749
750 /* Likewise for 32-bit regs. */
751 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
752
753 /* True if symbols are 64 bits wide. At present, n64 is the only
754 ABI for which this is true. */
755 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
756
757 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
758 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
759 || ISA_MIPS4 \
760 || ISA_MIPS64 \
761 || ISA_MIPS64R2)
762
763 /* ISA has branch likely instructions (e.g. mips2). */
764 /* Disable branchlikely for tx39 until compare rewrite. They haven't
765 been generated up to this point. */
766 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
767
768 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
769 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
770 || TARGET_MIPS5400 \
771 || TARGET_MIPS5500 \
772 || TARGET_MIPS7000 \
773 || TARGET_MIPS9000 \
774 || TARGET_MAD \
775 || ISA_MIPS32 \
776 || ISA_MIPS32R2 \
777 || ISA_MIPS64 \
778 || ISA_MIPS64R2) \
779 && !TARGET_MIPS16)
780
781 /* ISA has a three-operand multiplication instruction. */
782 #define ISA_HAS_DMUL3 (TARGET_64BIT && TARGET_OCTEON)
783
784 /* ISA has the floating-point conditional move instructions introduced
785 in mips4. */
786 #define ISA_HAS_FP_CONDMOVE ((ISA_MIPS4 \
787 || ISA_MIPS32 \
788 || ISA_MIPS32R2 \
789 || ISA_MIPS64 \
790 || ISA_MIPS64R2) \
791 && !TARGET_MIPS5500 \
792 && !TARGET_MIPS16)
793
794 /* ISA has the integer conditional move instructions introduced in mips4 and
795 ST Loongson 2E/2F. */
796 #define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
797
798 /* ISA has LDC1 and SDC1. */
799 #define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
800
801 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
802 branch on CC, and move (both FP and non-FP) on CC. */
803 #define ISA_HAS_8CC (ISA_MIPS4 \
804 || ISA_MIPS32 \
805 || ISA_MIPS32R2 \
806 || ISA_MIPS64 \
807 || ISA_MIPS64R2)
808
809 /* This is a catch all for other mips4 instructions: indexed load, the
810 FP madd and msub instructions, and the FP recip and recip sqrt
811 instructions. */
812 #define ISA_HAS_FP4 ((ISA_MIPS4 \
813 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
814 || ISA_MIPS64 \
815 || ISA_MIPS64R2) \
816 && !TARGET_MIPS16)
817
818 /* ISA has paired-single instructions. */
819 #define ISA_HAS_PAIRED_SINGLE (ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
820
821 /* ISA has conditional trap instructions. */
822 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
823 && !TARGET_MIPS16)
824
825 /* ISA has integer multiply-accumulate instructions, madd and msub. */
826 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
827 || ISA_MIPS32R2 \
828 || ISA_MIPS64 \
829 || ISA_MIPS64R2) \
830 && !TARGET_MIPS16)
831
832 /* Integer multiply-accumulate instructions should be generated. */
833 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
834
835 /* ISA has floating-point madd and msub instructions 'd = a * b [+-] c'. */
836 #define ISA_HAS_FP_MADD4_MSUB4 ISA_HAS_FP4
837
838 /* ISA has floating-point madd and msub instructions 'c = a * b [+-] c'. */
839 #define ISA_HAS_FP_MADD3_MSUB3 TARGET_LOONGSON_2EF
840
841 /* ISA has floating-point nmadd and nmsub instructions
842 'd = -((a * b) [+-] c)'. */
843 #define ISA_HAS_NMADD4_NMSUB4(MODE) \
844 ((ISA_MIPS4 \
845 || (ISA_MIPS32R2 && (MODE) == V2SFmode) \
846 || ISA_MIPS64 \
847 || ISA_MIPS64R2) \
848 && (!TARGET_MIPS5400 || TARGET_MAD) \
849 && !TARGET_MIPS16)
850
851 /* ISA has floating-point nmadd and nmsub instructions
852 'c = -((a * b) [+-] c)'. */
853 #define ISA_HAS_NMADD3_NMSUB3(MODE) \
854 TARGET_LOONGSON_2EF
855
856 /* ISA has count leading zeroes/ones instruction (not implemented). */
857 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
858 || ISA_MIPS32R2 \
859 || ISA_MIPS64 \
860 || ISA_MIPS64R2) \
861 && !TARGET_MIPS16)
862
863 /* ISA has three operand multiply instructions that put
864 the high part in an accumulator: mulhi or mulhiu. */
865 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
866 || TARGET_MIPS5500 \
867 || TARGET_SR71K) \
868 && !TARGET_MIPS16)
869
870 /* ISA has three operand multiply instructions that
871 negates the result and puts the result in an accumulator. */
872 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
873 || TARGET_MIPS5500 \
874 || TARGET_SR71K) \
875 && !TARGET_MIPS16)
876
877 /* ISA has three operand multiply instructions that subtracts the
878 result from a 4th operand and puts the result in an accumulator. */
879 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
880 || TARGET_MIPS5500 \
881 || TARGET_SR71K) \
882 && !TARGET_MIPS16)
883
884 /* ISA has three operand multiply instructions that the result
885 from a 4th operand and puts the result in an accumulator. */
886 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
887 || TARGET_MIPS4130 \
888 || TARGET_MIPS5400 \
889 || TARGET_MIPS5500 \
890 || TARGET_SR71K) \
891 && !TARGET_MIPS16)
892
893 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
894 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
895 || TARGET_MIPS4130) \
896 && !TARGET_MIPS16)
897
898 /* ISA has the "ror" (rotate right) instructions. */
899 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
900 || ISA_MIPS64R2 \
901 || TARGET_MIPS5400 \
902 || TARGET_MIPS5500 \
903 || TARGET_SR71K \
904 || TARGET_SMARTMIPS) \
905 && !TARGET_MIPS16)
906
907 /* ISA has data prefetch instructions. This controls use of 'pref'. */
908 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
909 || ISA_MIPS32 \
910 || ISA_MIPS32R2 \
911 || ISA_MIPS64 \
912 || ISA_MIPS64R2) \
913 && !TARGET_MIPS16)
914
915 /* ISA has data indexed prefetch instructions. This controls use of
916 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
917 (prefx is a cop1x instruction, so can only be used if FP is
918 enabled.) */
919 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
920 || ISA_MIPS32R2 \
921 || ISA_MIPS64 \
922 || ISA_MIPS64R2) \
923 && !TARGET_MIPS16)
924
925 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
926 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
927 also requires TARGET_DOUBLE_FLOAT. */
928 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
929
930 /* ISA includes the MIPS32r2 seb and seh instructions. */
931 #define ISA_HAS_SEB_SEH ((ISA_MIPS32R2 \
932 || ISA_MIPS64R2) \
933 && !TARGET_MIPS16)
934
935 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
936 #define ISA_HAS_EXT_INS ((ISA_MIPS32R2 \
937 || ISA_MIPS64R2) \
938 && !TARGET_MIPS16)
939
940 /* ISA has instructions for accessing top part of 64-bit fp regs. */
941 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 \
942 && (ISA_MIPS32R2 \
943 || ISA_MIPS64R2))
944
945 /* ISA has lwxs instruction (load w/scaled index address. */
946 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
947
948 /* The DSP ASE is available. */
949 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
950
951 /* Revision 2 of the DSP ASE is available. */
952 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
953
954 /* True if the result of a load is not available to the next instruction.
955 A nop will then be needed between instructions like "lw $4,..."
956 and "addiu $4,$4,1". */
957 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
958 && !TARGET_MIPS3900 \
959 && !TARGET_MIPS16)
960
961 /* Likewise mtc1 and mfc1. */
962 #define ISA_HAS_XFER_DELAY (mips_isa <= 3 \
963 && !TARGET_LOONGSON_2EF)
964
965 /* Likewise floating-point comparisons. */
966 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \
967 && !TARGET_LOONGSON_2EF)
968
969 /* True if mflo and mfhi can be immediately followed by instructions
970 which write to the HI and LO registers.
971
972 According to MIPS specifications, MIPS ISAs I, II, and III need
973 (at least) two instructions between the reads of HI/LO and
974 instructions which write them, and later ISAs do not. Contradicting
975 the MIPS specifications, some MIPS IV processor user manuals (e.g.
976 the UM for the NEC Vr5000) document needing the instructions between
977 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
978 MIPS64 and later ISAs to have the interlocks, plus any specific
979 earlier-ISA CPUs for which CPU documentation declares that the
980 instructions are really interlocked. */
981 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
982 || ISA_MIPS32R2 \
983 || ISA_MIPS64 \
984 || ISA_MIPS64R2 \
985 || TARGET_MIPS5500 \
986 || TARGET_LOONGSON_2EF)
987
988 /* ISA includes synci, jr.hb and jalr.hb. */
989 #define ISA_HAS_SYNCI ((ISA_MIPS32R2 \
990 || ISA_MIPS64R2) \
991 && !TARGET_MIPS16)
992
993 /* ISA includes sync. */
994 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
995 #define GENERATE_SYNC \
996 (target_flags_explicit & MASK_LLSC \
997 ? TARGET_LLSC && !TARGET_MIPS16 \
998 : ISA_HAS_SYNC)
999
1000 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
1001 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
1002 instructions. */
1003 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
1004 #define GENERATE_LL_SC \
1005 (target_flags_explicit & MASK_LLSC \
1006 ? TARGET_LLSC && !TARGET_MIPS16 \
1007 : ISA_HAS_LL_SC)
1008
1009 /* ISA includes the bbit* instructions. */
1010 #define ISA_HAS_BBIT TARGET_OCTEON
1011
1012 /* ISA includes the cins instruction. */
1013 #define ISA_HAS_CINS TARGET_OCTEON
1014
1015 /* ISA includes the pop instruction. */
1016 #define ISA_HAS_POP TARGET_OCTEON
1017 \f
1018 /* Add -G xx support. */
1019
1020 #undef SWITCH_TAKES_ARG
1021 #define SWITCH_TAKES_ARG(CHAR) \
1022 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
1023
1024 #define OVERRIDE_OPTIONS mips_override_options ()
1025
1026 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
1027
1028 /* Show we can debug even without a frame pointer. */
1029 #define CAN_DEBUG_WITHOUT_FP
1030 \f
1031 /* Tell collect what flags to pass to nm. */
1032 #ifndef NM_FLAGS
1033 #define NM_FLAGS "-Bn"
1034 #endif
1035
1036 \f
1037 #ifndef MIPS_ABI_DEFAULT
1038 #define MIPS_ABI_DEFAULT ABI_32
1039 #endif
1040
1041 /* Use the most portable ABI flag for the ASM specs. */
1042
1043 #if MIPS_ABI_DEFAULT == ABI_32
1044 #define MULTILIB_ABI_DEFAULT "mabi=32"
1045 #endif
1046
1047 #if MIPS_ABI_DEFAULT == ABI_O64
1048 #define MULTILIB_ABI_DEFAULT "mabi=o64"
1049 #endif
1050
1051 #if MIPS_ABI_DEFAULT == ABI_N32
1052 #define MULTILIB_ABI_DEFAULT "mabi=n32"
1053 #endif
1054
1055 #if MIPS_ABI_DEFAULT == ABI_64
1056 #define MULTILIB_ABI_DEFAULT "mabi=64"
1057 #endif
1058
1059 #if MIPS_ABI_DEFAULT == ABI_EABI
1060 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1061 #endif
1062
1063 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1064 to the assembler. It may be overridden by subtargets. */
1065 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1066 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1067 %{noasmopt:-O0} \
1068 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1069 #endif
1070
1071 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1072 the assembler. It may be overridden by subtargets.
1073
1074 Beginning with gas 2.13, -mdebug must be passed to correctly handle
1075 COFF debugging info. */
1076
1077 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1078 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1079 %{g} %{g0} %{g1} %{g2} %{g3} \
1080 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1081 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1082 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1083 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1084 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
1085 #endif
1086
1087 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1088 overridden by subtargets. */
1089
1090 #ifndef SUBTARGET_ASM_SPEC
1091 #define SUBTARGET_ASM_SPEC ""
1092 #endif
1093
1094 #undef ASM_SPEC
1095 #define ASM_SPEC "\
1096 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1097 %{mips32*} %{mips64*} \
1098 %{mips16} %{mno-mips16:-no-mips16} \
1099 %{mips3d} %{mno-mips3d:-no-mips3d} \
1100 %{mdmx} %{mno-mdmx:-no-mdmx} \
1101 %{mdsp} %{mno-dsp} \
1102 %{mdspr2} %{mno-dspr2} \
1103 %{msmartmips} %{mno-smartmips} \
1104 %{mmt} %{mno-mt} \
1105 %{mfix-vr4120} %{mfix-vr4130} \
1106 %(subtarget_asm_optimizing_spec) \
1107 %(subtarget_asm_debugging_spec) \
1108 %{mabi=*} %{!mabi=*: %(asm_abi_default_spec)} \
1109 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1110 %{mfp32} %{mfp64} \
1111 %{mshared} %{mno-shared} \
1112 %{msym32} %{mno-sym32} \
1113 %{mtune=*} %{v} \
1114 %(subtarget_asm_spec)"
1115
1116 /* Extra switches sometimes passed to the linker. */
1117 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1118 will interpret it as a -b option. */
1119
1120 #ifndef LINK_SPEC
1121 #define LINK_SPEC "\
1122 %(endian_spec) \
1123 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32*} %{mips64*} \
1124 %{bestGnum} %{shared} %{non_shared}"
1125 #endif /* LINK_SPEC defined */
1126
1127
1128 /* Specs for the compiler proper */
1129
1130 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1131 overridden by subtargets. */
1132 #ifndef SUBTARGET_CC1_SPEC
1133 #define SUBTARGET_CC1_SPEC ""
1134 #endif
1135
1136 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1137
1138 #undef CC1_SPEC
1139 #define CC1_SPEC "\
1140 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1141 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1142 %{save-temps: } \
1143 %(subtarget_cc1_spec)"
1144
1145 /* Preprocessor specs. */
1146
1147 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1148 overridden by subtargets. */
1149 #ifndef SUBTARGET_CPP_SPEC
1150 #define SUBTARGET_CPP_SPEC ""
1151 #endif
1152
1153 #define CPP_SPEC "%(subtarget_cpp_spec)"
1154
1155 /* This macro defines names of additional specifications to put in the specs
1156 that can be used in various specifications like CC1_SPEC. Its definition
1157 is an initializer with a subgrouping for each command option.
1158
1159 Each subgrouping contains a string constant, that defines the
1160 specification name, and a string constant that used by the GCC driver
1161 program.
1162
1163 Do not define this macro if it does not need to do anything. */
1164
1165 #define EXTRA_SPECS \
1166 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1167 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1168 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1169 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1170 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1171 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1172 { "endian_spec", ENDIAN_SPEC }, \
1173 SUBTARGET_EXTRA_SPECS
1174
1175 #ifndef SUBTARGET_EXTRA_SPECS
1176 #define SUBTARGET_EXTRA_SPECS
1177 #endif
1178 \f
1179 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1180 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1181
1182 #ifndef PREFERRED_DEBUGGING_TYPE
1183 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1184 #endif
1185
1186 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
1187
1188 /* By default, turn on GDB extensions. */
1189 #define DEFAULT_GDB_EXTENSIONS 1
1190
1191 /* Local compiler-generated symbols must have a prefix that the assembler
1192 understands. By default, this is $, although some targets (e.g.,
1193 NetBSD-ELF) need to override this. */
1194
1195 #ifndef LOCAL_LABEL_PREFIX
1196 #define LOCAL_LABEL_PREFIX "$"
1197 #endif
1198
1199 /* By default on the mips, external symbols do not have an underscore
1200 prepended, but some targets (e.g., NetBSD) require this. */
1201
1202 #ifndef USER_LABEL_PREFIX
1203 #define USER_LABEL_PREFIX ""
1204 #endif
1205
1206 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1207 since the length can run past this up to a continuation point. */
1208 #undef DBX_CONTIN_LENGTH
1209 #define DBX_CONTIN_LENGTH 1500
1210
1211 /* How to renumber registers for dbx and gdb. */
1212 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1213
1214 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1215 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1216
1217 /* The DWARF 2 CFA column which tracks the return address. */
1218 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1219
1220 /* Before the prologue, RA lives in r31. */
1221 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1222
1223 /* Describe how we implement __builtin_eh_return. */
1224 #define EH_RETURN_DATA_REGNO(N) \
1225 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1226
1227 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1228
1229 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1230 The default for this in 64-bit mode is 8, which causes problems with
1231 SFmode register saves. */
1232 #define DWARF_CIE_DATA_ALIGNMENT -4
1233
1234 /* Correct the offset of automatic variables and arguments. Note that
1235 the MIPS debug format wants all automatic variables and arguments
1236 to be in terms of the virtual frame pointer (stack pointer before
1237 any adjustment in the function), while the MIPS 3.0 linker wants
1238 the frame pointer to be the stack pointer after the initial
1239 adjustment. */
1240
1241 #define DEBUGGER_AUTO_OFFSET(X) \
1242 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1243 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1244 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1245 \f
1246 /* Target machine storage layout */
1247
1248 #define BITS_BIG_ENDIAN 0
1249 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1250 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1251
1252 /* Define this to set the endianness to use in libgcc2.c, which can
1253 not depend on target_flags. */
1254 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1255 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1256 #else
1257 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1258 #endif
1259
1260 #define MAX_BITS_PER_WORD 64
1261
1262 /* Width of a word, in units (bytes). */
1263 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1264 #ifndef IN_LIBGCC2
1265 #define MIN_UNITS_PER_WORD 4
1266 #endif
1267
1268 /* For MIPS, width of a floating point register. */
1269 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1270
1271 /* The number of consecutive floating-point registers needed to store the
1272 largest format supported by the FPU. */
1273 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1274
1275 /* The number of consecutive floating-point registers needed to store the
1276 smallest format supported by the FPU. */
1277 #define MIN_FPRS_PER_FMT \
1278 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2 \
1279 ? 1 : MAX_FPRS_PER_FMT)
1280
1281 /* The largest size of value that can be held in floating-point
1282 registers and moved with a single instruction. */
1283 #define UNITS_PER_HWFPVALUE \
1284 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1285
1286 /* The largest size of value that can be held in floating-point
1287 registers. */
1288 #define UNITS_PER_FPVALUE \
1289 (TARGET_SOFT_FLOAT_ABI ? 0 \
1290 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1291 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1292
1293 /* The number of bytes in a double. */
1294 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1295
1296 #define UNITS_PER_SIMD_WORD(MODE) \
1297 (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1298
1299 /* Set the sizes of the core types. */
1300 #define SHORT_TYPE_SIZE 16
1301 #define INT_TYPE_SIZE 32
1302 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1303 #define LONG_LONG_TYPE_SIZE 64
1304
1305 #define FLOAT_TYPE_SIZE 32
1306 #define DOUBLE_TYPE_SIZE 64
1307 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1308
1309 /* Define the sizes of fixed-point types. */
1310 #define SHORT_FRACT_TYPE_SIZE 8
1311 #define FRACT_TYPE_SIZE 16
1312 #define LONG_FRACT_TYPE_SIZE 32
1313 #define LONG_LONG_FRACT_TYPE_SIZE 64
1314
1315 #define SHORT_ACCUM_TYPE_SIZE 16
1316 #define ACCUM_TYPE_SIZE 32
1317 #define LONG_ACCUM_TYPE_SIZE 64
1318 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1319 doesn't support 128-bit integers for MIPS32 currently. */
1320 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1321
1322 /* long double is not a fixed mode, but the idea is that, if we
1323 support long double, we also want a 128-bit integer type. */
1324 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1325
1326 #ifdef IN_LIBGCC2
1327 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1328 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1329 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1330 # else
1331 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1332 # endif
1333 #endif
1334
1335 /* Width in bits of a pointer. */
1336 #ifndef POINTER_SIZE
1337 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1338 #endif
1339
1340 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1341 #define PARM_BOUNDARY BITS_PER_WORD
1342
1343 /* Allocation boundary (in *bits*) for the code of a function. */
1344 #define FUNCTION_BOUNDARY 32
1345
1346 /* Alignment of field after `int : 0' in a structure. */
1347 #define EMPTY_FIELD_BOUNDARY 32
1348
1349 /* Every structure's size must be a multiple of this. */
1350 /* 8 is observed right on a DECstation and on riscos 4.02. */
1351 #define STRUCTURE_SIZE_BOUNDARY 8
1352
1353 /* There is no point aligning anything to a rounder boundary than this. */
1354 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1355
1356 /* All accesses must be aligned. */
1357 #define STRICT_ALIGNMENT 1
1358
1359 /* Define this if you wish to imitate the way many other C compilers
1360 handle alignment of bitfields and the structures that contain
1361 them.
1362
1363 The behavior is that the type written for a bit-field (`int',
1364 `short', or other integer type) imposes an alignment for the
1365 entire structure, as if the structure really did contain an
1366 ordinary field of that type. In addition, the bit-field is placed
1367 within the structure so that it would fit within such a field,
1368 not crossing a boundary for it.
1369
1370 Thus, on most machines, a bit-field whose type is written as `int'
1371 would not cross a four-byte boundary, and would force four-byte
1372 alignment for the whole structure. (The alignment used may not
1373 be four bytes; it is controlled by the other alignment
1374 parameters.)
1375
1376 If the macro is defined, its definition should be a C expression;
1377 a nonzero value for the expression enables this behavior. */
1378
1379 #define PCC_BITFIELD_TYPE_MATTERS 1
1380
1381 /* If defined, a C expression to compute the alignment given to a
1382 constant that is being placed in memory. CONSTANT is the constant
1383 and ALIGN is the alignment that the object would ordinarily have.
1384 The value of this macro is used instead of that alignment to align
1385 the object.
1386
1387 If this macro is not defined, then ALIGN is used.
1388
1389 The typical use of this macro is to increase alignment for string
1390 constants to be word aligned so that `strcpy' calls that copy
1391 constants can be done inline. */
1392
1393 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1394 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1395 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1396
1397 /* If defined, a C expression to compute the alignment for a static
1398 variable. TYPE is the data type, and ALIGN is the alignment that
1399 the object would ordinarily have. The value of this macro is used
1400 instead of that alignment to align the object.
1401
1402 If this macro is not defined, then ALIGN is used.
1403
1404 One use of this macro is to increase alignment of medium-size
1405 data to make it all fit in fewer cache lines. Another is to
1406 cause character arrays to be word-aligned so that `strcpy' calls
1407 that copy constants to character arrays can be done inline. */
1408
1409 #undef DATA_ALIGNMENT
1410 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1411 ((((ALIGN) < BITS_PER_WORD) \
1412 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1413 || TREE_CODE (TYPE) == UNION_TYPE \
1414 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1415
1416 /* We need this for the same reason as DATA_ALIGNMENT, namely to cause
1417 character arrays to be word-aligned so that `strcpy' calls that copy
1418 constants to character arrays can be done inline, and 'strcmp' can be
1419 optimised to use word loads. */
1420 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
1421 DATA_ALIGNMENT (TYPE, ALIGN)
1422
1423 #define PAD_VARARGS_DOWN \
1424 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1425
1426 /* Define if operations between registers always perform the operation
1427 on the full register even if a narrower mode is specified. */
1428 #define WORD_REGISTER_OPERATIONS
1429
1430 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1431 moves. All other references are zero extended. */
1432 #define LOAD_EXTEND_OP(MODE) \
1433 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1434 ? SIGN_EXTEND : ZERO_EXTEND)
1435
1436 /* Define this macro if it is advisable to hold scalars in registers
1437 in a wider mode than that declared by the program. In such cases,
1438 the value is constrained to be within the bounds of the declared
1439 type, but kept valid in the wider mode. The signedness of the
1440 extension may differ from that of the type. */
1441
1442 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1443 if (GET_MODE_CLASS (MODE) == MODE_INT \
1444 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1445 { \
1446 if ((MODE) == SImode) \
1447 (UNSIGNEDP) = 0; \
1448 (MODE) = Pmode; \
1449 }
1450
1451 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1452 Extensions of pointers to word_mode must be signed. */
1453 #define POINTERS_EXTEND_UNSIGNED false
1454
1455 /* Define if loading short immediate values into registers sign extends. */
1456 #define SHORT_IMMEDIATES_SIGN_EXTEND
1457
1458 /* The [d]clz instructions have the natural values at 0. */
1459
1460 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1461 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1462 \f
1463 /* Standard register usage. */
1464
1465 /* Number of hardware registers. We have:
1466
1467 - 32 integer registers
1468 - 32 floating point registers
1469 - 8 condition code registers
1470 - 2 accumulator registers (hi and lo)
1471 - 32 registers each for coprocessors 0, 2 and 3
1472 - 3 fake registers:
1473 - ARG_POINTER_REGNUM
1474 - FRAME_POINTER_REGNUM
1475 - GOT_VERSION_REGNUM (see the comment above load_call<mode> for details)
1476 - 3 dummy entries that were used at various times in the past.
1477 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1478 - 6 DSP control registers */
1479
1480 #define FIRST_PSEUDO_REGISTER 188
1481
1482 /* By default, fix the kernel registers ($26 and $27), the global
1483 pointer ($28) and the stack pointer ($29). This can change
1484 depending on the command-line options.
1485
1486 Regarding coprocessor registers: without evidence to the contrary,
1487 it's best to assume that each coprocessor register has a unique
1488 use. This can be overridden, in, e.g., mips_override_options or
1489 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1490 for a particular target. */
1491
1492 #define FIXED_REGISTERS \
1493 { \
1494 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1495 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1496 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1497 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1498 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1499 /* COP0 registers */ \
1500 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1501 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1502 /* COP2 registers */ \
1503 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1504 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1505 /* COP3 registers */ \
1506 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1507 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1508 /* 6 DSP accumulator registers & 6 control registers */ \
1509 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1510 }
1511
1512
1513 /* Set up this array for o32 by default.
1514
1515 Note that we don't mark $31 as a call-clobbered register. The idea is
1516 that it's really the call instructions themselves which clobber $31.
1517 We don't care what the called function does with it afterwards.
1518
1519 This approach makes it easier to implement sibcalls. Unlike normal
1520 calls, sibcalls don't clobber $31, so the register reaches the
1521 called function in tact. EPILOGUE_USES says that $31 is useful
1522 to the called function. */
1523
1524 #define CALL_USED_REGISTERS \
1525 { \
1526 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1527 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1528 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1529 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1530 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1531 /* COP0 registers */ \
1532 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1533 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1534 /* COP2 registers */ \
1535 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1536 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1537 /* COP3 registers */ \
1538 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1539 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1540 /* 6 DSP accumulator registers & 6 control registers */ \
1541 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1542 }
1543
1544
1545 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1546
1547 #define CALL_REALLY_USED_REGISTERS \
1548 { /* General registers. */ \
1549 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1550 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1551 /* Floating-point registers. */ \
1552 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1553 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1554 /* Others. */ \
1555 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
1556 /* COP0 registers */ \
1557 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1558 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1559 /* COP2 registers */ \
1560 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1561 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1562 /* COP3 registers */ \
1563 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1564 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1565 /* 6 DSP accumulator registers & 6 control registers */ \
1566 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1567 }
1568
1569 /* Internal macros to classify a register number as to whether it's a
1570 general purpose register, a floating point register, a
1571 multiply/divide register, or a status register. */
1572
1573 #define GP_REG_FIRST 0
1574 #define GP_REG_LAST 31
1575 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1576 #define GP_DBX_FIRST 0
1577
1578 #define FP_REG_FIRST 32
1579 #define FP_REG_LAST 63
1580 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1581 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1582
1583 #define MD_REG_FIRST 64
1584 #define MD_REG_LAST 65
1585 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1586 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1587
1588 /* The DWARF 2 CFA column which tracks the return address from a
1589 signal handler context. This means that to maintain backwards
1590 compatibility, no hard register can be assigned this column if it
1591 would need to be handled by the DWARF unwinder. */
1592 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1593
1594 #define ST_REG_FIRST 67
1595 #define ST_REG_LAST 74
1596 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1597
1598
1599 /* FIXME: renumber. */
1600 #define COP0_REG_FIRST 80
1601 #define COP0_REG_LAST 111
1602 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1603
1604 #define COP2_REG_FIRST 112
1605 #define COP2_REG_LAST 143
1606 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1607
1608 #define COP3_REG_FIRST 144
1609 #define COP3_REG_LAST 175
1610 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1611 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1612 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1613
1614 #define DSP_ACC_REG_FIRST 176
1615 #define DSP_ACC_REG_LAST 181
1616 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1617
1618 #define AT_REGNUM (GP_REG_FIRST + 1)
1619 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1620 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1621
1622 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1623 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1624 should be used instead. */
1625 #define FPSW_REGNUM ST_REG_FIRST
1626
1627 #define GP_REG_P(REGNO) \
1628 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1629 #define M16_REG_P(REGNO) \
1630 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1631 #define FP_REG_P(REGNO) \
1632 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1633 #define MD_REG_P(REGNO) \
1634 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1635 #define ST_REG_P(REGNO) \
1636 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1637 #define COP0_REG_P(REGNO) \
1638 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1639 #define COP2_REG_P(REGNO) \
1640 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1641 #define COP3_REG_P(REGNO) \
1642 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1643 #define ALL_COP_REG_P(REGNO) \
1644 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1645 /* Test if REGNO is one of the 6 new DSP accumulators. */
1646 #define DSP_ACC_REG_P(REGNO) \
1647 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1648 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1649 #define ACC_REG_P(REGNO) \
1650 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1651
1652 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1653
1654 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1655 to initialize the mips16 gp pseudo register. */
1656 #define CONST_GP_P(X) \
1657 (GET_CODE (X) == CONST \
1658 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1659 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1660
1661 /* Return coprocessor number from register number. */
1662
1663 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1664 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1665 : COP3_REG_P (REGNO) ? '3' : '?')
1666
1667
1668 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1669
1670 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1671 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1672
1673 #define MODES_TIEABLE_P mips_modes_tieable_p
1674
1675 /* Register to use for pushing function arguments. */
1676 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1677
1678 /* These two registers don't really exist: they get eliminated to either
1679 the stack or hard frame pointer. */
1680 #define ARG_POINTER_REGNUM 77
1681 #define FRAME_POINTER_REGNUM 78
1682
1683 /* $30 is not available on the mips16, so we use $17 as the frame
1684 pointer. */
1685 #define HARD_FRAME_POINTER_REGNUM \
1686 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1687
1688 #define FRAME_POINTER_REQUIRED (mips_frame_pointer_required ())
1689
1690 /* Register in which static-chain is passed to a function. */
1691 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 15)
1692
1693 /* Registers used as temporaries in prologue/epilogue code:
1694
1695 - If a MIPS16 PIC function needs access to _gp, it first loads
1696 the value into MIPS16_PIC_TEMP and then copies it to $gp.
1697
1698 - The prologue can use MIPS_PROLOGUE_TEMP as a general temporary
1699 register. The register must not conflict with MIPS16_PIC_TEMP.
1700
1701 - The epilogue can use MIPS_EPILOGUE_TEMP as a general temporary
1702 register.
1703
1704 If we're generating MIPS16 code, these registers must come from the
1705 core set of 8. The prologue registers mustn't conflict with any
1706 incoming arguments, the static chain pointer, or the frame pointer.
1707 The epilogue temporary mustn't conflict with the return registers,
1708 the PIC call register ($25), the frame pointer, the EH stack adjustment,
1709 or the EH data registers. */
1710
1711 #define MIPS16_PIC_TEMP_REGNUM (GP_REG_FIRST + 2)
1712 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1713 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1714
1715 #define MIPS16_PIC_TEMP gen_rtx_REG (Pmode, MIPS16_PIC_TEMP_REGNUM)
1716 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1717 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1718
1719 /* Define this macro if it is as good or better to call a constant
1720 function address than to call an address kept in a register. */
1721 #define NO_FUNCTION_CSE 1
1722
1723 /* The ABI-defined global pointer. Sometimes we use a different
1724 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1725 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1726
1727 /* We normally use $28 as the global pointer. However, when generating
1728 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1729 register instead. They can then avoid saving and restoring $28
1730 and perhaps avoid using a frame at all.
1731
1732 When a leaf function uses something other than $28, mips_expand_prologue
1733 will modify pic_offset_table_rtx in place. Take the register number
1734 from there after reload. */
1735 #define PIC_OFFSET_TABLE_REGNUM \
1736 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1737
1738 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1739 \f
1740 /* Define the classes of registers for register constraints in the
1741 machine description. Also define ranges of constants.
1742
1743 One of the classes must always be named ALL_REGS and include all hard regs.
1744 If there is more than one class, another class must be named NO_REGS
1745 and contain no registers.
1746
1747 The name GENERAL_REGS must be the name of a class (or an alias for
1748 another name such as ALL_REGS). This is the class of registers
1749 that is allowed by "g" or "r" in a register constraint.
1750 Also, registers outside this class are allocated only when
1751 instructions express preferences for them.
1752
1753 The classes must be numbered in nondecreasing order; that is,
1754 a larger-numbered class must never be contained completely
1755 in a smaller-numbered class.
1756
1757 For any two classes, it is very desirable that there be another
1758 class that represents their union. */
1759
1760 enum reg_class
1761 {
1762 NO_REGS, /* no registers in set */
1763 M16_REGS, /* mips16 directly accessible registers */
1764 T_REG, /* mips16 T register ($24) */
1765 M16_T_REGS, /* mips16 registers plus T register */
1766 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1767 V1_REG, /* Register $v1 ($3) used for TLS access. */
1768 LEA_REGS, /* Every GPR except $25 */
1769 GR_REGS, /* integer registers */
1770 FP_REGS, /* floating point registers */
1771 MD0_REG, /* first multiply/divide register */
1772 MD1_REG, /* second multiply/divide register */
1773 MD_REGS, /* multiply/divide registers (hi/lo) */
1774 COP0_REGS, /* generic coprocessor classes */
1775 COP2_REGS,
1776 COP3_REGS,
1777 HI_AND_GR_REGS, /* union classes */
1778 LO_AND_GR_REGS,
1779 HI_AND_FP_REGS,
1780 COP0_AND_GR_REGS,
1781 COP2_AND_GR_REGS,
1782 COP3_AND_GR_REGS,
1783 ALL_COP_REGS,
1784 ALL_COP_AND_GR_REGS,
1785 ST_REGS, /* status registers (fp status) */
1786 DSP_ACC_REGS, /* DSP accumulator registers */
1787 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1788 ALL_REGS, /* all registers */
1789 LIM_REG_CLASSES /* max value + 1 */
1790 };
1791
1792 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1793
1794 #define GENERAL_REGS GR_REGS
1795
1796 /* An initializer containing the names of the register classes as C
1797 string constants. These names are used in writing some of the
1798 debugging dumps. */
1799
1800 #define REG_CLASS_NAMES \
1801 { \
1802 "NO_REGS", \
1803 "M16_REGS", \
1804 "T_REG", \
1805 "M16_T_REGS", \
1806 "PIC_FN_ADDR_REG", \
1807 "V1_REG", \
1808 "LEA_REGS", \
1809 "GR_REGS", \
1810 "FP_REGS", \
1811 "MD0_REG", \
1812 "MD1_REG", \
1813 "MD_REGS", \
1814 /* coprocessor registers */ \
1815 "COP0_REGS", \
1816 "COP2_REGS", \
1817 "COP3_REGS", \
1818 "HI_AND_GR_REGS", \
1819 "LO_AND_GR_REGS", \
1820 "HI_AND_FP_REGS", \
1821 "COP0_AND_GR_REGS", \
1822 "COP2_AND_GR_REGS", \
1823 "COP3_AND_GR_REGS", \
1824 "ALL_COP_REGS", \
1825 "ALL_COP_AND_GR_REGS", \
1826 "ST_REGS", \
1827 "DSP_ACC_REGS", \
1828 "ACC_REGS", \
1829 "ALL_REGS" \
1830 }
1831
1832 /* An initializer containing the contents of the register classes,
1833 as integers which are bit masks. The Nth integer specifies the
1834 contents of class N. The way the integer MASK is interpreted is
1835 that register R is in the class if `MASK & (1 << R)' is 1.
1836
1837 When the machine has more than 32 registers, an integer does not
1838 suffice. Then the integers are replaced by sub-initializers,
1839 braced groupings containing several integers. Each
1840 sub-initializer must be suitable as an initializer for the type
1841 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1842
1843 #define REG_CLASS_CONTENTS \
1844 { \
1845 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1846 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1847 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1848 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1849 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1850 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \
1851 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \
1852 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1853 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1854 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1855 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1856 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1857 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1858 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1859 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1860 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1861 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1862 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1863 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1864 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1865 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1866 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1867 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1868 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1869 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \
1870 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \
1871 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \
1872 }
1873
1874
1875 /* A C expression whose value is a register class containing hard
1876 register REGNO. In general there is more that one such class;
1877 choose a class which is "minimal", meaning that no smaller class
1878 also contains the register. */
1879
1880 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1881
1882 /* A macro whose definition is the name of the class to which a
1883 valid base register must belong. A base register is one used in
1884 an address which is the register value plus a displacement. */
1885
1886 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1887
1888 /* A macro whose definition is the name of the class to which a
1889 valid index register must belong. An index register is one used
1890 in an address where its value is either multiplied by a scale
1891 factor or added to another register (as well as added to a
1892 displacement). */
1893
1894 #define INDEX_REG_CLASS NO_REGS
1895
1896 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1897 registers explicitly used in the rtl to be used as spill registers
1898 but prevents the compiler from extending the lifetime of these
1899 registers. */
1900
1901 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1902
1903 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1904 is the default value (allocate the registers in numeric order). We
1905 define it just so that we can override it for the mips16 target in
1906 ORDER_REGS_FOR_LOCAL_ALLOC. */
1907
1908 #define REG_ALLOC_ORDER \
1909 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1910 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1911 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1912 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1913 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1914 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1915 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1916 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1917 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1918 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1919 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1920 176,177,178,179,180,181,182,183,184,185,186,187 \
1921 }
1922
1923 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1924 to be rearranged based on a particular function. On the mips16, we
1925 want to allocate $24 (T_REG) before other registers for
1926 instructions for which it is possible. */
1927
1928 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1929
1930 /* True if VALUE is an unsigned 6-bit number. */
1931
1932 #define UIMM6_OPERAND(VALUE) \
1933 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1934
1935 /* True if VALUE is a signed 10-bit number. */
1936
1937 #define IMM10_OPERAND(VALUE) \
1938 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1939
1940 /* True if VALUE is a signed 16-bit number. */
1941
1942 #define SMALL_OPERAND(VALUE) \
1943 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1944
1945 /* True if VALUE is an unsigned 16-bit number. */
1946
1947 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1948 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1949
1950 /* True if VALUE can be loaded into a register using LUI. */
1951
1952 #define LUI_OPERAND(VALUE) \
1953 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1954 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1955
1956 /* Return a value X with the low 16 bits clear, and such that
1957 VALUE - X is a signed 16-bit value. */
1958
1959 #define CONST_HIGH_PART(VALUE) \
1960 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1961
1962 #define CONST_LOW_PART(VALUE) \
1963 ((VALUE) - CONST_HIGH_PART (VALUE))
1964
1965 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1966 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1967 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1968
1969 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1970 mips_preferred_reload_class (X, CLASS)
1971
1972 /* The HI and LO registers can only be reloaded via the general
1973 registers. Condition code registers can only be loaded to the
1974 general registers, and from the floating point registers. */
1975
1976 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1977 mips_secondary_reload_class (CLASS, MODE, X, true)
1978 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1979 mips_secondary_reload_class (CLASS, MODE, X, false)
1980
1981 /* Return the maximum number of consecutive registers
1982 needed to represent mode MODE in a register of class CLASS. */
1983
1984 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
1985
1986 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1987 mips_cannot_change_mode_class (FROM, TO, CLASS)
1988 \f
1989 /* Stack layout; function entry, exit and calling. */
1990
1991 #define STACK_GROWS_DOWNWARD
1992
1993 /* The offset of the first local variable from the beginning of the frame.
1994 See mips_compute_frame_info for details about the frame layout. */
1995
1996 #define STARTING_FRAME_OFFSET \
1997 (crtl->outgoing_args_size \
1998 + (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1999
2000 #define RETURN_ADDR_RTX mips_return_addr
2001
2002 /* Mask off the MIPS16 ISA bit in unwind addresses.
2003
2004 The reason for this is a little subtle. When unwinding a call,
2005 we are given the call's return address, which on most targets
2006 is the address of the following instruction. However, what we
2007 actually want to find is the EH region for the call itself.
2008 The target-independent unwind code therefore searches for "RA - 1".
2009
2010 In the MIPS16 case, RA is always an odd-valued (ISA-encoded) address.
2011 RA - 1 is therefore the real (even-valued) start of the return
2012 instruction. EH region labels are usually odd-valued MIPS16 symbols
2013 too, so a search for an even address within a MIPS16 region would
2014 usually work.
2015
2016 However, there is an exception. If the end of an EH region is also
2017 the end of a function, the end label is allowed to be even. This is
2018 necessary because a following non-MIPS16 function may also need EH
2019 information for its first instruction.
2020
2021 Thus a MIPS16 region may be terminated by an ISA-encoded or a
2022 non-ISA-encoded address. This probably isn't ideal, but it is
2023 the traditional (legacy) behavior. It is therefore only safe
2024 to search MIPS EH regions for an _odd-valued_ address.
2025
2026 Masking off the ISA bit means that the target-independent code
2027 will search for "(RA & -2) - 1", which is guaranteed to be odd. */
2028 #define MASK_RETURN_ADDR GEN_INT (-2)
2029
2030
2031 /* Similarly, don't use the least-significant bit to tell pointers to
2032 code from vtable index. */
2033
2034 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2035
2036 /* The eliminations to $17 are only used for mips16 code. See the
2037 definition of HARD_FRAME_POINTER_REGNUM. */
2038
2039 #define ELIMINABLE_REGS \
2040 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2041 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2042 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2043 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2044 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2045 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2046
2047 /* Make sure that we're not trying to eliminate to the wrong hard frame
2048 pointer. */
2049 #define CAN_ELIMINATE(FROM, TO) \
2050 ((TO) == HARD_FRAME_POINTER_REGNUM || (TO) == STACK_POINTER_REGNUM)
2051
2052 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2053 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2054
2055 /* Allocate stack space for arguments at the beginning of each function. */
2056 #define ACCUMULATE_OUTGOING_ARGS 1
2057
2058 /* The argument pointer always points to the first argument. */
2059 #define FIRST_PARM_OFFSET(FNDECL) 0
2060
2061 /* o32 and o64 reserve stack space for all argument registers. */
2062 #define REG_PARM_STACK_SPACE(FNDECL) \
2063 (TARGET_OLDABI \
2064 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
2065 : 0)
2066
2067 /* Define this if it is the responsibility of the caller to
2068 allocate the area reserved for arguments passed in registers.
2069 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2070 of this macro is to determine whether the space is included in
2071 `crtl->outgoing_args_size'. */
2072 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
2073
2074 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
2075 \f
2076 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2077
2078 /* Symbolic macros for the registers used to return integer and floating
2079 point values. */
2080
2081 #define GP_RETURN (GP_REG_FIRST + 2)
2082 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2083
2084 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
2085
2086 /* Symbolic macros for the first/last argument registers. */
2087
2088 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2089 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2090 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2091 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2092
2093 #define LIBCALL_VALUE(MODE) \
2094 mips_function_value (NULL_TREE, MODE)
2095
2096 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2097 mips_function_value (VALTYPE, VOIDmode)
2098
2099 /* 1 if N is a possible register number for a function value.
2100 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2101 Currently, R2 and F0 are only implemented here (C has no complex type) */
2102
2103 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2104 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2105 && (N) == FP_RETURN + 2))
2106
2107 /* 1 if N is a possible register number for function argument passing.
2108 We have no FP argument registers when soft-float. When FP registers
2109 are 32 bits, we can't directly reference the odd numbered ones. */
2110
2111 #define FUNCTION_ARG_REGNO_P(N) \
2112 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2113 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2114 && !fixed_regs[N])
2115 \f
2116 /* This structure has to cope with two different argument allocation
2117 schemes. Most MIPS ABIs view the arguments as a structure, of which
2118 the first N words go in registers and the rest go on the stack. If I
2119 < N, the Ith word might go in Ith integer argument register or in a
2120 floating-point register. For these ABIs, we only need to remember
2121 the offset of the current argument into the structure.
2122
2123 The EABI instead allocates the integer and floating-point arguments
2124 separately. The first N words of FP arguments go in FP registers,
2125 the rest go on the stack. Likewise, the first N words of the other
2126 arguments go in integer registers, and the rest go on the stack. We
2127 need to maintain three counts: the number of integer registers used,
2128 the number of floating-point registers used, and the number of words
2129 passed on the stack.
2130
2131 We could keep separate information for the two ABIs (a word count for
2132 the standard ABIs, and three separate counts for the EABI). But it
2133 seems simpler to view the standard ABIs as forms of EABI that do not
2134 allocate floating-point registers.
2135
2136 So for the standard ABIs, the first N words are allocated to integer
2137 registers, and mips_function_arg decides on an argument-by-argument
2138 basis whether that argument should really go in an integer register,
2139 or in a floating-point one. */
2140
2141 typedef struct mips_args {
2142 /* Always true for varargs functions. Otherwise true if at least
2143 one argument has been passed in an integer register. */
2144 int gp_reg_found;
2145
2146 /* The number of arguments seen so far. */
2147 unsigned int arg_number;
2148
2149 /* The number of integer registers used so far. For all ABIs except
2150 EABI, this is the number of words that have been added to the
2151 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2152 unsigned int num_gprs;
2153
2154 /* For EABI, the number of floating-point registers used so far. */
2155 unsigned int num_fprs;
2156
2157 /* The number of words passed on the stack. */
2158 unsigned int stack_words;
2159
2160 /* On the mips16, we need to keep track of which floating point
2161 arguments were passed in general registers, but would have been
2162 passed in the FP regs if this were a 32-bit function, so that we
2163 can move them to the FP regs if we wind up calling a 32-bit
2164 function. We record this information in fp_code, encoded in base
2165 four. A zero digit means no floating point argument, a one digit
2166 means an SFmode argument, and a two digit means a DFmode argument,
2167 and a three digit is not used. The low order digit is the first
2168 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2169 an SFmode argument. ??? A more sophisticated approach will be
2170 needed if MIPS_ABI != ABI_32. */
2171 int fp_code;
2172
2173 /* True if the function has a prototype. */
2174 int prototype;
2175 } CUMULATIVE_ARGS;
2176
2177 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2178 for a call to a function whose data type is FNTYPE.
2179 For a library call, FNTYPE is 0. */
2180
2181 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2182 mips_init_cumulative_args (&CUM, FNTYPE)
2183
2184 /* Update the data in CUM to advance over an argument
2185 of mode MODE and data type TYPE.
2186 (TYPE is null for libcalls where that information may not be available.) */
2187
2188 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2189 mips_function_arg_advance (&CUM, MODE, TYPE, NAMED)
2190
2191 /* Determine where to put an argument to a function.
2192 Value is zero to push the argument on the stack,
2193 or a hard register in which to store the argument.
2194
2195 MODE is the argument's machine mode.
2196 TYPE is the data type of the argument (as a tree).
2197 This is null for libcalls where that information may
2198 not be available.
2199 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2200 the preceding args and about the function being called.
2201 NAMED is nonzero if this argument is a named parameter
2202 (otherwise it is an extra parameter matching an ellipsis). */
2203
2204 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2205 mips_function_arg (&CUM, MODE, TYPE, NAMED)
2206
2207 #define FUNCTION_ARG_BOUNDARY mips_function_arg_boundary
2208
2209 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2210 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2211
2212 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2213 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2214
2215 /* True if using EABI and varargs can be passed in floating-point
2216 registers. Under these conditions, we need a more complex form
2217 of va_list, which tracks GPR, FPR and stack arguments separately. */
2218 #define EABI_FLOAT_VARARGS_P \
2219 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2220
2221 \f
2222 /* Say that the epilogue uses the return address register. Note that
2223 in the case of sibcalls, the values "used by the epilogue" are
2224 considered live at the start of the called function.
2225
2226 If using a GOT, say that the epilogue also uses GOT_VERSION_REGNUM.
2227 See the comment above load_call<mode> for details. */
2228 #define EPILOGUE_USES(REGNO) \
2229 ((REGNO) == 31 || (TARGET_USE_GOT && (REGNO) == GOT_VERSION_REGNUM))
2230
2231 /* Treat LOC as a byte offset from the stack pointer and round it up
2232 to the next fully-aligned offset. */
2233 #define MIPS_STACK_ALIGN(LOC) \
2234 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2235
2236 \f
2237 /* Output assembler code to FILE to increment profiler label # LABELNO
2238 for profiling a function entry. */
2239
2240 #define FUNCTION_PROFILER(FILE, LABELNO) \
2241 { \
2242 if (TARGET_MIPS16) \
2243 sorry ("mips16 function profiling"); \
2244 fprintf (FILE, "\t.set\tnoat\n"); \
2245 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2246 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2247 /* _mcount treats $2 as the static chain register. */ \
2248 if (cfun->static_chain_decl != NULL) \
2249 fprintf (FILE, "\tmove\t%s,%s\n", reg_names[2], \
2250 reg_names[STATIC_CHAIN_REGNUM]); \
2251 if (!TARGET_NEWABI) \
2252 { \
2253 fprintf (FILE, \
2254 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2255 TARGET_64BIT ? "dsubu" : "subu", \
2256 reg_names[STACK_POINTER_REGNUM], \
2257 reg_names[STACK_POINTER_REGNUM], \
2258 Pmode == DImode ? 16 : 8); \
2259 } \
2260 fprintf (FILE, "\tjal\t_mcount\n"); \
2261 fprintf (FILE, "\t.set\tat\n"); \
2262 /* _mcount treats $2 as the static chain register. */ \
2263 if (cfun->static_chain_decl != NULL) \
2264 fprintf (FILE, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM], \
2265 reg_names[2]); \
2266 }
2267
2268 /* The profiler preserves all interesting registers, including $31. */
2269 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2270
2271 /* No mips port has ever used the profiler counter word, so don't emit it
2272 or the label for it. */
2273
2274 #define NO_PROFILE_COUNTERS 1
2275
2276 /* Define this macro if the code for function profiling should come
2277 before the function prologue. Normally, the profiling code comes
2278 after. */
2279
2280 /* #define PROFILE_BEFORE_PROLOGUE */
2281
2282 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2283 the stack pointer does not matter. The value is tested only in
2284 functions that have frame pointers.
2285 No definition is equivalent to always zero. */
2286
2287 #define EXIT_IGNORE_STACK 1
2288
2289 \f
2290 /* A C statement to output, on the stream FILE, assembler code for a
2291 block of data that contains the constant parts of a trampoline.
2292 This code should not include a label--the label is taken care of
2293 automatically. */
2294
2295 #define TRAMPOLINE_TEMPLATE(STREAM) \
2296 { \
2297 if (ptr_mode == DImode) \
2298 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \
2299 else \
2300 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2301 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2302 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2303 if (ptr_mode == DImode) \
2304 { \
2305 fprintf (STREAM, "\t.word\t0xdff90014\t\t# ld $25,20($31)\n"); \
2306 fprintf (STREAM, "\t.word\t0xdfef001c\t\t# ld $15,28($31)\n"); \
2307 } \
2308 else \
2309 { \
2310 fprintf (STREAM, "\t.word\t0x8ff90010\t\t# lw $25,16($31)\n"); \
2311 fprintf (STREAM, "\t.word\t0x8fef0014\t\t# lw $15,20($31)\n"); \
2312 } \
2313 fprintf (STREAM, "\t.word\t0x03200008\t\t# jr $25\n"); \
2314 if (ptr_mode == DImode) \
2315 { \
2316 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \
2317 fprintf (STREAM, "\t.word\t0x00000000\t\t# <padding>\n"); \
2318 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2319 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2320 } \
2321 else \
2322 { \
2323 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2324 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2325 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2326 } \
2327 }
2328
2329 /* A C expression for the size in bytes of the trampoline, as an
2330 integer. */
2331
2332 #define TRAMPOLINE_SIZE (ptr_mode == DImode ? 48 : 36)
2333
2334 /* Alignment required for trampolines, in bits. */
2335
2336 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2337
2338 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2339 program and data caches. */
2340
2341 #ifndef CACHE_FLUSH_FUNC
2342 #define CACHE_FLUSH_FUNC "_flush_cache"
2343 #endif
2344
2345 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2346 /* Flush both caches. We need to flush the data cache in case \
2347 the system has a write-back cache. */ \
2348 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2349 0, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2350 GEN_INT (3), TYPE_MODE (integer_type_node))
2351
2352 /* A C statement to initialize the variable parts of a trampoline.
2353 ADDR is an RTX for the address of the trampoline; FNADDR is an
2354 RTX for the address of the nested function; STATIC_CHAIN is an
2355 RTX for the static chain value that should be passed to the
2356 function when it is called. */
2357
2358 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2359 { \
2360 rtx func_addr, chain_addr, end_addr; \
2361 \
2362 func_addr = plus_constant (ADDR, ptr_mode == DImode ? 32 : 28); \
2363 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2364 mips_emit_move (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2365 mips_emit_move (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2366 end_addr = gen_reg_rtx (Pmode); \
2367 emit_insn (gen_add3_insn (end_addr, copy_rtx (ADDR), \
2368 GEN_INT (TRAMPOLINE_SIZE))); \
2369 emit_insn (gen_clear_cache (copy_rtx (ADDR), end_addr)); \
2370 }
2371 \f
2372 /* Addressing modes, and classification of registers for them. */
2373
2374 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2375 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2376 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2377
2378 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2379 and check its validity for a certain class.
2380 We have two alternate definitions for each of them.
2381 The usual definition accepts all pseudo regs; the other rejects them all.
2382 The symbol REG_OK_STRICT causes the latter definition to be used.
2383
2384 Most source files want to accept pseudo regs in the hope that
2385 they will get allocated to the class that the insn wants them to be in.
2386 Some source files that are used after register allocation
2387 need to be strict. */
2388
2389 #ifndef REG_OK_STRICT
2390 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2391 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2392 #else
2393 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2394 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2395 #endif
2396
2397 #define REG_OK_FOR_INDEX_P(X) 0
2398
2399 \f
2400 /* Maximum number of registers that can appear in a valid memory address. */
2401
2402 #define MAX_REGS_PER_ADDRESS 1
2403
2404 #ifdef REG_OK_STRICT
2405 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2406 { \
2407 if (mips_legitimate_address_p (MODE, X, 1)) \
2408 goto ADDR; \
2409 }
2410 #else
2411 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2412 { \
2413 if (mips_legitimate_address_p (MODE, X, 0)) \
2414 goto ADDR; \
2415 }
2416 #endif
2417
2418 /* Check for constness inline but use mips_legitimate_address_p
2419 to check whether a constant really is an address. */
2420
2421 #define CONSTANT_ADDRESS_P(X) \
2422 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2423
2424 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2425
2426 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2427 do { \
2428 if (mips_legitimize_address (&(X), MODE)) \
2429 goto WIN; \
2430 } while (0)
2431
2432
2433 /* A C statement or compound statement with a conditional `goto
2434 LABEL;' executed if memory address X (an RTX) can have different
2435 meanings depending on the machine mode of the memory reference it
2436 is used for.
2437
2438 Autoincrement and autodecrement addresses typically have
2439 mode-dependent effects because the amount of the increment or
2440 decrement is the size of the operand being addressed. Some
2441 machines have other mode-dependent addresses. Many RISC machines
2442 have no mode-dependent addresses.
2443
2444 You may assume that ADDR is a valid address for the machine. */
2445
2446 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2447
2448 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2449 'the start of the function that this code is output in'. */
2450
2451 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2452 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2453 asm_fprintf ((FILE), "%U%s", \
2454 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2455 else \
2456 asm_fprintf ((FILE), "%U%s", (NAME))
2457 \f
2458 /* Flag to mark a function decl symbol that requires a long call. */
2459 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2460 #define SYMBOL_REF_LONG_CALL_P(X) \
2461 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2462
2463 /* This flag marks functions that cannot be lazily bound. */
2464 #define SYMBOL_FLAG_BIND_NOW (SYMBOL_FLAG_MACH_DEP << 1)
2465 #define SYMBOL_REF_BIND_NOW_P(RTX) \
2466 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_BIND_NOW) != 0)
2467
2468 /* True if we're generating a form of MIPS16 code in which jump tables
2469 are stored in the text section and encoded as 16-bit PC-relative
2470 offsets. This is only possible when general text loads are allowed,
2471 since the table access itself will be an "lh" instruction. */
2472 /* ??? 16-bit offsets can overflow in large functions. */
2473 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2474
2475 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2476
2477 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2478
2479 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2480
2481 /* Define this as 1 if `char' should by default be signed; else as 0. */
2482 #ifndef DEFAULT_SIGNED_CHAR
2483 #define DEFAULT_SIGNED_CHAR 1
2484 #endif
2485
2486 /* Although LDC1 and SDC1 provide 64-bit moves on 32-bit targets,
2487 we generally don't want to use them for copying arbitrary data.
2488 A single N-word move is usually the same cost as N single-word moves. */
2489 #define MOVE_MAX UNITS_PER_WORD
2490 #define MAX_MOVE_MAX 8
2491
2492 /* Define this macro as a C expression which is nonzero if
2493 accessing less than a word of memory (i.e. a `char' or a
2494 `short') is no faster than accessing a word of memory, i.e., if
2495 such access require more than one instruction or if there is no
2496 difference in cost between byte and (aligned) word loads.
2497
2498 On RISC machines, it tends to generate better code to define
2499 this as 1, since it avoids making a QI or HI mode register.
2500
2501 But, generating word accesses for -mips16 is generally bad as shifts
2502 (often extended) would be needed for byte accesses. */
2503 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2504
2505 /* Define this to be nonzero if shift instructions ignore all but the low-order
2506 few bits. */
2507 #define SHIFT_COUNT_TRUNCATED 1
2508
2509 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2510 is done just by pretending it is already truncated. */
2511 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2512 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2513
2514
2515 /* Specify the machine mode that pointers have.
2516 After generation of rtl, the compiler makes no further distinction
2517 between pointers and any other objects of this machine mode. */
2518
2519 #ifndef Pmode
2520 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2521 #endif
2522
2523 /* Give call MEMs SImode since it is the "most permissive" mode
2524 for both 32-bit and 64-bit targets. */
2525
2526 #define FUNCTION_MODE SImode
2527
2528 \f
2529 /* A C expression for the cost of moving data from a register in
2530 class FROM to one in class TO. The classes are expressed using
2531 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2532 the default; other values are interpreted relative to that.
2533
2534 It is not required that the cost always equal 2 when FROM is the
2535 same as TO; on some machines it is expensive to move between
2536 registers if they are not general registers.
2537
2538 If reload sees an insn consisting of a single `set' between two
2539 hard registers, and if `REGISTER_MOVE_COST' applied to their
2540 classes returns a value of 2, reload does not check to ensure
2541 that the constraints of the insn are met. Setting a cost of
2542 other than 2 will allow reload to verify that the constraints are
2543 met. You should do this if the `movM' pattern's constraints do
2544 not allow such copying. */
2545
2546 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2547 mips_register_move_cost (MODE, FROM, TO)
2548
2549 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2550 (mips_cost->memory_latency \
2551 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2552
2553 /* Define if copies to/from condition code registers should be avoided.
2554
2555 This is needed for the MIPS because reload_outcc is not complete;
2556 it needs to handle cases where the source is a general or another
2557 condition code register. */
2558 #define AVOID_CCMODE_COPIES
2559
2560 /* A C expression for the cost of a branch instruction. A value of
2561 1 is the default; other values are interpreted relative to that. */
2562
2563 #define BRANCH_COST(speed_p, predictable_p) mips_branch_cost
2564 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2565
2566 /* If defined, modifies the length assigned to instruction INSN as a
2567 function of the context in which it is used. LENGTH is an lvalue
2568 that contains the initially computed length of the insn and should
2569 be updated with the correct length of the insn. */
2570 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2571 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2572
2573 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2574 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2575 its operands. */
2576 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2577 "%*" OPCODE "%?\t" OPERANDS "%/"
2578
2579 /* Return the asm template for a call. INSN is the instruction's mnemonic
2580 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number
2581 of the target.
2582
2583 When generating GOT code without explicit relocation operators,
2584 all calls should use assembly macros. Otherwise, all indirect
2585 calls should use "jr" or "jalr"; we will arrange to restore $gp
2586 afterwards if necessary. Finally, we can only generate direct
2587 calls for -mabicalls by temporarily switching to non-PIC mode. */
2588 #define MIPS_CALL(INSN, OPERANDS, OPNO) \
2589 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2590 ? "%*" INSN "\t%" #OPNO "%/" \
2591 : REG_P (OPERANDS[OPNO]) \
2592 ? "%*" INSN "r\t%" #OPNO "%/" \
2593 : TARGET_ABICALLS_PIC2 \
2594 ? (".option\tpic0\n\t" \
2595 "%*" INSN "\t%" #OPNO "%/\n\t" \
2596 ".option\tpic2") \
2597 : "%*" INSN "\t%" #OPNO "%/")
2598 \f
2599 /* Control the assembler format that we output. */
2600
2601 /* Output to assembler file text saying following lines
2602 may contain character constants, extra white space, comments, etc. */
2603
2604 #ifndef ASM_APP_ON
2605 #define ASM_APP_ON " #APP\n"
2606 #endif
2607
2608 /* Output to assembler file text saying following lines
2609 no longer contain unusual constructs. */
2610
2611 #ifndef ASM_APP_OFF
2612 #define ASM_APP_OFF " #NO_APP\n"
2613 #endif
2614
2615 #define REGISTER_NAMES \
2616 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2617 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2618 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2619 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2620 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2621 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2622 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2623 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2624 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2625 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2626 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2627 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2628 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2629 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2630 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2631 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2632 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2633 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2634 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2635 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2636 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2637 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2638 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2639 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2640
2641 /* List the "software" names for each register. Also list the numerical
2642 names for $fp and $sp. */
2643
2644 #define ADDITIONAL_REGISTER_NAMES \
2645 { \
2646 { "$29", 29 + GP_REG_FIRST }, \
2647 { "$30", 30 + GP_REG_FIRST }, \
2648 { "at", 1 + GP_REG_FIRST }, \
2649 { "v0", 2 + GP_REG_FIRST }, \
2650 { "v1", 3 + GP_REG_FIRST }, \
2651 { "a0", 4 + GP_REG_FIRST }, \
2652 { "a1", 5 + GP_REG_FIRST }, \
2653 { "a2", 6 + GP_REG_FIRST }, \
2654 { "a3", 7 + GP_REG_FIRST }, \
2655 { "t0", 8 + GP_REG_FIRST }, \
2656 { "t1", 9 + GP_REG_FIRST }, \
2657 { "t2", 10 + GP_REG_FIRST }, \
2658 { "t3", 11 + GP_REG_FIRST }, \
2659 { "t4", 12 + GP_REG_FIRST }, \
2660 { "t5", 13 + GP_REG_FIRST }, \
2661 { "t6", 14 + GP_REG_FIRST }, \
2662 { "t7", 15 + GP_REG_FIRST }, \
2663 { "s0", 16 + GP_REG_FIRST }, \
2664 { "s1", 17 + GP_REG_FIRST }, \
2665 { "s2", 18 + GP_REG_FIRST }, \
2666 { "s3", 19 + GP_REG_FIRST }, \
2667 { "s4", 20 + GP_REG_FIRST }, \
2668 { "s5", 21 + GP_REG_FIRST }, \
2669 { "s6", 22 + GP_REG_FIRST }, \
2670 { "s7", 23 + GP_REG_FIRST }, \
2671 { "t8", 24 + GP_REG_FIRST }, \
2672 { "t9", 25 + GP_REG_FIRST }, \
2673 { "k0", 26 + GP_REG_FIRST }, \
2674 { "k1", 27 + GP_REG_FIRST }, \
2675 { "gp", 28 + GP_REG_FIRST }, \
2676 { "sp", 29 + GP_REG_FIRST }, \
2677 { "fp", 30 + GP_REG_FIRST }, \
2678 { "ra", 31 + GP_REG_FIRST }, \
2679 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2680 }
2681
2682 /* This is meant to be redefined in the host dependent files. It is a
2683 set of alternative names and regnums for mips coprocessors. */
2684
2685 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2686
2687 #define PRINT_OPERAND mips_print_operand
2688 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2689 #define PRINT_OPERAND_ADDRESS mips_print_operand_address
2690
2691 /* A C statement, to be executed after all slot-filler instructions
2692 have been output. If necessary, call `dbr_sequence_length' to
2693 determine the number of slots filled in a sequence (zero if not
2694 currently outputting a sequence), to decide how many no-ops to
2695 output, or whatever.
2696
2697 Don't define this macro if it has nothing to do, but it is
2698 helpful in reading assembly output if the extent of the delay
2699 sequence is made explicit (e.g. with white space).
2700
2701 Note that output routines for instructions with delay slots must
2702 be prepared to deal with not being output as part of a sequence
2703 (i.e. when the scheduling pass is not run, or when no slot
2704 fillers could be found.) The variable `final_sequence' is null
2705 when not processing a sequence, otherwise it contains the
2706 `sequence' rtx being output. */
2707
2708 #define DBR_OUTPUT_SEQEND(STREAM) \
2709 do \
2710 { \
2711 if (set_nomacro > 0 && --set_nomacro == 0) \
2712 fputs ("\t.set\tmacro\n", STREAM); \
2713 \
2714 if (set_noreorder > 0 && --set_noreorder == 0) \
2715 fputs ("\t.set\treorder\n", STREAM); \
2716 \
2717 fputs ("\n", STREAM); \
2718 } \
2719 while (0)
2720
2721 /* How to tell the debugger about changes of source files. */
2722 #define ASM_OUTPUT_SOURCE_FILENAME mips_output_filename
2723
2724 /* mips-tfile does not understand .stabd directives. */
2725 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2726 dbxout_begin_stabn_sline (LINE); \
2727 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2728 } while (0)
2729
2730 /* Use .loc directives for SDB line numbers. */
2731 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2732 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2733
2734 /* The MIPS implementation uses some labels for its own purpose. The
2735 following lists what labels are created, and are all formed by the
2736 pattern $L[a-z].*. The machine independent portion of GCC creates
2737 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2738
2739 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2740 $Lb[0-9]+ Begin blocks for MIPS debug support
2741 $Lc[0-9]+ Label for use in s<xx> operation.
2742 $Le[0-9]+ End blocks for MIPS debug support */
2743
2744 #undef ASM_DECLARE_OBJECT_NAME
2745 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2746 mips_declare_object (STREAM, NAME, "", ":\n")
2747
2748 /* Globalizing directive for a label. */
2749 #define GLOBAL_ASM_OP "\t.globl\t"
2750
2751 /* This says how to define a global common symbol. */
2752
2753 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2754
2755 /* This says how to define a local common symbol (i.e., not visible to
2756 linker). */
2757
2758 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2759 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2760 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2761 #endif
2762
2763 /* This says how to output an external. It would be possible not to
2764 output anything and let undefined symbol become external. However
2765 the assembler uses length information on externals to allocate in
2766 data/sdata bss/sbss, thereby saving exec time. */
2767
2768 #undef ASM_OUTPUT_EXTERNAL
2769 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2770 mips_output_external(STREAM,DECL,NAME)
2771
2772 /* This is how to declare a function name. The actual work of
2773 emitting the label is moved to function_prologue, so that we can
2774 get the line number correctly emitted before the .ent directive,
2775 and after any .file directives. Define as empty so that the function
2776 is not declared before the .ent directive elsewhere. */
2777
2778 #undef ASM_DECLARE_FUNCTION_NAME
2779 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2780
2781 /* This is how to store into the string LABEL
2782 the symbol_ref name of an internal numbered label where
2783 PREFIX is the class of label and NUM is the number within the class.
2784 This is suitable for output with `assemble_name'. */
2785
2786 #undef ASM_GENERATE_INTERNAL_LABEL
2787 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2788 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2789
2790 /* This is how to output an element of a case-vector that is absolute. */
2791
2792 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2793 fprintf (STREAM, "\t%s\t%sL%d\n", \
2794 ptr_mode == DImode ? ".dword" : ".word", \
2795 LOCAL_LABEL_PREFIX, \
2796 VALUE)
2797
2798 /* This is how to output an element of a case-vector. We can make the
2799 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2800 is supported. */
2801
2802 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2803 do { \
2804 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2805 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2806 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2807 else if (TARGET_GPWORD) \
2808 fprintf (STREAM, "\t%s\t%sL%d\n", \
2809 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2810 LOCAL_LABEL_PREFIX, VALUE); \
2811 else if (TARGET_RTP_PIC) \
2812 { \
2813 /* Make the entry relative to the start of the function. */ \
2814 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2815 fprintf (STREAM, "\t%s\t%sL%d-", \
2816 Pmode == DImode ? ".dword" : ".word", \
2817 LOCAL_LABEL_PREFIX, VALUE); \
2818 assemble_name (STREAM, XSTR (fnsym, 0)); \
2819 fprintf (STREAM, "\n"); \
2820 } \
2821 else \
2822 fprintf (STREAM, "\t%s\t%sL%d\n", \
2823 ptr_mode == DImode ? ".dword" : ".word", \
2824 LOCAL_LABEL_PREFIX, VALUE); \
2825 } while (0)
2826
2827 /* This is how to output an assembler line
2828 that says to advance the location counter
2829 to a multiple of 2**LOG bytes. */
2830
2831 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2832 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2833
2834 /* This is how to output an assembler line to advance the location
2835 counter by SIZE bytes. */
2836
2837 #undef ASM_OUTPUT_SKIP
2838 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2839 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2840
2841 /* This is how to output a string. */
2842 #undef ASM_OUTPUT_ASCII
2843 #define ASM_OUTPUT_ASCII mips_output_ascii
2844
2845 /* Output #ident as a in the read-only data section. */
2846 #undef ASM_OUTPUT_IDENT
2847 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2848 { \
2849 const char *p = STRING; \
2850 int size = strlen (p) + 1; \
2851 switch_to_section (readonly_data_section); \
2852 assemble_string (p, size); \
2853 }
2854 \f
2855 /* Default to -G 8 */
2856 #ifndef MIPS_DEFAULT_GVALUE
2857 #define MIPS_DEFAULT_GVALUE 8
2858 #endif
2859
2860 /* Define the strings to put out for each section in the object file. */
2861 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2862 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2863
2864 #undef READONLY_DATA_SECTION_ASM_OP
2865 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2866 \f
2867 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2868 do \
2869 { \
2870 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2871 TARGET_64BIT ? "daddiu" : "addiu", \
2872 reg_names[STACK_POINTER_REGNUM], \
2873 reg_names[STACK_POINTER_REGNUM], \
2874 TARGET_64BIT ? "sd" : "sw", \
2875 reg_names[REGNO], \
2876 reg_names[STACK_POINTER_REGNUM]); \
2877 } \
2878 while (0)
2879
2880 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2881 do \
2882 { \
2883 if (! set_noreorder) \
2884 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2885 \
2886 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2887 TARGET_64BIT ? "ld" : "lw", \
2888 reg_names[REGNO], \
2889 reg_names[STACK_POINTER_REGNUM], \
2890 TARGET_64BIT ? "daddu" : "addu", \
2891 reg_names[STACK_POINTER_REGNUM], \
2892 reg_names[STACK_POINTER_REGNUM]); \
2893 \
2894 if (! set_noreorder) \
2895 fprintf (STREAM, "\t.set\treorder\n"); \
2896 } \
2897 while (0)
2898
2899 /* How to start an assembler comment.
2900 The leading space is important (the mips native assembler requires it). */
2901 #ifndef ASM_COMMENT_START
2902 #define ASM_COMMENT_START " #"
2903 #endif
2904 \f
2905 /* Default definitions for size_t and ptrdiff_t. We must override the
2906 definitions from ../svr4.h on mips-*-linux-gnu. */
2907
2908 #undef SIZE_TYPE
2909 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2910
2911 #undef PTRDIFF_TYPE
2912 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2913
2914 /* The maximum number of bytes that can be copied by one iteration of
2915 a movmemsi loop; see mips_block_move_loop. */
2916 #define MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER \
2917 (UNITS_PER_WORD * 4)
2918
2919 /* The maximum number of bytes that can be copied by a straight-line
2920 implementation of movmemsi; see mips_block_move_straight. We want
2921 to make sure that any loop-based implementation will iterate at
2922 least twice. */
2923 #define MIPS_MAX_MOVE_BYTES_STRAIGHT \
2924 (MIPS_MAX_MOVE_BYTES_PER_LOOP_ITER * 2)
2925
2926 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2927 values were determined experimentally by benchmarking with CSiBE.
2928 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2929 for o32 where we have to restore $gp afterwards as well as make an
2930 indirect call), but in practice, bumping this up higher for
2931 TARGET_ABICALLS doesn't make much difference to code size. */
2932
2933 #define MIPS_CALL_RATIO 8
2934
2935 /* Any loop-based implementation of movmemsi will have at least
2936 MIPS_MAX_MOVE_BYTES_STRAIGHT / UNITS_PER_WORD memory-to-memory
2937 moves, so allow individual copies of fewer elements.
2938
2939 When movmemsi is not available, use a value approximating
2940 the length of a memcpy call sequence, so that move_by_pieces
2941 will generate inline code if it is shorter than a function call.
2942 Since move_by_pieces_ninsns counts memory-to-memory moves, but
2943 we'll have to generate a load/store pair for each, halve the
2944 value of MIPS_CALL_RATIO to take that into account. */
2945
2946 #define MOVE_RATIO(speed) \
2947 (HAVE_movmemsi \
2948 ? MIPS_MAX_MOVE_BYTES_STRAIGHT / MOVE_MAX \
2949 : MIPS_CALL_RATIO / 2)
2950
2951 /* movmemsi is meant to generate code that is at least as good as
2952 move_by_pieces. However, movmemsi effectively uses a by-pieces
2953 implementation both for moves smaller than a word and for word-aligned
2954 moves of no more than MIPS_MAX_MOVE_BYTES_STRAIGHT bytes. We should
2955 allow the tree-level optimisers to do such moves by pieces, as it
2956 often exposes other optimization opportunities. We might as well
2957 continue to use movmemsi at the rtl level though, as it produces
2958 better code when scheduling is disabled (such as at -O). */
2959
2960 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \
2961 (HAVE_movmemsi \
2962 ? (!currently_expanding_to_rtl \
2963 && ((ALIGN) < BITS_PER_WORD \
2964 ? (SIZE) < UNITS_PER_WORD \
2965 : (SIZE) <= MIPS_MAX_MOVE_BYTES_STRAIGHT)) \
2966 : (move_by_pieces_ninsns (SIZE, ALIGN, MOVE_MAX_PIECES + 1) \
2967 < (unsigned int) MOVE_RATIO (false)))
2968
2969 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2970 of the length of a memset call, but use the default otherwise. */
2971
2972 #define CLEAR_RATIO(speed)\
2973 ((speed) ? 15 : MIPS_CALL_RATIO)
2974
2975 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2976 optimizing for size adjust the ratio to account for the overhead of
2977 loading the constant and replicating it across the word. */
2978
2979 #define SET_RATIO(speed) \
2980 ((speed) ? 15 : MIPS_CALL_RATIO - 2)
2981
2982 /* STORE_BY_PIECES_P can be used when copying a constant string, but
2983 in that case each word takes 3 insns (lui, ori, sw), or more in
2984 64-bit mode, instead of 2 (lw, sw). For now we always fail this
2985 and let the move_by_pieces code copy the string from read-only
2986 memory. In the future, this could be tuned further for multi-issue
2987 CPUs that can issue stores down one pipe and arithmetic instructions
2988 down another; in that case, the lui/ori/sw combination would be a
2989 win for long enough strings. */
2990
2991 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
2992 \f
2993 #ifndef __mips16
2994 /* Since the bits of the _init and _fini function is spread across
2995 many object files, each potentially with its own GP, we must assume
2996 we need to load our GP. We don't preserve $gp or $ra, since each
2997 init/fini chunk is supposed to initialize $gp, and crti/crtn
2998 already take care of preserving $ra and, when appropriate, $gp. */
2999 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
3000 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3001 asm (SECTION_OP "\n\
3002 .set noreorder\n\
3003 bal 1f\n\
3004 nop\n\
3005 1: .cpload $31\n\
3006 .set reorder\n\
3007 jal " USER_LABEL_PREFIX #FUNC "\n\
3008 " TEXT_SECTION_ASM_OP);
3009 #endif /* Switch to #elif when we're no longer limited by K&R C. */
3010 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
3011 || (defined _ABI64 && _MIPS_SIM == _ABI64)
3012 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
3013 asm (SECTION_OP "\n\
3014 .set noreorder\n\
3015 bal 1f\n\
3016 nop\n\
3017 1: .set reorder\n\
3018 .cpsetup $31, $2, 1b\n\
3019 jal " USER_LABEL_PREFIX #FUNC "\n\
3020 " TEXT_SECTION_ASM_OP);
3021 #endif
3022 #endif
3023
3024 #ifndef HAVE_AS_TLS
3025 #define HAVE_AS_TLS 0
3026 #endif
3027
3028 /* Return an asm string that atomically:
3029
3030 - Compares memory reference %1 to register %2 and, if they are
3031 equal, changes %1 to %3.
3032
3033 - Sets register %0 to the old value of memory reference %1.
3034
3035 SUFFIX is the suffix that should be added to "ll" and "sc" instructions
3036 and OP is the instruction that should be used to load %3 into a
3037 register. */
3038 #define MIPS_COMPARE_AND_SWAP(SUFFIX, OP) \
3039 "%(%<%[%|sync\n" \
3040 "1:\tll" SUFFIX "\t%0,%1\n" \
3041 "\tbne\t%0,%z2,2f\n" \
3042 "\t" OP "\t%@,%3\n" \
3043 "\tsc" SUFFIX "\t%@,%1\n" \
3044 "\tbeq\t%@,%.,1b\n" \
3045 "\tnop\n" \
3046 "\tsync%-%]%>%)\n" \
3047 "2:\n"
3048
3049 /* Return an asm string that atomically:
3050
3051 - Given that %2 contains a bit mask and %3 the inverted mask and
3052 that %4 and %5 have already been ANDed with %2.
3053
3054 - Compares the bits in memory reference %1 selected by mask %2 to
3055 register %4 and, if they are equal, changes the selected bits
3056 in memory to %5.
3057
3058 - Sets register %0 to the old value of memory reference %1.
3059
3060 OPS are the instructions needed to OR %5 with %@. */
3061 #define MIPS_COMPARE_AND_SWAP_12(OPS) \
3062 "%(%<%[%|sync\n" \
3063 "1:\tll\t%0,%1\n" \
3064 "\tand\t%@,%0,%2\n" \
3065 "\tbne\t%@,%z4,2f\n" \
3066 "\tand\t%@,%0,%3\n" \
3067 OPS \
3068 "\tsc\t%@,%1\n" \
3069 "\tbeq\t%@,%.,1b\n" \
3070 "\tnop\n" \
3071 "\tsync%-%]%>%)\n" \
3072 "2:\n"
3073
3074 #define MIPS_COMPARE_AND_SWAP_12_ZERO_OP ""
3075 #define MIPS_COMPARE_AND_SWAP_12_NONZERO_OP "\tor\t%@,%@,%5\n"
3076
3077
3078 /* Return an asm string that atomically:
3079
3080 - Sets memory reference %0 to %0 INSN %1.
3081
3082 SUFFIX is the suffix that should be added to "ll" and "sc"
3083 instructions. */
3084 #define MIPS_SYNC_OP(SUFFIX, INSN) \
3085 "%(%<%[%|sync\n" \
3086 "1:\tll" SUFFIX "\t%@,%0\n" \
3087 "\t" INSN "\t%@,%@,%1\n" \
3088 "\tsc" SUFFIX "\t%@,%0\n" \
3089 "\tbeq\t%@,%.,1b\n" \
3090 "\tnop\n" \
3091 "\tsync%-%]%>%)"
3092
3093 /* Return an asm string that atomically:
3094
3095 - Given that %1 contains a bit mask and %2 the inverted mask and
3096 that %3 has already been ANDed with %1.
3097
3098 - Sets the selected bits of memory reference %0 to %0 INSN %3.
3099
3100 - Uses scratch register %4.
3101
3102 NOT_OP are the optional instructions to do a bit-wise not
3103 operation in conjunction with an AND INSN to generate a sync_nand
3104 operation. */
3105 #define MIPS_SYNC_OP_12(INSN, NOT_OP) \
3106 "%(%<%[%|sync\n" \
3107 "1:\tll\t%4,%0\n" \
3108 "\tand\t%@,%4,%2\n" \
3109 NOT_OP \
3110 "\t" INSN "\t%4,%4,%z3\n" \
3111 "\tand\t%4,%4,%1\n" \
3112 "\tor\t%@,%@,%4\n" \
3113 "\tsc\t%@,%0\n" \
3114 "\tbeq\t%@,%.,1b\n" \
3115 "\tnop\n" \
3116 "\tsync%-%]%>%)"
3117
3118 #define MIPS_SYNC_OP_12_NOT_NOP ""
3119 #define MIPS_SYNC_OP_12_NOT_NOT "\tnor\t%4,%4,%.\n"
3120
3121 /* Return an asm string that atomically:
3122
3123 - Given that %2 contains a bit mask and %3 the inverted mask and
3124 that %4 has already been ANDed with %2.
3125
3126 - Sets the selected bits of memory reference %1 to %1 INSN %4.
3127
3128 - Sets %0 to the original value of %1.
3129
3130 - Uses scratch register %5.
3131
3132 NOT_OP are the optional instructions to do a bit-wise not
3133 operation in conjunction with an AND INSN to generate a sync_nand
3134 operation.
3135
3136 REG is used in conjunction with NOT_OP and is used to select the
3137 register operated on by the INSN. */
3138 #define MIPS_SYNC_OLD_OP_12(INSN, NOT_OP, REG) \
3139 "%(%<%[%|sync\n" \
3140 "1:\tll\t%0,%1\n" \
3141 "\tand\t%@,%0,%3\n" \
3142 NOT_OP \
3143 "\t" INSN "\t%5," REG ",%z4\n" \
3144 "\tand\t%5,%5,%2\n" \
3145 "\tor\t%@,%@,%5\n" \
3146 "\tsc\t%@,%1\n" \
3147 "\tbeq\t%@,%.,1b\n" \
3148 "\tnop\n" \
3149 "\tsync%-%]%>%)"
3150
3151 #define MIPS_SYNC_OLD_OP_12_NOT_NOP ""
3152 #define MIPS_SYNC_OLD_OP_12_NOT_NOP_REG "%0"
3153 #define MIPS_SYNC_OLD_OP_12_NOT_NOT "\tnor\t%5,%0,%.\n"
3154 #define MIPS_SYNC_OLD_OP_12_NOT_NOT_REG "%5"
3155
3156 /* Return an asm string that atomically:
3157
3158 - Given that %2 contains a bit mask and %3 the inverted mask and
3159 that %4 has already been ANDed with %2.
3160
3161 - Sets the selected bits of memory reference %1 to %1 INSN %4.
3162
3163 - Sets %0 to the new value of %1.
3164
3165 NOT_OP are the optional instructions to do a bit-wise not
3166 operation in conjunction with an AND INSN to generate a sync_nand
3167 operation. */
3168 #define MIPS_SYNC_NEW_OP_12(INSN, NOT_OP) \
3169 "%(%<%[%|sync\n" \
3170 "1:\tll\t%0,%1\n" \
3171 "\tand\t%@,%0,%3\n" \
3172 NOT_OP \
3173 "\t" INSN "\t%0,%0,%z4\n" \
3174 "\tand\t%0,%0,%2\n" \
3175 "\tor\t%@,%@,%0\n" \
3176 "\tsc\t%@,%1\n" \
3177 "\tbeq\t%@,%.,1b\n" \
3178 "\tnop\n" \
3179 "\tsync%-%]%>%)"
3180
3181 #define MIPS_SYNC_NEW_OP_12_NOT_NOP ""
3182 #define MIPS_SYNC_NEW_OP_12_NOT_NOT "\tnor\t%0,%0,%.\n"
3183
3184 /* Return an asm string that atomically:
3185
3186 - Sets memory reference %1 to %1 INSN %2.
3187
3188 - Sets register %0 to the old value of memory reference %1.
3189
3190 SUFFIX is the suffix that should be added to "ll" and "sc"
3191 instructions. */
3192 #define MIPS_SYNC_OLD_OP(SUFFIX, INSN) \
3193 "%(%<%[%|sync\n" \
3194 "1:\tll" SUFFIX "\t%0,%1\n" \
3195 "\t" INSN "\t%@,%0,%2\n" \
3196 "\tsc" SUFFIX "\t%@,%1\n" \
3197 "\tbeq\t%@,%.,1b\n" \
3198 "\tnop\n" \
3199 "\tsync%-%]%>%)"
3200
3201 /* Return an asm string that atomically:
3202
3203 - Sets memory reference %1 to %1 INSN %2.
3204
3205 - Sets register %0 to the new value of memory reference %1.
3206
3207 SUFFIX is the suffix that should be added to "ll" and "sc"
3208 instructions. */
3209 #define MIPS_SYNC_NEW_OP(SUFFIX, INSN) \
3210 "%(%<%[%|sync\n" \
3211 "1:\tll" SUFFIX "\t%0,%1\n" \
3212 "\t" INSN "\t%@,%0,%2\n" \
3213 "\tsc" SUFFIX "\t%@,%1\n" \
3214 "\tbeq\t%@,%.,1b\n" \
3215 "\t" INSN "\t%0,%0,%2\n" \
3216 "\tsync%-%]%>%)"
3217
3218 /* Return an asm string that atomically:
3219
3220 - Sets memory reference %0 to ~%0 AND %1.
3221
3222 SUFFIX is the suffix that should be added to "ll" and "sc"
3223 instructions. INSN is the and instruction needed to and a register
3224 with %2. */
3225 #define MIPS_SYNC_NAND(SUFFIX, INSN) \
3226 "%(%<%[%|sync\n" \
3227 "1:\tll" SUFFIX "\t%@,%0\n" \
3228 "\tnor\t%@,%@,%.\n" \
3229 "\t" INSN "\t%@,%@,%1\n" \
3230 "\tsc" SUFFIX "\t%@,%0\n" \
3231 "\tbeq\t%@,%.,1b\n" \
3232 "\tnop\n" \
3233 "\tsync%-%]%>%)"
3234
3235 /* Return an asm string that atomically:
3236
3237 - Sets memory reference %1 to ~%1 AND %2.
3238
3239 - Sets register %0 to the old value of memory reference %1.
3240
3241 SUFFIX is the suffix that should be added to "ll" and "sc"
3242 instructions. INSN is the and instruction needed to and a register
3243 with %2. */
3244 #define MIPS_SYNC_OLD_NAND(SUFFIX, INSN) \
3245 "%(%<%[%|sync\n" \
3246 "1:\tll" SUFFIX "\t%0,%1\n" \
3247 "\tnor\t%@,%0,%.\n" \
3248 "\t" INSN "\t%@,%@,%2\n" \
3249 "\tsc" SUFFIX "\t%@,%1\n" \
3250 "\tbeq\t%@,%.,1b\n" \
3251 "\tnop\n" \
3252 "\tsync%-%]%>%)"
3253
3254 /* Return an asm string that atomically:
3255
3256 - Sets memory reference %1 to ~%1 AND %2.
3257
3258 - Sets register %0 to the new value of memory reference %1.
3259
3260 SUFFIX is the suffix that should be added to "ll" and "sc"
3261 instructions. INSN is the and instruction needed to and a register
3262 with %2. */
3263 #define MIPS_SYNC_NEW_NAND(SUFFIX, INSN) \
3264 "%(%<%[%|sync\n" \
3265 "1:\tll" SUFFIX "\t%0,%1\n" \
3266 "\tnor\t%0,%0,%.\n" \
3267 "\t" INSN "\t%@,%0,%2\n" \
3268 "\tsc" SUFFIX "\t%@,%1\n" \
3269 "\tbeq\t%@,%.,1b\n" \
3270 "\t" INSN "\t%0,%0,%2\n" \
3271 "\tsync%-%]%>%)"
3272
3273 /* Return an asm string that atomically:
3274
3275 - Sets memory reference %1 to %2.
3276
3277 - Sets register %0 to the old value of memory reference %1.
3278
3279 SUFFIX is the suffix that should be added to "ll" and "sc"
3280 instructions. OP is the and instruction that should be used to
3281 load %2 into a register. */
3282 #define MIPS_SYNC_EXCHANGE(SUFFIX, OP) \
3283 "%(%<%[%|\n" \
3284 "1:\tll" SUFFIX "\t%0,%1\n" \
3285 "\t" OP "\t%@,%2\n" \
3286 "\tsc" SUFFIX "\t%@,%1\n" \
3287 "\tbeq\t%@,%.,1b\n" \
3288 "\tnop\n" \
3289 "\tsync%-%]%>%)"
3290
3291 /* Return an asm string that atomically:
3292
3293 - Given that %2 contains an inclusive mask, %3 and exclusive mask
3294 and %4 has already been ANDed with the inclusive mask.
3295
3296 - Sets bits selected by the inclusive mask of memory reference %1
3297 to %4.
3298
3299 - Sets register %0 to the old value of memory reference %1.
3300
3301 OPS are the instructions needed to OR %4 with %@.
3302
3303 Operand %2 is unused, but needed as to give the test_and_set_12
3304 insn the five operands expected by the expander. */
3305 #define MIPS_SYNC_EXCHANGE_12(OPS) \
3306 "%(%<%[%|\n" \
3307 "1:\tll\t%0,%1\n" \
3308 "\tand\t%@,%0,%3\n" \
3309 OPS \
3310 "\tsc\t%@,%1\n" \
3311 "\tbeq\t%@,%.,1b\n" \
3312 "\tnop\n" \
3313 "\tsync%-%]%>%)"
3314
3315 #define MIPS_SYNC_EXCHANGE_12_ZERO_OP ""
3316 #define MIPS_SYNC_EXCHANGE_12_NONZERO_OP "\tor\t%@,%@,%4\n"
3317
3318 #ifndef USED_FOR_TARGET
3319 extern const enum reg_class mips_regno_to_class[];
3320 extern bool mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
3321 extern bool mips_print_operand_punct[256];
3322 extern const char *current_function_file; /* filename current function is in */
3323 extern int num_source_filenames; /* current .file # */
3324 extern int set_noreorder; /* # of nested .set noreorder's */
3325 extern int set_nomacro; /* # of nested .set nomacro's */
3326 extern int mips_dbx_regno[];
3327 extern int mips_dwarf_regno[];
3328 extern bool mips_split_p[];
3329 extern bool mips_split_hi_p[];
3330 extern GTY(()) rtx cmp_operands[2];
3331 extern enum processor_type mips_arch; /* which cpu to codegen for */
3332 extern enum processor_type mips_tune; /* which cpu to schedule for */
3333 extern int mips_isa; /* architectural level */
3334 extern int mips_abi; /* which ABI to use */
3335 extern const struct mips_cpu_info *mips_arch_info;
3336 extern const struct mips_cpu_info *mips_tune_info;
3337 extern const struct mips_rtx_cost_data *mips_cost;
3338 extern bool mips_base_mips16;
3339 extern enum mips_code_readable_setting mips_code_readable;
3340 #endif
3341
3342 /* Enable querying of DFA units. */
3343 #define CPU_UNITS_QUERY 1
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