gcc/testsuite/gcc.target/powerpc/dform-3.c

   1 /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
   2 /* { dg-require-effective-target powerpc_p9vector_ok } */
   3 /* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
   4 /* { dg-options "-mcpu=power9 -O2" } */
   5
   6 #ifndef TYPE
   7 #define TYPE vector double
   8 #endif
   9
  10 struct foo {
  11   TYPE a, b, c, d;
  12 };
  13
  14 /* Test whether ISA 3.0 vector d-form instructions are implemented.  */
  15 void
  16 add (struct foo *p)
  17 {
  18   p->b = p->c + p->d;
  19 }
  20
  21 /* Make sure we don't use direct moves to get stuff into GPR registers.  */
  22 void
  23 gpr (struct foo *p)
  24 {
  25   TYPE x = p->c;
  26
  27   __asm__ (" # reg = %0" : "+r" (x));
  28
  29   p->b = x;
  30 }
  31
  32 /* { dg-final { scan-assembler     "lxv "      } } */
  33 /* { dg-final { scan-assembler     "stxv "     } } */
  34 /* { dg-final { scan-assembler-not "lxvx "     } } */
  35 /* { dg-final { scan-assembler-not "stxvx "    } } */
  36 /* { dg-final { scan-assembler-not "mfvsrd "   } } */
  37 /* { dg-final { scan-assembler-not "mfvsrld "  } } */
  38 /* { dg-final { scan-assembler     "l\[dq\] "  } } */
  39 /* { dg-final { scan-assembler     "st\[dq\] " } } */