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re PR target/33479 (SyncTest Intermittent failing on MIPS)
[official-gcc.git] / gcc / config / mips / mips.h
blob01d851d7f93bbfc32c82725ea5a5f60d5b31d232
1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007
4 Free Software Foundation, Inc.
5 Contributed by A. Lichnewsky (lich@inria.inria.fr).
6 Changed by Michael Meissner (meissner@osf.org).
7 64-bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
8 Brendan Eich (brendan@microunity.com).
9
10 This file is part of GCC.
11
12 GCC is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 3, or (at your option)
15 any later version.
16
17 GCC is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
21
22 You should have received a copy of the GNU General Public License
23 along with GCC; see the file COPYING3. If not see
24 <http://www.gnu.org/licenses/>. */
25
26
27 #include "config/vxworks-dummy.h"
28
29 /* MIPS external variables defined in mips.c. */
30
31 /* Which processor to schedule for. Since there is no difference between
32 a R2000 and R3000 in terms of the scheduler, we collapse them into
33 just an R3000. The elements of the enumeration must match exactly
34 the cpu attribute in the mips.md machine description. */
35
36 enum processor_type {
37 PROCESSOR_R3000,
38 PROCESSOR_4KC,
39 PROCESSOR_4KP,
40 PROCESSOR_5KC,
41 PROCESSOR_5KF,
42 PROCESSOR_20KC,
43 PROCESSOR_24KC,
44 PROCESSOR_24KF2_1,
45 PROCESSOR_24KF1_1,
46 PROCESSOR_74KC,
47 PROCESSOR_74KF2_1,
48 PROCESSOR_74KF1_1,
49 PROCESSOR_74KF3_2,
50 PROCESSOR_M4K,
51 PROCESSOR_R3900,
52 PROCESSOR_R6000,
53 PROCESSOR_R4000,
54 PROCESSOR_R4100,
55 PROCESSOR_R4111,
56 PROCESSOR_R4120,
57 PROCESSOR_R4130,
58 PROCESSOR_R4300,
59 PROCESSOR_R4600,
60 PROCESSOR_R4650,
61 PROCESSOR_R5000,
62 PROCESSOR_R5400,
63 PROCESSOR_R5500,
64 PROCESSOR_R7000,
65 PROCESSOR_R8000,
66 PROCESSOR_R9000,
67 PROCESSOR_SB1,
68 PROCESSOR_SB1A,
69 PROCESSOR_SR71000,
70 PROCESSOR_MAX
71 };
72
73 /* Costs of various operations on the different architectures. */
74
75 struct mips_rtx_cost_data
76 {
77 unsigned short fp_add;
78 unsigned short fp_mult_sf;
79 unsigned short fp_mult_df;
80 unsigned short fp_div_sf;
81 unsigned short fp_div_df;
82 unsigned short int_mult_si;
83 unsigned short int_mult_di;
84 unsigned short int_div_si;
85 unsigned short int_div_di;
86 unsigned short branch_cost;
87 unsigned short memory_latency;
88 };
89
90 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
91 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
92 to work on a 64-bit machine. */
93
94 #define ABI_32 0
95 #define ABI_N32 1
96 #define ABI_64 2
97 #define ABI_EABI 3
98 #define ABI_O64 4
99
100 /* Information about one recognized processor. Defined here for the
101 benefit of TARGET_CPU_CPP_BUILTINS. */
102 struct mips_cpu_info {
103 /* The 'canonical' name of the processor as far as GCC is concerned.
104 It's typically a manufacturer's prefix followed by a numerical
105 designation. It should be lowercase. */
106 const char *name;
107
108 /* The internal processor number that most closely matches this
109 entry. Several processors can have the same value, if there's no
110 difference between them from GCC's point of view. */
111 enum processor_type cpu;
112
113 /* The ISA level that the processor implements. */
114 int isa;
115 };
116
117 /* Enumerates the setting of the -mcode-readable option. */
118 enum mips_code_readable_setting {
119 CODE_READABLE_NO,
120 CODE_READABLE_PCREL,
121 CODE_READABLE_YES
122 };
123
124 #ifndef USED_FOR_TARGET
125 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
126 extern const char *current_function_file; /* filename current function is in */
127 extern int num_source_filenames; /* current .file # */
128 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
129 extern int sym_lineno; /* sgi next label # for each stmt */
130 extern int set_noreorder; /* # of nested .set noreorder's */
131 extern int set_nomacro; /* # of nested .set nomacro's */
132 extern int set_noat; /* # of nested .set noat's */
133 extern int set_volatile; /* # of nested .set volatile's */
134 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
135 extern int mips_dbx_regno[];
136 extern int mips_dwarf_regno[];
137 extern bool mips_split_p[];
138 extern GTY(()) rtx cmp_operands[2];
139 extern enum processor_type mips_arch; /* which cpu to codegen for */
140 extern enum processor_type mips_tune; /* which cpu to schedule for */
141 extern int mips_isa; /* architectural level */
142 extern int mips_abi; /* which ABI to use */
143 extern const struct mips_cpu_info mips_cpu_info_table[];
144 extern const struct mips_cpu_info *mips_arch_info;
145 extern const struct mips_cpu_info *mips_tune_info;
146 extern const struct mips_rtx_cost_data *mips_cost;
147 extern enum mips_code_readable_setting mips_code_readable;
148 #endif
149
150 /* Macros to silence warnings about numbers being signed in traditional
151 C and unsigned in ISO C when compiled on 32-bit hosts. */
152
153 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
154 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
155 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
156
157 \f
158 /* Run-time compilation parameters selecting different hardware subsets. */
159
160 /* True if we are generating position-independent VxWorks RTP code. */
161 #define TARGET_RTP_PIC (TARGET_VXWORKS_RTP && flag_pic)
162
163 /* True if the call patterns should be split into a jalr followed by
164 an instruction to restore $gp. It is only safe to split the load
165 from the call when every use of $gp is explicit. */
166
167 #define TARGET_SPLIT_CALLS \
168 (TARGET_EXPLICIT_RELOCS && TARGET_CALL_CLOBBERED_GP)
169
170 /* True if we're generating a form of -mabicalls in which we can use
171 operators like %hi and %lo to refer to locally-binding symbols.
172 We can only do this for -mno-shared, and only then if we can use
173 relocation operations instead of assembly macros. It isn't really
174 worth using absolute sequences for 64-bit symbols because GOT
175 accesses are so much shorter. */
176
177 #define TARGET_ABSOLUTE_ABICALLS \
178 (TARGET_ABICALLS \
179 && !TARGET_SHARED \
180 && TARGET_EXPLICIT_RELOCS \
181 && !ABI_HAS_64BIT_SYMBOLS)
182
183 /* True if we can optimize sibling calls. For simplicity, we only
184 handle cases in which call_insn_operand will reject invalid
185 sibcall addresses. There are two cases in which this isn't true:
186
187 - TARGET_MIPS16. call_insn_operand accepts constant addresses
188 but there is no direct jump instruction. It isn't worth
189 using sibling calls in this case anyway; they would usually
190 be longer than normal calls.
191
192 - TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS. call_insn_operand
193 accepts global constants, but all sibcalls must be indirect. */
194 #define TARGET_SIBCALLS \
195 (!TARGET_MIPS16 && (!TARGET_USE_GOT || TARGET_EXPLICIT_RELOCS))
196
197 /* True if we need to use a global offset table to access some symbols. */
198 #define TARGET_USE_GOT (TARGET_ABICALLS || TARGET_RTP_PIC)
199
200 /* True if TARGET_USE_GOT and if $gp is a call-clobbered register. */
201 #define TARGET_CALL_CLOBBERED_GP (TARGET_ABICALLS && TARGET_OLDABI)
202
203 /* True if TARGET_USE_GOT and if $gp is a call-saved register. */
204 #define TARGET_CALL_SAVED_GP (TARGET_USE_GOT && !TARGET_CALL_CLOBBERED_GP)
205
206 /* True if indirect calls must use register class PIC_FN_ADDR_REG.
207 This is true for both the PIC and non-PIC VxWorks RTP modes. */
208 #define TARGET_USE_PIC_FN_ADDR_REG (TARGET_ABICALLS || TARGET_VXWORKS_RTP)
209
210 /* True if .gpword or .gpdword should be used for switch tables.
211
212 Although GAS does understand .gpdword, the SGI linker mishandles
213 the relocations GAS generates (R_MIPS_GPREL32 followed by R_MIPS_64).
214 We therefore disable GP-relative switch tables for n64 on IRIX targets. */
215 #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
216
217 /* Generate mips16 code */
218 #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0)
219 /* Generate mips16e code. Default 16bit ASE for mips32/mips32r2/mips64 */
220 #define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32)
221 /* Generate mips16e register save/restore sequences. */
222 #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32)
223
224 /* True if we're generating a form of MIPS16 code in which general
225 text loads are allowed. */
226 #define TARGET_MIPS16_TEXT_LOADS \
227 (TARGET_MIPS16 && mips_code_readable == CODE_READABLE_YES)
228
229 /* True if we're generating a form of MIPS16 code in which PC-relative
230 loads are allowed. */
231 #define TARGET_MIPS16_PCREL_LOADS \
232 (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL)
233
234 /* Generic ISA defines. */
235 #define ISA_MIPS1 (mips_isa == 1)
236 #define ISA_MIPS2 (mips_isa == 2)
237 #define ISA_MIPS3 (mips_isa == 3)
238 #define ISA_MIPS4 (mips_isa == 4)
239 #define ISA_MIPS32 (mips_isa == 32)
240 #define ISA_MIPS32R2 (mips_isa == 33)
241 #define ISA_MIPS64 (mips_isa == 64)
242
243 /* Architecture target defines. */
244 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
245 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
246 #define TARGET_MIPS4120 (mips_arch == PROCESSOR_R4120)
247 #define TARGET_MIPS4130 (mips_arch == PROCESSOR_R4130)
248 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
249 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
250 #define TARGET_MIPS7000 (mips_arch == PROCESSOR_R7000)
251 #define TARGET_MIPS9000 (mips_arch == PROCESSOR_R9000)
252 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1 \
253 || mips_arch == PROCESSOR_SB1A)
254 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
255
256 /* Scheduling target defines. */
257 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
258 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
259 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
260 #define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
261 #define TUNE_MIPS4130 (mips_tune == PROCESSOR_R4130)
262 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
263 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
264 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
265 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
266 #define TUNE_MIPS7000 (mips_tune == PROCESSOR_R7000)
267 #define TUNE_MIPS9000 (mips_tune == PROCESSOR_R9000)
268 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1 \
269 || mips_tune == PROCESSOR_SB1A)
270 #define TUNE_24K (mips_tune == PROCESSOR_24KC \
271 || mips_tune == PROCESSOR_24KF2_1 \
272 || mips_tune == PROCESSOR_24KF1_1)
273 #define TUNE_74K (mips_tune == PROCESSOR_74KC \
274 || mips_tune == PROCESSOR_74KF2_1 \
275 || mips_tune == PROCESSOR_74KF1_1 \
276 || mips_tune == PROCESSOR_74KF3_2)
277 #define TUNE_20KC (mips_tune == PROCESSOR_20KC)
278
279 /* True if the pre-reload scheduler should try to create chains of
280 multiply-add or multiply-subtract instructions. For example,
281 suppose we have:
282
283 t1 = a * b
284 t2 = t1 + c * d
285 t3 = e * f
286 t4 = t3 - g * h
287
288 t1 will have a higher priority than t2 and t3 will have a higher
289 priority than t4. However, before reload, there is no dependence
290 between t1 and t3, and they can often have similar priorities.
291 The scheduler will then tend to prefer:
292
293 t1 = a * b
294 t3 = e * f
295 t2 = t1 + c * d
296 t4 = t3 - g * h
297
298 which stops us from making full use of macc/madd-style instructions.
299 This sort of situation occurs frequently in Fourier transforms and
300 in unrolled loops.
301
302 To counter this, the TUNE_MACC_CHAINS code will reorder the ready
303 queue so that chained multiply-add and multiply-subtract instructions
304 appear ahead of any other instruction that is likely to clobber lo.
305 In the example above, if t2 and t3 become ready at the same time,
306 the code ensures that t2 is scheduled first.
307
308 Multiply-accumulate instructions are a bigger win for some targets
309 than others, so this macro is defined on an opt-in basis. */
310 #define TUNE_MACC_CHAINS (TUNE_MIPS5500 \
311 || TUNE_MIPS4120 \
312 || TUNE_MIPS4130 \
313 || TUNE_24K)
314
315 #define TARGET_OLDABI (mips_abi == ABI_32 || mips_abi == ABI_O64)
316 #define TARGET_NEWABI (mips_abi == ABI_N32 || mips_abi == ABI_64)
317
318 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
319 directly accessible, while the command-line options select
320 TARGET_HARD_FLOAT_ABI and TARGET_SOFT_FLOAT_ABI to reflect the ABI
321 in use. */
322 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
323 #define TARGET_SOFT_FLOAT (TARGET_SOFT_FLOAT_ABI || TARGET_MIPS16)
324
325 /* IRIX specific stuff. */
326 #define TARGET_IRIX 0
327 #define TARGET_IRIX6 0
328
329 /* Define preprocessor macros for the -march and -mtune options.
330 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
331 processor. If INFO's canonical name is "foo", define PREFIX to
332 be "foo", and define an additional macro PREFIX_FOO. */
333 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
334 do \
335 { \
336 char *macro, *p; \
337 \
338 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
339 for (p = macro; *p != 0; p++) \
340 *p = TOUPPER (*p); \
341 \
342 builtin_define (macro); \
343 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
344 free (macro); \
345 } \
346 while (0)
347
348 /* Target CPU builtins. */
349 #define TARGET_CPU_CPP_BUILTINS() \
350 do \
351 { \
352 /* Everyone but IRIX defines this to mips. */ \
353 if (!TARGET_IRIX) \
354 builtin_assert ("machine=mips"); \
355 \
356 builtin_assert ("cpu=mips"); \
357 builtin_define ("__mips__"); \
358 builtin_define ("_mips"); \
359 \
360 /* We do this here because __mips is defined below and so we \
361 can't use builtin_define_std. We don't ever want to define \
362 "mips" for VxWorks because some of the VxWorks headers \
363 construct include filenames from a root directory macro, \
364 an architecture macro and a filename, where the architecture \
365 macro expands to 'mips'. If we define 'mips' to 1, the \
366 architecture macro expands to 1 as well. */ \
367 if (!flag_iso && !TARGET_VXWORKS) \
368 builtin_define ("mips"); \
369 \
370 if (TARGET_64BIT) \
371 builtin_define ("__mips64"); \
372 \
373 if (!TARGET_IRIX) \
374 { \
375 /* Treat _R3000 and _R4000 like register-size \
376 defines, which is how they've historically \
377 been used. */ \
378 if (TARGET_64BIT) \
379 { \
380 builtin_define_std ("R4000"); \
381 builtin_define ("_R4000"); \
382 } \
383 else \
384 { \
385 builtin_define_std ("R3000"); \
386 builtin_define ("_R3000"); \
387 } \
388 } \
389 if (TARGET_FLOAT64) \
390 builtin_define ("__mips_fpr=64"); \
391 else \
392 builtin_define ("__mips_fpr=32"); \
393 \
394 if (TARGET_MIPS16) \
395 builtin_define ("__mips16"); \
396 \
397 if (TARGET_MIPS3D) \
398 builtin_define ("__mips3d"); \
399 \
400 if (TARGET_SMARTMIPS) \
401 builtin_define ("__mips_smartmips"); \
402 \
403 if (TARGET_DSP) \
404 { \
405 builtin_define ("__mips_dsp"); \
406 if (TARGET_DSPR2) \
407 { \
408 builtin_define ("__mips_dspr2"); \
409 builtin_define ("__mips_dsp_rev=2"); \
410 } \
411 else \
412 builtin_define ("__mips_dsp_rev=1"); \
413 } \
414 \
415 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
416 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
417 \
418 if (ISA_MIPS1) \
419 { \
420 builtin_define ("__mips=1"); \
421 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
422 } \
423 else if (ISA_MIPS2) \
424 { \
425 builtin_define ("__mips=2"); \
426 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
427 } \
428 else if (ISA_MIPS3) \
429 { \
430 builtin_define ("__mips=3"); \
431 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
432 } \
433 else if (ISA_MIPS4) \
434 { \
435 builtin_define ("__mips=4"); \
436 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
437 } \
438 else if (ISA_MIPS32) \
439 { \
440 builtin_define ("__mips=32"); \
441 builtin_define ("__mips_isa_rev=1"); \
442 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
443 } \
444 else if (ISA_MIPS32R2) \
445 { \
446 builtin_define ("__mips=32"); \
447 builtin_define ("__mips_isa_rev=2"); \
448 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
449 } \
450 else if (ISA_MIPS64) \
451 { \
452 builtin_define ("__mips=64"); \
453 builtin_define ("__mips_isa_rev=1"); \
454 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
455 } \
456 \
457 switch (mips_abi) \
458 { \
459 case ABI_32: \
460 builtin_define ("_ABIO32=1"); \
461 builtin_define ("_MIPS_SIM=_ABIO32"); \
462 break; \
463 \
464 case ABI_N32: \
465 builtin_define ("_ABIN32=2"); \
466 builtin_define ("_MIPS_SIM=_ABIN32"); \
467 break; \
468 \
469 case ABI_64: \
470 builtin_define ("_ABI64=3"); \
471 builtin_define ("_MIPS_SIM=_ABI64"); \
472 break; \
473 \
474 case ABI_O64: \
475 builtin_define ("_ABIO64=4"); \
476 builtin_define ("_MIPS_SIM=_ABIO64"); \
477 break; \
478 } \
479 \
480 builtin_define_with_int_value ("_MIPS_SZINT", INT_TYPE_SIZE); \
481 builtin_define_with_int_value ("_MIPS_SZLONG", LONG_TYPE_SIZE); \
482 builtin_define_with_int_value ("_MIPS_SZPTR", POINTER_SIZE); \
483 builtin_define_with_int_value ("_MIPS_FPSET", \
484 32 / MAX_FPRS_PER_FMT); \
485 \
486 /* These defines reflect the ABI in use, not whether the \
487 FPU is directly accessible. */ \
488 if (TARGET_HARD_FLOAT_ABI) \
489 builtin_define ("__mips_hard_float"); \
490 else \
491 builtin_define ("__mips_soft_float"); \
492 \
493 if (TARGET_SINGLE_FLOAT) \
494 builtin_define ("__mips_single_float"); \
495 \
496 if (TARGET_PAIRED_SINGLE_FLOAT) \
497 builtin_define ("__mips_paired_single_float"); \
498 \
499 if (TARGET_BIG_ENDIAN) \
500 { \
501 builtin_define_std ("MIPSEB"); \
502 builtin_define ("_MIPSEB"); \
503 } \
504 else \
505 { \
506 builtin_define_std ("MIPSEL"); \
507 builtin_define ("_MIPSEL"); \
508 } \
509 \
510 /* Macros dependent on the C dialect. */ \
511 if (preprocessing_asm_p ()) \
512 { \
513 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
514 builtin_define ("_LANGUAGE_ASSEMBLY"); \
515 } \
516 else if (c_dialect_cxx ()) \
517 { \
518 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
519 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
520 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
521 } \
522 else \
523 { \
524 builtin_define_std ("LANGUAGE_C"); \
525 builtin_define ("_LANGUAGE_C"); \
526 } \
527 if (c_dialect_objc ()) \
528 { \
529 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
530 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
531 /* Bizarre, but needed at least for Irix. */ \
532 builtin_define_std ("LANGUAGE_C"); \
533 builtin_define ("_LANGUAGE_C"); \
534 } \
535 \
536 if (mips_abi == ABI_EABI) \
537 builtin_define ("__mips_eabi"); \
538 } \
539 while (0)
540
541 /* Default target_flags if no switches are specified */
542
543 #ifndef TARGET_DEFAULT
544 #define TARGET_DEFAULT 0
545 #endif
546
547 #ifndef TARGET_CPU_DEFAULT
548 #define TARGET_CPU_DEFAULT 0
549 #endif
550
551 #ifndef TARGET_ENDIAN_DEFAULT
552 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
553 #endif
554
555 #ifndef TARGET_FP_EXCEPTIONS_DEFAULT
556 #define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
557 #endif
558
559 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
560 #ifndef MIPS_ISA_DEFAULT
561 #ifndef MIPS_CPU_STRING_DEFAULT
562 #define MIPS_CPU_STRING_DEFAULT "from-abi"
563 #endif
564 #endif
565
566 #ifdef IN_LIBGCC2
567 #undef TARGET_64BIT
568 /* Make this compile time constant for libgcc2 */
569 #ifdef __mips64
570 #define TARGET_64BIT 1
571 #else
572 #define TARGET_64BIT 0
573 #endif
574 #endif /* IN_LIBGCC2 */
575
576 /* Force the call stack unwinders in unwind.inc not to be MIPS16 code
577 when compiled with hardware floating point. This is because MIPS16
578 code cannot save and restore the floating-point registers, which is
579 important if in a mixed MIPS16/non-MIPS16 environment. */
580
581 #ifdef IN_LIBGCC2
582 #if __mips_hard_float
583 #define LIBGCC2_UNWIND_ATTRIBUTE __attribute__((__nomips16__))
584 #endif
585 #endif /* IN_LIBGCC2 */
586
587 #define TARGET_LIBGCC_SDATA_SECTION ".sdata"
588
589 #ifndef MULTILIB_ENDIAN_DEFAULT
590 #if TARGET_ENDIAN_DEFAULT == 0
591 #define MULTILIB_ENDIAN_DEFAULT "EL"
592 #else
593 #define MULTILIB_ENDIAN_DEFAULT "EB"
594 #endif
595 #endif
596
597 #ifndef MULTILIB_ISA_DEFAULT
598 # if MIPS_ISA_DEFAULT == 1
599 # define MULTILIB_ISA_DEFAULT "mips1"
600 # else
601 # if MIPS_ISA_DEFAULT == 2
602 # define MULTILIB_ISA_DEFAULT "mips2"
603 # else
604 # if MIPS_ISA_DEFAULT == 3
605 # define MULTILIB_ISA_DEFAULT "mips3"
606 # else
607 # if MIPS_ISA_DEFAULT == 4
608 # define MULTILIB_ISA_DEFAULT "mips4"
609 # else
610 # if MIPS_ISA_DEFAULT == 32
611 # define MULTILIB_ISA_DEFAULT "mips32"
612 # else
613 # if MIPS_ISA_DEFAULT == 33
614 # define MULTILIB_ISA_DEFAULT "mips32r2"
615 # else
616 # if MIPS_ISA_DEFAULT == 64
617 # define MULTILIB_ISA_DEFAULT "mips64"
618 # else
619 # define MULTILIB_ISA_DEFAULT "mips1"
620 # endif
621 # endif
622 # endif
623 # endif
624 # endif
625 # endif
626 # endif
627 #endif
628
629 #ifndef MULTILIB_DEFAULTS
630 #define MULTILIB_DEFAULTS \
631 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
632 #endif
633
634 /* We must pass -EL to the linker by default for little endian embedded
635 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
636 linker will default to using big-endian output files. The OUTPUT_FORMAT
637 line must be in the linker script, otherwise -EB/-EL will not work. */
638
639 #ifndef ENDIAN_SPEC
640 #if TARGET_ENDIAN_DEFAULT == 0
641 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
642 #else
643 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
644 #endif
645 #endif
646
647 /* A spec condition that matches all non-mips16 -mips arguments. */
648
649 #define MIPS_ISA_LEVEL_OPTION_SPEC \
650 "mips1|mips2|mips3|mips4|mips32*|mips64*"
651
652 /* A spec condition that matches all non-mips16 architecture arguments. */
653
654 #define MIPS_ARCH_OPTION_SPEC \
655 MIPS_ISA_LEVEL_OPTION_SPEC "|march=*"
656
657 /* A spec that infers a -mips argument from an -march argument,
658 or injects the default if no architecture is specified. */
659
660 #define MIPS_ISA_LEVEL_SPEC \
661 "%{" MIPS_ISA_LEVEL_OPTION_SPEC ":;: \
662 %{march=mips1|march=r2000|march=r3000|march=r3900:-mips1} \
663 %{march=mips2|march=r6000:-mips2} \
664 %{march=mips3|march=r4*|march=vr4*|march=orion:-mips3} \
665 %{march=mips4|march=r8000|march=vr5*|march=rm7000|march=rm9000:-mips4} \
666 %{march=mips32|march=4kc|march=4km|march=4kp|march=4ksc:-mips32} \
667 %{march=mips32r2|march=m4k|march=4ke*|march=4ksd|march=24k* \
668 |march=34k*|march=74k*: -mips32r2} \
669 %{march=mips64|march=5k*|march=20k*|march=sb1*|march=sr71000: -mips64} \
670 %{!march=*: -" MULTILIB_ISA_DEFAULT "}}"
671
672 /* A spec that infers a -mhard-float or -msoft-float setting from an
673 -march argument. Note that soft-float and hard-float code are not
674 link-compatible. */
675
676 #define MIPS_ARCH_FLOAT_SPEC \
677 "%{mhard-float|msoft-float|march=mips*:; \
678 march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
679 |march=34kc|march=74kc|march=5kc: -msoft-float; \
680 march=*: -mhard-float}"
681
682 /* A spec condition that matches 32-bit options. It only works if
683 MIPS_ISA_LEVEL_SPEC has been applied. */
684
685 #define MIPS_32BIT_OPTION_SPEC \
686 "mips1|mips2|mips32*|mgp32"
687
688 /* Support for a compile-time default CPU, et cetera. The rules are:
689 --with-arch is ignored if -march is specified or a -mips is specified
690 (other than -mips16).
691 --with-tune is ignored if -mtune is specified.
692 --with-abi is ignored if -mabi is specified.
693 --with-float is ignored if -mhard-float or -msoft-float are
694 specified.
695 --with-divide is ignored if -mdivide-traps or -mdivide-breaks are
696 specified. */
697 #define OPTION_DEFAULT_SPECS \
698 {"arch", "%{" MIPS_ARCH_OPTION_SPEC ":;: -march=%(VALUE)}" }, \
699 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \
700 {"abi", "%{!mabi=*:-mabi=%(VALUE)}" }, \
701 {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
702 {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
703 {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }
704
705
706 #define GENERATE_DIVIDE_TRAPS (TARGET_DIVIDE_TRAPS \
707 && ISA_HAS_COND_TRAP)
708
709 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
710 && !TARGET_SR71K \
711 && !TARGET_MIPS16)
712
713 /* True if the ABI can only work with 64-bit integer registers. We
714 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
715 otherwise floating-point registers must also be 64-bit. */
716 #define ABI_NEEDS_64BIT_REGS (TARGET_NEWABI || mips_abi == ABI_O64)
717
718 /* Likewise for 32-bit regs. */
719 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
720
721 /* True if symbols are 64 bits wide. At present, n64 is the only
722 ABI for which this is true. */
723 #define ABI_HAS_64BIT_SYMBOLS (mips_abi == ABI_64 && !TARGET_SYM32)
724
725 /* ISA has instructions for managing 64-bit fp and gp regs (e.g. mips3). */
726 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
727 || ISA_MIPS4 \
728 || ISA_MIPS64)
729
730 /* ISA has branch likely instructions (e.g. mips2). */
731 /* Disable branchlikely for tx39 until compare rewrite. They haven't
732 been generated up to this point. */
733 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1)
734
735 /* ISA has a three-operand multiplication instruction (usually spelt "mul"). */
736 #define ISA_HAS_MUL3 ((TARGET_MIPS3900 \
737 || TARGET_MIPS5400 \
738 || TARGET_MIPS5500 \
739 || TARGET_MIPS7000 \
740 || TARGET_MIPS9000 \
741 || TARGET_MAD \
742 || ISA_MIPS32 \
743 || ISA_MIPS32R2 \
744 || ISA_MIPS64) \
745 && !TARGET_MIPS16)
746
747 /* ISA has the conditional move instructions introduced in mips4. */
748 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
749 || ISA_MIPS32 \
750 || ISA_MIPS32R2 \
751 || ISA_MIPS64) \
752 && !TARGET_MIPS5500 \
753 && !TARGET_MIPS16)
754
755 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
756 branch on CC, and move (both FP and non-FP) on CC. */
757 #define ISA_HAS_8CC (ISA_MIPS4 \
758 || ISA_MIPS32 \
759 || ISA_MIPS32R2 \
760 || ISA_MIPS64)
761
762 /* This is a catch all for other mips4 instructions: indexed load, the
763 FP madd and msub instructions, and the FP recip and recip sqrt
764 instructions. */
765 #define ISA_HAS_FP4 ((ISA_MIPS4 \
766 || (ISA_MIPS32R2 && TARGET_FLOAT64) \
767 || ISA_MIPS64) \
768 && !TARGET_MIPS16)
769
770 /* ISA has conditional trap instructions. */
771 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
772 && !TARGET_MIPS16)
773
774 /* ISA has integer multiply-accumulate instructions, madd and msub. */
775 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
776 || ISA_MIPS32R2 \
777 || ISA_MIPS64) \
778 && !TARGET_MIPS16)
779
780 /* Integer multiply-accumulate instructions should be generated. */
781 #define GENERATE_MADD_MSUB (ISA_HAS_MADD_MSUB && !TUNE_74K)
782
783 /* ISA has floating-point nmadd and nmsub instructions. */
784 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
785 || ISA_MIPS64) \
786 && (!TARGET_MIPS5400 || TARGET_MAD) \
787 && !TARGET_MIPS16)
788
789 /* ISA has count leading zeroes/ones instruction (not implemented). */
790 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
791 || ISA_MIPS32R2 \
792 || ISA_MIPS64) \
793 && !TARGET_MIPS16)
794
795 /* ISA has three operand multiply instructions that put
796 the high part in an accumulator: mulhi or mulhiu. */
797 #define ISA_HAS_MULHI ((TARGET_MIPS5400 \
798 || TARGET_MIPS5500 \
799 || TARGET_SR71K) \
800 && !TARGET_MIPS16)
801
802 /* ISA has three operand multiply instructions that
803 negates the result and puts the result in an accumulator. */
804 #define ISA_HAS_MULS ((TARGET_MIPS5400 \
805 || TARGET_MIPS5500 \
806 || TARGET_SR71K) \
807 && !TARGET_MIPS16)
808
809 /* ISA has three operand multiply instructions that subtracts the
810 result from a 4th operand and puts the result in an accumulator. */
811 #define ISA_HAS_MSAC ((TARGET_MIPS5400 \
812 || TARGET_MIPS5500 \
813 || TARGET_SR71K) \
814 && !TARGET_MIPS16)
815
816 /* ISA has three operand multiply instructions that the result
817 from a 4th operand and puts the result in an accumulator. */
818 #define ISA_HAS_MACC ((TARGET_MIPS4120 \
819 || TARGET_MIPS4130 \
820 || TARGET_MIPS5400 \
821 || TARGET_MIPS5500 \
822 || TARGET_SR71K) \
823 && !TARGET_MIPS16)
824
825 /* ISA has NEC VR-style MACC, MACCHI, DMACC and DMACCHI instructions. */
826 #define ISA_HAS_MACCHI ((TARGET_MIPS4120 \
827 || TARGET_MIPS4130) \
828 && !TARGET_MIPS16)
829
830 /* ISA has the "ror" (rotate right) instructions. */
831 #define ISA_HAS_ROR ((ISA_MIPS32R2 \
832 || TARGET_MIPS5400 \
833 || TARGET_MIPS5500 \
834 || TARGET_SR71K \
835 || TARGET_SMARTMIPS) \
836 && !TARGET_MIPS16)
837
838 /* ISA has data prefetch instructions. This controls use of 'pref'. */
839 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
840 || ISA_MIPS32 \
841 || ISA_MIPS32R2 \
842 || ISA_MIPS64) \
843 && !TARGET_MIPS16)
844
845 /* ISA has data indexed prefetch instructions. This controls use of
846 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
847 (prefx is a cop1x instruction, so can only be used if FP is
848 enabled.) */
849 #define ISA_HAS_PREFETCHX ((ISA_MIPS4 \
850 || ISA_MIPS32R2 \
851 || ISA_MIPS64) \
852 && !TARGET_MIPS16)
853
854 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
855 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
856 also requires TARGET_DOUBLE_FLOAT. */
857 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
858
859 /* ISA includes the MIPS32r2 seb and seh instructions. */
860 #define ISA_HAS_SEB_SEH (ISA_MIPS32R2 \
861 && !TARGET_MIPS16)
862
863 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions. */
864 #define ISA_HAS_EXT_INS (ISA_MIPS32R2 \
865 && !TARGET_MIPS16)
866
867 /* ISA has instructions for accessing top part of 64-bit fp regs. */
868 #define ISA_HAS_MXHC1 (TARGET_FLOAT64 && ISA_MIPS32R2)
869
870 /* ISA has lwxs instruction (load w/scaled index address. */
871 #define ISA_HAS_LWXS (TARGET_SMARTMIPS && !TARGET_MIPS16)
872
873 /* The DSP ASE is available. */
874 #define ISA_HAS_DSP (TARGET_DSP && !TARGET_MIPS16)
875
876 /* Revision 2 of the DSP ASE is available. */
877 #define ISA_HAS_DSPR2 (TARGET_DSPR2 && !TARGET_MIPS16)
878
879 /* True if the result of a load is not available to the next instruction.
880 A nop will then be needed between instructions like "lw $4,..."
881 and "addiu $4,$4,1". */
882 #define ISA_HAS_LOAD_DELAY (ISA_MIPS1 \
883 && !TARGET_MIPS3900 \
884 && !TARGET_MIPS16)
885
886 /* Likewise mtc1 and mfc1. */
887 #define ISA_HAS_XFER_DELAY (mips_isa <= 3)
888
889 /* Likewise floating-point comparisons. */
890 #define ISA_HAS_FCMP_DELAY (mips_isa <= 3)
891
892 /* True if mflo and mfhi can be immediately followed by instructions
893 which write to the HI and LO registers.
894
895 According to MIPS specifications, MIPS ISAs I, II, and III need
896 (at least) two instructions between the reads of HI/LO and
897 instructions which write them, and later ISAs do not. Contradicting
898 the MIPS specifications, some MIPS IV processor user manuals (e.g.
899 the UM for the NEC Vr5000) document needing the instructions between
900 HI/LO reads and writes, as well. Therefore, we declare only MIPS32,
901 MIPS64 and later ISAs to have the interlocks, plus any specific
902 earlier-ISA CPUs for which CPU documentation declares that the
903 instructions are really interlocked. */
904 #define ISA_HAS_HILO_INTERLOCKS (ISA_MIPS32 \
905 || ISA_MIPS32R2 \
906 || ISA_MIPS64 \
907 || TARGET_MIPS5500)
908
909 /* ISA includes synci, jr.hb and jalr.hb. */
910 #define ISA_HAS_SYNCI (ISA_MIPS32R2 && !TARGET_MIPS16)
911
912 /* ISA includes sync. */
913 #define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
914 #define GENERATE_SYNC \
915 (target_flags_explicit & MASK_LLSC \
916 ? TARGET_LLSC && !TARGET_MIPS16 \
917 : ISA_HAS_SYNC)
918
919 /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
920 because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
921 instructions. */
922 #define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
923 #define GENERATE_LL_SC \
924 (target_flags_explicit & MASK_LLSC \
925 ? TARGET_LLSC && !TARGET_MIPS16 \
926 : ISA_HAS_LL_SC)
927 \f
928 /* Add -G xx support. */
929
930 #undef SWITCH_TAKES_ARG
931 #define SWITCH_TAKES_ARG(CHAR) \
932 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
933
934 #define OVERRIDE_OPTIONS override_options ()
935
936 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
937
938 /* Show we can debug even without a frame pointer. */
939 #define CAN_DEBUG_WITHOUT_FP
940 \f
941 /* Tell collect what flags to pass to nm. */
942 #ifndef NM_FLAGS
943 #define NM_FLAGS "-Bn"
944 #endif
945
946 \f
947 #ifndef MIPS_ABI_DEFAULT
948 #define MIPS_ABI_DEFAULT ABI_32
949 #endif
950
951 /* Use the most portable ABI flag for the ASM specs. */
952
953 #if MIPS_ABI_DEFAULT == ABI_32
954 #define MULTILIB_ABI_DEFAULT "mabi=32"
955 #endif
956
957 #if MIPS_ABI_DEFAULT == ABI_O64
958 #define MULTILIB_ABI_DEFAULT "mabi=o64"
959 #endif
960
961 #if MIPS_ABI_DEFAULT == ABI_N32
962 #define MULTILIB_ABI_DEFAULT "mabi=n32"
963 #endif
964
965 #if MIPS_ABI_DEFAULT == ABI_64
966 #define MULTILIB_ABI_DEFAULT "mabi=64"
967 #endif
968
969 #if MIPS_ABI_DEFAULT == ABI_EABI
970 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
971 #endif
972
973 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
974 to the assembler. It may be overridden by subtargets. */
975 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
976 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
977 %{noasmopt:-O0} \
978 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
979 #endif
980
981 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
982 the assembler. It may be overridden by subtargets.
983
984 Beginning with gas 2.13, -mdebug must be passed to correctly handle
985 COFF debugging info. */
986
987 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
988 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
989 %{g} %{g0} %{g1} %{g2} %{g3} \
990 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
991 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
992 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
993 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
994 %{gcoff*:-mdebug} %{!gcoff*:-no-mdebug}"
995 #endif
996
997 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
998 overridden by subtargets. */
999
1000 #ifndef SUBTARGET_ASM_SPEC
1001 #define SUBTARGET_ASM_SPEC ""
1002 #endif
1003
1004 #undef ASM_SPEC
1005 #define ASM_SPEC "\
1006 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
1007 %{mips32} %{mips32r2} %{mips64} \
1008 %{mips16} %{mno-mips16:-no-mips16} \
1009 %{mips3d} %{mno-mips3d:-no-mips3d} \
1010 %{mdmx} %{mno-mdmx:-no-mdmx} \
1011 %{mdsp} %{mno-dsp} \
1012 %{mdspr2} %{mno-dspr2} \
1013 %{msmartmips} %{mno-smartmips} \
1014 %{mmt} %{mno-mt} \
1015 %{mfix-vr4120} %{mfix-vr4130} \
1016 %(subtarget_asm_optimizing_spec) \
1017 %(subtarget_asm_debugging_spec) \
1018 %{mabi=*} %{!mabi*: %(asm_abi_default_spec)} \
1019 %{mgp32} %{mgp64} %{march=*} %{mxgot:-xgot} \
1020 %{mfp32} %{mfp64} \
1021 %{mshared} %{mno-shared} \
1022 %{msym32} %{mno-sym32} \
1023 %{mtune=*} %{v} \
1024 %(subtarget_asm_spec)"
1025
1026 /* Extra switches sometimes passed to the linker. */
1027 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1028 will interpret it as a -b option. */
1029
1030 #ifndef LINK_SPEC
1031 #define LINK_SPEC "\
1032 %(endian_spec) \
1033 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips32r2} %{mips64} \
1034 %{bestGnum} %{shared} %{non_shared}"
1035 #endif /* LINK_SPEC defined */
1036
1037
1038 /* Specs for the compiler proper */
1039
1040 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1041 overridden by subtargets. */
1042 #ifndef SUBTARGET_CC1_SPEC
1043 #define SUBTARGET_CC1_SPEC ""
1044 #endif
1045
1046 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1047
1048 #undef CC1_SPEC
1049 #define CC1_SPEC "\
1050 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1051 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1052 %{save-temps: } \
1053 %(subtarget_cc1_spec)"
1054
1055 /* Preprocessor specs. */
1056
1057 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1058 overridden by subtargets. */
1059 #ifndef SUBTARGET_CPP_SPEC
1060 #define SUBTARGET_CPP_SPEC ""
1061 #endif
1062
1063 #define CPP_SPEC "%(subtarget_cpp_spec)"
1064
1065 /* This macro defines names of additional specifications to put in the specs
1066 that can be used in various specifications like CC1_SPEC. Its definition
1067 is an initializer with a subgrouping for each command option.
1068
1069 Each subgrouping contains a string constant, that defines the
1070 specification name, and a string constant that used by the GCC driver
1071 program.
1072
1073 Do not define this macro if it does not need to do anything. */
1074
1075 #define EXTRA_SPECS \
1076 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1077 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1078 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1079 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1080 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1081 { "asm_abi_default_spec", "-" MULTILIB_ABI_DEFAULT }, \
1082 { "endian_spec", ENDIAN_SPEC }, \
1083 SUBTARGET_EXTRA_SPECS
1084
1085 #ifndef SUBTARGET_EXTRA_SPECS
1086 #define SUBTARGET_EXTRA_SPECS
1087 #endif
1088 \f
1089 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1090 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1091 #define DWARF2_DEBUGGING_INFO 1 /* dwarf2 debugging info */
1092
1093 #ifndef PREFERRED_DEBUGGING_TYPE
1094 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
1095 #endif
1096
1097 #define DWARF2_ADDR_SIZE (ABI_HAS_64BIT_SYMBOLS ? 8 : 4)
1098
1099 /* By default, turn on GDB extensions. */
1100 #define DEFAULT_GDB_EXTENSIONS 1
1101
1102 /* Local compiler-generated symbols must have a prefix that the assembler
1103 understands. By default, this is $, although some targets (e.g.,
1104 NetBSD-ELF) need to override this. */
1105
1106 #ifndef LOCAL_LABEL_PREFIX
1107 #define LOCAL_LABEL_PREFIX "$"
1108 #endif
1109
1110 /* By default on the mips, external symbols do not have an underscore
1111 prepended, but some targets (e.g., NetBSD) require this. */
1112
1113 #ifndef USER_LABEL_PREFIX
1114 #define USER_LABEL_PREFIX ""
1115 #endif
1116
1117 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1118 since the length can run past this up to a continuation point. */
1119 #undef DBX_CONTIN_LENGTH
1120 #define DBX_CONTIN_LENGTH 1500
1121
1122 /* How to renumber registers for dbx and gdb. */
1123 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[REGNO]
1124
1125 /* The mapping from gcc register number to DWARF 2 CFA column number. */
1126 #define DWARF_FRAME_REGNUM(REGNO) mips_dwarf_regno[REGNO]
1127
1128 /* The DWARF 2 CFA column which tracks the return address. */
1129 #define DWARF_FRAME_RETURN_COLUMN (GP_REG_FIRST + 31)
1130
1131 /* Before the prologue, RA lives in r31. */
1132 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1133
1134 /* Describe how we implement __builtin_eh_return. */
1135 #define EH_RETURN_DATA_REGNO(N) \
1136 ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1137
1138 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1139
1140 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1141 The default for this in 64-bit mode is 8, which causes problems with
1142 SFmode register saves. */
1143 #define DWARF_CIE_DATA_ALIGNMENT -4
1144
1145 /* Correct the offset of automatic variables and arguments. Note that
1146 the MIPS debug format wants all automatic variables and arguments
1147 to be in terms of the virtual frame pointer (stack pointer before
1148 any adjustment in the function), while the MIPS 3.0 linker wants
1149 the frame pointer to be the stack pointer after the initial
1150 adjustment. */
1151
1152 #define DEBUGGER_AUTO_OFFSET(X) \
1153 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1154 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1155 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1156 \f
1157 /* Target machine storage layout */
1158
1159 #define BITS_BIG_ENDIAN 0
1160 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1161 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1162
1163 /* Define this to set the endianness to use in libgcc2.c, which can
1164 not depend on target_flags. */
1165 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1166 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1167 #else
1168 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1169 #endif
1170
1171 #define MAX_BITS_PER_WORD 64
1172
1173 /* Width of a word, in units (bytes). */
1174 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1175 #ifndef IN_LIBGCC2
1176 #define MIN_UNITS_PER_WORD 4
1177 #endif
1178
1179 /* For MIPS, width of a floating point register. */
1180 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1181
1182 /* The number of consecutive floating-point registers needed to store the
1183 largest format supported by the FPU. */
1184 #define MAX_FPRS_PER_FMT (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1185
1186 /* The number of consecutive floating-point registers needed to store the
1187 smallest format supported by the FPU. */
1188 #define MIN_FPRS_PER_FMT \
1189 (ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 ? 1 : MAX_FPRS_PER_FMT)
1190
1191 /* The largest size of value that can be held in floating-point
1192 registers and moved with a single instruction. */
1193 #define UNITS_PER_HWFPVALUE \
1194 (TARGET_SOFT_FLOAT_ABI ? 0 : MAX_FPRS_PER_FMT * UNITS_PER_FPREG)
1195
1196 /* The largest size of value that can be held in floating-point
1197 registers. */
1198 #define UNITS_PER_FPVALUE \
1199 (TARGET_SOFT_FLOAT_ABI ? 0 \
1200 : TARGET_SINGLE_FLOAT ? UNITS_PER_FPREG \
1201 : LONG_DOUBLE_TYPE_SIZE / BITS_PER_UNIT)
1202
1203 /* The number of bytes in a double. */
1204 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1205
1206 #define UNITS_PER_SIMD_WORD (TARGET_PAIRED_SINGLE_FLOAT ? 8 : UNITS_PER_WORD)
1207
1208 /* Set the sizes of the core types. */
1209 #define SHORT_TYPE_SIZE 16
1210 #define INT_TYPE_SIZE 32
1211 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1212 #define LONG_LONG_TYPE_SIZE 64
1213
1214 #define FLOAT_TYPE_SIZE 32
1215 #define DOUBLE_TYPE_SIZE 64
1216 #define LONG_DOUBLE_TYPE_SIZE (TARGET_NEWABI ? 128 : 64)
1217
1218 /* Define the sizes of fixed-point types. */
1219 #define SHORT_FRACT_TYPE_SIZE 8
1220 #define FRACT_TYPE_SIZE 16
1221 #define LONG_FRACT_TYPE_SIZE 32
1222 #define LONG_LONG_FRACT_TYPE_SIZE 64
1223
1224 #define SHORT_ACCUM_TYPE_SIZE 16
1225 #define ACCUM_TYPE_SIZE 32
1226 #define LONG_ACCUM_TYPE_SIZE 64
1227 /* FIXME. LONG_LONG_ACCUM_TYPE_SIZE should be 128 bits, but GCC
1228 doesn't support 128-bit integers for MIPS32 currently. */
1229 #define LONG_LONG_ACCUM_TYPE_SIZE (TARGET_64BIT ? 128 : 64)
1230
1231 /* long double is not a fixed mode, but the idea is that, if we
1232 support long double, we also want a 128-bit integer type. */
1233 #define MAX_FIXED_MODE_SIZE LONG_DOUBLE_TYPE_SIZE
1234
1235 #ifdef IN_LIBGCC2
1236 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
1237 || (defined _ABI64 && _MIPS_SIM == _ABI64)
1238 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128
1239 # else
1240 # define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64
1241 # endif
1242 #endif
1243
1244 /* Width in bits of a pointer. */
1245 #ifndef POINTER_SIZE
1246 #define POINTER_SIZE ((TARGET_LONG64 && TARGET_64BIT) ? 64 : 32)
1247 #endif
1248
1249 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1250 #define PARM_BOUNDARY BITS_PER_WORD
1251
1252 /* Allocation boundary (in *bits*) for the code of a function. */
1253 #define FUNCTION_BOUNDARY 32
1254
1255 /* Alignment of field after `int : 0' in a structure. */
1256 #define EMPTY_FIELD_BOUNDARY 32
1257
1258 /* Every structure's size must be a multiple of this. */
1259 /* 8 is observed right on a DECstation and on riscos 4.02. */
1260 #define STRUCTURE_SIZE_BOUNDARY 8
1261
1262 /* There is no point aligning anything to a rounder boundary than this. */
1263 #define BIGGEST_ALIGNMENT LONG_DOUBLE_TYPE_SIZE
1264
1265 /* All accesses must be aligned. */
1266 #define STRICT_ALIGNMENT 1
1267
1268 /* Define this if you wish to imitate the way many other C compilers
1269 handle alignment of bitfields and the structures that contain
1270 them.
1271
1272 The behavior is that the type written for a bit-field (`int',
1273 `short', or other integer type) imposes an alignment for the
1274 entire structure, as if the structure really did contain an
1275 ordinary field of that type. In addition, the bit-field is placed
1276 within the structure so that it would fit within such a field,
1277 not crossing a boundary for it.
1278
1279 Thus, on most machines, a bit-field whose type is written as `int'
1280 would not cross a four-byte boundary, and would force four-byte
1281 alignment for the whole structure. (The alignment used may not
1282 be four bytes; it is controlled by the other alignment
1283 parameters.)
1284
1285 If the macro is defined, its definition should be a C expression;
1286 a nonzero value for the expression enables this behavior. */
1287
1288 #define PCC_BITFIELD_TYPE_MATTERS 1
1289
1290 /* If defined, a C expression to compute the alignment given to a
1291 constant that is being placed in memory. CONSTANT is the constant
1292 and ALIGN is the alignment that the object would ordinarily have.
1293 The value of this macro is used instead of that alignment to align
1294 the object.
1295
1296 If this macro is not defined, then ALIGN is used.
1297
1298 The typical use of this macro is to increase alignment for string
1299 constants to be word aligned so that `strcpy' calls that copy
1300 constants can be done inline. */
1301
1302 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1303 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1304 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1305
1306 /* If defined, a C expression to compute the alignment for a static
1307 variable. TYPE is the data type, and ALIGN is the alignment that
1308 the object would ordinarily have. The value of this macro is used
1309 instead of that alignment to align the object.
1310
1311 If this macro is not defined, then ALIGN is used.
1312
1313 One use of this macro is to increase alignment of medium-size
1314 data to make it all fit in fewer cache lines. Another is to
1315 cause character arrays to be word-aligned so that `strcpy' calls
1316 that copy constants to character arrays can be done inline. */
1317
1318 #undef DATA_ALIGNMENT
1319 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1320 ((((ALIGN) < BITS_PER_WORD) \
1321 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1322 || TREE_CODE (TYPE) == UNION_TYPE \
1323 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1324
1325
1326 #define PAD_VARARGS_DOWN \
1327 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
1328
1329 /* Define if operations between registers always perform the operation
1330 on the full register even if a narrower mode is specified. */
1331 #define WORD_REGISTER_OPERATIONS
1332
1333 /* When in 64-bit mode, move insns will sign extend SImode and CCmode
1334 moves. All other references are zero extended. */
1335 #define LOAD_EXTEND_OP(MODE) \
1336 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1337 ? SIGN_EXTEND : ZERO_EXTEND)
1338
1339 /* Define this macro if it is advisable to hold scalars in registers
1340 in a wider mode than that declared by the program. In such cases,
1341 the value is constrained to be within the bounds of the declared
1342 type, but kept valid in the wider mode. The signedness of the
1343 extension may differ from that of the type. */
1344
1345 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1346 if (GET_MODE_CLASS (MODE) == MODE_INT \
1347 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
1348 { \
1349 if ((MODE) == SImode) \
1350 (UNSIGNEDP) = 0; \
1351 (MODE) = Pmode; \
1352 }
1353
1354 /* Pmode is always the same as ptr_mode, but not always the same as word_mode.
1355 Extensions of pointers to word_mode must be signed. */
1356 #define POINTERS_EXTEND_UNSIGNED false
1357
1358 /* Define if loading short immediate values into registers sign extends. */
1359 #define SHORT_IMMEDIATES_SIGN_EXTEND
1360
1361 /* The [d]clz instructions have the natural values at 0. */
1362
1363 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \
1364 ((VALUE) = GET_MODE_BITSIZE (MODE), 2)
1365 \f
1366 /* Standard register usage. */
1367
1368 /* Number of hardware registers. We have:
1369
1370 - 32 integer registers
1371 - 32 floating point registers
1372 - 8 condition code registers
1373 - 2 accumulator registers (hi and lo)
1374 - 32 registers each for coprocessors 0, 2 and 3
1375 - 3 fake registers:
1376 - ARG_POINTER_REGNUM
1377 - FRAME_POINTER_REGNUM
1378 - FAKE_CALL_REGNO (see the comment above load_callsi for details)
1379 - 3 dummy entries that were used at various times in the past.
1380 - 6 DSP accumulator registers (3 hi-lo pairs) for MIPS DSP ASE
1381 - 6 DSP control registers */
1382
1383 #define FIRST_PSEUDO_REGISTER 188
1384
1385 /* By default, fix the kernel registers ($26 and $27), the global
1386 pointer ($28) and the stack pointer ($29). This can change
1387 depending on the command-line options.
1388
1389 Regarding coprocessor registers: without evidence to the contrary,
1390 it's best to assume that each coprocessor register has a unique
1391 use. This can be overridden, in, e.g., override_options() or
1392 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1393 for a particular target. */
1394
1395 #define FIXED_REGISTERS \
1396 { \
1397 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1398 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \
1399 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1400 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1401 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
1402 /* COP0 registers */ \
1403 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1404 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1405 /* COP2 registers */ \
1406 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1407 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1408 /* COP3 registers */ \
1409 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1410 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1411 /* 6 DSP accumulator registers & 6 control registers */ \
1412 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1 \
1413 }
1414
1415
1416 /* Set up this array for o32 by default.
1417
1418 Note that we don't mark $31 as a call-clobbered register. The idea is
1419 that it's really the call instructions themselves which clobber $31.
1420 We don't care what the called function does with it afterwards.
1421
1422 This approach makes it easier to implement sibcalls. Unlike normal
1423 calls, sibcalls don't clobber $31, so the register reaches the
1424 called function in tact. EPILOGUE_USES says that $31 is useful
1425 to the called function. */
1426
1427 #define CALL_USED_REGISTERS \
1428 { \
1429 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1430 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
1431 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1432 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1433 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1434 /* COP0 registers */ \
1435 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1436 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1437 /* COP2 registers */ \
1438 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1439 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1440 /* COP3 registers */ \
1441 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1442 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1443 /* 6 DSP accumulator registers & 6 control registers */ \
1444 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1445 }
1446
1447
1448 /* Define this since $28, though fixed, is call-saved in many ABIs. */
1449
1450 #define CALL_REALLY_USED_REGISTERS \
1451 { /* General registers. */ \
1452 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1453 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, \
1454 /* Floating-point registers. */ \
1455 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1456 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1457 /* Others. */ \
1458 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1459 /* COP0 registers */ \
1460 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1461 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1462 /* COP2 registers */ \
1463 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1464 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1465 /* COP3 registers */ \
1466 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1467 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1468 /* 6 DSP accumulator registers & 6 control registers */ \
1469 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0 \
1470 }
1471
1472 /* Internal macros to classify a register number as to whether it's a
1473 general purpose register, a floating point register, a
1474 multiply/divide register, or a status register. */
1475
1476 #define GP_REG_FIRST 0
1477 #define GP_REG_LAST 31
1478 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1479 #define GP_DBX_FIRST 0
1480
1481 #define FP_REG_FIRST 32
1482 #define FP_REG_LAST 63
1483 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1484 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1485
1486 #define MD_REG_FIRST 64
1487 #define MD_REG_LAST 65
1488 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1489 #define MD_DBX_FIRST (FP_DBX_FIRST + FP_REG_NUM)
1490
1491 /* The DWARF 2 CFA column which tracks the return address from a
1492 signal handler context. This means that to maintain backwards
1493 compatibility, no hard register can be assigned this column if it
1494 would need to be handled by the DWARF unwinder. */
1495 #define DWARF_ALT_FRAME_RETURN_COLUMN 66
1496
1497 #define ST_REG_FIRST 67
1498 #define ST_REG_LAST 74
1499 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1500
1501
1502 /* FIXME: renumber. */
1503 #define COP0_REG_FIRST 80
1504 #define COP0_REG_LAST 111
1505 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1506
1507 #define COP2_REG_FIRST 112
1508 #define COP2_REG_LAST 143
1509 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1510
1511 #define COP3_REG_FIRST 144
1512 #define COP3_REG_LAST 175
1513 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1514 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1515 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1516
1517 #define DSP_ACC_REG_FIRST 176
1518 #define DSP_ACC_REG_LAST 181
1519 #define DSP_ACC_REG_NUM (DSP_ACC_REG_LAST - DSP_ACC_REG_FIRST + 1)
1520
1521 #define AT_REGNUM (GP_REG_FIRST + 1)
1522 #define HI_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST : MD_REG_FIRST + 1)
1523 #define LO_REGNUM (TARGET_BIG_ENDIAN ? MD_REG_FIRST + 1 : MD_REG_FIRST)
1524
1525 /* FPSW_REGNUM is the single condition code used if !ISA_HAS_8CC.
1526 If ISA_HAS_8CC, it should not be used, and an arbitrary ST_REG
1527 should be used instead. */
1528 #define FPSW_REGNUM ST_REG_FIRST
1529
1530 #define GP_REG_P(REGNO) \
1531 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1532 #define M16_REG_P(REGNO) \
1533 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1534 #define FP_REG_P(REGNO) \
1535 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1536 #define MD_REG_P(REGNO) \
1537 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1538 #define ST_REG_P(REGNO) \
1539 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1540 #define COP0_REG_P(REGNO) \
1541 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1542 #define COP2_REG_P(REGNO) \
1543 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1544 #define COP3_REG_P(REGNO) \
1545 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1546 #define ALL_COP_REG_P(REGNO) \
1547 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1548 /* Test if REGNO is one of the 6 new DSP accumulators. */
1549 #define DSP_ACC_REG_P(REGNO) \
1550 ((unsigned int) ((int) (REGNO) - DSP_ACC_REG_FIRST) < DSP_ACC_REG_NUM)
1551 /* Test if REGNO is hi, lo, or one of the 6 new DSP accumulators. */
1552 #define ACC_REG_P(REGNO) \
1553 (MD_REG_P (REGNO) || DSP_ACC_REG_P (REGNO))
1554
1555 #define FP_REG_RTX_P(X) (REG_P (X) && FP_REG_P (REGNO (X)))
1556
1557 /* True if X is (const (unspec [(const_int 0)] UNSPEC_GP)). This is used
1558 to initialize the mips16 gp pseudo register. */
1559 #define CONST_GP_P(X) \
1560 (GET_CODE (X) == CONST \
1561 && GET_CODE (XEXP (X, 0)) == UNSPEC \
1562 && XINT (XEXP (X, 0), 1) == UNSPEC_GP)
1563
1564 /* Return coprocessor number from register number. */
1565
1566 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1567 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1568 : COP3_REG_P (REGNO) ? '3' : '?')
1569
1570
1571 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1572
1573 /* To make the code simpler, HARD_REGNO_MODE_OK just references an
1574 array built in override_options. Because machmodes.h is not yet
1575 included before this file is processed, the MODE bound can't be
1576 expressed here. */
1577
1578 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1579
1580 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1581 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1582
1583 /* Value is 1 if it is a good idea to tie two pseudo registers
1584 when one has mode MODE1 and one has mode MODE2.
1585 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1586 for any hard reg, then this must be 0 for correct output. */
1587 #define MODES_TIEABLE_P(MODE1, MODE2) \
1588 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1589 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1590 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1591 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1592
1593 /* Register to use for pushing function arguments. */
1594 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1595
1596 /* These two registers don't really exist: they get eliminated to either
1597 the stack or hard frame pointer. */
1598 #define ARG_POINTER_REGNUM 77
1599 #define FRAME_POINTER_REGNUM 78
1600
1601 /* $30 is not available on the mips16, so we use $17 as the frame
1602 pointer. */
1603 #define HARD_FRAME_POINTER_REGNUM \
1604 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1605
1606 /* Value should be nonzero if functions must have frame pointers.
1607 Zero means the frame pointer need not be set up (and parms
1608 may be accessed via the stack pointer) in functions that seem suitable.
1609 This is computed in `reload', in reload1.c. */
1610 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1611
1612 /* Register in which static-chain is passed to a function. */
1613 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1614
1615 /* Registers used as temporaries in prologue/epilogue code. If we're
1616 generating mips16 code, these registers must come from the core set
1617 of 8. The prologue register mustn't conflict with any incoming
1618 arguments, the static chain pointer, or the frame pointer. The
1619 epilogue temporary mustn't conflict with the return registers, the
1620 frame pointer, the EH stack adjustment, or the EH data registers. */
1621
1622 #define MIPS_PROLOGUE_TEMP_REGNUM (GP_REG_FIRST + 3)
1623 #define MIPS_EPILOGUE_TEMP_REGNUM (GP_REG_FIRST + (TARGET_MIPS16 ? 6 : 8))
1624
1625 #define MIPS_PROLOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_PROLOGUE_TEMP_REGNUM)
1626 #define MIPS_EPILOGUE_TEMP(MODE) gen_rtx_REG (MODE, MIPS_EPILOGUE_TEMP_REGNUM)
1627
1628 /* Define this macro if it is as good or better to call a constant
1629 function address than to call an address kept in a register. */
1630 #define NO_FUNCTION_CSE 1
1631
1632 /* The ABI-defined global pointer. Sometimes we use a different
1633 register in leaf functions: see PIC_OFFSET_TABLE_REGNUM. */
1634 #define GLOBAL_POINTER_REGNUM (GP_REG_FIRST + 28)
1635
1636 /* We normally use $28 as the global pointer. However, when generating
1637 n32/64 PIC, it is better for leaf functions to use a call-clobbered
1638 register instead. They can then avoid saving and restoring $28
1639 and perhaps avoid using a frame at all.
1640
1641 When a leaf function uses something other than $28, mips_expand_prologue
1642 will modify pic_offset_table_rtx in place. Take the register number
1643 from there after reload. */
1644 #define PIC_OFFSET_TABLE_REGNUM \
1645 (reload_completed ? REGNO (pic_offset_table_rtx) : GLOBAL_POINTER_REGNUM)
1646
1647 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1648 \f
1649 /* Define the classes of registers for register constraints in the
1650 machine description. Also define ranges of constants.
1651
1652 One of the classes must always be named ALL_REGS and include all hard regs.
1653 If there is more than one class, another class must be named NO_REGS
1654 and contain no registers.
1655
1656 The name GENERAL_REGS must be the name of a class (or an alias for
1657 another name such as ALL_REGS). This is the class of registers
1658 that is allowed by "g" or "r" in a register constraint.
1659 Also, registers outside this class are allocated only when
1660 instructions express preferences for them.
1661
1662 The classes must be numbered in nondecreasing order; that is,
1663 a larger-numbered class must never be contained completely
1664 in a smaller-numbered class.
1665
1666 For any two classes, it is very desirable that there be another
1667 class that represents their union. */
1668
1669 enum reg_class
1670 {
1671 NO_REGS, /* no registers in set */
1672 M16_NA_REGS, /* mips16 regs not used to pass args */
1673 M16_REGS, /* mips16 directly accessible registers */
1674 T_REG, /* mips16 T register ($24) */
1675 M16_T_REGS, /* mips16 registers plus T register */
1676 PIC_FN_ADDR_REG, /* SVR4 PIC function address register */
1677 V1_REG, /* Register $v1 ($3) used for TLS access. */
1678 LEA_REGS, /* Every GPR except $25 */
1679 GR_REGS, /* integer registers */
1680 FP_REGS, /* floating point registers */
1681 MD0_REG, /* first multiply/divide register */
1682 MD1_REG, /* second multiply/divide register */
1683 MD_REGS, /* multiply/divide registers (hi/lo) */
1684 COP0_REGS, /* generic coprocessor classes */
1685 COP2_REGS,
1686 COP3_REGS,
1687 HI_AND_GR_REGS, /* union classes */
1688 LO_AND_GR_REGS,
1689 HI_AND_FP_REGS,
1690 COP0_AND_GR_REGS,
1691 COP2_AND_GR_REGS,
1692 COP3_AND_GR_REGS,
1693 ALL_COP_REGS,
1694 ALL_COP_AND_GR_REGS,
1695 ST_REGS, /* status registers (fp status) */
1696 DSP_ACC_REGS, /* DSP accumulator registers */
1697 ACC_REGS, /* Hi/Lo and DSP accumulator registers */
1698 ALL_REGS, /* all registers */
1699 LIM_REG_CLASSES /* max value + 1 */
1700 };
1701
1702 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1703
1704 #define GENERAL_REGS GR_REGS
1705
1706 /* An initializer containing the names of the register classes as C
1707 string constants. These names are used in writing some of the
1708 debugging dumps. */
1709
1710 #define REG_CLASS_NAMES \
1711 { \
1712 "NO_REGS", \
1713 "M16_NA_REGS", \
1714 "M16_REGS", \
1715 "T_REG", \
1716 "M16_T_REGS", \
1717 "PIC_FN_ADDR_REG", \
1718 "V1_REG", \
1719 "LEA_REGS", \
1720 "GR_REGS", \
1721 "FP_REGS", \
1722 "MD0_REG", \
1723 "MD1_REG", \
1724 "MD_REGS", \
1725 /* coprocessor registers */ \
1726 "COP0_REGS", \
1727 "COP2_REGS", \
1728 "COP3_REGS", \
1729 "HI_AND_GR_REGS", \
1730 "LO_AND_GR_REGS", \
1731 "HI_AND_FP_REGS", \
1732 "COP0_AND_GR_REGS", \
1733 "COP2_AND_GR_REGS", \
1734 "COP3_AND_GR_REGS", \
1735 "ALL_COP_REGS", \
1736 "ALL_COP_AND_GR_REGS", \
1737 "ST_REGS", \
1738 "DSP_ACC_REGS", \
1739 "ACC_REGS", \
1740 "ALL_REGS" \
1741 }
1742
1743 /* An initializer containing the contents of the register classes,
1744 as integers which are bit masks. The Nth integer specifies the
1745 contents of class N. The way the integer MASK is interpreted is
1746 that register R is in the class if `MASK & (1 << R)' is 1.
1747
1748 When the machine has more than 32 registers, an integer does not
1749 suffice. Then the integers are replaced by sub-initializers,
1750 braced groupings containing several integers. Each
1751 sub-initializer must be suitable as an initializer for the type
1752 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1753
1754 #define REG_CLASS_CONTENTS \
1755 { \
1756 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1757 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
1758 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
1759 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
1760 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
1761 { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* SVR4 PIC function address register */ \
1762 { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* only $v1 */ \
1763 { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* Every other GPR except $25 */ \
1764 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
1765 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
1766 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
1767 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
1768 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
1769 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
1770 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
1771 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
1772 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
1773 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
1774 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
1775 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
1776 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
1777 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
1778 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1779 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
1780 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
1781 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x003f0000 }, /* dsp accumulator registers */ \
1782 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x003f0000 }, /* hi/lo and dsp accumulator registers */ \
1783 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0fffffff } /* all registers */ \
1784 }
1785
1786
1787 /* A C expression whose value is a register class containing hard
1788 register REGNO. In general there is more that one such class;
1789 choose a class which is "minimal", meaning that no smaller class
1790 also contains the register. */
1791
1792 extern const enum reg_class mips_regno_to_class[];
1793
1794 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1795
1796 /* A macro whose definition is the name of the class to which a
1797 valid base register must belong. A base register is one used in
1798 an address which is the register value plus a displacement. */
1799
1800 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
1801
1802 /* A macro whose definition is the name of the class to which a
1803 valid index register must belong. An index register is one used
1804 in an address where its value is either multiplied by a scale
1805 factor or added to another register (as well as added to a
1806 displacement). */
1807
1808 #define INDEX_REG_CLASS NO_REGS
1809
1810 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1811 registers explicitly used in the rtl to be used as spill registers
1812 but prevents the compiler from extending the lifetime of these
1813 registers. */
1814
1815 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
1816
1817 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
1818 is the default value (allocate the registers in numeric order). We
1819 define it just so that we can override it for the mips16 target in
1820 ORDER_REGS_FOR_LOCAL_ALLOC. */
1821
1822 #define REG_ALLOC_ORDER \
1823 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
1824 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
1825 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
1826 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
1827 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
1828 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
1829 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
1830 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
1831 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
1832 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
1833 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175, \
1834 176,177,178,179,180,181,182,183,184,185,186,187 \
1835 }
1836
1837 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
1838 to be rearranged based on a particular function. On the mips16, we
1839 want to allocate $24 (T_REG) before other registers for
1840 instructions for which it is possible. */
1841
1842 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
1843
1844 /* True if VALUE is an unsigned 6-bit number. */
1845
1846 #define UIMM6_OPERAND(VALUE) \
1847 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0x3f) == 0)
1848
1849 /* True if VALUE is a signed 10-bit number. */
1850
1851 #define IMM10_OPERAND(VALUE) \
1852 ((unsigned HOST_WIDE_INT) (VALUE) + 0x200 < 0x400)
1853
1854 /* True if VALUE is a signed 16-bit number. */
1855
1856 #define SMALL_OPERAND(VALUE) \
1857 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
1858
1859 /* True if VALUE is an unsigned 16-bit number. */
1860
1861 #define SMALL_OPERAND_UNSIGNED(VALUE) \
1862 (((VALUE) & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
1863
1864 /* True if VALUE can be loaded into a register using LUI. */
1865
1866 #define LUI_OPERAND(VALUE) \
1867 (((VALUE) | 0x7fff0000) == 0x7fff0000 \
1868 || ((VALUE) | 0x7fff0000) + 0x10000 == 0)
1869
1870 /* Return a value X with the low 16 bits clear, and such that
1871 VALUE - X is a signed 16-bit value. */
1872
1873 #define CONST_HIGH_PART(VALUE) \
1874 (((VALUE) + 0x8000) & ~(unsigned HOST_WIDE_INT) 0xffff)
1875
1876 #define CONST_LOW_PART(VALUE) \
1877 ((VALUE) - CONST_HIGH_PART (VALUE))
1878
1879 #define SMALL_INT(X) SMALL_OPERAND (INTVAL (X))
1880 #define SMALL_INT_UNSIGNED(X) SMALL_OPERAND_UNSIGNED (INTVAL (X))
1881 #define LUI_INT(X) LUI_OPERAND (INTVAL (X))
1882
1883 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1884 mips_preferred_reload_class (X, CLASS)
1885
1886 /* The HI and LO registers can only be reloaded via the general
1887 registers. Condition code registers can only be loaded to the
1888 general registers, and from the floating point registers. */
1889
1890 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1891 mips_secondary_reload_class (CLASS, MODE, X, 1)
1892 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1893 mips_secondary_reload_class (CLASS, MODE, X, 0)
1894
1895 /* Return the maximum number of consecutive registers
1896 needed to represent mode MODE in a register of class CLASS. */
1897
1898 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
1899
1900 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
1901 mips_cannot_change_mode_class (FROM, TO, CLASS)
1902 \f
1903 /* Stack layout; function entry, exit and calling. */
1904
1905 #define STACK_GROWS_DOWNWARD
1906
1907 /* The offset of the first local variable from the beginning of the frame.
1908 See compute_frame_size for details about the frame layout.
1909
1910 ??? If flag_profile_values is true, and we are generating 32-bit code, then
1911 we assume that we will need 16 bytes of argument space. This is because
1912 the value profiling code may emit calls to cmpdi2 in leaf functions.
1913 Without this hack, the local variables will start at sp+8 and the gp save
1914 area will be at sp+16, and thus they will overlap. compute_frame_size is
1915 OK because it uses STARTING_FRAME_OFFSET to compute cprestore_size, which
1916 will end up as 24 instead of 8. This won't be needed if profiling code is
1917 inserted before virtual register instantiation. */
1918
1919 #define STARTING_FRAME_OFFSET \
1920 ((flag_profile_values && ! TARGET_64BIT \
1921 ? MAX (REG_PARM_STACK_SPACE(NULL), current_function_outgoing_args_size) \
1922 : current_function_outgoing_args_size) \
1923 + (TARGET_CALL_CLOBBERED_GP ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
1924
1925 #define RETURN_ADDR_RTX mips_return_addr
1926
1927 /* Since the mips16 ISA mode is encoded in the least-significant bit
1928 of the address, mask it off return addresses for purposes of
1929 finding exception handling regions. */
1930
1931 #define MASK_RETURN_ADDR GEN_INT (-2)
1932
1933
1934 /* Similarly, don't use the least-significant bit to tell pointers to
1935 code from vtable index. */
1936
1937 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
1938
1939 /* The eliminations to $17 are only used for mips16 code. See the
1940 definition of HARD_FRAME_POINTER_REGNUM. */
1941
1942 #define ELIMINABLE_REGS \
1943 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1944 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1945 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
1946 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
1947 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
1948 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
1949
1950 /* We can always eliminate to the hard frame pointer. We can eliminate
1951 to the stack pointer unless a frame pointer is needed.
1952
1953 In mips16 mode, we need a frame pointer for a large frame; otherwise,
1954 reload may be unable to compute the address of a local variable,
1955 since there is no way to add a large constant to the stack pointer
1956 without using a temporary register. */
1957 #define CAN_ELIMINATE(FROM, TO) \
1958 ((TO) == HARD_FRAME_POINTER_REGNUM \
1959 || ((TO) == STACK_POINTER_REGNUM && !frame_pointer_needed \
1960 && (!TARGET_MIPS16 \
1961 || compute_frame_size (get_frame_size ()) < 32768)))
1962
1963 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1964 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
1965
1966 /* Allocate stack space for arguments at the beginning of each function. */
1967 #define ACCUMULATE_OUTGOING_ARGS 1
1968
1969 /* The argument pointer always points to the first argument. */
1970 #define FIRST_PARM_OFFSET(FNDECL) 0
1971
1972 /* o32 and o64 reserve stack space for all argument registers. */
1973 #define REG_PARM_STACK_SPACE(FNDECL) \
1974 (TARGET_OLDABI \
1975 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) \
1976 : 0)
1977
1978 /* Define this if it is the responsibility of the caller to
1979 allocate the area reserved for arguments passed in registers.
1980 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1981 of this macro is to determine whether the space is included in
1982 `current_function_outgoing_args_size'. */
1983 #define OUTGOING_REG_PARM_STACK_SPACE 1
1984
1985 #define STACK_BOUNDARY (TARGET_NEWABI ? 128 : 64)
1986 \f
1987 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
1988
1989 /* Symbolic macros for the registers used to return integer and floating
1990 point values. */
1991
1992 #define GP_RETURN (GP_REG_FIRST + 2)
1993 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
1994
1995 #define MAX_ARGS_IN_REGISTERS (TARGET_OLDABI ? 4 : 8)
1996
1997 /* Symbolic macros for the first/last argument registers. */
1998
1999 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2000 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2001 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2002 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2003
2004 #define LIBCALL_VALUE(MODE) \
2005 mips_function_value (NULL_TREE, NULL, (MODE))
2006
2007 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2008 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2009
2010 /* 1 if N is a possible register number for a function value.
2011 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2012 Currently, R2 and F0 are only implemented here (C has no complex type) */
2013
2014 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN \
2015 || (LONG_DOUBLE_TYPE_SIZE == 128 && FP_RETURN != GP_RETURN \
2016 && (N) == FP_RETURN + 2))
2017
2018 /* 1 if N is a possible register number for function argument passing.
2019 We have no FP argument registers when soft-float. When FP registers
2020 are 32 bits, we can't directly reference the odd numbered ones. */
2021
2022 #define FUNCTION_ARG_REGNO_P(N) \
2023 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2024 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST))) \
2025 && !fixed_regs[N])
2026 \f
2027 /* This structure has to cope with two different argument allocation
2028 schemes. Most MIPS ABIs view the arguments as a structure, of which
2029 the first N words go in registers and the rest go on the stack. If I
2030 < N, the Ith word might go in Ith integer argument register or in a
2031 floating-point register. For these ABIs, we only need to remember
2032 the offset of the current argument into the structure.
2033
2034 The EABI instead allocates the integer and floating-point arguments
2035 separately. The first N words of FP arguments go in FP registers,
2036 the rest go on the stack. Likewise, the first N words of the other
2037 arguments go in integer registers, and the rest go on the stack. We
2038 need to maintain three counts: the number of integer registers used,
2039 the number of floating-point registers used, and the number of words
2040 passed on the stack.
2041
2042 We could keep separate information for the two ABIs (a word count for
2043 the standard ABIs, and three separate counts for the EABI). But it
2044 seems simpler to view the standard ABIs as forms of EABI that do not
2045 allocate floating-point registers.
2046
2047 So for the standard ABIs, the first N words are allocated to integer
2048 registers, and function_arg decides on an argument-by-argument basis
2049 whether that argument should really go in an integer register, or in
2050 a floating-point one. */
2051
2052 typedef struct mips_args {
2053 /* Always true for varargs functions. Otherwise true if at least
2054 one argument has been passed in an integer register. */
2055 int gp_reg_found;
2056
2057 /* The number of arguments seen so far. */
2058 unsigned int arg_number;
2059
2060 /* The number of integer registers used so far. For all ABIs except
2061 EABI, this is the number of words that have been added to the
2062 argument structure, limited to MAX_ARGS_IN_REGISTERS. */
2063 unsigned int num_gprs;
2064
2065 /* For EABI, the number of floating-point registers used so far. */
2066 unsigned int num_fprs;
2067
2068 /* The number of words passed on the stack. */
2069 unsigned int stack_words;
2070
2071 /* On the mips16, we need to keep track of which floating point
2072 arguments were passed in general registers, but would have been
2073 passed in the FP regs if this were a 32-bit function, so that we
2074 can move them to the FP regs if we wind up calling a 32-bit
2075 function. We record this information in fp_code, encoded in base
2076 four. A zero digit means no floating point argument, a one digit
2077 means an SFmode argument, and a two digit means a DFmode argument,
2078 and a three digit is not used. The low order digit is the first
2079 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2080 an SFmode argument. ??? A more sophisticated approach will be
2081 needed if MIPS_ABI != ABI_32. */
2082 int fp_code;
2083
2084 /* True if the function has a prototype. */
2085 int prototype;
2086 } CUMULATIVE_ARGS;
2087
2088 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2089 for a call to a function whose data type is FNTYPE.
2090 For a library call, FNTYPE is 0. */
2091
2092 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
2093 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2094
2095 /* Update the data in CUM to advance over an argument
2096 of mode MODE and data type TYPE.
2097 (TYPE is null for libcalls where that information may not be available.) */
2098
2099 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2100 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2101
2102 /* Determine where to put an argument to a function.
2103 Value is zero to push the argument on the stack,
2104 or a hard register in which to store the argument.
2105
2106 MODE is the argument's machine mode.
2107 TYPE is the data type of the argument (as a tree).
2108 This is null for libcalls where that information may
2109 not be available.
2110 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2111 the preceding args and about the function being called.
2112 NAMED is nonzero if this argument is a named parameter
2113 (otherwise it is an extra parameter matching an ellipsis). */
2114
2115 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2116 function_arg( &CUM, MODE, TYPE, NAMED)
2117
2118 #define FUNCTION_ARG_BOUNDARY function_arg_boundary
2119
2120 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2121 (mips_pad_arg_upward (MODE, TYPE) ? upward : downward)
2122
2123 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
2124 (mips_pad_reg_upward (MODE, TYPE) ? upward : downward)
2125
2126 /* True if using EABI and varargs can be passed in floating-point
2127 registers. Under these conditions, we need a more complex form
2128 of va_list, which tracks GPR, FPR and stack arguments separately. */
2129 #define EABI_FLOAT_VARARGS_P \
2130 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2131
2132 \f
2133 /* Say that the epilogue uses the return address register. Note that
2134 in the case of sibcalls, the values "used by the epilogue" are
2135 considered live at the start of the called function. */
2136 #define EPILOGUE_USES(REGNO) ((REGNO) == 31)
2137
2138 /* Treat LOC as a byte offset from the stack pointer and round it up
2139 to the next fully-aligned offset. */
2140 #define MIPS_STACK_ALIGN(LOC) \
2141 (TARGET_NEWABI ? ((LOC) + 15) & -16 : ((LOC) + 7) & -8)
2142
2143 \f
2144 /* Implement `va_start' for varargs and stdarg. */
2145 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2146 mips_va_start (valist, nextarg)
2147 \f
2148 /* Output assembler code to FILE to increment profiler label # LABELNO
2149 for profiling a function entry. */
2150
2151 #define FUNCTION_PROFILER(FILE, LABELNO) \
2152 { \
2153 if (TARGET_MIPS16) \
2154 sorry ("mips16 function profiling"); \
2155 fprintf (FILE, "\t.set\tnoat\n"); \
2156 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2157 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2158 if (!TARGET_NEWABI) \
2159 { \
2160 fprintf (FILE, \
2161 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2162 TARGET_64BIT ? "dsubu" : "subu", \
2163 reg_names[STACK_POINTER_REGNUM], \
2164 reg_names[STACK_POINTER_REGNUM], \
2165 Pmode == DImode ? 16 : 8); \
2166 } \
2167 fprintf (FILE, "\tjal\t_mcount\n"); \
2168 fprintf (FILE, "\t.set\tat\n"); \
2169 }
2170
2171 /* The profiler preserves all interesting registers, including $31. */
2172 #define MIPS_SAVE_REG_FOR_PROFILING_P(REGNO) false
2173
2174 /* No mips port has ever used the profiler counter word, so don't emit it
2175 or the label for it. */
2176
2177 #define NO_PROFILE_COUNTERS 1
2178
2179 /* Define this macro if the code for function profiling should come
2180 before the function prologue. Normally, the profiling code comes
2181 after. */
2182
2183 /* #define PROFILE_BEFORE_PROLOGUE */
2184
2185 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2186 the stack pointer does not matter. The value is tested only in
2187 functions that have frame pointers.
2188 No definition is equivalent to always zero. */
2189
2190 #define EXIT_IGNORE_STACK 1
2191
2192 \f
2193 /* A C statement to output, on the stream FILE, assembler code for a
2194 block of data that contains the constant parts of a trampoline.
2195 This code should not include a label--the label is taken care of
2196 automatically. */
2197
2198 #define TRAMPOLINE_TEMPLATE(STREAM) \
2199 { \
2200 if (ptr_mode == DImode) \
2201 fprintf (STREAM, "\t.word\t0x03e0082d\t\t# dmove $1,$31\n"); \
2202 else \
2203 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2204 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2205 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2206 if (ptr_mode == DImode) \
2207 { \
2208 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2209 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2210 fprintf (STREAM, "\t.word\t0x0060c82d\t\t# dmove $25,$3\n"); \
2211 } \
2212 else \
2213 { \
2214 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2215 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2216 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3\n"); \
2217 } \
2218 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2219 if (ptr_mode == DImode) \
2220 { \
2221 fprintf (STREAM, "\t.word\t0x0020f82d\t\t# dmove $31,$1\n"); \
2222 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2223 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2224 } \
2225 else \
2226 { \
2227 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2228 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2229 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2230 } \
2231 }
2232
2233 /* A C expression for the size in bytes of the trampoline, as an
2234 integer. */
2235
2236 #define TRAMPOLINE_SIZE (32 + GET_MODE_SIZE (ptr_mode) * 2)
2237
2238 /* Alignment required for trampolines, in bits. */
2239
2240 #define TRAMPOLINE_ALIGNMENT GET_MODE_BITSIZE (ptr_mode)
2241
2242 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2243 program and data caches. */
2244
2245 #ifndef CACHE_FLUSH_FUNC
2246 #define CACHE_FLUSH_FUNC "_flush_cache"
2247 #endif
2248
2249 #define MIPS_ICACHE_SYNC(ADDR, SIZE) \
2250 /* Flush both caches. We need to flush the data cache in case \
2251 the system has a write-back cache. */ \
2252 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2253 0, VOIDmode, 3, ADDR, Pmode, SIZE, Pmode, \
2254 GEN_INT (3), TYPE_MODE (integer_type_node))
2255
2256 /* A C statement to initialize the variable parts of a trampoline.
2257 ADDR is an RTX for the address of the trampoline; FNADDR is an
2258 RTX for the address of the nested function; STATIC_CHAIN is an
2259 RTX for the static chain value that should be passed to the
2260 function when it is called. */
2261
2262 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2263 { \
2264 rtx func_addr, chain_addr, end_addr; \
2265 \
2266 func_addr = plus_constant (ADDR, 32); \
2267 chain_addr = plus_constant (func_addr, GET_MODE_SIZE (ptr_mode)); \
2268 mips_emit_move (gen_rtx_MEM (ptr_mode, func_addr), FUNC); \
2269 mips_emit_move (gen_rtx_MEM (ptr_mode, chain_addr), CHAIN); \
2270 end_addr = gen_reg_rtx (Pmode); \
2271 emit_insn (gen_add3_insn (end_addr, copy_rtx (ADDR), \
2272 GEN_INT (TRAMPOLINE_SIZE))); \
2273 emit_insn (gen_clear_cache (copy_rtx (ADDR), end_addr)); \
2274 }
2275 \f
2276 /* Addressing modes, and classification of registers for them. */
2277
2278 #define REGNO_OK_FOR_INDEX_P(REGNO) 0
2279 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
2280 mips_regno_mode_ok_for_base_p (REGNO, MODE, 1)
2281
2282 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
2283 and check its validity for a certain class.
2284 We have two alternate definitions for each of them.
2285 The usual definition accepts all pseudo regs; the other rejects them all.
2286 The symbol REG_OK_STRICT causes the latter definition to be used.
2287
2288 Most source files want to accept pseudo regs in the hope that
2289 they will get allocated to the class that the insn wants them to be in.
2290 Some source files that are used after register allocation
2291 need to be strict. */
2292
2293 #ifndef REG_OK_STRICT
2294 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2295 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 0)
2296 #else
2297 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
2298 mips_regno_mode_ok_for_base_p (REGNO (X), MODE, 1)
2299 #endif
2300
2301 #define REG_OK_FOR_INDEX_P(X) 0
2302
2303 \f
2304 /* Maximum number of registers that can appear in a valid memory address. */
2305
2306 #define MAX_REGS_PER_ADDRESS 1
2307
2308 #ifdef REG_OK_STRICT
2309 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2310 { \
2311 if (mips_legitimate_address_p (MODE, X, 1)) \
2312 goto ADDR; \
2313 }
2314 #else
2315 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
2316 { \
2317 if (mips_legitimate_address_p (MODE, X, 0)) \
2318 goto ADDR; \
2319 }
2320 #endif
2321
2322 /* Check for constness inline but use mips_legitimate_address_p
2323 to check whether a constant really is an address. */
2324
2325 #define CONSTANT_ADDRESS_P(X) \
2326 (CONSTANT_P (X) && mips_legitimate_address_p (SImode, X, 0))
2327
2328 #define LEGITIMATE_CONSTANT_P(X) (mips_const_insns (X) > 0)
2329
2330 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
2331 do { \
2332 if (mips_legitimize_address (&(X), MODE)) \
2333 goto WIN; \
2334 } while (0)
2335
2336
2337 /* A C statement or compound statement with a conditional `goto
2338 LABEL;' executed if memory address X (an RTX) can have different
2339 meanings depending on the machine mode of the memory reference it
2340 is used for.
2341
2342 Autoincrement and autodecrement addresses typically have
2343 mode-dependent effects because the amount of the increment or
2344 decrement is the size of the operand being addressed. Some
2345 machines have other mode-dependent addresses. Many RISC machines
2346 have no mode-dependent addresses.
2347
2348 You may assume that ADDR is a valid address for the machine. */
2349
2350 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2351
2352 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
2353 'the start of the function that this code is output in'. */
2354
2355 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
2356 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
2357 asm_fprintf ((FILE), "%U%s", \
2358 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
2359 else \
2360 asm_fprintf ((FILE), "%U%s", (NAME))
2361 \f
2362 /* Flag to mark a function decl symbol that requires a long call. */
2363 #define SYMBOL_FLAG_LONG_CALL (SYMBOL_FLAG_MACH_DEP << 0)
2364 #define SYMBOL_REF_LONG_CALL_P(X) \
2365 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_LONG_CALL) != 0)
2366
2367 /* True if we're generating a form of MIPS16 code in which jump tables
2368 are stored in the text section and encoded as 16-bit PC-relative
2369 offsets. This is only possible when general text loads are allowed,
2370 since the table access itself will be an "lh" instruction. */
2371 /* ??? 16-bit offsets can overflow in large functions. */
2372 #define TARGET_MIPS16_SHORT_JUMP_TABLES TARGET_MIPS16_TEXT_LOADS
2373
2374 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_MIPS16_SHORT_JUMP_TABLES
2375
2376 #define CASE_VECTOR_MODE (TARGET_MIPS16_SHORT_JUMP_TABLES ? HImode : ptr_mode)
2377
2378 #define CASE_VECTOR_PC_RELATIVE TARGET_MIPS16_SHORT_JUMP_TABLES
2379
2380 /* Define this as 1 if `char' should by default be signed; else as 0. */
2381 #ifndef DEFAULT_SIGNED_CHAR
2382 #define DEFAULT_SIGNED_CHAR 1
2383 #endif
2384
2385 /* Max number of bytes we can move from memory to memory
2386 in one reasonably fast instruction. */
2387 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
2388 #define MAX_MOVE_MAX 8
2389
2390 /* Define this macro as a C expression which is nonzero if
2391 accessing less than a word of memory (i.e. a `char' or a
2392 `short') is no faster than accessing a word of memory, i.e., if
2393 such access require more than one instruction or if there is no
2394 difference in cost between byte and (aligned) word loads.
2395
2396 On RISC machines, it tends to generate better code to define
2397 this as 1, since it avoids making a QI or HI mode register.
2398
2399 But, generating word accesses for -mips16 is generally bad as shifts
2400 (often extended) would be needed for byte accesses. */
2401 #define SLOW_BYTE_ACCESS (!TARGET_MIPS16)
2402
2403 /* Define this to be nonzero if shift instructions ignore all but the low-order
2404 few bits. */
2405 #define SHIFT_COUNT_TRUNCATED 1
2406
2407 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2408 is done just by pretending it is already truncated. */
2409 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
2410 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
2411
2412
2413 /* Specify the machine mode that pointers have.
2414 After generation of rtl, the compiler makes no further distinction
2415 between pointers and any other objects of this machine mode. */
2416
2417 #ifndef Pmode
2418 #define Pmode (TARGET_64BIT && TARGET_LONG64 ? DImode : SImode)
2419 #endif
2420
2421 /* Give call MEMs SImode since it is the "most permissive" mode
2422 for both 32-bit and 64-bit targets. */
2423
2424 #define FUNCTION_MODE SImode
2425
2426 \f
2427 /* A C expression for the cost of moving data from a register in
2428 class FROM to one in class TO. The classes are expressed using
2429 the enumeration values such as `GENERAL_REGS'. A value of 2 is
2430 the default; other values are interpreted relative to that.
2431
2432 It is not required that the cost always equal 2 when FROM is the
2433 same as TO; on some machines it is expensive to move between
2434 registers if they are not general registers.
2435
2436 If reload sees an insn consisting of a single `set' between two
2437 hard registers, and if `REGISTER_MOVE_COST' applied to their
2438 classes returns a value of 2, reload does not check to ensure
2439 that the constraints of the insn are met. Setting a cost of
2440 other than 2 will allow reload to verify that the constraints are
2441 met. You should do this if the `movM' pattern's constraints do
2442 not allow such copying. */
2443
2444 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
2445 mips_register_move_cost (MODE, FROM, TO)
2446
2447 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
2448 (mips_cost->memory_latency \
2449 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
2450
2451 /* Define if copies to/from condition code registers should be avoided.
2452
2453 This is needed for the MIPS because reload_outcc is not complete;
2454 it needs to handle cases where the source is a general or another
2455 condition code register. */
2456 #define AVOID_CCMODE_COPIES
2457
2458 /* A C expression for the cost of a branch instruction. A value of
2459 1 is the default; other values are interpreted relative to that. */
2460
2461 #define BRANCH_COST mips_branch_cost
2462 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0
2463
2464 /* If defined, modifies the length assigned to instruction INSN as a
2465 function of the context in which it is used. LENGTH is an lvalue
2466 that contains the initially computed length of the insn and should
2467 be updated with the correct length of the insn. */
2468 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
2469 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
2470
2471 /* Return the asm template for a non-MIPS16 conditional branch instruction.
2472 OPCODE is the opcode's mnemonic and OPERANDS is the asm template for
2473 its operands. */
2474 #define MIPS_BRANCH(OPCODE, OPERANDS) \
2475 "%*" OPCODE "%?\t" OPERANDS "%/"
2476
2477 /* Return the asm template for a call. INSN is the instruction's mnemonic
2478 ("j" or "jal"), OPERANDS are its operands, and OPNO is the operand number
2479 of the target.
2480
2481 When generating GOT code without explicit relocation operators,
2482 all calls should use assembly macros. Otherwise, all indirect
2483 calls should use "jr" or "jalr"; we will arrange to restore $gp
2484 afterwards if necessary. Finally, we can only generate direct
2485 calls for -mabicalls by temporarily switching to non-PIC mode. */
2486 #define MIPS_CALL(INSN, OPERANDS, OPNO) \
2487 (TARGET_USE_GOT && !TARGET_EXPLICIT_RELOCS \
2488 ? "%*" INSN "\t%" #OPNO "%/" \
2489 : REG_P (OPERANDS[OPNO]) \
2490 ? "%*" INSN "r\t%" #OPNO "%/" \
2491 : TARGET_ABICALLS \
2492 ? (".option\tpic0\n\t" \
2493 "%*" INSN "\t%" #OPNO "%/\n\t" \
2494 ".option\tpic2") \
2495 : "%*" INSN "\t%" #OPNO "%/")
2496 \f
2497 /* Control the assembler format that we output. */
2498
2499 /* Output to assembler file text saying following lines
2500 may contain character constants, extra white space, comments, etc. */
2501
2502 #ifndef ASM_APP_ON
2503 #define ASM_APP_ON " #APP\n"
2504 #endif
2505
2506 /* Output to assembler file text saying following lines
2507 no longer contain unusual constructs. */
2508
2509 #ifndef ASM_APP_OFF
2510 #define ASM_APP_OFF " #NO_APP\n"
2511 #endif
2512
2513 #define REGISTER_NAMES \
2514 { "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", \
2515 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", \
2516 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", \
2517 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31", \
2518 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
2519 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
2520 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
2521 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
2522 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
2523 "$fcc5","$fcc6","$fcc7","", "", "$arg", "$frame", "$fakec", \
2524 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7", \
2525 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15", \
2526 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23", \
2527 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31", \
2528 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7", \
2529 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15", \
2530 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23", \
2531 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31", \
2532 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7", \
2533 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15", \
2534 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23", \
2535 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31", \
2536 "$ac1hi","$ac1lo","$ac2hi","$ac2lo","$ac3hi","$ac3lo","$dsp_po","$dsp_sc", \
2537 "$dsp_ca","$dsp_ou","$dsp_cc","$dsp_ef" }
2538
2539 /* List the "software" names for each register. Also list the numerical
2540 names for $fp and $sp. */
2541
2542 #define ADDITIONAL_REGISTER_NAMES \
2543 { \
2544 { "$29", 29 + GP_REG_FIRST }, \
2545 { "$30", 30 + GP_REG_FIRST }, \
2546 { "at", 1 + GP_REG_FIRST }, \
2547 { "v0", 2 + GP_REG_FIRST }, \
2548 { "v1", 3 + GP_REG_FIRST }, \
2549 { "a0", 4 + GP_REG_FIRST }, \
2550 { "a1", 5 + GP_REG_FIRST }, \
2551 { "a2", 6 + GP_REG_FIRST }, \
2552 { "a3", 7 + GP_REG_FIRST }, \
2553 { "t0", 8 + GP_REG_FIRST }, \
2554 { "t1", 9 + GP_REG_FIRST }, \
2555 { "t2", 10 + GP_REG_FIRST }, \
2556 { "t3", 11 + GP_REG_FIRST }, \
2557 { "t4", 12 + GP_REG_FIRST }, \
2558 { "t5", 13 + GP_REG_FIRST }, \
2559 { "t6", 14 + GP_REG_FIRST }, \
2560 { "t7", 15 + GP_REG_FIRST }, \
2561 { "s0", 16 + GP_REG_FIRST }, \
2562 { "s1", 17 + GP_REG_FIRST }, \
2563 { "s2", 18 + GP_REG_FIRST }, \
2564 { "s3", 19 + GP_REG_FIRST }, \
2565 { "s4", 20 + GP_REG_FIRST }, \
2566 { "s5", 21 + GP_REG_FIRST }, \
2567 { "s6", 22 + GP_REG_FIRST }, \
2568 { "s7", 23 + GP_REG_FIRST }, \
2569 { "t8", 24 + GP_REG_FIRST }, \
2570 { "t9", 25 + GP_REG_FIRST }, \
2571 { "k0", 26 + GP_REG_FIRST }, \
2572 { "k1", 27 + GP_REG_FIRST }, \
2573 { "gp", 28 + GP_REG_FIRST }, \
2574 { "sp", 29 + GP_REG_FIRST }, \
2575 { "fp", 30 + GP_REG_FIRST }, \
2576 { "ra", 31 + GP_REG_FIRST }, \
2577 ALL_COP_ADDITIONAL_REGISTER_NAMES \
2578 }
2579
2580 /* This is meant to be redefined in the host dependent files. It is a
2581 set of alternative names and regnums for mips coprocessors. */
2582
2583 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
2584
2585 /* A C compound statement to output to stdio stream STREAM the
2586 assembler syntax for an instruction operand X. X is an RTL
2587 expression.
2588
2589 CODE is a value that can be used to specify one of several ways
2590 of printing the operand. It is used when identical operands
2591 must be printed differently depending on the context. CODE
2592 comes from the `%' specification that was used to request
2593 printing of the operand. If the specification was just `%DIGIT'
2594 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2595 is the ASCII code for LTR.
2596
2597 If X is a register, this macro should print the register's name.
2598 The names can be found in an array `reg_names' whose type is
2599 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2600
2601 When the machine description has a specification `%PUNCT' (a `%'
2602 followed by a punctuation character), this macro is called with
2603 a null pointer for X and the punctuation character for CODE.
2604
2605 See mips.c for the MIPS specific codes. */
2606
2607 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2608
2609 /* A C expression which evaluates to true if CODE is a valid
2610 punctuation character for use in the `PRINT_OPERAND' macro. If
2611 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
2612 punctuation characters (except for the standard one, `%') are
2613 used in this way. */
2614
2615 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2616
2617 /* A C compound statement to output to stdio stream STREAM the
2618 assembler syntax for an instruction operand that is a memory
2619 reference whose address is ADDR. ADDR is an RTL expression. */
2620
2621 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2622
2623
2624 /* A C statement, to be executed after all slot-filler instructions
2625 have been output. If necessary, call `dbr_sequence_length' to
2626 determine the number of slots filled in a sequence (zero if not
2627 currently outputting a sequence), to decide how many no-ops to
2628 output, or whatever.
2629
2630 Don't define this macro if it has nothing to do, but it is
2631 helpful in reading assembly output if the extent of the delay
2632 sequence is made explicit (e.g. with white space).
2633
2634 Note that output routines for instructions with delay slots must
2635 be prepared to deal with not being output as part of a sequence
2636 (i.e. when the scheduling pass is not run, or when no slot
2637 fillers could be found.) The variable `final_sequence' is null
2638 when not processing a sequence, otherwise it contains the
2639 `sequence' rtx being output. */
2640
2641 #define DBR_OUTPUT_SEQEND(STREAM) \
2642 do \
2643 { \
2644 if (set_nomacro > 0 && --set_nomacro == 0) \
2645 fputs ("\t.set\tmacro\n", STREAM); \
2646 \
2647 if (set_noreorder > 0 && --set_noreorder == 0) \
2648 fputs ("\t.set\treorder\n", STREAM); \
2649 \
2650 fputs ("\n", STREAM); \
2651 } \
2652 while (0)
2653
2654
2655 /* How to tell the debugger about changes of source files. */
2656 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2657 mips_output_filename (STREAM, NAME)
2658
2659 /* mips-tfile does not understand .stabd directives. */
2660 #define DBX_OUTPUT_SOURCE_LINE(STREAM, LINE, COUNTER) do { \
2661 dbxout_begin_stabn_sline (LINE); \
2662 dbxout_stab_value_internal_label ("LM", &COUNTER); \
2663 } while (0)
2664
2665 /* Use .loc directives for SDB line numbers. */
2666 #define SDB_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2667 fprintf (STREAM, "\t.loc\t%d %d\n", num_source_filenames, LINE)
2668
2669 /* The MIPS implementation uses some labels for its own purpose. The
2670 following lists what labels are created, and are all formed by the
2671 pattern $L[a-z].*. The machine independent portion of GCC creates
2672 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2673
2674 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
2675 $Lb[0-9]+ Begin blocks for MIPS debug support
2676 $Lc[0-9]+ Label for use in s<xx> operation.
2677 $Le[0-9]+ End blocks for MIPS debug support */
2678
2679 #undef ASM_DECLARE_OBJECT_NAME
2680 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
2681 mips_declare_object (STREAM, NAME, "", ":\n")
2682
2683 /* Globalizing directive for a label. */
2684 #define GLOBAL_ASM_OP "\t.globl\t"
2685
2686 /* This says how to define a global common symbol. */
2687
2688 #define ASM_OUTPUT_ALIGNED_DECL_COMMON mips_output_aligned_decl_common
2689
2690 /* This says how to define a local common symbol (i.e., not visible to
2691 linker). */
2692
2693 #ifndef ASM_OUTPUT_ALIGNED_LOCAL
2694 #define ASM_OUTPUT_ALIGNED_LOCAL(STREAM, NAME, SIZE, ALIGN) \
2695 mips_declare_common_object (STREAM, NAME, "\n\t.lcomm\t", SIZE, ALIGN, false)
2696 #endif
2697
2698 /* This says how to output an external. It would be possible not to
2699 output anything and let undefined symbol become external. However
2700 the assembler uses length information on externals to allocate in
2701 data/sdata bss/sbss, thereby saving exec time. */
2702
2703 #undef ASM_OUTPUT_EXTERNAL
2704 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2705 mips_output_external(STREAM,DECL,NAME)
2706
2707 /* This is how to declare a function name. The actual work of
2708 emitting the label is moved to function_prologue, so that we can
2709 get the line number correctly emitted before the .ent directive,
2710 and after any .file directives. Define as empty so that the function
2711 is not declared before the .ent directive elsewhere. */
2712
2713 #undef ASM_DECLARE_FUNCTION_NAME
2714 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
2715
2716 #ifndef FUNCTION_NAME_ALREADY_DECLARED
2717 #define FUNCTION_NAME_ALREADY_DECLARED 0
2718 #endif
2719
2720 /* This is how to store into the string LABEL
2721 the symbol_ref name of an internal numbered label where
2722 PREFIX is the class of label and NUM is the number within the class.
2723 This is suitable for output with `assemble_name'. */
2724
2725 #undef ASM_GENERATE_INTERNAL_LABEL
2726 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2727 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
2728
2729 /* This is how to output an element of a case-vector that is absolute. */
2730
2731 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
2732 fprintf (STREAM, "\t%s\t%sL%d\n", \
2733 ptr_mode == DImode ? ".dword" : ".word", \
2734 LOCAL_LABEL_PREFIX, \
2735 VALUE)
2736
2737 /* This is how to output an element of a case-vector. We can make the
2738 entries PC-relative in MIPS16 code and GP-relative when .gp(d)word
2739 is supported. */
2740
2741 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
2742 do { \
2743 if (TARGET_MIPS16_SHORT_JUMP_TABLES) \
2744 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
2745 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
2746 else if (TARGET_GPWORD) \
2747 fprintf (STREAM, "\t%s\t%sL%d\n", \
2748 ptr_mode == DImode ? ".gpdword" : ".gpword", \
2749 LOCAL_LABEL_PREFIX, VALUE); \
2750 else if (TARGET_RTP_PIC) \
2751 { \
2752 /* Make the entry relative to the start of the function. */ \
2753 rtx fnsym = XEXP (DECL_RTL (current_function_decl), 0); \
2754 fprintf (STREAM, "\t%s\t%sL%d-", \
2755 Pmode == DImode ? ".dword" : ".word", \
2756 LOCAL_LABEL_PREFIX, VALUE); \
2757 assemble_name (STREAM, XSTR (fnsym, 0)); \
2758 fprintf (STREAM, "\n"); \
2759 } \
2760 else \
2761 fprintf (STREAM, "\t%s\t%sL%d\n", \
2762 ptr_mode == DImode ? ".dword" : ".word", \
2763 LOCAL_LABEL_PREFIX, VALUE); \
2764 } while (0)
2765
2766 /* This is how to output an assembler line
2767 that says to advance the location counter
2768 to a multiple of 2**LOG bytes. */
2769
2770 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
2771 fprintf (STREAM, "\t.align\t%d\n", (LOG))
2772
2773 /* This is how to output an assembler line to advance the location
2774 counter by SIZE bytes. */
2775
2776 #undef ASM_OUTPUT_SKIP
2777 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
2778 fprintf (STREAM, "\t.space\t"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE))
2779
2780 /* This is how to output a string. */
2781 #undef ASM_OUTPUT_ASCII
2782 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
2783 mips_output_ascii (STREAM, STRING, LEN, "\t.ascii\t")
2784
2785 /* Output #ident as a in the read-only data section. */
2786 #undef ASM_OUTPUT_IDENT
2787 #define ASM_OUTPUT_IDENT(FILE, STRING) \
2788 { \
2789 const char *p = STRING; \
2790 int size = strlen (p) + 1; \
2791 switch_to_section (readonly_data_section); \
2792 assemble_string (p, size); \
2793 }
2794 \f
2795 /* Default to -G 8 */
2796 #ifndef MIPS_DEFAULT_GVALUE
2797 #define MIPS_DEFAULT_GVALUE 8
2798 #endif
2799
2800 /* Define the strings to put out for each section in the object file. */
2801 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
2802 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
2803
2804 #undef READONLY_DATA_SECTION_ASM_OP
2805 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
2806 \f
2807 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
2808 do \
2809 { \
2810 fprintf (STREAM, "\t%s\t%s,%s,-8\n\t%s\t%s,0(%s)\n", \
2811 TARGET_64BIT ? "daddiu" : "addiu", \
2812 reg_names[STACK_POINTER_REGNUM], \
2813 reg_names[STACK_POINTER_REGNUM], \
2814 TARGET_64BIT ? "sd" : "sw", \
2815 reg_names[REGNO], \
2816 reg_names[STACK_POINTER_REGNUM]); \
2817 } \
2818 while (0)
2819
2820 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
2821 do \
2822 { \
2823 if (! set_noreorder) \
2824 fprintf (STREAM, "\t.set\tnoreorder\n"); \
2825 \
2826 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
2827 TARGET_64BIT ? "ld" : "lw", \
2828 reg_names[REGNO], \
2829 reg_names[STACK_POINTER_REGNUM], \
2830 TARGET_64BIT ? "daddu" : "addu", \
2831 reg_names[STACK_POINTER_REGNUM], \
2832 reg_names[STACK_POINTER_REGNUM]); \
2833 \
2834 if (! set_noreorder) \
2835 fprintf (STREAM, "\t.set\treorder\n"); \
2836 } \
2837 while (0)
2838
2839 /* How to start an assembler comment.
2840 The leading space is important (the mips native assembler requires it). */
2841 #ifndef ASM_COMMENT_START
2842 #define ASM_COMMENT_START " #"
2843 #endif
2844 \f
2845 /* Default definitions for size_t and ptrdiff_t. We must override the
2846 definitions from ../svr4.h on mips-*-linux-gnu. */
2847
2848 #undef SIZE_TYPE
2849 #define SIZE_TYPE (POINTER_SIZE == 64 ? "long unsigned int" : "unsigned int")
2850
2851 #undef PTRDIFF_TYPE
2852 #define PTRDIFF_TYPE (POINTER_SIZE == 64 ? "long int" : "int")
2853
2854 /* The base cost of a memcpy call, for MOVE_RATIO and friends. These
2855 values were determined experimentally by benchmarking with CSiBE.
2856 In theory, the call overhead is higher for TARGET_ABICALLS (especially
2857 for o32 where we have to restore $gp afterwards as well as make an
2858 indirect call), but in practice, bumping this up higher for
2859 TARGET_ABICALLS doesn't make much difference to code size. */
2860
2861 #define MIPS_CALL_RATIO 8
2862
2863 /* Define MOVE_RATIO to encourage use of movmemsi when enabled,
2864 since it should always generate code at least as good as
2865 move_by_pieces(). But when inline movmemsi pattern is disabled
2866 (i.e., with -mips16 or -mmemcpy), instead use a value approximating
2867 the length of a memcpy call sequence, so that move_by_pieces will
2868 generate inline code if it is shorter than a function call.
2869 Since move_by_pieces_ninsns() counts memory-to-memory moves, but
2870 we'll have to generate a load/store pair for each, halve the value of
2871 MIPS_CALL_RATIO to take that into account.
2872 The default value for MOVE_RATIO when HAVE_movmemsi is true is 2.
2873 There is no point to setting it to less than this to try to disable
2874 move_by_pieces entirely, because that also disables some desirable
2875 tree-level optimizations, specifically related to optimizing a
2876 one-byte string copy into a simple move byte operation. */
2877
2878 #define MOVE_RATIO \
2879 ((TARGET_MIPS16 || TARGET_MEMCPY) ? MIPS_CALL_RATIO / 2 : 2)
2880
2881 /* For CLEAR_RATIO, when optimizing for size, give a better estimate
2882 of the length of a memset call, but use the default otherwise. */
2883
2884 #define CLEAR_RATIO \
2885 (optimize_size ? MIPS_CALL_RATIO : 15)
2886
2887 /* This is similar to CLEAR_RATIO, but for a non-zero constant, so when
2888 optimizing for size adjust the ratio to account for the overhead of
2889 loading the constant and replicating it across the word. */
2890
2891 #define SET_RATIO \
2892 (optimize_size ? MIPS_CALL_RATIO - 2 : 15)
2893
2894 /* STORE_BY_PIECES_P can be used when copying a constant string, but
2895 in that case each word takes 3 insns (lui, ori, sw), or more in
2896 64-bit mode, instead of 2 (lw, sw). For now we always fail this
2897 and let the move_by_pieces code copy the string from read-only
2898 memory. In the future, this could be tuned further for multi-issue
2899 CPUs that can issue stores down one pipe and arithmetic instructions
2900 down another; in that case, the lui/ori/sw combination would be a
2901 win for long enough strings. */
2902
2903 #define STORE_BY_PIECES_P(SIZE, ALIGN) 0
2904 \f
2905 #ifndef __mips16
2906 /* Since the bits of the _init and _fini function is spread across
2907 many object files, each potentially with its own GP, we must assume
2908 we need to load our GP. We don't preserve $gp or $ra, since each
2909 init/fini chunk is supposed to initialize $gp, and crti/crtn
2910 already take care of preserving $ra and, when appropriate, $gp. */
2911 #if (defined _ABIO32 && _MIPS_SIM == _ABIO32)
2912 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2913 asm (SECTION_OP "\n\
2914 .set noreorder\n\
2915 bal 1f\n\
2916 nop\n\
2917 1: .cpload $31\n\
2918 .set reorder\n\
2919 jal " USER_LABEL_PREFIX #FUNC "\n\
2920 " TEXT_SECTION_ASM_OP);
2921 #endif /* Switch to #elif when we're no longer limited by K&R C. */
2922 #if (defined _ABIN32 && _MIPS_SIM == _ABIN32) \
2923 || (defined _ABI64 && _MIPS_SIM == _ABI64)
2924 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
2925 asm (SECTION_OP "\n\
2926 .set noreorder\n\
2927 bal 1f\n\
2928 nop\n\
2929 1: .set reorder\n\
2930 .cpsetup $31, $2, 1b\n\
2931 jal " USER_LABEL_PREFIX #FUNC "\n\
2932 " TEXT_SECTION_ASM_OP);
2933 #endif
2934 #endif
2935
2936 #ifndef HAVE_AS_TLS
2937 #define HAVE_AS_TLS 0
2938 #endif
2939
2940 /* Return an asm string that atomically:
2941
2942 - Compares memory reference %1 to register %2 and, if they are
2943 equal, changes %1 to %3.
2944
2945 - Sets register %0 to the old value of memory reference %1.
2946
2947 SUFFIX is the suffix that should be added to "ll" and "sc" instructions
2948 and OP is the instruction that should be used to load %3 into a
2949 register. */
2950 #define MIPS_COMPARE_AND_SWAP(SUFFIX, OP) \
2951 "%(%<%[%|sync\n" \
2952 "1:\tll" SUFFIX "\t%0,%1\n" \
2953 "\tbne\t%0,%2,2f\n" \
2954 "\t" OP "\t%@,%3\n" \
2955 "\tsc" SUFFIX "\t%@,%1\n" \
2956 "\tbeq\t%@,%.,1b\n" \
2957 "\tnop\n" \
2958 "2:\tsync%-%]%>%)"
2959
2960 /* Return an asm string that atomically:
2961
2962 - Sets memory reference %0 to %0 INSN %1.
2963
2964 SUFFIX is the suffix that should be added to "ll" and "sc"
2965 instructions. */
2966 #define MIPS_SYNC_OP(SUFFIX, INSN) \
2967 "%(%<%[%|sync\n" \
2968 "1:\tll" SUFFIX "\t%@,%0\n" \
2969 "\t" INSN "\t%@,%@,%1\n" \
2970 "\tsc" SUFFIX "\t%@,%0\n" \
2971 "\tbeq\t%@,%.,1b\n" \
2972 "\tnop\n" \
2973 "\tsync%-%]%>%)"
2974
2975 /* Return an asm string that atomically:
2976
2977 - Sets memory reference %1 to %1 INSN %2.
2978
2979 - Sets register %0 to the old value of memory reference %1.
2980
2981 SUFFIX is the suffix that should be added to "ll" and "sc"
2982 instructions. */
2983 #define MIPS_SYNC_OLD_OP(SUFFIX, INSN) \
2984 "%(%<%[%|sync\n" \
2985 "1:\tll" SUFFIX "\t%0,%1\n" \
2986 "\t" INSN "\t%@,%0,%2\n" \
2987 "\tsc" SUFFIX "\t%@,%1\n" \
2988 "\tbeq\t%@,%.,1b\n" \
2989 "\tnop\n" \
2990 "\tsync%-%]%>%)"
2991
2992 /* Return an asm string that atomically:
2993
2994 - Sets memory reference %1 to %1 INSN %2.
2995
2996 - Sets register %0 to the new value of memory reference %1.
2997
2998 SUFFIX is the suffix that should be added to "ll" and "sc"
2999 instructions. */
3000 #define MIPS_SYNC_NEW_OP(SUFFIX, INSN) \
3001 "%(%<%[%|sync\n" \
3002 "1:\tll" SUFFIX "\t%0,%1\n" \
3003 "\t" INSN "\t%@,%0,%2\n" \
3004 "\tsc" SUFFIX "\t%@,%1\n" \
3005 "\tbeq\t%@,%.,1b\n" \
3006 "\t" INSN "\t%0,%0,%2\n" \
3007 "\tsync%-%]%>%)"
3008
3009 /* Return an asm string that atomically:
3010
3011 - Sets memory reference %0 to ~%0 AND %1.
3012
3013 SUFFIX is the suffix that should be added to "ll" and "sc"
3014 instructions. INSN is the and instruction needed to and a register
3015 with %2. */
3016 #define MIPS_SYNC_NAND(SUFFIX, INSN) \
3017 "%(%<%[%|sync\n" \
3018 "1:\tll" SUFFIX "\t%@,%0\n" \
3019 "\tnor\t%@,%@,%.\n" \
3020 "\t" INSN "\t%@,%@,%1\n" \
3021 "\tsc" SUFFIX "\t%@,%0\n" \
3022 "\tbeq\t%@,%.,1b\n" \
3023 "\tnop\n" \
3024 "\tsync%-%]%>%)"
3025
3026 /* Return an asm string that atomically:
3027
3028 - Sets memory reference %1 to ~%1 AND %2.
3029
3030 - Sets register %0 to the old value of memory reference %1.
3031
3032 SUFFIX is the suffix that should be added to "ll" and "sc"
3033 instructions. INSN is the and instruction needed to and a register
3034 with %2. */
3035 #define MIPS_SYNC_OLD_NAND(SUFFIX, INSN) \
3036 "%(%<%[%|sync\n" \
3037 "1:\tll" SUFFIX "\t%0,%1\n" \
3038 "\tnor\t%@,%0,%.\n" \
3039 "\t" INSN "\t%@,%@,%2\n" \
3040 "\tsc" SUFFIX "\t%@,%1\n" \
3041 "\tbeq\t%@,%.,1b\n" \
3042 "\tnop\n" \
3043 "\tsync%-%]%>%)"
3044
3045 /* Return an asm string that atomically:
3046
3047 - Sets memory reference %1 to ~%1 AND %2.
3048
3049 - Sets register %0 to the new value of memory reference %1.
3050
3051 SUFFIX is the suffix that should be added to "ll" and "sc"
3052 instructions. INSN is the and instruction needed to and a register
3053 with %2. */
3054 #define MIPS_SYNC_NEW_NAND(SUFFIX, INSN) \
3055 "%(%<%[%|sync\n" \
3056 "1:\tll" SUFFIX "\t%0,%1\n" \
3057 "\tnor\t%0,%0,%.\n" \
3058 "\t" INSN "\t%@,%0,%2\n" \
3059 "\tsc" SUFFIX "\t%@,%1\n" \
3060 "\tbeq\t%@,%.,1b\n" \
3061 "\t" INSN "\t%0,%0,%2\n" \
3062 "\tsync%-%]%>%)"
3063
3064 /* Return an asm string that atomically:
3065
3066 - Sets memory reference %1 to %2.
3067
3068 - Sets register %0 to the old value of memory reference %1.
3069
3070 SUFFIX is the suffix that should be added to "ll" and "sc"
3071 instructions. OP is the and instruction that should be used to
3072 load %2 into a register. */
3073 #define MIPS_SYNC_EXCHANGE(SUFFIX, OP) \
3074 "%(%<%[%|\n" \
3075 "1:\tll" SUFFIX "\t%0,%1\n" \
3076 "\t" OP "\t%@,%2\n" \
3077 "\tsc" SUFFIX "\t%@,%1\n" \
3078 "\tbeq\t%@,%.,1b\n" \
3079 "\tnop\n" \
3080 "\tsync%-%]%>%)"
3081
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