x86/iflags.ph

   1 # -*- perl -*-
   2
   3 #
   4 # dword bound, index 0 - specific flags
   5 #
   6 if_align('IGEN');
   7
   8 if_("SM",                "Size match");
   9 if_("SM2",               "Size match first two operands");
  10 if_("SB",                "Unsized operands can't be non-byte");
  11 if_("SW",                "Unsized operands can't be non-word");
  12 if_("SD",                "Unsized operands can't be non-dword");
  13 if_("SQ",                "Unsized operands can't be non-qword");
  14 if_("SO",                "Unsized operands can't be non-oword");
  15 if_("SY",                "Unsized operands can't be non-yword");
  16 if_("SZ",                "Unsized operands can't be non-zword");
  17 if_("SIZE",              "Unsized operands must match the bitsize");
  18 if_("SX",                "Unsized operands not allowed");
  19 if_("ANYSIZE",           "Ignore operand size even if explicit");
  20 if_("AR0",               "SB, SW, SD applies to argument 0");
  21 if_("AR1",               "SB, SW, SD applies to argument 1");
  22 if_("AR2",               "SB, SW, SD applies to argument 2");
  23 if_("AR3",               "SB, SW, SD applies to argument 3");
  24 if_("AR4",               "SB, SW, SD applies to argument 4");
  25 if_("OPT",               "Optimizing assembly only");
  26
  27 #
  28 # dword bound - instruction feature filtering flags
  29 #
  30 if_align('FEATURE');
  31
  32 if_("PRIV",              "Privileged instruction");
  33 if_("SMM",               "Only valid in SMM");
  34 if_("PROT",              "Protected mode only");
  35 if_("LOCK",              "Lockable if operand 0 is memory");
  36 if_("NOLONG",            "Not available in long mode");
  37 if_("LONG",              "Long mode");
  38 if_("NOHLE",             "HLE prefixes forbidden");
  39 if_("MIB",               "disassemble with split EA");
  40 if_("BND",               "BND (0xF2) prefix available");
  41 if_("UNDOC",             "Undocumented");
  42 if_("HLE",               "HLE prefixed");
  43 if_("FPU",               "FPU");
  44 if_("MMX",               "MMX");
  45 if_("3DNOW",             "3DNow!");
  46 if_("SSE",               "SSE (KNI, MMX2)");
  47 if_("SSE2",              "SSE2");
  48 if_("SSE3",              "SSE3 (PNI)");
  49 if_("VMX",               "VMX");
  50 if_("SSSE3",             "SSSE3");
  51 if_("SSE4A",             "AMD SSE4a");
  52 if_("SSE41",             "SSE4.1");
  53 if_("SSE42",             "SSE4.2");
  54 if_("SSE5",              "SSE5");
  55 if_("AVX",               "AVX  (256-bit floating point)");
  56 if_("AVX2",              "AVX2 (256-bit integer)");
  57 if_("FMA",               "");
  58 if_("BMI1",              "");
  59 if_("BMI2",              "");
  60 if_("TBM",               "");
  61 if_("RTM",               "");
  62 if_("INVPCID",           "");
  63 if_("AVX512",            "AVX-512F (512-bit base architecture)");
  64 if_("AVX512CD",          "AVX-512 Conflict Detection");
  65 if_("AVX512ER",          "AVX-512 Exponential and Reciprocal");
  66 if_("AVX512PF",          "AVX-512 Prefetch");
  67 if_("MPX",               "MPX");
  68 if_("SHA",               "SHA");
  69 if_("PREFETCHWT1",       "PREFETCHWT1");
  70 if_("AVX512VL",          "AVX-512 Vector Length Orthogonality");
  71 if_("AVX512DQ",          "AVX-512 Dword and Qword");
  72 if_("AVX512BW",          "AVX-512 Byte and Word");
  73 if_("AVX512IFMA",        "AVX-512 IFMA instructions");
  74 if_("AVX512VBMI",        "AVX-512 VBMI instructions");
  75 if_("AES",               "AES instructions");
  76 if_("VAES",              "AES AVX instructions");
  77 if_("VPCLMULQDQ",        "AVX Carryless Multiplication");
  78 if_("GFNI",              "Galois Field instructions");
  79 if_("AVX512VBMI2",       "AVX-512 VBMI2 instructions");
  80 if_("AVX512VNNI",        "AVX-512 VNNI instructions");
  81 if_("AVX512BITALG",      "AVX-512 Bit Algorithm instructions");
  82 if_("AVX512VPOPCNTDQ",   "AVX-512 VPOPCNTD/VPOPCNTQ");
  83 if_("AVX5124FMAPS",      "AVX-512 4-iteration multiply-add");
  84 if_("AVX5124VNNIW",      "AVX-512 4-iteration dot product");
  85 if_("SGX",               "Intel Software Guard Extensions (SGX)");
  86 if_("CET",               "Intel Control-Flow Enforcement Technology (CET)");
  87
  88 # Put these last [hpa: why?]
  89 if_("OBSOLETE",          "Instruction removed from architecture");
  90 if_("NEVER",             "Instruction never implemented");
  91 if_("NOP",               "Instruction is always a (nonintentional) NOP");
  92 if_("VEX",               "VEX or XOP encoded instruction");
  93 if_("EVEX",              "EVEX encoded instruction");
  94
  95 #
  96 # dword bound - cpu type flags
  97 #
  98 # The CYRIX and AMD flags should have the highest bit values; the
  99 # disassembler selection algorithm depends on it.
 100 #
 101 if_align('CPU');
 102
 103 if_("8086",              "8086");
 104 if_("186",               "186+");
 105 if_("286",               "286+");
 106 if_("386",               "386+");
 107 if_("486",               "486+");
 108 if_("PENT",              "Pentium");
 109 if_("P6",                "P6");
 110 if_("KATMAI",            "Katmai");
 111 if_("WILLAMETTE",        "Willamette");
 112 if_("PRESCOTT",          "Prescott");
 113 if_("X86_64",            "x86-64 (long or legacy mode)");
 114 if_("NEHALEM",           "Nehalem");
 115 if_("WESTMERE",          "Westmere");
 116 if_("SANDYBRIDGE",       "Sandy Bridge");
 117 if_("FUTURE",            "Ivy Bridge or newer");
 118 if_("IA64",              "IA64 (in x86 mode)");
 119
 120 # Must be the last CPU definition
 121 if_("ANY",               "Any x86 CPU");
 122
 123 # These must come after the CPU defitions proper
 124 if_("CYRIX",             "Cyrix-specific");
 125 if_("AMD",               "AMD-specific");