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output: remove ABSOLUTE handling, OUT_RAWDATA asserts
[nasm.git] / asm / assemble.c
blobe71e907a66258e2d3b6ffcf17d1f36da1584670d
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2018 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * Bytecode specification
38 * ----------------------
39 *
40 *
41 * Codes Mnemonic Explanation
42 *
43 * \0 terminates the code. (Unless it's a literal of course.)
44 * \1..\4 that many literal bytes follow in the code stream
45 * \5 add 4 to the primary operand number (b, low octdigit)
46 * \6 add 4 to the secondary operand number (a, middle octdigit)
47 * \7 add 4 to both the primary and the secondary operand number
48 * \10..\13 a literal byte follows in the code stream, to be added
49 * to the register value of operand 0..3
50 * \14..\17 the position of index register operand in MIB (BND insns)
51 * \20..\23 ib a byte immediate operand, from operand 0..3
52 * \24..\27 ib,u a zero-extended byte immediate operand, from operand 0..3
53 * \30..\33 iw a word immediate operand, from operand 0..3
54 * \34..\37 iwd select between \3[0-3] and \4[0-3] depending on 16/32 bit
55 * assembly mode or the operand-size override on the operand
56 * \40..\43 id a long immediate operand, from operand 0..3
57 * \44..\47 iwdq select between \3[0-3], \4[0-3] and \5[4-7]
58 * depending on the address size of the instruction.
59 * \50..\53 rel8 a byte relative operand, from operand 0..3
60 * \54..\57 iq a qword immediate operand, from operand 0..3
61 * \60..\63 rel16 a word relative operand, from operand 0..3
62 * \64..\67 rel select between \6[0-3] and \7[0-3] depending on 16/32 bit
63 * assembly mode or the operand-size override on the operand
64 * \70..\73 rel32 a long relative operand, from operand 0..3
65 * \74..\77 seg a word constant, from the _segment_ part of operand 0..3
66 * \1ab a ModRM, calculated on EA in operand a, with the spare
67 * field the register value of operand b.
68 * \172\ab the register number from operand a in bits 7..4, with
69 * the 4-bit immediate from operand b in bits 3..0.
70 * \173\xab the register number from operand a in bits 7..4, with
71 * the value b in bits 3..0.
72 * \174..\177 the register number from operand 0..3 in bits 7..4, and
73 * an arbitrary value in bits 3..0 (assembled as zero.)
74 * \2ab a ModRM, calculated on EA in operand a, with the spare
75 * field equal to digit b.
76 *
77 * \240..\243 this instruction uses EVEX rather than REX or VEX/XOP, with the
78 * V field taken from operand 0..3.
79 * \250 this instruction uses EVEX rather than REX or VEX/XOP, with the
80 * V field set to 1111b.
81 *
82 * EVEX prefixes are followed by the sequence:
83 * \cm\wlp\tup where cm is:
84 * cc 00m mmm
85 * c = 2 for EVEX and mmmm is the M field (EVEX.P0[3:0])
86 * and wlp is:
87 * 00 wwl lpp
88 * [l0] ll = 0 (.128, .lz)
89 * [l1] ll = 1 (.256)
90 * [l2] ll = 2 (.512)
91 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
92 *
93 * [w0] ww = 0 for W = 0
94 * [w1] ww = 1 for W = 1
95 * [wig] ww = 2 for W don't care (always assembled as 0)
96 * [ww] ww = 3 for W used as REX.W
97 *
98 * [p0] pp = 0 for no prefix
99 * [60] pp = 1 for legacy prefix 60
100 * [f3] pp = 2
101 * [f2] pp = 3
102 *
103 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
104 * (compressed displacement encoding)
105 *
106 * \254..\257 id,s a signed 32-bit operand to be extended to 64 bits.
107 * \260..\263 this instruction uses VEX/XOP rather than REX, with the
108 * V field taken from operand 0..3.
109 * \270 this instruction uses VEX/XOP rather than REX, with the
110 * V field set to 1111b.
111 *
112 * VEX/XOP prefixes are followed by the sequence:
113 * \tmm\wlp where mm is the M field; and wlp is:
114 * 00 wwl lpp
115 * [l0] ll = 0 for L = 0 (.128, .lz)
116 * [l1] ll = 1 for L = 1 (.256)
117 * [lig] ll = 2 for L don't care (always assembled as 0)
118 *
119 * [w0] ww = 0 for W = 0
120 * [w1 ] ww = 1 for W = 1
121 * [wig] ww = 2 for W don't care (always assembled as 0)
122 * [ww] ww = 3 for W used as REX.W
123 *
124 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
125 *
126 * \271 hlexr instruction takes XRELEASE (F3) with or without lock
127 * \272 hlenl instruction takes XACQUIRE/XRELEASE with or without lock
128 * \273 hle instruction takes XACQUIRE/XRELEASE with lock only
129 * \274..\277 ib,s a byte immediate operand, from operand 0..3, sign-extended
130 * to the operand size (if o16/o32/o64 present) or the bit size
131 * \310 a16 indicates fixed 16-bit address size, i.e. optional 0x67.
132 * \311 a32 indicates fixed 32-bit address size, i.e. optional 0x67.
133 * \312 adf (disassembler only) invalid with non-default address size.
134 * \313 a64 indicates fixed 64-bit address size, 0x67 invalid.
135 * \314 norexb (disassembler only) invalid with REX.B
136 * \315 norexx (disassembler only) invalid with REX.X
137 * \316 norexr (disassembler only) invalid with REX.R
138 * \317 norexw (disassembler only) invalid with REX.W
139 * \320 o16 indicates fixed 16-bit operand size, i.e. optional 0x66.
140 * \321 o32 indicates fixed 32-bit operand size, i.e. optional 0x66.
141 * \322 odf indicates that this instruction is only valid when the
142 * operand size is the default (instruction to disassembler,
143 * generates no code in the assembler)
144 * \323 o64nw indicates fixed 64-bit operand size, REX on extensions only.
145 * \324 o64 indicates 64-bit operand size requiring REX prefix.
146 * \325 nohi instruction which always uses spl/bpl/sil/dil
147 * \326 nof3 instruction not valid with 0xF3 REP prefix. Hint for
148 disassembler only; for SSE instructions.
149 * \330 a literal byte follows in the code stream, to be added
150 * to the condition code value of the instruction.
151 * \331 norep instruction not valid with REP prefix. Hint for
152 * disassembler only; for SSE instructions.
153 * \332 f2i REP prefix (0xF2 byte) used as opcode extension.
154 * \333 f3i REP prefix (0xF3 byte) used as opcode extension.
155 * \334 rex.l LOCK prefix used as REX.R (used in non-64-bit mode)
156 * \335 repe disassemble a rep (0xF3 byte) prefix as repe not rep.
157 * \336 mustrep force a REP(E) prefix (0xF3) even if not specified.
158 * \337 mustrepne force a REPNE prefix (0xF2) even if not specified.
159 * \336-\337 are still listed as prefixes in the disassembler.
160 * \340 resb reserve <operand 0> bytes of uninitialized storage.
161 * Operand 0 had better be a segmentless constant.
162 * \341 wait this instruction needs a WAIT "prefix"
163 * \360 np no SSE prefix (== \364\331)
164 * \361 66 SSE prefix (== \366\331)
165 * \364 !osp operand-size prefix (0x66) not permitted
166 * \365 !asp address-size prefix (0x67) not permitted
167 * \366 operand-size prefix (0x66) used as opcode extension
168 * \367 address-size prefix (0x67) used as opcode extension
169 * \370,\371 jcc8 match only if operand 0 meets byte jump criteria.
170 * jmp8 370 is used for Jcc, 371 is used for JMP.
171 * \373 jlen assemble 0x03 if bits==16, 0x05 if bits==32;
172 * used for conditional jump over longer jump
173 * \374 vsibx|vm32x|vm64x this instruction takes an XMM VSIB memory EA
174 * \375 vsiby|vm32y|vm64y this instruction takes an YMM VSIB memory EA
175 * \376 vsibz|vm32z|vm64z this instruction takes an ZMM VSIB memory EA
176 */
177
178 #include "compiler.h"
179
180 #include <stdio.h>
181 #include <string.h>
182 #include <stdlib.h>
183
184 #include "nasm.h"
185 #include "nasmlib.h"
186 #include "error.h"
187 #include "assemble.h"
188 #include "insns.h"
189 #include "tables.h"
190 #include "disp8.h"
191 #include "listing.h"
192
193 enum match_result {
194 /*
195 * Matching errors. These should be sorted so that more specific
196 * errors come later in the sequence.
197 */
198 MERR_INVALOP,
199 MERR_OPSIZEMISSING,
200 MERR_OPSIZEMISMATCH,
201 MERR_BRNOTHERE,
202 MERR_BRNUMMISMATCH,
203 MERR_MASKNOTHERE,
204 MERR_DECONOTHERE,
205 MERR_BADCPU,
206 MERR_BADMODE,
207 MERR_BADHLE,
208 MERR_ENCMISMATCH,
209 MERR_BADBND,
210 MERR_BADREPNE,
211 /*
212 * Matching success; the conditional ones first
213 */
214 MOK_JUMP, /* Matching OK but needs jmp_match() */
215 MOK_GOOD /* Matching unconditionally OK */
216 };
217
218 typedef struct {
219 enum ea_type type; /* what kind of EA is this? */
220 int sib_present; /* is a SIB byte necessary? */
221 int bytes; /* # of bytes of offset needed */
222 int size; /* lazy - this is sib+bytes+1 */
223 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
224 int8_t disp8; /* compressed displacement for EVEX */
225 } ea;
226
227 #define GEN_SIB(scale, index, base) \
228 (((scale) << 6) | ((index) << 3) | ((base)))
229
230 #define GEN_MODRM(mod, reg, rm) \
231 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
232
233 static int64_t calcsize(int32_t, int64_t, int, insn *,
234 const struct itemplate *);
235 static int emit_prefix(struct out_data *data, const int bits, insn *ins);
236 static void gencode(struct out_data *data, insn *ins);
237 static enum match_result find_match(const struct itemplate **tempp,
238 insn *instruction,
239 int32_t segment, int64_t offset, int bits);
240 static enum match_result matches(const struct itemplate *, insn *, int bits);
241 static opflags_t regflag(const operand *);
242 static int32_t regval(const operand *);
243 static int rexflags(int, opflags_t, int);
244 static int op_rexflags(const operand *, int);
245 static int op_evexflags(const operand *, int, uint8_t);
246 static void add_asp(insn *, int);
247
248 static enum ea_type process_ea(operand *, ea *, int, int,
249 opflags_t, insn *, const char **);
250
251 static inline bool absolute_op(const struct operand *o)
252 {
253 return o->segment == NO_SEG && o->wrt == NO_SEG &&
254 !(o->opflags & OPFLAG_RELATIVE);
255 }
256
257 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
258 {
259 return ins->prefixes[pos] == prefix;
260 }
261
262 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
263 {
264 if (ins->prefixes[pos])
265 nasm_error(ERR_NONFATAL, "invalid %s prefix",
266 prefix_name(ins->prefixes[pos]));
267 }
268
269 static const char *size_name(int size)
270 {
271 switch (size) {
272 case 1:
273 return "byte";
274 case 2:
275 return "word";
276 case 4:
277 return "dword";
278 case 8:
279 return "qword";
280 case 10:
281 return "tword";
282 case 16:
283 return "oword";
284 case 32:
285 return "yword";
286 case 64:
287 return "zword";
288 default:
289 return "???";
290 }
291 }
292
293 static void warn_overflow(int size)
294 {
295 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
296 "%s data exceeds bounds", size_name(size));
297 }
298
299 static void warn_overflow_const(int64_t data, int size)
300 {
301 if (overflow_general(data, size))
302 warn_overflow(size);
303 }
304
305 static void warn_overflow_out(int64_t data, int size, enum out_sign sign)
306 {
307 bool err;
308
309 switch (sign) {
310 case OUT_WRAP:
311 err = overflow_general(data, size);
312 break;
313 case OUT_SIGNED:
314 err = overflow_signed(data, size);
315 break;
316 case OUT_UNSIGNED:
317 err = overflow_unsigned(data, size);
318 break;
319 default:
320 panic();
321 break;
322 }
323
324 if (err)
325 warn_overflow(size);
326 }
327
328 /*
329 * This routine wrappers the real output format's output routine,
330 * in order to pass a copy of the data off to the listing file
331 * generator at the same time, flatten unnecessary relocations,
332 * and verify backend compatibility.
333 */
334 static void out(struct out_data *data)
335 {
336 static int32_t lineno = 0; /* static!!! */
337 static const char *lnfname = NULL;
338 union {
339 uint8_t b[8];
340 uint64_t q;
341 } xdata;
342 size_t asize, amax;
343 uint64_t zeropad = 0;
344 int64_t addrval;
345 int32_t fixseg; /* Segment for which to produce fixed data */
346
347 if (!data->size)
348 return; /* Nothing to do */
349
350 /*
351 * Convert addresses to RAWDATA if possible
352 * XXX: not all backends want this for global symbols!!!!
353 */
354 switch (data->type) {
355 case OUT_ADDRESS:
356 addrval = data->toffset;
357 fixseg = NO_SEG; /* Absolute address is fixed data */
358 goto address;
359
360 case OUT_RELADDR:
361 addrval = data->toffset - data->relbase;
362 fixseg = data->segment; /* Our own segment is fixed data */
363 goto address;
364
365 address:
366 nasm_assert(data->size <= 8);
367 asize = data->size;
368 amax = ofmt->maxbits >> 3; /* Maximum address size in bytes */
369 if ((ofmt->flags & OFMT_KEEP_ADDR) == 0 && data->tsegment == fixseg &&
370 data->twrt == NO_SEG) {
371 warn_overflow_out(addrval, asize, data->sign);
372 xdata.q = cpu_to_le64(addrval);
373 data->data = xdata.b;
374 data->type = OUT_RAWDATA;
375 asize = amax = 0; /* No longer an address */
376 }
377 break;
378
379 case OUT_SEGMENT:
380 nasm_assert(data->size <= 8);
381 asize = data->size;
382 amax = 2;
383 break;
384
385 default:
386 asize = amax = 0; /* Not an address */
387 break;
388 }
389
390 /*
391 * this call to src_get determines when we call the
392 * debug-format-specific "linenum" function
393 * it updates lineno and lnfname to the current values
394 * returning 0 if "same as last time", -2 if lnfname
395 * changed, and the amount by which lineno changed,
396 * if it did. thus, these variables must be static
397 */
398
399 if (src_get(&lineno, &lnfname))
400 dfmt->linenum(lnfname, lineno, data->segment);
401
402 if (asize > amax) {
403 if (data->type == OUT_RELADDR || data->sign == OUT_SIGNED) {
404 nasm_error(ERR_NONFATAL,
405 "%u-bit signed relocation unsupported by output format %s",
406 (unsigned int)(asize << 3), ofmt->shortname);
407 } else {
408 nasm_error(ERR_WARNING | ERR_WARN_ZEXTRELOC,
409 "%u-bit %s relocation zero-extended from %u bits",
410 (unsigned int)(asize << 3),
411 data->type == OUT_SEGMENT ? "segment" : "unsigned",
412 (unsigned int)(amax << 3));
413 }
414 zeropad = data->size - amax;
415 data->size = amax;
416 }
417 lfmt->output(data);
418
419 if (likely(data->segment != NO_SEG)) {
420 ofmt->output(data);
421 } else {
422 /* Outputting to ABSOLUTE section - only reserve is permitted */
423 if (data->type != OUT_RESERVE) {
424 nasm_error(ERR_NONFATAL, "attempt to assemble code in [ABSOLUTE]"
425 " space");
426 }
427 /* No need to push to the backend */
428 }
429
430 data->offset += data->size;
431 data->insoffs += data->size;
432
433 if (zeropad) {
434 data->type = OUT_ZERODATA;
435 data->size = zeropad;
436 lfmt->output(data);
437 ofmt->output(data);
438 data->offset += zeropad;
439 data->insoffs += zeropad;
440 data->size += zeropad; /* Restore original size value */
441 }
442 }
443
444 static inline void out_rawdata(struct out_data *data, const void *rawdata,
445 size_t size)
446 {
447 data->type = OUT_RAWDATA;
448 data->data = rawdata;
449 data->size = size;
450 out(data);
451 }
452
453 static void out_rawbyte(struct out_data *data, uint8_t byte)
454 {
455 data->type = OUT_RAWDATA;
456 data->data = &byte;
457 data->size = 1;
458 out(data);
459 }
460
461 static inline void out_reserve(struct out_data *data, uint64_t size)
462 {
463 data->type = OUT_RESERVE;
464 data->size = size;
465 out(data);
466 }
467
468 static void out_segment(struct out_data *data, const struct operand *opx)
469 {
470 if (opx->opflags & OPFLAG_RELATIVE)
471 nasm_error(ERR_NONFATAL, "segment references cannot be relative");
472
473 data->type = OUT_SEGMENT;
474 data->sign = OUT_UNSIGNED;
475 data->size = 2;
476 data->toffset = opx->offset;
477 data->tsegment = ofmt->segbase(opx->segment | 1);
478 data->twrt = opx->wrt;
479 out(data);
480 }
481
482 static void out_imm(struct out_data *data, const struct operand *opx,
483 int size, enum out_sign sign)
484 {
485 if (opx->segment != NO_SEG && (opx->segment & 1)) {
486 /*
487 * This is actually a segment reference, but eval() has
488 * already called ofmt->segbase() for us. Sigh.
489 */
490 if (size < 2)
491 nasm_error(ERR_NONFATAL, "segment reference must be 16 bits");
492
493 data->type = OUT_SEGMENT;
494 } else {
495 data->type = (opx->opflags & OPFLAG_RELATIVE)
496 ? OUT_RELADDR : OUT_ADDRESS;
497 }
498 data->sign = sign;
499 data->toffset = opx->offset;
500 data->tsegment = opx->segment;
501 data->twrt = opx->wrt;
502 /*
503 * XXX: improve this if at some point in the future we can
504 * distinguish the subtrahend in expressions like [foo - bar]
505 * where bar is a symbol in the current segment. However, at the
506 * current point, if OPFLAG_RELATIVE is set that subtraction has
507 * already occurred.
508 */
509 data->relbase = 0;
510 data->size = size;
511 out(data);
512 }
513
514 static void out_reladdr(struct out_data *data, const struct operand *opx,
515 int size)
516 {
517 if (opx->opflags & OPFLAG_RELATIVE)
518 nasm_error(ERR_NONFATAL, "invalid use of self-relative expression");
519
520 data->type = OUT_RELADDR;
521 data->sign = OUT_SIGNED;
522 data->size = size;
523 data->toffset = opx->offset;
524 data->tsegment = opx->segment;
525 data->twrt = opx->wrt;
526 data->relbase = data->offset + (data->inslen - data->insoffs);
527 out(data);
528 }
529
530 static bool jmp_match(int32_t segment, int64_t offset, int bits,
531 insn * ins, const struct itemplate *temp)
532 {
533 int64_t isize;
534 const uint8_t *code = temp->code;
535 uint8_t c = code[0];
536 bool is_byte;
537
538 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
539 return false;
540 if (!optimizing)
541 return false;
542 if (optimizing < 0 && c == 0371)
543 return false;
544
545 isize = calcsize(segment, offset, bits, ins, temp);
546
547 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
548 /* Be optimistic in pass 1 */
549 return true;
550
551 if (ins->oprs[0].segment != segment)
552 return false;
553
554 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
555 is_byte = (isize >= -128 && isize <= 127); /* is it byte size? */
556
557 if (is_byte && c == 0371 && ins->prefixes[PPS_REP] == P_BND) {
558 /* jmp short (opcode eb) cannot be used with bnd prefix. */
559 ins->prefixes[PPS_REP] = P_none;
560 nasm_error(ERR_WARNING | ERR_WARN_BND | ERR_PASS2 ,
561 "jmp short does not init bnd regs - bnd prefix dropped.");
562 }
563
564 return is_byte;
565 }
566
567 /* This is totally just a wild guess what is reasonable... */
568 #define INCBIN_MAX_BUF (ZERO_BUF_SIZE * 16)
569
570 int64_t assemble(int32_t segment, int64_t start, int bits, insn *instruction)
571 {
572 struct out_data data;
573 const struct itemplate *temp;
574 enum match_result m;
575 int64_t wsize; /* size for DB etc. */
576
577 nasm_zero(data);
578 data.offset = start;
579 data.segment = segment;
580 data.itemp = NULL;
581 data.bits = bits;
582
583 wsize = db_bytes(instruction->opcode);
584 if (wsize == -1)
585 return 0;
586
587 if (wsize) {
588 extop *e;
589
590 list_for_each(e, instruction->eops) {
591 if (e->type == EOT_DB_NUMBER) {
592 if (wsize > 8) {
593 nasm_error(ERR_NONFATAL,
594 "integer supplied to a DT, DO, DY or DZ"
595 " instruction");
596 } else {
597 data.insoffs = 0;
598 data.inslen = data.size = wsize;
599 data.toffset = e->offset;
600 data.twrt = e->wrt;
601 data.relbase = 0;
602 if (e->segment != NO_SEG && (e->segment & 1)) {
603 data.tsegment = e->segment;
604 data.type = OUT_SEGMENT;
605 data.sign = OUT_UNSIGNED;
606 } else {
607 data.tsegment = e->segment;
608 data.type = e->relative ? OUT_RELADDR : OUT_ADDRESS;
609 data.sign = OUT_WRAP;
610 }
611 out(&data);
612 }
613 } else if (e->type == EOT_DB_STRING ||
614 e->type == EOT_DB_STRING_FREE) {
615 int align = e->stringlen % wsize;
616 if (align)
617 align = wsize - align;
618
619 data.insoffs = 0;
620 data.inslen = e->stringlen + align;
621
622 out_rawdata(&data, e->stringval, e->stringlen);
623 out_rawdata(&data, zero_buffer, align);
624 }
625 }
626 } else if (instruction->opcode == I_INCBIN) {
627 const char *fname = instruction->eops->stringval;
628 FILE *fp;
629 size_t t = instruction->times; /* INCBIN handles TIMES by itself */
630 off_t base = 0;
631 off_t len;
632 const void *map = NULL;
633 char *buf = NULL;
634 size_t blk = 0; /* Buffered I/O block size */
635 size_t m = 0; /* Bytes last read */
636
637 if (!t)
638 goto done;
639
640 fp = nasm_open_read(fname, NF_BINARY|NF_FORMAP);
641 if (!fp) {
642 nasm_error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
643 fname);
644 goto done;
645 }
646
647 len = nasm_file_size(fp);
648
649 if (len == (off_t)-1) {
650 nasm_error(ERR_NONFATAL, "`incbin': unable to get length of file `%s'",
651 fname);
652 goto close_done;
653 }
654
655 if (instruction->eops->next) {
656 base = instruction->eops->next->offset;
657 if (base >= len) {
658 len = 0;
659 } else {
660 len -= base;
661 if (instruction->eops->next->next &&
662 len > (off_t)instruction->eops->next->next->offset)
663 len = (off_t)instruction->eops->next->next->offset;
664 }
665 }
666
667 lfmt->set_offset(data.offset);
668 lfmt->uplevel(LIST_INCBIN);
669
670 if (!len)
671 goto end_incbin;
672
673 /* Try to map file data */
674 map = nasm_map_file(fp, base, len);
675 if (!map) {
676 blk = len < (off_t)INCBIN_MAX_BUF ? (size_t)len : INCBIN_MAX_BUF;
677 buf = nasm_malloc(blk);
678 }
679
680 while (t--) {
681 /*
682 * Consider these irrelevant for INCBIN, since it is fully
683 * possible that these might be (way) bigger than an int
684 * can hold; there is, however, no reason to widen these
685 * types just for INCBIN. data.inslen == 0 signals to the
686 * backend that these fields are meaningless, if at all
687 * needed.
688 */
689 data.insoffs = 0;
690 data.inslen = 0;
691
692 if (map) {
693 out_rawdata(&data, map, len);
694 } else if ((off_t)m == len) {
695 out_rawdata(&data, buf, len);
696 } else {
697 off_t l = len;
698
699 if (fseeko(fp, base, SEEK_SET) < 0 || ferror(fp)) {
700 nasm_error(ERR_NONFATAL,
701 "`incbin': unable to seek on file `%s'",
702 fname);
703 goto end_incbin;
704 }
705 while (l > 0) {
706 m = fread(buf, 1, l < (off_t)blk ? (size_t)l : blk, fp);
707 if (!m || feof(fp)) {
708 /*
709 * This shouldn't happen unless the file
710 * actually changes while we are reading
711 * it.
712 */
713 nasm_error(ERR_NONFATAL,
714 "`incbin': unexpected EOF while"
715 " reading file `%s'", fname);
716 goto end_incbin;
717 }
718 out_rawdata(&data, buf, m);
719 l -= m;
720 }
721 }
722 }
723 end_incbin:
724 lfmt->downlevel(LIST_INCBIN);
725 if (instruction->times > 1) {
726 lfmt->uplevel(LIST_TIMES);
727 lfmt->downlevel(LIST_TIMES);
728 }
729 if (ferror(fp)) {
730 nasm_error(ERR_NONFATAL,
731 "`incbin': error while"
732 " reading file `%s'", fname);
733 }
734 close_done:
735 if (buf)
736 nasm_free(buf);
737 if (map)
738 nasm_unmap_file(map, len);
739 fclose(fp);
740 done:
741 instruction->times = 1; /* Tell the upper layer not to iterate */
742 ;
743 } else {
744 /* "Real" instruction */
745
746 /* Check to see if we need an address-size prefix */
747 add_asp(instruction, bits);
748
749 m = find_match(&temp, instruction, data.segment, data.offset, bits);
750
751 if (m == MOK_GOOD) {
752 /* Matches! */
753 int64_t insn_size = calcsize(data.segment, data.offset,
754 bits, instruction, temp);
755 nasm_assert(insn_size >= 0);
756
757 data.itemp = temp;
758 data.bits = bits;
759 data.insoffs = 0;
760 data.inslen = insn_size;
761
762 gencode(&data, instruction);
763 nasm_assert(data.insoffs == insn_size);
764 } else {
765 /* No match */
766 switch (m) {
767 case MERR_OPSIZEMISSING:
768 nasm_error(ERR_NONFATAL, "operation size not specified");
769 break;
770 case MERR_OPSIZEMISMATCH:
771 nasm_error(ERR_NONFATAL, "mismatch in operand sizes");
772 break;
773 case MERR_BRNOTHERE:
774 nasm_error(ERR_NONFATAL,
775 "broadcast not permitted on this operand");
776 break;
777 case MERR_BRNUMMISMATCH:
778 nasm_error(ERR_NONFATAL,
779 "mismatch in the number of broadcasting elements");
780 break;
781 case MERR_MASKNOTHERE:
782 nasm_error(ERR_NONFATAL,
783 "mask not permitted on this operand");
784 break;
785 case MERR_DECONOTHERE:
786 nasm_error(ERR_NONFATAL, "unsupported mode decorator for instruction");
787 break;
788 case MERR_BADCPU:
789 nasm_error(ERR_NONFATAL, "no instruction for this cpu level");
790 break;
791 case MERR_BADMODE:
792 nasm_error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
793 bits);
794 break;
795 case MERR_ENCMISMATCH:
796 nasm_error(ERR_NONFATAL, "specific encoding scheme not available");
797 break;
798 case MERR_BADBND:
799 nasm_error(ERR_NONFATAL, "bnd prefix is not allowed");
800 break;
801 case MERR_BADREPNE:
802 nasm_error(ERR_NONFATAL, "%s prefix is not allowed",
803 (has_prefix(instruction, PPS_REP, P_REPNE) ?
804 "repne" : "repnz"));
805 break;
806 default:
807 nasm_error(ERR_NONFATAL,
808 "invalid combination of opcode and operands");
809 break;
810 }
811
812 instruction->times = 1; /* Avoid repeated error messages */
813 }
814 }
815 return data.offset - start;
816 }
817
818 int64_t insn_size(int32_t segment, int64_t offset, int bits, insn *instruction)
819 {
820 const struct itemplate *temp;
821 enum match_result m;
822
823 if (instruction->opcode == I_none)
824 return 0;
825
826 if (opcode_is_db(instruction->opcode)) {
827 extop *e;
828 int32_t isize, osize, wsize;
829
830 isize = 0;
831 wsize = db_bytes(instruction->opcode);
832 nasm_assert(wsize > 0);
833
834 list_for_each(e, instruction->eops) {
835 int32_t align;
836
837 osize = 0;
838 if (e->type == EOT_DB_NUMBER) {
839 osize = 1;
840 warn_overflow_const(e->offset, wsize);
841 } else if (e->type == EOT_DB_STRING ||
842 e->type == EOT_DB_STRING_FREE)
843 osize = e->stringlen;
844
845 align = (-osize) % wsize;
846 if (align < 0)
847 align += wsize;
848 isize += osize + align;
849 }
850 return isize;
851 }
852
853 if (instruction->opcode == I_INCBIN) {
854 const char *fname = instruction->eops->stringval;
855 off_t len;
856
857 len = nasm_file_size_by_path(fname);
858 if (len == (off_t)-1) {
859 nasm_error(ERR_NONFATAL, "`incbin': unable to get length of file `%s'",
860 fname);
861 return 0;
862 }
863
864 if (instruction->eops->next) {
865 if (len <= (off_t)instruction->eops->next->offset) {
866 len = 0;
867 } else {
868 len -= instruction->eops->next->offset;
869 if (instruction->eops->next->next &&
870 len > (off_t)instruction->eops->next->next->offset) {
871 len = (off_t)instruction->eops->next->next->offset;
872 }
873 }
874 }
875
876 len *= instruction->times;
877 instruction->times = 1; /* Tell the upper layer to not iterate */
878
879 return len;
880 }
881
882 /* Check to see if we need an address-size prefix */
883 add_asp(instruction, bits);
884
885 m = find_match(&temp, instruction, segment, offset, bits);
886 if (m == MOK_GOOD) {
887 /* we've matched an instruction. */
888 return calcsize(segment, offset, bits, instruction, temp);
889 } else {
890 return -1; /* didn't match any instruction */
891 }
892 }
893
894 static void bad_hle_warn(const insn * ins, uint8_t hleok)
895 {
896 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
897 enum whatwarn { w_none, w_lock, w_inval } ww;
898 static const enum whatwarn warn[2][4] =
899 {
900 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
901 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
902 };
903 unsigned int n;
904
905 n = (unsigned int)rep_pfx - P_XACQUIRE;
906 if (n > 1)
907 return; /* Not XACQUIRE/XRELEASE */
908
909 ww = warn[n][hleok];
910 if (!is_class(MEMORY, ins->oprs[0].type))
911 ww = w_inval; /* HLE requires operand 0 to be memory */
912
913 switch (ww) {
914 case w_none:
915 break;
916
917 case w_lock:
918 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
919 nasm_error(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
920 "%s with this instruction requires lock",
921 prefix_name(rep_pfx));
922 }
923 break;
924
925 case w_inval:
926 nasm_error(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
927 "%s invalid with this instruction",
928 prefix_name(rep_pfx));
929 break;
930 }
931 }
932
933 /* Common construct */
934 #define case3(x) case (x): case (x)+1: case (x)+2
935 #define case4(x) case3(x): case (x)+3
936
937 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
938 insn * ins, const struct itemplate *temp)
939 {
940 const uint8_t *codes = temp->code;
941 int64_t length = 0;
942 uint8_t c;
943 int rex_mask = ~0;
944 int op1, op2;
945 struct operand *opx;
946 uint8_t opex = 0;
947 enum ea_type eat;
948 uint8_t hleok = 0;
949 bool lockcheck = true;
950 enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
951 const char *errmsg;
952
953 ins->rex = 0; /* Ensure REX is reset */
954 eat = EA_SCALAR; /* Expect a scalar EA */
955 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
956
957 if (ins->prefixes[PPS_OSIZE] == P_O64)
958 ins->rex |= REX_W;
959
960 (void)segment; /* Don't warn that this parameter is unused */
961 (void)offset; /* Don't warn that this parameter is unused */
962
963 while (*codes) {
964 c = *codes++;
965 op1 = (c & 3) + ((opex & 1) << 2);
966 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
967 opx = &ins->oprs[op1];
968 opex = 0; /* For the next iteration */
969
970 switch (c) {
971 case4(01):
972 codes += c, length += c;
973 break;
974
975 case3(05):
976 opex = c;
977 break;
978
979 case4(010):
980 ins->rex |=
981 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
982 codes++, length++;
983 break;
984
985 case4(014):
986 /* this is an index reg of MIB operand */
987 mib_index = opx->basereg;
988 break;
989
990 case4(020):
991 case4(024):
992 length++;
993 break;
994
995 case4(030):
996 length += 2;
997 break;
998
999 case4(034):
1000 if (opx->type & (BITS16 | BITS32 | BITS64))
1001 length += (opx->type & BITS16) ? 2 : 4;
1002 else
1003 length += (bits == 16) ? 2 : 4;
1004 break;
1005
1006 case4(040):
1007 length += 4;
1008 break;
1009
1010 case4(044):
1011 length += ins->addr_size >> 3;
1012 break;
1013
1014 case4(050):
1015 length++;
1016 break;
1017
1018 case4(054):
1019 length += 8; /* MOV reg64/imm */
1020 break;
1021
1022 case4(060):
1023 length += 2;
1024 break;
1025
1026 case4(064):
1027 if (opx->type & (BITS16 | BITS32 | BITS64))
1028 length += (opx->type & BITS16) ? 2 : 4;
1029 else
1030 length += (bits == 16) ? 2 : 4;
1031 break;
1032
1033 case4(070):
1034 length += 4;
1035 break;
1036
1037 case4(074):
1038 length += 2;
1039 break;
1040
1041 case 0172:
1042 case 0173:
1043 codes++;
1044 length++;
1045 break;
1046
1047 case4(0174):
1048 length++;
1049 break;
1050
1051 case4(0240):
1052 ins->rex |= REX_EV;
1053 ins->vexreg = regval(opx);
1054 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
1055 ins->vex_cm = *codes++;
1056 ins->vex_wlp = *codes++;
1057 ins->evex_tuple = (*codes++ - 0300);
1058 break;
1059
1060 case 0250:
1061 ins->rex |= REX_EV;
1062 ins->vexreg = 0;
1063 ins->vex_cm = *codes++;
1064 ins->vex_wlp = *codes++;
1065 ins->evex_tuple = (*codes++ - 0300);
1066 break;
1067
1068 case4(0254):
1069 length += 4;
1070 break;
1071
1072 case4(0260):
1073 ins->rex |= REX_V;
1074 ins->vexreg = regval(opx);
1075 ins->vex_cm = *codes++;
1076 ins->vex_wlp = *codes++;
1077 break;
1078
1079 case 0270:
1080 ins->rex |= REX_V;
1081 ins->vexreg = 0;
1082 ins->vex_cm = *codes++;
1083 ins->vex_wlp = *codes++;
1084 break;
1085
1086 case3(0271):
1087 hleok = c & 3;
1088 break;
1089
1090 case4(0274):
1091 length++;
1092 break;
1093
1094 case4(0300):
1095 break;
1096
1097 case 0310:
1098 if (bits == 64)
1099 return -1;
1100 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1101 break;
1102
1103 case 0311:
1104 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1105 break;
1106
1107 case 0312:
1108 break;
1109
1110 case 0313:
1111 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1112 has_prefix(ins, PPS_ASIZE, P_A32))
1113 return -1;
1114 break;
1115
1116 case4(0314):
1117 break;
1118
1119 case 0320:
1120 {
1121 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1122 if (pfx == P_O16)
1123 break;
1124 if (pfx != P_none)
1125 nasm_error(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1126 else
1127 ins->prefixes[PPS_OSIZE] = P_O16;
1128 break;
1129 }
1130
1131 case 0321:
1132 {
1133 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1134 if (pfx == P_O32)
1135 break;
1136 if (pfx != P_none)
1137 nasm_error(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1138 else
1139 ins->prefixes[PPS_OSIZE] = P_O32;
1140 break;
1141 }
1142
1143 case 0322:
1144 break;
1145
1146 case 0323:
1147 rex_mask &= ~REX_W;
1148 break;
1149
1150 case 0324:
1151 ins->rex |= REX_W;
1152 break;
1153
1154 case 0325:
1155 ins->rex |= REX_NH;
1156 break;
1157
1158 case 0326:
1159 break;
1160
1161 case 0330:
1162 codes++, length++;
1163 break;
1164
1165 case 0331:
1166 break;
1167
1168 case 0332:
1169 case 0333:
1170 length++;
1171 break;
1172
1173 case 0334:
1174 ins->rex |= REX_L;
1175 break;
1176
1177 case 0335:
1178 break;
1179
1180 case 0336:
1181 if (!ins->prefixes[PPS_REP])
1182 ins->prefixes[PPS_REP] = P_REP;
1183 break;
1184
1185 case 0337:
1186 if (!ins->prefixes[PPS_REP])
1187 ins->prefixes[PPS_REP] = P_REPNE;
1188 break;
1189
1190 case 0340:
1191 if (!absolute_op(&ins->oprs[0]))
1192 nasm_error(ERR_NONFATAL, "attempt to reserve non-constant"
1193 " quantity of BSS space");
1194 else if (ins->oprs[0].opflags & OPFLAG_FORWARD)
1195 nasm_error(ERR_WARNING | ERR_PASS1,
1196 "forward reference in RESx can have unpredictable results");
1197 else
1198 length += ins->oprs[0].offset;
1199 break;
1200
1201 case 0341:
1202 if (!ins->prefixes[PPS_WAIT])
1203 ins->prefixes[PPS_WAIT] = P_WAIT;
1204 break;
1205
1206 case 0360:
1207 break;
1208
1209 case 0361:
1210 length++;
1211 break;
1212
1213 case 0364:
1214 case 0365:
1215 break;
1216
1217 case 0366:
1218 case 0367:
1219 length++;
1220 break;
1221
1222 case 0370:
1223 case 0371:
1224 break;
1225
1226 case 0373:
1227 length++;
1228 break;
1229
1230 case 0374:
1231 eat = EA_XMMVSIB;
1232 break;
1233
1234 case 0375:
1235 eat = EA_YMMVSIB;
1236 break;
1237
1238 case 0376:
1239 eat = EA_ZMMVSIB;
1240 break;
1241
1242 case4(0100):
1243 case4(0110):
1244 case4(0120):
1245 case4(0130):
1246 case4(0200):
1247 case4(0204):
1248 case4(0210):
1249 case4(0214):
1250 case4(0220):
1251 case4(0224):
1252 case4(0230):
1253 case4(0234):
1254 {
1255 ea ea_data;
1256 int rfield;
1257 opflags_t rflags;
1258 struct operand *opy = &ins->oprs[op2];
1259 struct operand *op_er_sae;
1260
1261 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1262
1263 if (c <= 0177) {
1264 /* pick rfield from operand b (opx) */
1265 rflags = regflag(opx);
1266 rfield = nasm_regvals[opx->basereg];
1267 } else {
1268 rflags = 0;
1269 rfield = c & 7;
1270 }
1271
1272 /* EVEX.b1 : evex_brerop contains the operand position */
1273 op_er_sae = (ins->evex_brerop >= 0 ?
1274 &ins->oprs[ins->evex_brerop] : NULL);
1275
1276 if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
1277 /* set EVEX.b */
1278 ins->evex_p[2] |= EVEX_P2B;
1279 if (op_er_sae->decoflags & ER) {
1280 /* set EVEX.RC (rounding control) */
1281 ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
1282 & EVEX_P2RC;
1283 }
1284 } else {
1285 /* set EVEX.L'L (vector length) */
1286 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1287 ins->evex_p[1] |= ((ins->vex_wlp << (7 - 4)) & EVEX_P1W);
1288 if (opy->decoflags & BRDCAST_MASK) {
1289 /* set EVEX.b */
1290 ins->evex_p[2] |= EVEX_P2B;
1291 }
1292 }
1293
1294 if (itemp_has(temp, IF_MIB)) {
1295 opy->eaflags |= EAF_MIB;
1296 /*
1297 * if a separate form of MIB (ICC style) is used,
1298 * the index reg info is merged into mem operand
1299 */
1300 if (mib_index != R_none) {
1301 opy->indexreg = mib_index;
1302 opy->scale = 1;
1303 opy->hintbase = mib_index;
1304 opy->hinttype = EAH_NOTBASE;
1305 }
1306 }
1307
1308 if (process_ea(opy, &ea_data, bits,
1309 rfield, rflags, ins, &errmsg) != eat) {
1310 nasm_error(ERR_NONFATAL, "%s", errmsg);
1311 return -1;
1312 } else {
1313 ins->rex |= ea_data.rex;
1314 length += ea_data.size;
1315 }
1316 }
1317 break;
1318
1319 default:
1320 nasm_panic(0, "internal instruction table corrupt"
1321 ": instruction code \\%o (0x%02X) given", c, c);
1322 break;
1323 }
1324 }
1325
1326 ins->rex &= rex_mask;
1327
1328 if (ins->rex & REX_NH) {
1329 if (ins->rex & REX_H) {
1330 nasm_error(ERR_NONFATAL, "instruction cannot use high registers");
1331 return -1;
1332 }
1333 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1334 }
1335
1336 switch (ins->prefixes[PPS_VEX]) {
1337 case P_EVEX:
1338 if (!(ins->rex & REX_EV))
1339 return -1;
1340 break;
1341 case P_VEX3:
1342 case P_VEX2:
1343 if (!(ins->rex & REX_V))
1344 return -1;
1345 break;
1346 default:
1347 break;
1348 }
1349
1350 if (ins->rex & (REX_V | REX_EV)) {
1351 int bad32 = REX_R|REX_W|REX_X|REX_B;
1352
1353 if (ins->rex & REX_H) {
1354 nasm_error(ERR_NONFATAL, "cannot use high register in AVX instruction");
1355 return -1;
1356 }
1357 switch (ins->vex_wlp & 060) {
1358 case 000:
1359 case 040:
1360 ins->rex &= ~REX_W;
1361 break;
1362 case 020:
1363 ins->rex |= REX_W;
1364 bad32 &= ~REX_W;
1365 break;
1366 case 060:
1367 /* Follow REX_W */
1368 break;
1369 }
1370
1371 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1372 nasm_error(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1373 return -1;
1374 } else if (!(ins->rex & REX_EV) &&
1375 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1376 nasm_error(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1377 return -1;
1378 }
1379 if (ins->rex & REX_EV)
1380 length += 4;
1381 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1382 ins->prefixes[PPS_VEX] == P_VEX3)
1383 length += 3;
1384 else
1385 length += 2;
1386 } else if (ins->rex & REX_MASK) {
1387 if (ins->rex & REX_H) {
1388 nasm_error(ERR_NONFATAL, "cannot use high register in rex instruction");
1389 return -1;
1390 } else if (bits == 64) {
1391 length++;
1392 } else if ((ins->rex & REX_L) &&
1393 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1394 iflag_cpu_level_ok(&cpu, IF_X86_64)) {
1395 /* LOCK-as-REX.R */
1396 assert_no_prefix(ins, PPS_LOCK);
1397 lockcheck = false; /* Already errored, no need for warning */
1398 length++;
1399 } else {
1400 nasm_error(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1401 return -1;
1402 }
1403 }
1404
1405 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1406 (!itemp_has(temp,IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1407 nasm_error(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1408 "instruction is not lockable");
1409 }
1410
1411 bad_hle_warn(ins, hleok);
1412
1413 /*
1414 * when BND prefix is set by DEFAULT directive,
1415 * BND prefix is added to every appropriate instruction line
1416 * unless it is overridden by NOBND prefix.
1417 */
1418 if (globalbnd &&
1419 (itemp_has(temp, IF_BND) && !has_prefix(ins, PPS_REP, P_NOBND)))
1420 ins->prefixes[PPS_REP] = P_BND;
1421
1422 /*
1423 * Add length of legacy prefixes
1424 */
1425 length += emit_prefix(NULL, bits, ins);
1426
1427 return length;
1428 }
1429
1430 static inline void emit_rex(struct out_data *data, insn *ins)
1431 {
1432 if (data->bits == 64) {
1433 if ((ins->rex & REX_MASK) &&
1434 !(ins->rex & (REX_V | REX_EV)) &&
1435 !ins->rex_done) {
1436 uint8_t rex = (ins->rex & REX_MASK) | REX_P;
1437 out_rawbyte(data, rex);
1438 ins->rex_done = true;
1439 }
1440 }
1441 }
1442
1443 static int emit_prefix(struct out_data *data, const int bits, insn *ins)
1444 {
1445 int bytes = 0;
1446 int j;
1447
1448 for (j = 0; j < MAXPREFIX; j++) {
1449 uint8_t c = 0;
1450 switch (ins->prefixes[j]) {
1451 case P_WAIT:
1452 c = 0x9B;
1453 break;
1454 case P_LOCK:
1455 c = 0xF0;
1456 break;
1457 case P_REPNE:
1458 case P_REPNZ:
1459 case P_XACQUIRE:
1460 case P_BND:
1461 c = 0xF2;
1462 break;
1463 case P_REPE:
1464 case P_REPZ:
1465 case P_REP:
1466 case P_XRELEASE:
1467 c = 0xF3;
1468 break;
1469 case R_CS:
1470 if (bits == 64) {
1471 nasm_error(ERR_WARNING | ERR_PASS2,
1472 "cs segment base generated, but will be ignored in 64-bit mode");
1473 }
1474 c = 0x2E;
1475 break;
1476 case R_DS:
1477 if (bits == 64) {
1478 nasm_error(ERR_WARNING | ERR_PASS2,
1479 "ds segment base generated, but will be ignored in 64-bit mode");
1480 }
1481 c = 0x3E;
1482 break;
1483 case R_ES:
1484 if (bits == 64) {
1485 nasm_error(ERR_WARNING | ERR_PASS2,
1486 "es segment base generated, but will be ignored in 64-bit mode");
1487 }
1488 c = 0x26;
1489 break;
1490 case R_FS:
1491 c = 0x64;
1492 break;
1493 case R_GS:
1494 c = 0x65;
1495 break;
1496 case R_SS:
1497 if (bits == 64) {
1498 nasm_error(ERR_WARNING | ERR_PASS2,
1499 "ss segment base generated, but will be ignored in 64-bit mode");
1500 }
1501 c = 0x36;
1502 break;
1503 case R_SEGR6:
1504 case R_SEGR7:
1505 nasm_error(ERR_NONFATAL,
1506 "segr6 and segr7 cannot be used as prefixes");
1507 break;
1508 case P_A16:
1509 if (bits == 64) {
1510 nasm_error(ERR_NONFATAL,
1511 "16-bit addressing is not supported "
1512 "in 64-bit mode");
1513 } else if (bits != 16)
1514 c = 0x67;
1515 break;
1516 case P_A32:
1517 if (bits != 32)
1518 c = 0x67;
1519 break;
1520 case P_A64:
1521 if (bits != 64) {
1522 nasm_error(ERR_NONFATAL,
1523 "64-bit addressing is only supported "
1524 "in 64-bit mode");
1525 }
1526 break;
1527 case P_ASP:
1528 c = 0x67;
1529 break;
1530 case P_O16:
1531 if (bits != 16)
1532 c = 0x66;
1533 break;
1534 case P_O32:
1535 if (bits == 16)
1536 c = 0x66;
1537 break;
1538 case P_O64:
1539 /* REX.W */
1540 break;
1541 case P_OSP:
1542 c = 0x66;
1543 break;
1544 case P_EVEX:
1545 case P_VEX3:
1546 case P_VEX2:
1547 case P_NOBND:
1548 case P_none:
1549 break;
1550 default:
1551 nasm_panic(0, "invalid instruction prefix");
1552 }
1553 if (c) {
1554 if (data)
1555 out_rawbyte(data, c);
1556 bytes++;
1557 }
1558 }
1559 return bytes;
1560 }
1561
1562 static void gencode(struct out_data *data, insn *ins)
1563 {
1564 uint8_t c;
1565 uint8_t bytes[4];
1566 int64_t size;
1567 int op1, op2;
1568 struct operand *opx;
1569 const uint8_t *codes = data->itemp->code;
1570 uint8_t opex = 0;
1571 enum ea_type eat = EA_SCALAR;
1572 int r;
1573 const int bits = data->bits;
1574 const char *errmsg;
1575
1576 ins->rex_done = false;
1577
1578 emit_prefix(data, bits, ins);
1579
1580 while (*codes) {
1581 c = *codes++;
1582 op1 = (c & 3) + ((opex & 1) << 2);
1583 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1584 opx = &ins->oprs[op1];
1585 opex = 0; /* For the next iteration */
1586
1587
1588 switch (c) {
1589 case 01:
1590 case 02:
1591 case 03:
1592 case 04:
1593 emit_rex(data, ins);
1594 out_rawdata(data, codes, c);
1595 codes += c;
1596 break;
1597
1598 case 05:
1599 case 06:
1600 case 07:
1601 opex = c;
1602 break;
1603
1604 case4(010):
1605 emit_rex(data, ins);
1606 out_rawbyte(data, *codes++ + (regval(opx) & 7));
1607 break;
1608
1609 case4(014):
1610 break;
1611
1612 case4(020):
1613 out_imm(data, opx, 1, OUT_WRAP);
1614 break;
1615
1616 case4(024):
1617 out_imm(data, opx, 1, OUT_UNSIGNED);
1618 break;
1619
1620 case4(030):
1621 out_imm(data, opx, 2, OUT_WRAP);
1622 break;
1623
1624 case4(034):
1625 if (opx->type & (BITS16 | BITS32))
1626 size = (opx->type & BITS16) ? 2 : 4;
1627 else
1628 size = (bits == 16) ? 2 : 4;
1629 out_imm(data, opx, size, OUT_WRAP);
1630 break;
1631
1632 case4(040):
1633 out_imm(data, opx, 4, OUT_WRAP);
1634 break;
1635
1636 case4(044):
1637 size = ins->addr_size >> 3;
1638 out_imm(data, opx, size, OUT_WRAP);
1639 break;
1640
1641 case4(050):
1642 if (opx->segment == data->segment) {
1643 int64_t delta = opx->offset - data->offset
1644 - (data->inslen - data->insoffs);
1645 if (delta > 127 || delta < -128)
1646 nasm_error(ERR_NONFATAL, "short jump is out of range");
1647 }
1648 out_reladdr(data, opx, 1);
1649 break;
1650
1651 case4(054):
1652 out_imm(data, opx, 8, OUT_WRAP);
1653 break;
1654
1655 case4(060):
1656 out_reladdr(data, opx, 2);
1657 break;
1658
1659 case4(064):
1660 if (opx->type & (BITS16 | BITS32 | BITS64))
1661 size = (opx->type & BITS16) ? 2 : 4;
1662 else
1663 size = (bits == 16) ? 2 : 4;
1664
1665 out_reladdr(data, opx, size);
1666 break;
1667
1668 case4(070):
1669 out_reladdr(data, opx, 4);
1670 break;
1671
1672 case4(074):
1673 if (opx->segment == NO_SEG)
1674 nasm_error(ERR_NONFATAL, "value referenced by FAR is not"
1675 " relocatable");
1676 out_segment(data, opx);
1677 break;
1678
1679 case 0172:
1680 {
1681 int mask = ins->prefixes[PPS_VEX] == P_EVEX ? 7 : 15;
1682 const struct operand *opy;
1683
1684 c = *codes++;
1685 opx = &ins->oprs[c >> 3];
1686 opy = &ins->oprs[c & 7];
1687 if (!absolute_op(opy)) {
1688 nasm_error(ERR_NONFATAL,
1689 "non-absolute expression not permitted as argument %d",
1690 c & 7);
1691 } else if (opy->offset & ~mask) {
1692 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1693 "is4 argument exceeds bounds");
1694 }
1695 c = opy->offset & mask;
1696 goto emit_is4;
1697 }
1698
1699 case 0173:
1700 c = *codes++;
1701 opx = &ins->oprs[c >> 4];
1702 c &= 15;
1703 goto emit_is4;
1704
1705 case4(0174):
1706 c = 0;
1707 emit_is4:
1708 r = nasm_regvals[opx->basereg];
1709 out_rawbyte(data, (r << 4) | ((r & 0x10) >> 1) | c);
1710 break;
1711
1712 case4(0254):
1713 if (absolute_op(opx) &&
1714 (int32_t)opx->offset != (int64_t)opx->offset) {
1715 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1716 "signed dword immediate exceeds bounds");
1717 }
1718 out_imm(data, opx, 4, OUT_SIGNED);
1719 break;
1720
1721 case4(0240):
1722 case 0250:
1723 codes += 3;
1724 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1725 EVEX_P2Z | EVEX_P2AAA, 2);
1726 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1727 bytes[0] = 0x62;
1728 /* EVEX.X can be set by either REX or EVEX for different reasons */
1729 bytes[1] = ((((ins->rex & 7) << 5) |
1730 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) ^ 0xf0) |
1731 (ins->vex_cm & EVEX_P0MM);
1732 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1733 ((~ins->vexreg & 15) << 3) |
1734 (1 << 2) | (ins->vex_wlp & 3);
1735 bytes[3] = ins->evex_p[2];
1736 out_rawdata(data, bytes, 4);
1737 break;
1738
1739 case4(0260):
1740 case 0270:
1741 codes += 2;
1742 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1743 ins->prefixes[PPS_VEX] == P_VEX3) {
1744 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1745 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1746 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1747 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1748 out_rawdata(data, bytes, 3);
1749 } else {
1750 bytes[0] = 0xc5;
1751 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1752 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1753 out_rawdata(data, bytes, 2);
1754 }
1755 break;
1756
1757 case 0271:
1758 case 0272:
1759 case 0273:
1760 break;
1761
1762 case4(0274):
1763 {
1764 uint64_t uv, um;
1765 int s;
1766
1767 if (absolute_op(opx)) {
1768 if (ins->rex & REX_W)
1769 s = 64;
1770 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1771 s = 16;
1772 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1773 s = 32;
1774 else
1775 s = bits;
1776
1777 um = (uint64_t)2 << (s-1);
1778 uv = opx->offset;
1779
1780 if (uv > 127 && uv < (uint64_t)-128 &&
1781 (uv < um-128 || uv > um-1)) {
1782 /* If this wasn't explicitly byte-sized, warn as though we
1783 * had fallen through to the imm16/32/64 case.
1784 */
1785 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1786 "%s value exceeds bounds",
1787 (opx->type & BITS8) ? "signed byte" :
1788 s == 16 ? "word" :
1789 s == 32 ? "dword" :
1790 "signed dword");
1791 }
1792
1793 /* Output as a raw byte to avoid byte overflow check */
1794 out_rawbyte(data, (uint8_t)uv);
1795 } else {
1796 out_imm(data, opx, 1, OUT_WRAP); /* XXX: OUT_SIGNED? */
1797 }
1798 break;
1799 }
1800
1801 case4(0300):
1802 break;
1803
1804 case 0310:
1805 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16))
1806 out_rawbyte(data, 0x67);
1807 break;
1808
1809 case 0311:
1810 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32))
1811 out_rawbyte(data, 0x67);
1812 break;
1813
1814 case 0312:
1815 break;
1816
1817 case 0313:
1818 ins->rex = 0;
1819 break;
1820
1821 case4(0314):
1822 break;
1823
1824 case 0320:
1825 case 0321:
1826 break;
1827
1828 case 0322:
1829 case 0323:
1830 break;
1831
1832 case 0324:
1833 ins->rex |= REX_W;
1834 break;
1835
1836 case 0325:
1837 break;
1838
1839 case 0326:
1840 break;
1841
1842 case 0330:
1843 out_rawbyte(data, *codes++ ^ get_cond_opcode(ins->condition));
1844 break;
1845
1846 case 0331:
1847 break;
1848
1849 case 0332:
1850 case 0333:
1851 out_rawbyte(data, c - 0332 + 0xF2);
1852 break;
1853
1854 case 0334:
1855 if (ins->rex & REX_R)
1856 out_rawbyte(data, 0xF0);
1857 ins->rex &= ~(REX_L|REX_R);
1858 break;
1859
1860 case 0335:
1861 break;
1862
1863 case 0336:
1864 case 0337:
1865 break;
1866
1867 case 0340:
1868 if (ins->oprs[0].segment != NO_SEG)
1869 nasm_panic(0, "non-constant BSS size in pass two");
1870
1871 out_reserve(data, ins->oprs[0].offset);
1872 break;
1873
1874 case 0341:
1875 break;
1876
1877 case 0360:
1878 break;
1879
1880 case 0361:
1881 out_rawbyte(data, 0x66);
1882 break;
1883
1884 case 0364:
1885 case 0365:
1886 break;
1887
1888 case 0366:
1889 case 0367:
1890 out_rawbyte(data, c - 0366 + 0x66);
1891 break;
1892
1893 case3(0370):
1894 break;
1895
1896 case 0373:
1897 out_rawbyte(data, bits == 16 ? 3 : 5);
1898 break;
1899
1900 case 0374:
1901 eat = EA_XMMVSIB;
1902 break;
1903
1904 case 0375:
1905 eat = EA_YMMVSIB;
1906 break;
1907
1908 case 0376:
1909 eat = EA_ZMMVSIB;
1910 break;
1911
1912 case4(0100):
1913 case4(0110):
1914 case4(0120):
1915 case4(0130):
1916 case4(0200):
1917 case4(0204):
1918 case4(0210):
1919 case4(0214):
1920 case4(0220):
1921 case4(0224):
1922 case4(0230):
1923 case4(0234):
1924 {
1925 ea ea_data;
1926 int rfield;
1927 opflags_t rflags;
1928 uint8_t *p;
1929 struct operand *opy = &ins->oprs[op2];
1930
1931 if (c <= 0177) {
1932 /* pick rfield from operand b (opx) */
1933 rflags = regflag(opx);
1934 rfield = nasm_regvals[opx->basereg];
1935 } else {
1936 /* rfield is constant */
1937 rflags = 0;
1938 rfield = c & 7;
1939 }
1940
1941 if (process_ea(opy, &ea_data, bits,
1942 rfield, rflags, ins, &errmsg) != eat)
1943 nasm_error(ERR_NONFATAL, "%s", errmsg);
1944
1945 p = bytes;
1946 *p++ = ea_data.modrm;
1947 if (ea_data.sib_present)
1948 *p++ = ea_data.sib;
1949 out_rawdata(data, bytes, p - bytes);
1950
1951 /*
1952 * Make sure the address gets the right offset in case
1953 * the line breaks in the .lst file (BR 1197827)
1954 */
1955
1956 if (ea_data.bytes) {
1957 /* use compressed displacement, if available */
1958 if (ea_data.disp8) {
1959 out_rawbyte(data, ea_data.disp8);
1960 } else if (ea_data.rip) {
1961 out_reladdr(data, opy, ea_data.bytes);
1962 } else {
1963 int asize = ins->addr_size >> 3;
1964
1965 if (overflow_general(opy->offset, asize) ||
1966 signed_bits(opy->offset, ins->addr_size) !=
1967 signed_bits(opy->offset, ea_data.bytes << 3))
1968 warn_overflow(ea_data.bytes);
1969
1970 out_imm(data, opy, ea_data.bytes,
1971 (asize > ea_data.bytes)
1972 ? OUT_SIGNED : OUT_WRAP);
1973 }
1974 }
1975 }
1976 break;
1977
1978 default:
1979 nasm_panic(0, "internal instruction table corrupt"
1980 ": instruction code \\%o (0x%02X) given", c, c);
1981 break;
1982 }
1983 }
1984 }
1985
1986 static opflags_t regflag(const operand * o)
1987 {
1988 if (!is_register(o->basereg))
1989 nasm_panic(0, "invalid operand passed to regflag()");
1990 return nasm_reg_flags[o->basereg];
1991 }
1992
1993 static int32_t regval(const operand * o)
1994 {
1995 if (!is_register(o->basereg))
1996 nasm_panic(0, "invalid operand passed to regval()");
1997 return nasm_regvals[o->basereg];
1998 }
1999
2000 static int op_rexflags(const operand * o, int mask)
2001 {
2002 opflags_t flags;
2003 int val;
2004
2005 if (!is_register(o->basereg))
2006 nasm_panic(0, "invalid operand passed to op_rexflags()");
2007
2008 flags = nasm_reg_flags[o->basereg];
2009 val = nasm_regvals[o->basereg];
2010
2011 return rexflags(val, flags, mask);
2012 }
2013
2014 static int rexflags(int val, opflags_t flags, int mask)
2015 {
2016 int rex = 0;
2017
2018 if (val >= 0 && (val & 8))
2019 rex |= REX_B|REX_X|REX_R;
2020 if (flags & BITS64)
2021 rex |= REX_W;
2022 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
2023 rex |= REX_H;
2024 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
2025 rex |= REX_P;
2026
2027 return rex & mask;
2028 }
2029
2030 static int evexflags(int val, decoflags_t deco,
2031 int mask, uint8_t byte)
2032 {
2033 int evex = 0;
2034
2035 switch (byte) {
2036 case 0:
2037 if (val >= 0 && (val & 16))
2038 evex |= (EVEX_P0RP | EVEX_P0X);
2039 break;
2040 case 2:
2041 if (val >= 0 && (val & 16))
2042 evex |= EVEX_P2VP;
2043 if (deco & Z)
2044 evex |= EVEX_P2Z;
2045 if (deco & OPMASK_MASK)
2046 evex |= deco & EVEX_P2AAA;
2047 break;
2048 }
2049 return evex & mask;
2050 }
2051
2052 static int op_evexflags(const operand * o, int mask, uint8_t byte)
2053 {
2054 int val;
2055
2056 val = nasm_regvals[o->basereg];
2057
2058 return evexflags(val, o->decoflags, mask, byte);
2059 }
2060
2061 static enum match_result find_match(const struct itemplate **tempp,
2062 insn *instruction,
2063 int32_t segment, int64_t offset, int bits)
2064 {
2065 const struct itemplate *temp;
2066 enum match_result m, merr;
2067 opflags_t xsizeflags[MAX_OPERANDS];
2068 bool opsizemissing = false;
2069 int8_t broadcast = instruction->evex_brerop;
2070 int i;
2071
2072 /* broadcasting uses a different data element size */
2073 for (i = 0; i < instruction->operands; i++)
2074 if (i == broadcast)
2075 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
2076 else
2077 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
2078
2079 merr = MERR_INVALOP;
2080
2081 for (temp = nasm_instructions[instruction->opcode];
2082 temp->opcode != I_none; temp++) {
2083 m = matches(temp, instruction, bits);
2084 if (m == MOK_JUMP) {
2085 if (jmp_match(segment, offset, bits, instruction, temp))
2086 m = MOK_GOOD;
2087 else
2088 m = MERR_INVALOP;
2089 } else if (m == MERR_OPSIZEMISSING && !itemp_has(temp, IF_SX)) {
2090 /*
2091 * Missing operand size and a candidate for fuzzy matching...
2092 */
2093 for (i = 0; i < temp->operands; i++)
2094 if (i == broadcast)
2095 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
2096 else
2097 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
2098 opsizemissing = true;
2099 }
2100 if (m > merr)
2101 merr = m;
2102 if (merr == MOK_GOOD)
2103 goto done;
2104 }
2105
2106 /* No match, but see if we can get a fuzzy operand size match... */
2107 if (!opsizemissing)
2108 goto done;
2109
2110 for (i = 0; i < instruction->operands; i++) {
2111 /*
2112 * We ignore extrinsic operand sizes on registers, so we should
2113 * never try to fuzzy-match on them. This also resolves the case
2114 * when we have e.g. "xmmrm128" in two different positions.
2115 */
2116 if (is_class(REGISTER, instruction->oprs[i].type))
2117 continue;
2118
2119 /* This tests if xsizeflags[i] has more than one bit set */
2120 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2121 goto done; /* No luck */
2122
2123 if (i == broadcast) {
2124 instruction->oprs[i].decoflags |= xsizeflags[i];
2125 instruction->oprs[i].type |= (xsizeflags[i] == BR_BITS32 ?
2126 BITS32 : BITS64);
2127 } else {
2128 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2129 }
2130 }
2131
2132 /* Try matching again... */
2133 for (temp = nasm_instructions[instruction->opcode];
2134 temp->opcode != I_none; temp++) {
2135 m = matches(temp, instruction, bits);
2136 if (m == MOK_JUMP) {
2137 if (jmp_match(segment, offset, bits, instruction, temp))
2138 m = MOK_GOOD;
2139 else
2140 m = MERR_INVALOP;
2141 }
2142 if (m > merr)
2143 merr = m;
2144 if (merr == MOK_GOOD)
2145 goto done;
2146 }
2147
2148 done:
2149 *tempp = temp;
2150 return merr;
2151 }
2152
2153 static uint8_t get_broadcast_num(opflags_t opflags, opflags_t brsize)
2154 {
2155 unsigned int opsize = (opflags & SIZE_MASK) >> SIZE_SHIFT;
2156 uint8_t brcast_num;
2157
2158 if (brsize > BITS64)
2159 nasm_error(ERR_FATAL,
2160 "size of broadcasting element is greater than 64 bits");
2161
2162 /*
2163 * The shift term is to take care of the extra BITS80 inserted
2164 * between BITS64 and BITS128.
2165 */
2166 brcast_num = ((opsize / (BITS64 >> SIZE_SHIFT)) * (BITS64 / brsize))
2167 >> (opsize > (BITS64 >> SIZE_SHIFT));
2168
2169 return brcast_num;
2170 }
2171
2172 static enum match_result matches(const struct itemplate *itemp,
2173 insn *instruction, int bits)
2174 {
2175 opflags_t size[MAX_OPERANDS], asize;
2176 bool opsizemissing = false;
2177 int i, oprs;
2178
2179 /*
2180 * Check the opcode
2181 */
2182 if (itemp->opcode != instruction->opcode)
2183 return MERR_INVALOP;
2184
2185 /*
2186 * Count the operands
2187 */
2188 if (itemp->operands != instruction->operands)
2189 return MERR_INVALOP;
2190
2191 /*
2192 * Is it legal?
2193 */
2194 if (!(optimizing > 0) && itemp_has(itemp, IF_OPT))
2195 return MERR_INVALOP;
2196
2197 /*
2198 * {evex} available?
2199 */
2200 switch (instruction->prefixes[PPS_VEX]) {
2201 case P_EVEX:
2202 if (!itemp_has(itemp, IF_EVEX))
2203 return MERR_ENCMISMATCH;
2204 break;
2205 case P_VEX3:
2206 case P_VEX2:
2207 if (!itemp_has(itemp, IF_VEX))
2208 return MERR_ENCMISMATCH;
2209 break;
2210 default:
2211 break;
2212 }
2213
2214 /*
2215 * Check that no spurious colons or TOs are present
2216 */
2217 for (i = 0; i < itemp->operands; i++)
2218 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2219 return MERR_INVALOP;
2220
2221 /*
2222 * Process size flags
2223 */
2224 switch (itemp_smask(itemp)) {
2225 case IF_GENBIT(IF_SB):
2226 asize = BITS8;
2227 break;
2228 case IF_GENBIT(IF_SW):
2229 asize = BITS16;
2230 break;
2231 case IF_GENBIT(IF_SD):
2232 asize = BITS32;
2233 break;
2234 case IF_GENBIT(IF_SQ):
2235 asize = BITS64;
2236 break;
2237 case IF_GENBIT(IF_SO):
2238 asize = BITS128;
2239 break;
2240 case IF_GENBIT(IF_SY):
2241 asize = BITS256;
2242 break;
2243 case IF_GENBIT(IF_SZ):
2244 asize = BITS512;
2245 break;
2246 case IF_GENBIT(IF_SIZE):
2247 switch (bits) {
2248 case 16:
2249 asize = BITS16;
2250 break;
2251 case 32:
2252 asize = BITS32;
2253 break;
2254 case 64:
2255 asize = BITS64;
2256 break;
2257 default:
2258 asize = 0;
2259 break;
2260 }
2261 break;
2262 default:
2263 asize = 0;
2264 break;
2265 }
2266
2267 if (itemp_armask(itemp)) {
2268 /* S- flags only apply to a specific operand */
2269 i = itemp_arg(itemp);
2270 memset(size, 0, sizeof size);
2271 size[i] = asize;
2272 } else {
2273 /* S- flags apply to all operands */
2274 for (i = 0; i < MAX_OPERANDS; i++)
2275 size[i] = asize;
2276 }
2277
2278 /*
2279 * Check that the operand flags all match up,
2280 * it's a bit tricky so lets be verbose:
2281 *
2282 * 1) Find out the size of operand. If instruction
2283 * doesn't have one specified -- we're trying to
2284 * guess it either from template (IF_S* flag) or
2285 * from code bits.
2286 *
2287 * 2) If template operand do not match the instruction OR
2288 * template has an operand size specified AND this size differ
2289 * from which instruction has (perhaps we got it from code bits)
2290 * we are:
2291 * a) Check that only size of instruction and operand is differ
2292 * other characteristics do match
2293 * b) Perhaps it's a register specified in instruction so
2294 * for such a case we just mark that operand as "size
2295 * missing" and this will turn on fuzzy operand size
2296 * logic facility (handled by a caller)
2297 */
2298 for (i = 0; i < itemp->operands; i++) {
2299 opflags_t type = instruction->oprs[i].type;
2300 decoflags_t deco = instruction->oprs[i].decoflags;
2301 decoflags_t ideco = itemp->deco[i];
2302 bool is_broadcast = deco & BRDCAST_MASK;
2303 uint8_t brcast_num = 0;
2304 opflags_t template_opsize, insn_opsize;
2305
2306 if (!(type & SIZE_MASK))
2307 type |= size[i];
2308
2309 insn_opsize = type & SIZE_MASK;
2310 if (!is_broadcast) {
2311 template_opsize = itemp->opd[i] & SIZE_MASK;
2312 } else {
2313 decoflags_t deco_brsize = ideco & BRSIZE_MASK;
2314
2315 if (~ideco & BRDCAST_MASK)
2316 return MERR_BRNOTHERE;
2317
2318 /*
2319 * when broadcasting, the element size depends on
2320 * the instruction type. decorator flag should match.
2321 */
2322 if (deco_brsize) {
2323 template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
2324 /* calculate the proper number : {1to<brcast_num>} */
2325 brcast_num = get_broadcast_num(itemp->opd[i], template_opsize);
2326 } else {
2327 template_opsize = 0;
2328 }
2329 }
2330
2331 if (~ideco & deco & OPMASK_MASK)
2332 return MERR_MASKNOTHERE;
2333
2334 if (~ideco & deco & (Z_MASK|STATICRND_MASK|SAE_MASK))
2335 return MERR_DECONOTHERE;
2336
2337 if (itemp->opd[i] & ~type & ~SIZE_MASK) {
2338 return MERR_INVALOP;
2339 } else if (template_opsize) {
2340 if (template_opsize != insn_opsize) {
2341 if (insn_opsize) {
2342 return MERR_INVALOP;
2343 } else if (!is_class(REGISTER, type)) {
2344 /*
2345 * Note: we don't honor extrinsic operand sizes for registers,
2346 * so "missing operand size" for a register should be
2347 * considered a wildcard match rather than an error.
2348 */
2349 opsizemissing = true;
2350 }
2351 } else if (is_broadcast &&
2352 (brcast_num !=
2353 (2U << ((deco & BRNUM_MASK) >> BRNUM_SHIFT)))) {
2354 /*
2355 * broadcasting opsize matches but the number of repeated memory
2356 * element does not match.
2357 * if 64b double precision float is broadcasted to ymm (256b),
2358 * broadcasting decorator must be {1to4}.
2359 */
2360 return MERR_BRNUMMISMATCH;
2361 }
2362 }
2363 }
2364
2365 if (opsizemissing)
2366 return MERR_OPSIZEMISSING;
2367
2368 /*
2369 * Check operand sizes
2370 */
2371 if (itemp_has(itemp, IF_SM) || itemp_has(itemp, IF_SM2)) {
2372 oprs = (itemp_has(itemp, IF_SM2) ? 2 : itemp->operands);
2373 for (i = 0; i < oprs; i++) {
2374 asize = itemp->opd[i] & SIZE_MASK;
2375 if (asize) {
2376 for (i = 0; i < oprs; i++)
2377 size[i] = asize;
2378 break;
2379 }
2380 }
2381 } else {
2382 oprs = itemp->operands;
2383 }
2384
2385 for (i = 0; i < itemp->operands; i++) {
2386 if (!(itemp->opd[i] & SIZE_MASK) &&
2387 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2388 return MERR_OPSIZEMISMATCH;
2389 }
2390
2391 /*
2392 * Check template is okay at the set cpu level
2393 */
2394 if (iflag_cmp_cpu_level(&insns_flags[itemp->iflag_idx], &cpu) > 0)
2395 return MERR_BADCPU;
2396
2397 /*
2398 * Verify the appropriate long mode flag.
2399 */
2400 if (itemp_has(itemp, (bits == 64 ? IF_NOLONG : IF_LONG)))
2401 return MERR_BADMODE;
2402
2403 /*
2404 * If we have a HLE prefix, look for the NOHLE flag
2405 */
2406 if (itemp_has(itemp, IF_NOHLE) &&
2407 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2408 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2409 return MERR_BADHLE;
2410
2411 /*
2412 * Check if special handling needed for Jumps
2413 */
2414 if ((itemp->code[0] & ~1) == 0370)
2415 return MOK_JUMP;
2416
2417 /*
2418 * Check if BND prefix is allowed.
2419 * Other 0xF2 (REPNE/REPNZ) prefix is prohibited.
2420 */
2421 if (!itemp_has(itemp, IF_BND) &&
2422 (has_prefix(instruction, PPS_REP, P_BND) ||
2423 has_prefix(instruction, PPS_REP, P_NOBND)))
2424 return MERR_BADBND;
2425 else if (itemp_has(itemp, IF_BND) &&
2426 (has_prefix(instruction, PPS_REP, P_REPNE) ||
2427 has_prefix(instruction, PPS_REP, P_REPNZ)))
2428 return MERR_BADREPNE;
2429
2430 return MOK_GOOD;
2431 }
2432
2433 /*
2434 * Check if ModR/M.mod should/can be 01.
2435 * - EAF_BYTEOFFS is set
2436 * - offset can fit in a byte when EVEX is not used
2437 * - offset can be compressed when EVEX is used
2438 */
2439 #define IS_MOD_01() (!(input->eaflags & EAF_WORDOFFS) && \
2440 (ins->rex & REX_EV ? seg == NO_SEG && !forw_ref && \
2441 is_disp8n(input, ins, &output->disp8) : \
2442 input->eaflags & EAF_BYTEOFFS || (o >= -128 && \
2443 o <= 127 && seg == NO_SEG && !forw_ref)))
2444
2445 static enum ea_type process_ea(operand *input, ea *output, int bits,
2446 int rfield, opflags_t rflags, insn *ins,
2447 const char **errmsg)
2448 {
2449 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2450 int addrbits = ins->addr_size;
2451 int eaflags = input->eaflags;
2452
2453 *errmsg = "invalid effective address"; /* Default error message */
2454
2455 output->type = EA_SCALAR;
2456 output->rip = false;
2457 output->disp8 = 0;
2458
2459 /* REX flags for the rfield operand */
2460 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2461 /* EVEX.R' flag for the REG operand */
2462 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2463
2464 if (is_class(REGISTER, input->type)) {
2465 /*
2466 * It's a direct register.
2467 */
2468 if (!is_register(input->basereg))
2469 goto err;
2470
2471 if (!is_reg_class(REG_EA, input->basereg))
2472 goto err;
2473
2474 /* broadcasting is not available with a direct register operand. */
2475 if (input->decoflags & BRDCAST_MASK) {
2476 *errmsg = "broadcast not allowed with register operand";
2477 goto err;
2478 }
2479
2480 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2481 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2482 output->sib_present = false; /* no SIB necessary */
2483 output->bytes = 0; /* no offset necessary either */
2484 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2485 } else {
2486 /*
2487 * It's a memory reference.
2488 */
2489
2490 /* Embedded rounding or SAE is not available with a mem ref operand. */
2491 if (input->decoflags & (ER | SAE)) {
2492 *errmsg = "embedded rounding is available only with "
2493 "register-register operations";
2494 goto err;
2495 }
2496
2497 if (input->basereg == -1 &&
2498 (input->indexreg == -1 || input->scale == 0)) {
2499 /*
2500 * It's a pure offset.
2501 */
2502 if (bits == 64 && ((input->type & IP_REL) == IP_REL)) {
2503 if (input->segment == NO_SEG ||
2504 (input->opflags & OPFLAG_RELATIVE)) {
2505 nasm_error(ERR_WARNING | ERR_PASS2,
2506 "absolute address can not be RIP-relative");
2507 input->type &= ~IP_REL;
2508 input->type |= MEMORY;
2509 }
2510 }
2511
2512 if (bits == 64 &&
2513 !(IP_REL & ~input->type) && (eaflags & EAF_MIB)) {
2514 *errmsg = "RIP-relative addressing is prohibited for MIB";
2515 goto err;
2516 }
2517
2518 if (eaflags & EAF_BYTEOFFS ||
2519 (eaflags & EAF_WORDOFFS &&
2520 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2521 nasm_error(ERR_WARNING | ERR_PASS1,
2522 "displacement size ignored on absolute address");
2523 }
2524
2525 if (bits == 64 && (~input->type & IP_REL)) {
2526 output->sib_present = true;
2527 output->sib = GEN_SIB(0, 4, 5);
2528 output->bytes = 4;
2529 output->modrm = GEN_MODRM(0, rfield, 4);
2530 output->rip = false;
2531 } else {
2532 output->sib_present = false;
2533 output->bytes = (addrbits != 16 ? 4 : 2);
2534 output->modrm = GEN_MODRM(0, rfield,
2535 (addrbits != 16 ? 5 : 6));
2536 output->rip = bits == 64;
2537 }
2538 } else {
2539 /*
2540 * It's an indirection.
2541 */
2542 int i = input->indexreg, b = input->basereg, s = input->scale;
2543 int32_t seg = input->segment;
2544 int hb = input->hintbase, ht = input->hinttype;
2545 int t, it, bt; /* register numbers */
2546 opflags_t x, ix, bx; /* register flags */
2547
2548 if (s == 0)
2549 i = -1; /* make this easy, at least */
2550
2551 if (is_register(i)) {
2552 it = nasm_regvals[i];
2553 ix = nasm_reg_flags[i];
2554 } else {
2555 it = -1;
2556 ix = 0;
2557 }
2558
2559 if (is_register(b)) {
2560 bt = nasm_regvals[b];
2561 bx = nasm_reg_flags[b];
2562 } else {
2563 bt = -1;
2564 bx = 0;
2565 }
2566
2567 /* if either one are a vector register... */
2568 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2569 opflags_t sok = BITS32 | BITS64;
2570 int32_t o = input->offset;
2571 int mod, scale, index, base;
2572
2573 /*
2574 * For a vector SIB, one has to be a vector and the other,
2575 * if present, a GPR. The vector must be the index operand.
2576 */
2577 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2578 if (s == 0)
2579 s = 1;
2580 else if (s != 1)
2581 goto err;
2582
2583 t = bt, bt = it, it = t;
2584 x = bx, bx = ix, ix = x;
2585 }
2586
2587 if (bt != -1) {
2588 if (REG_GPR & ~bx)
2589 goto err;
2590 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2591 sok &= bx;
2592 else
2593 goto err;
2594 }
2595
2596 /*
2597 * While we're here, ensure the user didn't specify
2598 * WORD or QWORD
2599 */
2600 if (input->disp_size == 16 || input->disp_size == 64)
2601 goto err;
2602
2603 if (addrbits == 16 ||
2604 (addrbits == 32 && !(sok & BITS32)) ||
2605 (addrbits == 64 && !(sok & BITS64)))
2606 goto err;
2607
2608 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2609 : ((ix & YMMREG & ~REG_EA)
2610 ? EA_YMMVSIB : EA_XMMVSIB));
2611
2612 output->rex |= rexflags(it, ix, REX_X);
2613 output->rex |= rexflags(bt, bx, REX_B);
2614 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2615
2616 index = it & 7; /* it is known to be != -1 */
2617
2618 switch (s) {
2619 case 1:
2620 scale = 0;
2621 break;
2622 case 2:
2623 scale = 1;
2624 break;
2625 case 4:
2626 scale = 2;
2627 break;
2628 case 8:
2629 scale = 3;
2630 break;
2631 default: /* then what the smeg is it? */
2632 goto err; /* panic */
2633 }
2634
2635 if (bt == -1) {
2636 base = 5;
2637 mod = 0;
2638 } else {
2639 base = (bt & 7);
2640 if (base != REG_NUM_EBP && o == 0 &&
2641 seg == NO_SEG && !forw_ref &&
2642 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2643 mod = 0;
2644 else if (IS_MOD_01())
2645 mod = 1;
2646 else
2647 mod = 2;
2648 }
2649
2650 output->sib_present = true;
2651 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2652 output->modrm = GEN_MODRM(mod, rfield, 4);
2653 output->sib = GEN_SIB(scale, index, base);
2654 } else if ((ix|bx) & (BITS32|BITS64)) {
2655 /*
2656 * it must be a 32/64-bit memory reference. Firstly we have
2657 * to check that all registers involved are type E/Rxx.
2658 */
2659 opflags_t sok = BITS32 | BITS64;
2660 int32_t o = input->offset;
2661
2662 if (it != -1) {
2663 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2664 sok &= ix;
2665 else
2666 goto err;
2667 }
2668
2669 if (bt != -1) {
2670 if (REG_GPR & ~bx)
2671 goto err; /* Invalid register */
2672 if (~sok & bx & SIZE_MASK)
2673 goto err; /* Invalid size */
2674 sok &= bx;
2675 }
2676
2677 /*
2678 * While we're here, ensure the user didn't specify
2679 * WORD or QWORD
2680 */
2681 if (input->disp_size == 16 || input->disp_size == 64)
2682 goto err;
2683
2684 if (addrbits == 16 ||
2685 (addrbits == 32 && !(sok & BITS32)) ||
2686 (addrbits == 64 && !(sok & BITS64)))
2687 goto err;
2688
2689 /* now reorganize base/index */
2690 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2691 ((hb == b && ht == EAH_NOTBASE) ||
2692 (hb == i && ht == EAH_MAKEBASE))) {
2693 /* swap if hints say so */
2694 t = bt, bt = it, it = t;
2695 x = bx, bx = ix, ix = x;
2696 }
2697
2698 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
2699 /* make single reg base, unless hint */
2700 bt = it, bx = ix, it = -1, ix = 0;
2701 }
2702 if (eaflags & EAF_MIB) {
2703 /* only for mib operands */
2704 if (it == -1 && (hb == b && ht == EAH_NOTBASE)) {
2705 /*
2706 * make a single reg index [reg*1].
2707 * gas uses this form for an explicit index register.
2708 */
2709 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2710 }
2711 if ((ht == EAH_SUMMED) && bt == -1) {
2712 /* separate once summed index into [base, index] */
2713 bt = it, bx = ix, s--;
2714 }
2715 } else {
2716 if (((s == 2 && it != REG_NUM_ESP &&
2717 (!(eaflags & EAF_TIMESTWO) || (ht == EAH_SUMMED))) ||
2718 s == 3 || s == 5 || s == 9) && bt == -1) {
2719 /* convert 3*EAX to EAX+2*EAX */
2720 bt = it, bx = ix, s--;
2721 }
2722 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2723 (eaflags & EAF_TIMESTWO) &&
2724 (hb == b && ht == EAH_NOTBASE)) {
2725 /*
2726 * convert [NOSPLIT EAX*1]
2727 * to sib format with 0x0 displacement - [EAX*1+0].
2728 */
2729 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2730 }
2731 }
2732 if (s == 1 && it == REG_NUM_ESP) {
2733 /* swap ESP into base if scale is 1 */
2734 t = it, it = bt, bt = t;
2735 x = ix, ix = bx, bx = x;
2736 }
2737 if (it == REG_NUM_ESP ||
2738 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2739 goto err; /* wrong, for various reasons */
2740
2741 output->rex |= rexflags(it, ix, REX_X);
2742 output->rex |= rexflags(bt, bx, REX_B);
2743
2744 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2745 /* no SIB needed */
2746 int mod, rm;
2747
2748 if (bt == -1) {
2749 rm = 5;
2750 mod = 0;
2751 } else {
2752 rm = (bt & 7);
2753 if (rm != REG_NUM_EBP && o == 0 &&
2754 seg == NO_SEG && !forw_ref &&
2755 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2756 mod = 0;
2757 else if (IS_MOD_01())
2758 mod = 1;
2759 else
2760 mod = 2;
2761 }
2762
2763 output->sib_present = false;
2764 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2765 output->modrm = GEN_MODRM(mod, rfield, rm);
2766 } else {
2767 /* we need a SIB */
2768 int mod, scale, index, base;
2769
2770 if (it == -1)
2771 index = 4, s = 1;
2772 else
2773 index = (it & 7);
2774
2775 switch (s) {
2776 case 1:
2777 scale = 0;
2778 break;
2779 case 2:
2780 scale = 1;
2781 break;
2782 case 4:
2783 scale = 2;
2784 break;
2785 case 8:
2786 scale = 3;
2787 break;
2788 default: /* then what the smeg is it? */
2789 goto err; /* panic */
2790 }
2791
2792 if (bt == -1) {
2793 base = 5;
2794 mod = 0;
2795 } else {
2796 base = (bt & 7);
2797 if (base != REG_NUM_EBP && o == 0 &&
2798 seg == NO_SEG && !forw_ref &&
2799 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2800 mod = 0;
2801 else if (IS_MOD_01())
2802 mod = 1;
2803 else
2804 mod = 2;
2805 }
2806
2807 output->sib_present = true;
2808 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2809 output->modrm = GEN_MODRM(mod, rfield, 4);
2810 output->sib = GEN_SIB(scale, index, base);
2811 }
2812 } else { /* it's 16-bit */
2813 int mod, rm;
2814 int16_t o = input->offset;
2815
2816 /* check for 64-bit long mode */
2817 if (addrbits == 64)
2818 goto err;
2819
2820 /* check all registers are BX, BP, SI or DI */
2821 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2822 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2823 goto err;
2824
2825 /* ensure the user didn't specify DWORD/QWORD */
2826 if (input->disp_size == 32 || input->disp_size == 64)
2827 goto err;
2828
2829 if (s != 1 && i != -1)
2830 goto err; /* no can do, in 16-bit EA */
2831 if (b == -1 && i != -1) {
2832 int tmp = b;
2833 b = i;
2834 i = tmp;
2835 } /* swap */
2836 if ((b == R_SI || b == R_DI) && i != -1) {
2837 int tmp = b;
2838 b = i;
2839 i = tmp;
2840 }
2841 /* have BX/BP as base, SI/DI index */
2842 if (b == i)
2843 goto err; /* shouldn't ever happen, in theory */
2844 if (i != -1 && b != -1 &&
2845 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2846 goto err; /* invalid combinations */
2847 if (b == -1) /* pure offset: handled above */
2848 goto err; /* so if it gets to here, panic! */
2849
2850 rm = -1;
2851 if (i != -1)
2852 switch (i * 256 + b) {
2853 case R_SI * 256 + R_BX:
2854 rm = 0;
2855 break;
2856 case R_DI * 256 + R_BX:
2857 rm = 1;
2858 break;
2859 case R_SI * 256 + R_BP:
2860 rm = 2;
2861 break;
2862 case R_DI * 256 + R_BP:
2863 rm = 3;
2864 break;
2865 } else
2866 switch (b) {
2867 case R_SI:
2868 rm = 4;
2869 break;
2870 case R_DI:
2871 rm = 5;
2872 break;
2873 case R_BP:
2874 rm = 6;
2875 break;
2876 case R_BX:
2877 rm = 7;
2878 break;
2879 }
2880 if (rm == -1) /* can't happen, in theory */
2881 goto err; /* so panic if it does */
2882
2883 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2884 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2885 mod = 0;
2886 else if (IS_MOD_01())
2887 mod = 1;
2888 else
2889 mod = 2;
2890
2891 output->sib_present = false; /* no SIB - it's 16-bit */
2892 output->bytes = mod; /* bytes of offset needed */
2893 output->modrm = GEN_MODRM(mod, rfield, rm);
2894 }
2895 }
2896 }
2897
2898 output->size = 1 + output->sib_present + output->bytes;
2899 return output->type;
2900
2901 err:
2902 return output->type = EA_INVALID;
2903 }
2904
2905 static void add_asp(insn *ins, int addrbits)
2906 {
2907 int j, valid;
2908 int defdisp;
2909
2910 valid = (addrbits == 64) ? 64|32 : 32|16;
2911
2912 switch (ins->prefixes[PPS_ASIZE]) {
2913 case P_A16:
2914 valid &= 16;
2915 break;
2916 case P_A32:
2917 valid &= 32;
2918 break;
2919 case P_A64:
2920 valid &= 64;
2921 break;
2922 case P_ASP:
2923 valid &= (addrbits == 32) ? 16 : 32;
2924 break;
2925 default:
2926 break;
2927 }
2928
2929 for (j = 0; j < ins->operands; j++) {
2930 if (is_class(MEMORY, ins->oprs[j].type)) {
2931 opflags_t i, b;
2932
2933 /* Verify as Register */
2934 if (!is_register(ins->oprs[j].indexreg))
2935 i = 0;
2936 else
2937 i = nasm_reg_flags[ins->oprs[j].indexreg];
2938
2939 /* Verify as Register */
2940 if (!is_register(ins->oprs[j].basereg))
2941 b = 0;
2942 else
2943 b = nasm_reg_flags[ins->oprs[j].basereg];
2944
2945 if (ins->oprs[j].scale == 0)
2946 i = 0;
2947
2948 if (!i && !b) {
2949 int ds = ins->oprs[j].disp_size;
2950 if ((addrbits != 64 && ds > 8) ||
2951 (addrbits == 64 && ds == 16))
2952 valid &= ds;
2953 } else {
2954 if (!(REG16 & ~b))
2955 valid &= 16;
2956 if (!(REG32 & ~b))
2957 valid &= 32;
2958 if (!(REG64 & ~b))
2959 valid &= 64;
2960
2961 if (!(REG16 & ~i))
2962 valid &= 16;
2963 if (!(REG32 & ~i))
2964 valid &= 32;
2965 if (!(REG64 & ~i))
2966 valid &= 64;
2967 }
2968 }
2969 }
2970
2971 if (valid & addrbits) {
2972 ins->addr_size = addrbits;
2973 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2974 /* Add an address size prefix */
2975 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2976 ins->addr_size = (addrbits == 32) ? 16 : 32;
2977 } else {
2978 /* Impossible... */
2979 nasm_error(ERR_NONFATAL, "impossible combination of address sizes");
2980 ins->addr_size = addrbits; /* Error recovery */
2981 }
2982
2983 defdisp = ins->addr_size == 16 ? 16 : 32;
2984
2985 for (j = 0; j < ins->operands; j++) {
2986 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2987 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2988 /*
2989 * mem_offs sizes must match the address size; if not,
2990 * strip the MEM_OFFS bit and match only EA instructions
2991 */
2992 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2993 }
2994 }
2995 }
The Netwide Assembler