insns-iflags.pl

   1 #!/usr/bin/perl
   2 ## --------------------------------------------------------------------------
   3 ##
   4 ##   Copyright 1996-2013 The NASM Authors - All Rights Reserved
   5 ##   See the file AUTHORS included with the NASM distribution for
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  13 ##     notice, this list of conditions and the following disclaimer.
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  32 ##
  33 ## --------------------------------------------------------------------------
  34
  35 #
  36 # Instruction template flags. These specify which processor
  37 # targets the instruction is eligible for, whether it is
  38 # privileged or undocumented, and also specify extra error
  39 # checking on the matching of the instruction.
  40 #
  41 # IF_SM stands for Size Match: any operand whose size is not
  42 # explicitly specified by the template is `really' intended to be
  43 # the same size as the first size-specified operand.
  44 # Non-specification is tolerated in the input instruction, but
  45 # _wrong_ specification is not.
  46 #
  47 # IF_SM2 invokes Size Match on only the first _two_ operands, for
  48 # three-operand instructions such as SHLD: it implies that the
  49 # first two operands must match in size, but that the third is
  50 # required to be _unspecified_.
  51 #
  52 # IF_SB invokes Size Byte: operands with unspecified size in the
  53 # template are really bytes, and so no non-byte specification in
  54 # the input instruction will be tolerated. IF_SW similarly invokes
  55 # Size Word, and IF_SD invokes Size Doubleword.
  56 #
  57 # (The default state if neither IF_SM nor IF_SM2 is specified is
  58 # that any operand with unspecified size in the template is
  59 # required to have unspecified size in the instruction too...)
  60 #
  61 # iflag_t is defined to store these flags.
  62 #
  63 # The order does matter here. We use some predefined masks to quick test
  64 # for a set of flags, so be careful moving bits (and
  65 # don't forget to update C code generation then).
  66 #
  67 my %insns_flag_bit = (
  68     #
  69     # dword bound, index 0 - specific flags
  70     #
  71     "SM"                => [  0, "Size match"],
  72     "SM2"               => [  1, "Size match first two operands"],
  73     "SB"                => [  2, "Unsized operands can't be non-byte"],
  74     "SW"                => [  3, "Unsized operands can't be non-word"],
  75     "SD"                => [  4, "Unsized operands can't be non-dword"],
  76     "SQ"                => [  5, "Unsized operands can't be non-qword"],
  77     "SO"                => [  6, "Unsized operands can't be non-oword"],
  78     "SY"                => [  7, "Unsized operands can't be non-yword"],
  79     "SZ"                => [  8, "Unsized operands can't be non-zword"],
  80     "SIZE"              => [  9, "Unsized operands must match the bitsize"],
  81     "SX"                => [ 10, "Unsized operands not allowed"],
  82     "AR0"               => [ 11, "SB, SW, SD applies to argument 0"],
  83     "AR1"               => [ 12, "SB, SW, SD applies to argument 1"],
  84     "AR2"               => [ 13, "SB, SW, SD applies to argument 2"],
  85     "AR3"               => [ 14, "SB, SW, SD applies to argument 3"],
  86     "AR4"               => [ 15, "SB, SW, SD applies to argument 4"],
  87     "OPT"               => [ 16, "Optimizing assembly only"],
  88
  89     #
  90     # dword bound, index 1 - instruction filtering flags
  91     #
  92     "PRIV"              => [ 32, "Privileged instruction"],
  93     "SMM"               => [ 33, "Only valid in SMM"],
  94     "PROT"              => [ 34, "Protected mode only"],
  95     "LOCK"              => [ 35, "Lockable if operand 0 is memory"],
  96     "NOLONG"            => [ 36, "Not available in long mode"],
  97     "LONG"              => [ 37, "Long mode"],
  98     "NOHLE"             => [ 38, "HLE prefixes forbidden"],
  99     "MIB"               => [ 39, "disassemble with split EA"],
 100     "BND"               => [ 40, "BND (0xF2) prefix available"],
 101     "UNDOC"             => [ 41, "Undocumented"],
 102     "HLE"               => [ 42, "HLE prefixed"],
 103     "FPU"               => [ 43, "FPU"],
 104     "MMX"               => [ 44, "MMX"],
 105     "3DNOW"             => [ 45, "3DNow!"],
 106     "SSE"               => [ 46, "SSE (KNI, MMX2)"],
 107     "SSE2"              => [ 47, "SSE2"],
 108     "SSE3"              => [ 48, "SSE3 (PNI)"],
 109     "VMX"               => [ 49, "VMX"],
 110     "SSSE3"             => [ 50, "SSSE3"],
 111     "SSE4A"             => [ 51, "AMD SSE4a"],
 112     "SSE41"             => [ 52, "SSE4.1"],
 113     "SSE42"             => [ 53, "SSE4.2"],
 114     "SSE5"              => [ 54, "SSE5"],
 115     "AVX"               => [ 55, "AVX (128b)"],
 116     "AVX2"              => [ 56, "AVX2 (256b)"],
 117     "FMA"               => [ 57, ""],
 118     "BMI1"              => [ 58, ""],
 119     "BMI2"              => [ 59, ""],
 120     "TBM"               => [ 60, ""],
 121     "RTM"               => [ 61, ""],
 122     "INVPCID"           => [ 62, ""],
 123
 124     #
 125     # dword bound, index 2 - instruction filtering flags
 126     #
 127     "AVX512"            => [ 64, "AVX-512F (512b)"],
 128     "AVX512CD"          => [ 65, "AVX-512 Conflict Detection"],
 129     "AVX512ER"          => [ 66, "AVX-512 Exponential and Reciprocal"],
 130     "AVX512PF"          => [ 67, "AVX-512 Prefetch"],
 131     "MPX"               => [ 68 ,"MPX"],
 132     "SHA"               => [ 69 ,"SHA"],
 133     "PREFETCHWT1"       => [ 70 ,"PREFETCHWT1"],
 134     "AVX512VL"          => [ 71, "AVX-512 Vector Length Orthogonality"],
 135     "AVX512DQ"          => [ 72, "AVX-512 Dword and Qword"],
 136     "AVX512BW"          => [ 73, "AVX-512 Byte and Word"],
 137     "AVX512IFMA"        => [ 74, "AVX-512 IFMA instructions"],
 138     "AVX512VBMI"        => [ 75, "AVX-512 VBMI instructions"],
 139     "VEX"               => [ 94, "VEX or XOP encoded instruction"],
 140     "EVEX"              => [ 95, "EVEX encoded instruction"],
 141
 142     #
 143     # dword bound, index 3 - cpu type flags
 144     #
 145     # The CYRIX and AMD flags should have the highest bit values; the
 146     # disassembler selection algorithm depends on it.
 147     #
 148     "8086"              => [ 96, "8086"],
 149     "186"               => [ 97, "186+"],
 150     "286"               => [ 98, "286+"],
 151     "386"               => [ 99, "386+"],
 152     "486"               => [100, "486+"],
 153     "PENT"              => [101, "Pentium"],
 154     "P6"                => [102, "P6"],
 155     "KATMAI"            => [103, "Katmai"],
 156     "WILLAMETTE"        => [104, "Willamette"],
 157     "PRESCOTT"          => [105, "Prescott"],
 158     "X86_64"            => [106, "x86-64 (long or legacy mode)"],
 159     "NEHALEM"           => [107, "Nehalem"],
 160     "WESTMERE"          => [108, "Westmere"],
 161     "SANDYBRIDGE"       => [109, "Sandy Bridge"],
 162     "FUTURE"            => [110, "Future processor (not yet disclosed)"],
 163     "IA64"              => [111, "IA64 (in x86 mode)"],
 164     "CYRIX"             => [126, "Cyrix-specific"],
 165     "AMD"               => [127, "AMD-specific"],
 166 );
 167
 168 my %insns_flag_hash = ();
 169 my @insns_flag_values = ();
 170 my $iflag_words;
 171
 172 sub get_flag_words() {
 173     my $max = -1;
 174
 175     foreach my $key (keys(%insns_flag_bit)) {
 176         if (${$insns_flag_bit{$key}}[0] > $max) {
 177             $max = ${$insns_flag_bit{$key}}[0];
 178         }
 179     }
 180
 181     return int($max/32)+1;
 182 }
 183
 184 sub insns_flag_index(@) {
 185     return undef if $_[0] eq "ignore";
 186
 187     my @prekey = sort(@_);
 188     my $key = join("", @prekey);
 189
 190     if (not defined($insns_flag_hash{$key})) {
 191         my @newkey = (0) x $iflag_words;
 192
 193         for my $i (@prekey) {
 194             die "No key for $i\n" if not defined($insns_flag_bit{$i});
 195             $newkey[$insns_flag_bit{$i}[0]/32] |=
 196                 (1 << ($insns_flag_bit{$i}[0] % 32));
 197         }
 198
 199         my $str = join(',', map { sprintf("UINT32_C(0x%08x)",$_) } @newkey);
 200
 201         push @insns_flag_values, $str;
 202         $insns_flag_hash{$key} = $#insns_flag_values;
 203     }
 204
 205     return $insns_flag_hash{$key};
 206 }
 207
 208 sub write_iflaggen_h() {
 209     print STDERR "Writing iflaggen.h ...\n";
 210
 211     open(N, ">iflaggen.h") or die "$0: $!\n";
 212
 213     print N "/* This file is auto-generated. Don't edit. */\n";
 214     print N "#ifndef NASM_IFLAGGEN_H\n";
 215     print N "#define NASM_IFLAGGEN_H 1\n\n";
 216
 217     foreach my $key (sort { $insns_flag_bit{$a}[0] <=> $insns_flag_bit{$b}[0] } keys(%insns_flag_bit)) {
 218         print N sprintf("#define IF_%-16s %3d /* %-64s */\n",
 219             $key, $insns_flag_bit{$key}[0], $insns_flag_bit{$key}[1]);
 220     }
 221
 222     print N "\n";
 223     print N "typedef struct {\n";
 224     printf N "    uint32_t field[%d];\n", $iflag_words;
 225     print N "} iflag_t;\n";
 226
 227     print N "\n";
 228     printf N "extern const iflag_t insns_flags[%d];\n\n",
 229         $#insns_flag_values + 1;
 230
 231     print N "#endif /* NASM_IFLAGGEN_H */\n";
 232     close N;
 233 }
 234
 235 sub write_iflag_c() {
 236     print STDERR "Writing iflag.c ...\n";
 237
 238     open N, ">iflag.c";
 239
 240     print N "/* This file is auto-generated. Don't edit. */\n";
 241     print N "#include \"iflag.h\"\n\n";
 242     print N "/* Global flags referenced from instruction templates */\n";
 243     printf N "const iflag_t insns_flags[%d] = {\n",
 244         $#insns_flag_values + 1;
 245     foreach my $i (0 .. $#insns_flag_values) {
 246         print N sprintf("    /* %4d */ {{ %s }},\n", $i, $insns_flag_values[$i]);
 247     }
 248     print N "};\n\n";
 249     close N;
 250 }
 251
 252 $iflag_words = get_flag_words();
 253
 254 1;