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Add extension bytecodes to support operands 4+
[nasm.git] / disasm.c
blob70bbfc1c9bc0928f45000e8fbced80fe845ad8dc
1 /* disasm.c where all the _work_ gets done in the Netwide Disassembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
7 *
8 * initial version 27/iii/95 by Simon Tatham
9 */
10
11 #include "compiler.h"
12
13 #include <stdio.h>
14 #include <string.h>
15 #include <limits.h>
16 #include <inttypes.h>
17
18 #include "nasm.h"
19 #include "disasm.h"
20 #include "sync.h"
21 #include "insns.h"
22 #include "tables.h"
23 #include "regdis.h"
24
25 /*
26 * Flags that go into the `segment' field of `insn' structures
27 * during disassembly.
28 */
29 #define SEG_RELATIVE 1
30 #define SEG_32BIT 2
31 #define SEG_RMREG 4
32 #define SEG_DISP8 8
33 #define SEG_DISP16 16
34 #define SEG_DISP32 32
35 #define SEG_NODISP 64
36 #define SEG_SIGNED 128
37 #define SEG_64BIT 256
38
39 /*
40 * Prefix information
41 */
42 struct prefix_info {
43 uint8_t osize; /* Operand size */
44 uint8_t asize; /* Address size */
45 uint8_t osp; /* Operand size prefix present */
46 uint8_t asp; /* Address size prefix present */
47 uint8_t rep; /* Rep prefix present */
48 uint8_t seg; /* Segment override prefix present */
49 uint8_t lock; /* Lock prefix present */
50 uint8_t vex[3]; /* VEX prefix present */
51 uint8_t vex_m; /* VEX.M field */
52 uint8_t vex_v;
53 uint8_t vex_lp; /* VEX.LP fields */
54 uint32_t rex; /* REX prefix present */
55 };
56
57 #define getu8(x) (*(uint8_t *)(x))
58 #if X86_MEMORY
59 /* Littleendian CPU which can handle unaligned references */
60 #define getu16(x) (*(uint16_t *)(x))
61 #define getu32(x) (*(uint32_t *)(x))
62 #define getu64(x) (*(uint64_t *)(x))
63 #else
64 static uint16_t getu16(uint8_t *data)
65 {
66 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
67 }
68 static uint32_t getu32(uint8_t *data)
69 {
70 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
71 }
72 static uint64_t getu64(uint8_t *data)
73 {
74 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
75 }
76 #endif
77
78 #define gets8(x) ((int8_t)getu8(x))
79 #define gets16(x) ((int16_t)getu16(x))
80 #define gets32(x) ((int32_t)getu32(x))
81 #define gets64(x) ((int64_t)getu64(x))
82
83 /* Important: regval must already have been adjusted for rex extensions */
84 static enum reg_enum whichreg(int32_t regflags, int regval, int rex)
85 {
86 if (!(regflags & (REGISTER|REGMEM)))
87 return 0; /* Registers not permissible?! */
88
89 regflags |= REGISTER;
90
91 if (!(REG_AL & ~regflags))
92 return R_AL;
93 if (!(REG_AX & ~regflags))
94 return R_AX;
95 if (!(REG_EAX & ~regflags))
96 return R_EAX;
97 if (!(REG_RAX & ~regflags))
98 return R_RAX;
99 if (!(REG_DL & ~regflags))
100 return R_DL;
101 if (!(REG_DX & ~regflags))
102 return R_DX;
103 if (!(REG_EDX & ~regflags))
104 return R_EDX;
105 if (!(REG_RDX & ~regflags))
106 return R_RDX;
107 if (!(REG_CL & ~regflags))
108 return R_CL;
109 if (!(REG_CX & ~regflags))
110 return R_CX;
111 if (!(REG_ECX & ~regflags))
112 return R_ECX;
113 if (!(REG_RCX & ~regflags))
114 return R_RCX;
115 if (!(FPU0 & ~regflags))
116 return R_ST0;
117 if (!(XMM0 & ~regflags))
118 return R_XMM0;
119 if (!(YMM0 & ~regflags))
120 return R_YMM0;
121 if (!(REG_CS & ~regflags))
122 return (regval == 1) ? R_CS : 0;
123 if (!(REG_DESS & ~regflags))
124 return (regval == 0 || regval == 2
125 || regval == 3 ? nasm_rd_sreg[regval] : 0);
126 if (!(REG_FSGS & ~regflags))
127 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
128 if (!(REG_SEG67 & ~regflags))
129 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
130
131 /* All the entries below look up regval in an 16-entry array */
132 if (regval < 0 || regval > 15)
133 return 0;
134
135 if (!(REG8 & ~regflags)) {
136 if (rex & REX_P)
137 return nasm_rd_reg8_rex[regval];
138 else
139 return nasm_rd_reg8[regval];
140 }
141 if (!(REG16 & ~regflags))
142 return nasm_rd_reg16[regval];
143 if (!(REG32 & ~regflags))
144 return nasm_rd_reg32[regval];
145 if (!(REG64 & ~regflags))
146 return nasm_rd_reg64[regval];
147 if (!(REG_SREG & ~regflags))
148 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
149 if (!(REG_CREG & ~regflags))
150 return nasm_rd_creg[regval];
151 if (!(REG_DREG & ~regflags))
152 return nasm_rd_dreg[regval];
153 if (!(REG_TREG & ~regflags)) {
154 if (rex & REX_P)
155 return 0; /* TR registers are ill-defined with rex */
156 return nasm_rd_treg[regval];
157 }
158 if (!(FPUREG & ~regflags))
159 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
160 if (!(MMXREG & ~regflags))
161 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
162 if (!(XMMREG & ~regflags))
163 return nasm_rd_xmmreg[regval];
164 if (!(YMMREG & ~regflags))
165 return nasm_rd_ymmreg[regval];
166
167 return 0;
168 }
169
170 /*
171 * Process a DREX suffix
172 */
173 static uint8_t *do_drex(uint8_t *data, insn *ins)
174 {
175 uint8_t drex = *data++;
176 operand *dst = &ins->oprs[ins->drexdst];
177
178 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
179 return NULL; /* OC0 mismatch */
180 ins->rex = (ins->rex & ~7) | (drex & 7);
181
182 dst->segment = SEG_RMREG;
183 dst->basereg = drex >> 4;
184 return data;
185 }
186
187
188 /*
189 * Process an effective address (ModRM) specification.
190 */
191 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
192 int segsize, operand * op, insn *ins)
193 {
194 int mod, rm, scale, index, base;
195 int rex;
196 uint8_t sib = 0;
197
198 mod = (modrm >> 6) & 03;
199 rm = modrm & 07;
200
201 if (mod != 3 && rm == 4 && asize != 16)
202 sib = *data++;
203
204 if (ins->rex & REX_D) {
205 data = do_drex(data, ins);
206 if (!data)
207 return NULL;
208 }
209 rex = ins->rex;
210
211 if (mod == 3) { /* pure register version */
212 op->basereg = rm+(rex & REX_B ? 8 : 0);
213 op->segment |= SEG_RMREG;
214 return data;
215 }
216
217 op->disp_size = 0;
218 op->eaflags = 0;
219
220 if (asize == 16) {
221 /*
222 * <mod> specifies the displacement size (none, byte or
223 * word), and <rm> specifies the register combination.
224 * Exception: mod=0,rm=6 does not specify [BP] as one might
225 * expect, but instead specifies [disp16].
226 */
227 op->indexreg = op->basereg = -1;
228 op->scale = 1; /* always, in 16 bits */
229 switch (rm) {
230 case 0:
231 op->basereg = R_BX;
232 op->indexreg = R_SI;
233 break;
234 case 1:
235 op->basereg = R_BX;
236 op->indexreg = R_DI;
237 break;
238 case 2:
239 op->basereg = R_BP;
240 op->indexreg = R_SI;
241 break;
242 case 3:
243 op->basereg = R_BP;
244 op->indexreg = R_DI;
245 break;
246 case 4:
247 op->basereg = R_SI;
248 break;
249 case 5:
250 op->basereg = R_DI;
251 break;
252 case 6:
253 op->basereg = R_BP;
254 break;
255 case 7:
256 op->basereg = R_BX;
257 break;
258 }
259 if (rm == 6 && mod == 0) { /* special case */
260 op->basereg = -1;
261 if (segsize != 16)
262 op->disp_size = 16;
263 mod = 2; /* fake disp16 */
264 }
265 switch (mod) {
266 case 0:
267 op->segment |= SEG_NODISP;
268 break;
269 case 1:
270 op->segment |= SEG_DISP8;
271 op->offset = (int8_t)*data++;
272 break;
273 case 2:
274 op->segment |= SEG_DISP16;
275 op->offset = *data++;
276 op->offset |= ((unsigned)*data++) << 8;
277 break;
278 }
279 return data;
280 } else {
281 /*
282 * Once again, <mod> specifies displacement size (this time
283 * none, byte or *dword*), while <rm> specifies the base
284 * register. Again, [EBP] is missing, replaced by a pure
285 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
286 * and RIP-relative addressing in 64-bit mode.
287 *
288 * However, rm=4
289 * indicates not a single base register, but instead the
290 * presence of a SIB byte...
291 */
292 int a64 = asize == 64;
293
294 op->indexreg = -1;
295
296 if (a64)
297 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
298 else
299 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
300
301 if (rm == 5 && mod == 0) {
302 if (segsize == 64) {
303 op->eaflags |= EAF_REL;
304 op->segment |= SEG_RELATIVE;
305 mod = 2; /* fake disp32 */
306 }
307
308 if (asize != 64)
309 op->disp_size = asize;
310
311 op->basereg = -1;
312 mod = 2; /* fake disp32 */
313 }
314
315 if (rm == 4) { /* process SIB */
316 scale = (sib >> 6) & 03;
317 index = (sib >> 3) & 07;
318 base = sib & 07;
319
320 op->scale = 1 << scale;
321
322 if (index == 4 && !(rex & REX_X))
323 op->indexreg = -1; /* ESP/RSP cannot be an index */
324 else if (a64)
325 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
326 else
327 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
328
329 if (base == 5 && mod == 0) {
330 op->basereg = -1;
331 mod = 2; /* Fake disp32 */
332 } else if (a64)
333 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
334 else
335 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
336
337 if (segsize == 16)
338 op->disp_size = 32;
339 }
340
341 switch (mod) {
342 case 0:
343 op->segment |= SEG_NODISP;
344 break;
345 case 1:
346 op->segment |= SEG_DISP8;
347 op->offset = gets8(data);
348 data++;
349 break;
350 case 2:
351 op->segment |= SEG_DISP32;
352 op->offset = gets32(data);
353 data += 4;
354 break;
355 }
356 return data;
357 }
358 }
359
360 /*
361 * Determine whether the instruction template in t corresponds to the data
362 * stream in data. Return the number of bytes matched if so.
363 */
364 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
365
366 static int matches(const struct itemplate *t, uint8_t *data,
367 const struct prefix_info *prefix, int segsize, insn *ins)
368 {
369 uint8_t *r = (uint8_t *)(t->code);
370 uint8_t *origdata = data;
371 bool a_used = false, o_used = false;
372 enum prefixes drep = 0;
373 uint8_t lock = prefix->lock;
374 int osize = prefix->osize;
375 int asize = prefix->asize;
376 int i, c;
377 struct operand *opx;
378 int s_field_for = -1; /* No 144/154 series code encountered */
379 bool vex_ok = false;
380 int regmask = (segsize == 64) ? 15 : 7;
381
382 for (i = 0; i < MAX_OPERANDS; i++) {
383 ins->oprs[i].segment = ins->oprs[i].disp_size =
384 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
385 }
386 ins->condition = -1;
387 ins->rex = prefix->rex;
388 memset(ins->prefixes, 0, sizeof ins->prefixes);
389
390 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
391 return false;
392
393 if (prefix->rep == 0xF2)
394 drep = P_REPNE;
395 else if (prefix->rep == 0xF3)
396 drep = P_REP;
397
398 while ((c = *r++) != 0) {
399 opx = &ins->oprs[c & 3];
400
401 switch (c) {
402 case 01:
403 case 02:
404 case 03:
405 case 04:
406 while (c--)
407 if (*r++ != *data++)
408 return false;
409 break;
410
411 case4(010):
412 {
413 int t = *r++, d = *data++;
414 if (d < t || d > t + 7)
415 return false;
416 else {
417 opx->basereg = (d-t)+
418 (ins->rex & REX_B ? 8 : 0);
419 opx->segment |= SEG_RMREG;
420 }
421 break;
422 }
423
424 case4(014):
425 case4(0274):
426 opx->offset = (int8_t)*data++;
427 opx->segment |= SEG_SIGNED;
428 break;
429
430 case4(020):
431 opx->offset = *data++;
432 break;
433
434 case4(024):
435 opx->offset = *data++;
436 break;
437
438 case4(030):
439 opx->offset = getu16(data);
440 data += 2;
441 break;
442
443 case4(034):
444 if (osize == 32) {
445 opx->offset = getu32(data);
446 data += 4;
447 } else {
448 opx->offset = getu16(data);
449 data += 2;
450 }
451 if (segsize != asize)
452 opx->disp_size = asize;
453 break;
454
455 case4(040):
456 case4(0254):
457 opx->offset = getu32(data);
458 data += 4;
459 break;
460
461 case4(044):
462 switch (asize) {
463 case 16:
464 opx->offset = getu16(data);
465 data += 2;
466 if (segsize != 16)
467 opx->disp_size = 16;
468 break;
469 case 32:
470 opx->offset = getu32(data);
471 data += 4;
472 if (segsize == 16)
473 opx->disp_size = 32;
474 break;
475 case 64:
476 opx->offset = getu64(data);
477 opx->disp_size = 64;
478 data += 8;
479 break;
480 }
481 break;
482
483 case4(050):
484 opx->offset = gets8(data++);
485 opx->segment |= SEG_RELATIVE;
486 break;
487
488 case4(054):
489 opx->offset = getu64(data);
490 data += 8;
491 break;
492
493 case4(060):
494 opx->offset = gets16(data);
495 data += 2;
496 opx->segment |= SEG_RELATIVE;
497 opx->segment &= ~SEG_32BIT;
498 break;
499
500 case4(064):
501 opx->segment |= SEG_RELATIVE;
502 if (osize == 16) {
503 opx->offset = gets16(data);
504 data += 2;
505 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
506 } else if (osize == 32) {
507 opx->offset = gets32(data);
508 data += 4;
509 opx->segment &= ~SEG_64BIT;
510 opx->segment |= SEG_32BIT;
511 }
512 if (segsize != osize) {
513 opx->type =
514 (opx->type & ~SIZE_MASK)
515 | ((osize == 16) ? BITS16 : BITS32);
516 }
517 break;
518
519 case4(070):
520 opx->offset = gets32(data);
521 data += 4;
522 opx->segment |= SEG_32BIT | SEG_RELATIVE;
523 break;
524
525 case4(0100):
526 case4(0110):
527 case4(0120):
528 case4(0130):
529 {
530 int modrm = *data++;
531 opx->segment |= SEG_RMREG;
532 data = do_ea(data, modrm, asize, segsize,
533 &ins->oprs[(c >> 3) & 3], ins);
534 if (!data)
535 return false;
536 opx->basereg = ((modrm >> 3)&7)+
537 (ins->rex & REX_R ? 8 : 0);
538 break;
539 }
540
541 case4(0140):
542 if (s_field_for == (c & 3)) {
543 opx->offset = gets8(data);
544 data++;
545 } else {
546 opx->offset = getu16(data);
547 data += 2;
548 }
549 break;
550
551 case4(0144):
552 case4(0154):
553 s_field_for = (*data & 0x02) ? c & 3 : -1;
554 if ((*data++ & ~0x02) != *r++)
555 return false;
556 break;
557
558 case4(0150):
559 if (s_field_for == (c & 3)) {
560 opx->offset = gets8(data);
561 data++;
562 } else {
563 opx->offset = getu32(data);
564 data += 4;
565 }
566 break;
567
568 case4(0160):
569 ins->rex |= REX_D;
570 ins->drexdst = c & 3;
571 break;
572
573 case4(0164):
574 ins->rex |= REX_D|REX_OC;
575 ins->drexdst = c & 3;
576 break;
577
578 case 0171:
579 data = do_drex(data, ins);
580 if (!data)
581 return false;
582 break;
583
584 case 0172:
585 {
586 uint8_t ximm = *data++;
587 c = *r++;
588 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
589 ins->oprs[c >> 3].segment |= SEG_RMREG;
590 ins->oprs[c & 7].offset = ximm & 15;
591 }
592 break;
593
594 case 0173:
595 {
596 uint8_t ximm = *data++;
597 c = *r++;
598
599 if ((c ^ ximm) & 15)
600 return false;
601
602 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
603 ins->oprs[c >> 4].segment |= SEG_RMREG;
604 }
605 break;
606
607 case 0174:
608 {
609 uint8_t ximm = *data++;
610 c = *r++;
611
612 ins->oprs[c].basereg = (ximm >> 4) & regmask;
613 ins->oprs[c].segment |= SEG_RMREG;
614 }
615 break;
616
617 case4(0200):
618 case4(0204):
619 case4(0210):
620 case4(0214):
621 case4(0220):
622 case4(0224):
623 case4(0230):
624 case4(0234):
625 {
626 int modrm = *data++;
627 if (((modrm >> 3) & 07) != (c & 07))
628 return false; /* spare field doesn't match up */
629 data = do_ea(data, modrm, asize, segsize,
630 &ins->oprs[(c >> 3) & 07], ins);
631 if (!data)
632 return false;
633 break;
634 }
635
636 case4(0260):
637 {
638 int vexm = *r++;
639 int vexwlp = *r++;
640 ins->rex |= REX_V;
641 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
642 return false;
643
644 if ((vexm & 0x1f) != prefix->vex_m)
645 return false;
646
647 switch (vexwlp & 030) {
648 case 000:
649 if (prefix->rex & REX_W)
650 return false;
651 break;
652 case 010:
653 if (!(prefix->rex & REX_W))
654 return false;
655 ins->rex &= ~REX_W;
656 break;
657 case 020: /* VEX.W is a don't care */
658 ins->rex &= ~REX_W;
659 break;
660 case 030:
661 break;
662 }
663
664 if ((vexwlp & 007) != prefix->vex_lp)
665 return false;
666
667 opx->segment |= SEG_RMREG;
668 opx->basereg = prefix->vex_v;
669 vex_ok = true;
670 break;
671 }
672
673 case 0270:
674 {
675 int vexm = *r++;
676 int vexwlp = *r++;
677 ins->rex |= REX_V;
678 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
679 return false;
680
681 if ((vexm & 0x1f) != prefix->vex_m)
682 return false;
683
684 switch (vexwlp & 030) {
685 case 000:
686 if (ins->rex & REX_W)
687 return false;
688 break;
689 case 010:
690 if (!(ins->rex & REX_W))
691 return false;
692 break;
693 default:
694 break; /* Need to do anything special here? */
695 }
696
697 if ((vexwlp & 007) != prefix->vex_lp)
698 return false;
699
700 if (prefix->vex_v != 0)
701 return false;
702
703 vex_ok = true;
704 break;
705 }
706
707 case 0310:
708 if (asize != 16)
709 return false;
710 else
711 a_used = true;
712 break;
713
714 case 0311:
715 if (asize == 16)
716 return false;
717 else
718 a_used = true;
719 break;
720
721 case 0312:
722 if (asize != segsize)
723 return false;
724 else
725 a_used = true;
726 break;
727
728 case 0313:
729 if (asize != 64)
730 return false;
731 else
732 a_used = true;
733 break;
734
735 case 0314:
736 if (prefix->rex & REX_B)
737 return false;
738 break;
739
740 case 0315:
741 if (prefix->rex & REX_X)
742 return false;
743 break;
744
745 case 0316:
746 if (prefix->rex & REX_R)
747 return false;
748 break;
749
750 case 0317:
751 if (prefix->rex & REX_W)
752 return false;
753 break;
754
755 case 0320:
756 if (osize != 16)
757 return false;
758 else
759 o_used = true;
760 break;
761
762 case 0321:
763 if (osize != 32)
764 return false;
765 else
766 o_used = true;
767 break;
768
769 case 0322:
770 if (osize != (segsize == 16) ? 16 : 32)
771 return false;
772 else
773 o_used = true;
774 break;
775
776 case 0323:
777 ins->rex |= REX_W; /* 64-bit only instruction */
778 osize = 64;
779 o_used = true;
780 break;
781
782 case 0324:
783 if (!(ins->rex & (REX_P|REX_W)) || osize != 64)
784 return false;
785 o_used = true;
786 break;
787
788 case 0330:
789 {
790 int t = *r++, d = *data++;
791 if (d < t || d > t + 15)
792 return false;
793 else
794 ins->condition = d - t;
795 break;
796 }
797
798 case 0331:
799 if (prefix->rep)
800 return false;
801 break;
802
803 case 0332:
804 if (prefix->rep != 0xF2)
805 return false;
806 drep = 0;
807 break;
808
809 case 0333:
810 if (prefix->rep != 0xF3)
811 return false;
812 drep = 0;
813 break;
814
815 case 0334:
816 if (lock) {
817 ins->rex |= REX_R;
818 lock = 0;
819 }
820 break;
821
822 case 0335:
823 if (drep == P_REP)
824 drep = P_REPE;
825 break;
826
827 case 0336:
828 case 0337:
829 break;
830
831 case 0340:
832 return false;
833
834 case4(0344):
835 ins->oprs[0].basereg = (*data++ >> 3) & 7;
836 break;
837
838 case 0360:
839 if (prefix->osp || prefix->rep)
840 return false;
841 break;
842
843 case 0361:
844 if (!prefix->osp || prefix->rep)
845 return false;
846 o_used = true;
847 break;
848
849 case 0362:
850 if (prefix->osp || prefix->rep != 0xf2)
851 return false;
852 drep = 0;
853 break;
854
855 case 0363:
856 if (prefix->osp || prefix->rep != 0xf3)
857 return false;
858 drep = 0;
859 break;
860
861 case 0364:
862 if (prefix->osp)
863 return false;
864 break;
865
866 case 0365:
867 if (prefix->asp)
868 return false;
869 break;
870
871 case 0366:
872 if (!prefix->osp)
873 return false;
874 o_used = true;
875 break;
876
877 case 0367:
878 if (!prefix->asp)
879 return false;
880 a_used = true;
881 break;
882
883 default:
884 return false; /* Unknown code */
885 }
886 }
887
888 if (!vex_ok && (ins->rex & REX_V))
889 return false;
890
891 /* REX cannot be combined with DREX or VEX */
892 if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
893 return false;
894
895 /*
896 * Check for unused rep or a/o prefixes.
897 */
898 for (i = 0; i < t->operands; i++) {
899 if (ins->oprs[i].segment != SEG_RMREG)
900 a_used = true;
901 }
902
903 if (lock) {
904 if (ins->prefixes[PPS_LREP])
905 return false;
906 ins->prefixes[PPS_LREP] = P_LOCK;
907 }
908 if (drep) {
909 if (ins->prefixes[PPS_LREP])
910 return false;
911 ins->prefixes[PPS_LREP] = drep;
912 }
913 if (!o_used) {
914 if (osize != ((segsize == 16) ? 16 : 32)) {
915 enum prefixes pfx = 0;
916
917 switch (osize) {
918 case 16:
919 pfx = P_O16;
920 break;
921 case 32:
922 pfx = P_O32;
923 break;
924 case 64:
925 pfx = P_O64;
926 break;
927 }
928
929 if (ins->prefixes[PPS_OSIZE])
930 return false;
931 ins->prefixes[PPS_OSIZE] = pfx;
932 }
933 }
934 if (!a_used && asize != segsize) {
935 if (ins->prefixes[PPS_ASIZE])
936 return false;
937 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
938 }
939
940 /* Fix: check for redundant REX prefixes */
941
942 return data - origdata;
943 }
944
945 /* Condition names for disassembly, sorted by x86 code */
946 static const char * const condition_name[16] = {
947 "o", "no", "c", "nc", "z", "nz", "na", "a",
948 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
949 };
950
951 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
952 int32_t offset, int autosync, uint32_t prefer)
953 {
954 const struct itemplate * const *p, * const *best_p;
955 const struct disasm_index *ix;
956 uint8_t *dp;
957 int length, best_length = 0;
958 char *segover;
959 int i, slen, colon, n;
960 uint8_t *origdata;
961 int works;
962 insn tmp_ins, ins;
963 uint32_t goodness, best;
964 int best_pref;
965 struct prefix_info prefix;
966 bool end_prefix;
967
968 memset(&ins, 0, sizeof ins);
969
970 /*
971 * Scan for prefixes.
972 */
973 memset(&prefix, 0, sizeof prefix);
974 prefix.asize = segsize;
975 prefix.osize = (segsize == 64) ? 32 : segsize;
976 segover = NULL;
977 origdata = data;
978
979 ix = itable;
980
981 end_prefix = false;
982 while (!end_prefix) {
983 switch (*data) {
984 case 0xF2:
985 case 0xF3:
986 prefix.rep = *data++;
987 break;
988
989 case 0xF0:
990 prefix.lock = *data++;
991 break;
992
993 case 0x2E:
994 segover = "cs", prefix.seg = *data++;
995 break;
996 case 0x36:
997 segover = "ss", prefix.seg = *data++;
998 break;
999 case 0x3E:
1000 segover = "ds", prefix.seg = *data++;
1001 break;
1002 case 0x26:
1003 segover = "es", prefix.seg = *data++;
1004 break;
1005 case 0x64:
1006 segover = "fs", prefix.seg = *data++;
1007 break;
1008 case 0x65:
1009 segover = "gs", prefix.seg = *data++;
1010 break;
1011
1012 case 0x66:
1013 prefix.osize = (segsize == 16) ? 32 : 16;
1014 prefix.osp = *data++;
1015 break;
1016 case 0x67:
1017 prefix.asize = (segsize == 32) ? 16 : 32;
1018 prefix.asp = *data++;
1019 break;
1020
1021 case 0xC4:
1022 case 0xC5:
1023 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1024 prefix.vex[0] = *data++;
1025 prefix.vex[1] = *data++;
1026
1027 prefix.rex = REX_V;
1028
1029 if (prefix.vex[0] == 0xc4) {
1030 prefix.vex[2] = *data++;
1031 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1032 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1033 prefix.vex_m = prefix.vex[1] & 0x1f;
1034 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1035 prefix.vex_lp = prefix.vex[2] & 7;
1036 } else {
1037 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1038 prefix.vex_m = 1;
1039 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1040 prefix.vex_lp = prefix.vex[1] & 7;
1041 }
1042
1043 ix = itable_VEX[prefix.vex_m][prefix.vex_lp];
1044 }
1045 end_prefix = true;
1046 break;
1047
1048 case REX_P + 0x0:
1049 case REX_P + 0x1:
1050 case REX_P + 0x2:
1051 case REX_P + 0x3:
1052 case REX_P + 0x4:
1053 case REX_P + 0x5:
1054 case REX_P + 0x6:
1055 case REX_P + 0x7:
1056 case REX_P + 0x8:
1057 case REX_P + 0x9:
1058 case REX_P + 0xA:
1059 case REX_P + 0xB:
1060 case REX_P + 0xC:
1061 case REX_P + 0xD:
1062 case REX_P + 0xE:
1063 case REX_P + 0xF:
1064 if (segsize == 64) {
1065 prefix.rex = *data++;
1066 if (prefix.rex & REX_W)
1067 prefix.osize = 64;
1068 }
1069 end_prefix = true;
1070 break;
1071
1072 default:
1073 end_prefix = true;
1074 break;
1075 }
1076 }
1077
1078 best = -1; /* Worst possible */
1079 best_p = NULL;
1080 best_pref = INT_MAX;
1081
1082 if (!ix)
1083 return 0; /* No instruction table at all... */
1084
1085 dp = data;
1086 ix += *dp++;
1087 while (ix->n == -1) {
1088 ix = (const struct disasm_index *)ix->p + *dp++;
1089 }
1090
1091 p = (const struct itemplate * const *)ix->p;
1092 for (n = ix->n; n; n--, p++) {
1093 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1094 works = true;
1095 /*
1096 * Final check to make sure the types of r/m match up.
1097 * XXX: Need to make sure this is actually correct.
1098 */
1099 for (i = 0; i < (*p)->operands; i++) {
1100 if (!((*p)->opd[i] & SAME_AS) &&
1101 (
1102 /* If it's a mem-only EA but we have a
1103 register, die. */
1104 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1105 !(MEMORY & ~(*p)->opd[i])) ||
1106 /* If it's a reg-only EA but we have a memory
1107 ref, die. */
1108 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1109 !(REG_EA & ~(*p)->opd[i]) &&
1110 !((*p)->opd[i] & REG_SMASK)) ||
1111 /* Register type mismatch (eg FS vs REG_DESS):
1112 die. */
1113 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1114 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1115 !whichreg((*p)->opd[i],
1116 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1117 )) {
1118 works = false;
1119 break;
1120 }
1121 }
1122
1123 /*
1124 * Note: we always prefer instructions which incorporate
1125 * prefixes in the instructions themselves. This is to allow
1126 * e.g. PAUSE to be preferred to REP NOP, and deal with
1127 * MMX/SSE instructions where prefixes are used to select
1128 * between MMX and SSE register sets or outright opcode
1129 * selection.
1130 */
1131 if (works) {
1132 int i, nprefix;
1133 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1134 nprefix = 0;
1135 for (i = 0; i < MAXPREFIX; i++)
1136 if (tmp_ins.prefixes[i])
1137 nprefix++;
1138 if (nprefix < best_pref ||
1139 (nprefix == best_pref && goodness < best)) {
1140 /* This is the best one found so far */
1141 best = goodness;
1142 best_p = p;
1143 best_pref = nprefix;
1144 best_length = length;
1145 ins = tmp_ins;
1146 }
1147 }
1148 }
1149 }
1150
1151 if (!best_p)
1152 return 0; /* no instruction was matched */
1153
1154 /* Pick the best match */
1155 p = best_p;
1156 length = best_length;
1157
1158 slen = 0;
1159
1160 /* TODO: snprintf returns the value that the string would have if
1161 * the buffer were long enough, and not the actual length of
1162 * the returned string, so each instance of using the return
1163 * value of snprintf should actually be checked to assure that
1164 * the return value is "sane." Maybe a macro wrapper could
1165 * be used for that purpose.
1166 */
1167 for (i = 0; i < MAXPREFIX; i++)
1168 switch (ins.prefixes[i]) {
1169 case P_LOCK:
1170 slen += snprintf(output + slen, outbufsize - slen, "lock ");
1171 break;
1172 case P_REP:
1173 slen += snprintf(output + slen, outbufsize - slen, "rep ");
1174 break;
1175 case P_REPE:
1176 slen += snprintf(output + slen, outbufsize - slen, "repe ");
1177 break;
1178 case P_REPNE:
1179 slen += snprintf(output + slen, outbufsize - slen, "repne ");
1180 break;
1181 case P_A16:
1182 slen += snprintf(output + slen, outbufsize - slen, "a16 ");
1183 break;
1184 case P_A32:
1185 slen += snprintf(output + slen, outbufsize - slen, "a32 ");
1186 break;
1187 case P_A64:
1188 slen += snprintf(output + slen, outbufsize - slen, "a64 ");
1189 break;
1190 case P_O16:
1191 slen += snprintf(output + slen, outbufsize - slen, "o16 ");
1192 break;
1193 case P_O32:
1194 slen += snprintf(output + slen, outbufsize - slen, "o32 ");
1195 break;
1196 case P_O64:
1197 slen += snprintf(output + slen, outbufsize - slen, "o64 ");
1198 break;
1199 default:
1200 break;
1201 }
1202
1203 i = (*p)->opcode;
1204 if (i >= FIRST_COND_OPCODE)
1205 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1206 nasm_insn_names[i], condition_name[ins.condition]);
1207 else
1208 slen += snprintf(output + slen, outbufsize - slen, "%s",
1209 nasm_insn_names[i]);
1210
1211 colon = false;
1212 length += data - origdata; /* fix up for prefixes */
1213 for (i = 0; i < (*p)->operands; i++) {
1214 opflags_t t = (*p)->opd[i];
1215 const operand *o = &ins.oprs[i];
1216 int64_t offs;
1217
1218 if (t & SAME_AS) {
1219 o = &ins.oprs[t & ~SAME_AS];
1220 t = (*p)->opd[t & ~SAME_AS];
1221 }
1222
1223 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1224
1225 offs = o->offset;
1226 if (o->segment & SEG_RELATIVE) {
1227 offs += offset + length;
1228 /*
1229 * sort out wraparound
1230 */
1231 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1232 offs &= 0xffff;
1233 else if (segsize != 64)
1234 offs &= 0xffffffff;
1235
1236 /*
1237 * add sync marker, if autosync is on
1238 */
1239 if (autosync)
1240 add_sync(offs, 0L);
1241 }
1242
1243 if (t & COLON)
1244 colon = true;
1245 else
1246 colon = false;
1247
1248 if ((t & (REGISTER | FPUREG)) ||
1249 (o->segment & SEG_RMREG)) {
1250 enum reg_enum reg;
1251 reg = whichreg(t, o->basereg, ins.rex);
1252 if (t & TO)
1253 slen += snprintf(output + slen, outbufsize - slen, "to ");
1254 slen += snprintf(output + slen, outbufsize - slen, "%s",
1255 nasm_reg_names[reg-EXPR_REG_START]);
1256 } else if (!(UNITY & ~t)) {
1257 output[slen++] = '1';
1258 } else if (t & IMMEDIATE) {
1259 if (t & BITS8) {
1260 slen +=
1261 snprintf(output + slen, outbufsize - slen, "byte ");
1262 if (o->segment & SEG_SIGNED) {
1263 if (offs < 0) {
1264 offs *= -1;
1265 output[slen++] = '-';
1266 } else
1267 output[slen++] = '+';
1268 }
1269 } else if (t & BITS16) {
1270 slen +=
1271 snprintf(output + slen, outbufsize - slen, "word ");
1272 } else if (t & BITS32) {
1273 slen +=
1274 snprintf(output + slen, outbufsize - slen, "dword ");
1275 } else if (t & BITS64) {
1276 slen +=
1277 snprintf(output + slen, outbufsize - slen, "qword ");
1278 } else if (t & NEAR) {
1279 slen +=
1280 snprintf(output + slen, outbufsize - slen, "near ");
1281 } else if (t & SHORT) {
1282 slen +=
1283 snprintf(output + slen, outbufsize - slen, "short ");
1284 }
1285 slen +=
1286 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1287 offs);
1288 } else if (!(MEM_OFFS & ~t)) {
1289 slen +=
1290 snprintf(output + slen, outbufsize - slen,
1291 "[%s%s%s0x%"PRIx64"]",
1292 (segover ? segover : ""),
1293 (segover ? ":" : ""),
1294 (o->disp_size == 64 ? "qword " :
1295 o->disp_size == 32 ? "dword " :
1296 o->disp_size == 16 ? "word " : ""), offs);
1297 segover = NULL;
1298 } else if (!(REGMEM & ~t)) {
1299 int started = false;
1300 if (t & BITS8)
1301 slen +=
1302 snprintf(output + slen, outbufsize - slen, "byte ");
1303 if (t & BITS16)
1304 slen +=
1305 snprintf(output + slen, outbufsize - slen, "word ");
1306 if (t & BITS32)
1307 slen +=
1308 snprintf(output + slen, outbufsize - slen, "dword ");
1309 if (t & BITS64)
1310 slen +=
1311 snprintf(output + slen, outbufsize - slen, "qword ");
1312 if (t & BITS80)
1313 slen +=
1314 snprintf(output + slen, outbufsize - slen, "tword ");
1315 if (t & BITS128)
1316 slen +=
1317 snprintf(output + slen, outbufsize - slen, "oword ");
1318 if (t & BITS256)
1319 slen +=
1320 snprintf(output + slen, outbufsize - slen, "yword ");
1321 if (t & FAR)
1322 slen += snprintf(output + slen, outbufsize - slen, "far ");
1323 if (t & NEAR)
1324 slen +=
1325 snprintf(output + slen, outbufsize - slen, "near ");
1326 output[slen++] = '[';
1327 if (o->disp_size)
1328 slen += snprintf(output + slen, outbufsize - slen, "%s",
1329 (o->disp_size == 64 ? "qword " :
1330 o->disp_size == 32 ? "dword " :
1331 o->disp_size == 16 ? "word " :
1332 ""));
1333 if (o->eaflags & EAF_REL)
1334 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1335 if (segover) {
1336 slen +=
1337 snprintf(output + slen, outbufsize - slen, "%s:",
1338 segover);
1339 segover = NULL;
1340 }
1341 if (o->basereg != -1) {
1342 slen += snprintf(output + slen, outbufsize - slen, "%s",
1343 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1344 started = true;
1345 }
1346 if (o->indexreg != -1) {
1347 if (started)
1348 output[slen++] = '+';
1349 slen += snprintf(output + slen, outbufsize - slen, "%s",
1350 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1351 if (o->scale > 1)
1352 slen +=
1353 snprintf(output + slen, outbufsize - slen, "*%d",
1354 o->scale);
1355 started = true;
1356 }
1357
1358
1359 if (o->segment & SEG_DISP8) {
1360 const char *prefix;
1361 uint8_t offset = offs;
1362 if ((int8_t)offset < 0) {
1363 prefix = "-";
1364 offset = -offset;
1365 } else {
1366 prefix = "+";
1367 }
1368 slen +=
1369 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1370 prefix, offset);
1371 } else if (o->segment & SEG_DISP16) {
1372 const char *prefix;
1373 uint16_t offset = offs;
1374 if ((int16_t)offset < 0 && started) {
1375 offset = -offset;
1376 prefix = "-";
1377 } else {
1378 prefix = started ? "+" : "";
1379 }
1380 slen +=
1381 snprintf(output + slen, outbufsize - slen,
1382 "%s0x%"PRIx16"", prefix, offset);
1383 } else if (o->segment & SEG_DISP32) {
1384 if (prefix.asize == 64) {
1385 const char *prefix;
1386 uint64_t offset = (int64_t)(int32_t)offs;
1387 if ((int32_t)offs < 0 && started) {
1388 offset = -offset;
1389 prefix = "-";
1390 } else {
1391 prefix = started ? "+" : "";
1392 }
1393 slen +=
1394 snprintf(output + slen, outbufsize - slen,
1395 "%s0x%"PRIx64"", prefix, offset);
1396 } else {
1397 const char *prefix;
1398 uint32_t offset = offs;
1399 if ((int32_t) offset < 0 && started) {
1400 offset = -offset;
1401 prefix = "-";
1402 } else {
1403 prefix = started ? "+" : "";
1404 }
1405 slen +=
1406 snprintf(output + slen, outbufsize - slen,
1407 "%s0x%"PRIx32"", prefix, offset);
1408 }
1409 }
1410 output[slen++] = ']';
1411 } else {
1412 slen +=
1413 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1414 i);
1415 }
1416 }
1417 output[slen] = '\0';
1418 if (segover) { /* unused segment override */
1419 char *p = output;
1420 int count = slen + 1;
1421 while (count--)
1422 p[count + 3] = p[count];
1423 strncpy(output, segover, 2);
1424 output[2] = ' ';
1425 }
1426 return length;
1427 }
1428
1429 int32_t eatbyte(uint8_t *data, char *output, int outbufsize)
1430 {
1431 snprintf(output, outbufsize, "db 0x%02X", *data);
1432 return 1;
1433 }
The Netwide Assembler