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First cut at AVX machinery.
[nasm.git] / assemble.c
blob0c3f5f1b8b3b9e8142d651ce782c7680904b30a7
1 /* assemble.c code generation for the Netwide Assembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
7 *
8 * the actual codes (C syntax, i.e. octal):
9 * \0 - terminates the code. (Unless it's a literal of course.)
10 * \1, \2, \3 - that many literal bytes follow in the code stream
11 * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
12 * (POP is never used for CS) depending on operand 0
13 * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
14 * on operand 0
15 * \10..\13 - a literal byte follows in the code stream, to be added
16 * to the register value of operand 0..3
17 * \14..\17 - a signed byte immediate operand, from operand 0..3
18 * \20..\23 - a byte immediate operand, from operand 0..3
19 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
20 * \30..\33 - a word immediate operand, from operand 0..3
21 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
22 * assembly mode or the operand-size override on the operand
23 * \40..\43 - a long immediate operand, from operand 0..3
24 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
25 * depending on the address size of the instruction.
26 * \50..\53 - a byte relative operand, from operand 0..3
27 * \54..\57 - a qword immediate operand, from operand 0..3
28 * \60..\63 - a word relative operand, from operand 0..3
29 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
30 * assembly mode or the operand-size override on the operand
31 * \70..\73 - a long relative operand, from operand 0..3
32 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
33 * \1ab - a ModRM, calculated on EA in operand a, with the spare
34 * field the register value of operand b.
35 * \140..\143 - an immediate word or signed byte for operand 0..3
36 * \144..\147 - or 2 (s-field) into opcode byte if operand 0..3
37 * is a signed byte rather than a word. Opcode byte follows.
38 * \150..\153 - an immediate dword or signed byte for operand 0..3
39 * \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
40 * is a signed byte rather than a dword. Opcode byte follows.
41 * \160..\163 - this instruction uses DREX rather than REX, with the
42 * OC0 field set to 0, and the dest field taken from
43 * operand 0..3.
44 * \164..\167 - this instruction uses DREX rather than REX, with the
45 * OC0 field set to 1, and the dest field taken from
46 * operand 0..3.
47 * \170 - encodes the literal byte 0. (Some compilers don't take
48 * kindly to a zero byte in the _middle_ of a compile time
49 * string constant, so I had to put this hack in.)
50 * \171 - placement of DREX suffix in the absence of an EA
51 * \172\ab - the register number from operand a in bits 7..4, with
52 * the 4-bit immediate from operand b in bits 0..3.
53 * \2ab - a ModRM, calculated on EA in operand a, with the spare
54 * field equal to digit b.
55 * \250..\253 - same as \150..\153, except warn if the 64-bit operand
56 * is not equal to the truncated and sign-extended 32-bit
57 * operand; used for 32-bit immediates in 64-bit mode.
58 * \260..\263 - this instruction uses VEX rather than REX, with the
59 * V field taken from operand 0..3.
60 * \270 - this instruction uses VEX rather than REX, with the
61 * V field set to 1111b.
62 *
63 * VEX prefixes are followed by the sequence:
64 * \1mm\1wp where mm is the M field; and wp is:
65 * 01 0ww lpp
66 * ww = 0 for W = 0
67 * ww = 1 for W = 1
68 * ww = 2 for W used as REX.W
69 *
70 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
71 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
72 * \312 - (disassembler only) marker on LOOP, LOOPxx instructions.
73 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
74 * \314 - (disassembler only) invalid with REX.B
75 * \315 - (disassembler only) invalid with REX.X
76 * \316 - (disassembler only) invalid with REX.R
77 * \317 - (disassembler only) invalid with REX.W
78 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
79 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
80 * \322 - indicates that this instruction is only valid when the
81 * operand size is the default (instruction to disassembler,
82 * generates no code in the assembler)
83 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
84 * \324 - indicates 64-bit operand size requiring REX prefix.
85 * \330 - a literal byte follows in the code stream, to be added
86 * to the condition code value of the instruction.
87 * \331 - instruction not valid with REP prefix. Hint for
88 * disassembler only; for SSE instructions.
89 * \332 - REP prefix (0xF2 byte) used as opcode extension.
90 * \333 - REP prefix (0xF3 byte) used as opcode extension.
91 * \334 - LOCK prefix used instead of REX.R
92 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
93 * \340 - reserve <operand 0> bytes of uninitialized storage.
94 * Operand 0 had better be a segmentless constant.
95 * \364 - operand-size prefix (0x66) not permitted
96 * \365 - address-size prefix (0x67) not permitted
97 * \366 - operand-size prefix (0x66) used as opcode extension
98 * \367 - address-size prefix (0x67) used as opcode extension
99 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
100 * 370 is used for Jcc, 371 is used for JMP.
101 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
102 * used for conditional jump over longer jump
103 */
104
105 #include "compiler.h"
106
107 #include <stdio.h>
108 #include <string.h>
109 #include <inttypes.h>
110
111 #include "nasm.h"
112 #include "nasmlib.h"
113 #include "assemble.h"
114 #include "insns.h"
115 #include "preproc.h"
116 #include "regflags.c"
117 #include "regvals.c"
118
119 typedef struct {
120 int sib_present; /* is a SIB byte necessary? */
121 int bytes; /* # of bytes of offset needed */
122 int size; /* lazy - this is sib+bytes+1 */
123 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
124 } ea;
125
126 static uint32_t cpu; /* cpu level received from nasm.c */
127 static efunc errfunc;
128 static struct ofmt *outfmt;
129 static ListGen *list;
130
131 static int64_t calcsize(int32_t, int64_t, int, insn *, const char *);
132 static void gencode(int32_t, int64_t, int, insn *, const char *, int64_t);
133 static int matches(const struct itemplate *, insn *, int bits);
134 static int32_t regflag(const operand *);
135 static int32_t regval(const operand *);
136 static int rexflags(int, int32_t, int);
137 static int op_rexflags(const operand *, int);
138 static ea *process_ea(operand *, ea *, int, int, int, int32_t, int);
139 static void add_asp(insn *, int);
140
141 static int has_prefix(insn * ins, enum prefix_pos pos, enum prefixes prefix)
142 {
143 return ins->prefixes[pos] == prefix;
144 }
145
146 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
147 {
148 if (ins->prefixes[pos])
149 errfunc(ERR_NONFATAL, "invalid %s prefix",
150 prefix_name(ins->prefixes[pos]));
151 }
152
153 static const char *size_name(int size)
154 {
155 switch (size) {
156 case 1:
157 return "byte";
158 case 2:
159 return "word";
160 case 4:
161 return "dword";
162 case 8:
163 return "qword";
164 case 10:
165 return "tword";
166 case 16:
167 return "oword";
168 default:
169 return "???";
170 }
171 }
172
173 static void warn_overflow(int size, int64_t data)
174 {
175 if (size < 8) {
176 int64_t lim = ((int64_t)1 << (size*8))-1;
177
178 if (data < ~lim || data > lim)
179 errfunc(ERR_WARNING | ERR_WARN_NOV,
180 "%s data exceeds bounds", size_name(size));
181 }
182 }
183 /*
184 * This routine wrappers the real output format's output routine,
185 * in order to pass a copy of the data off to the listing file
186 * generator at the same time.
187 */
188 static void out(int64_t offset, int32_t segto, const void *data,
189 enum out_type type, uint64_t size,
190 int32_t segment, int32_t wrt)
191 {
192 static int32_t lineno = 0; /* static!!! */
193 static char *lnfname = NULL;
194 uint8_t p[8];
195
196 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
197 /*
198 * This is a non-relocated address, and we're going to
199 * convert it into RAWDATA format.
200 */
201 uint8_t *q = p;
202
203 if (size > 8) {
204 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
205 return;
206 }
207
208 WRITEADDR(q, *(int64_t *)data, size);
209 data = p;
210 type = OUT_RAWDATA;
211 }
212
213 list->output(offset, data, type, size);
214
215 /*
216 * this call to src_get determines when we call the
217 * debug-format-specific "linenum" function
218 * it updates lineno and lnfname to the current values
219 * returning 0 if "same as last time", -2 if lnfname
220 * changed, and the amount by which lineno changed,
221 * if it did. thus, these variables must be static
222 */
223
224 if (src_get(&lineno, &lnfname)) {
225 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
226 }
227
228 outfmt->output(segto, data, type, size, segment, wrt);
229 }
230
231 static int jmp_match(int32_t segment, int64_t offset, int bits,
232 insn * ins, const char *code)
233 {
234 int64_t isize;
235 uint8_t c = code[0];
236
237 if (c != 0370 && c != 0371)
238 return 0;
239 if (ins->oprs[0].opflags & OPFLAG_FORWARD) {
240 if ((optimizing < 0 || (ins->oprs[0].type & STRICT))
241 && c == 0370)
242 return 1;
243 else
244 return (pass0 == 0); /* match a forward reference */
245 }
246 isize = calcsize(segment, offset, bits, ins, code);
247 if (ins->oprs[0].segment != segment)
248 return 0;
249 isize = ins->oprs[0].offset - offset - isize; /* isize is now the delta */
250 if (isize >= -128L && isize <= 127L)
251 return 1; /* it is byte size */
252
253 return 0;
254 }
255
256 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
257 insn * instruction, struct ofmt *output, efunc error,
258 ListGen * listgen)
259 {
260 const struct itemplate *temp;
261 int j;
262 int size_prob;
263 int64_t insn_end;
264 int32_t itimes;
265 int64_t start = offset;
266 int64_t wsize = 0; /* size for DB etc. */
267
268 errfunc = error; /* to pass to other functions */
269 cpu = cp;
270 outfmt = output; /* likewise */
271 list = listgen; /* and again */
272
273 switch (instruction->opcode) {
274 case -1:
275 return 0;
276 case I_DB:
277 wsize = 1;
278 break;
279 case I_DW:
280 wsize = 2;
281 break;
282 case I_DD:
283 wsize = 4;
284 break;
285 case I_DQ:
286 wsize = 8;
287 break;
288 case I_DT:
289 wsize = 10;
290 break;
291 case I_DO:
292 wsize = 16;
293 break;
294 default:
295 break;
296 }
297
298 if (wsize) {
299 extop *e;
300 int32_t t = instruction->times;
301 if (t < 0)
302 errfunc(ERR_PANIC,
303 "instruction->times < 0 (%ld) in assemble()", t);
304
305 while (t--) { /* repeat TIMES times */
306 for (e = instruction->eops; e; e = e->next) {
307 if (e->type == EOT_DB_NUMBER) {
308 if (wsize == 1) {
309 if (e->segment != NO_SEG)
310 errfunc(ERR_NONFATAL,
311 "one-byte relocation attempted");
312 else {
313 uint8_t out_byte = e->offset;
314 out(offset, segment, &out_byte,
315 OUT_RAWDATA, 1, NO_SEG, NO_SEG);
316 }
317 } else if (wsize > 8) {
318 errfunc(ERR_NONFATAL, "integer supplied to a DT or DO"
319 " instruction");
320 } else
321 out(offset, segment, &e->offset,
322 OUT_ADDRESS, wsize, e->segment, e->wrt);
323 offset += wsize;
324 } else if (e->type == EOT_DB_STRING) {
325 int align;
326
327 out(offset, segment, e->stringval,
328 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
329 align = e->stringlen % wsize;
330
331 if (align) {
332 align = wsize - align;
333 out(offset, segment,
334 "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0",
335 OUT_RAWDATA, align, NO_SEG, NO_SEG);
336 }
337 offset += e->stringlen + align;
338 }
339 }
340 if (t > 0 && t == instruction->times - 1) {
341 /*
342 * Dummy call to list->output to give the offset to the
343 * listing module.
344 */
345 list->output(offset, NULL, OUT_RAWDATA, 0);
346 list->uplevel(LIST_TIMES);
347 }
348 }
349 if (instruction->times > 1)
350 list->downlevel(LIST_TIMES);
351 return offset - start;
352 }
353
354 if (instruction->opcode == I_INCBIN) {
355 static char fname[FILENAME_MAX];
356 FILE *fp;
357 int32_t len;
358 char *prefix = "", *combine;
359 char **pPrevPath = NULL;
360
361 len = FILENAME_MAX - 1;
362 if (len > instruction->eops->stringlen)
363 len = instruction->eops->stringlen;
364 strncpy(fname, instruction->eops->stringval, len);
365 fname[len] = '\0';
366
367 while (1) { /* added by alexfru: 'incbin' uses include paths */
368 combine = nasm_malloc(strlen(prefix) + len + 1);
369 strcpy(combine, prefix);
370 strcat(combine, fname);
371
372 if ((fp = fopen(combine, "rb")) != NULL) {
373 nasm_free(combine);
374 break;
375 }
376
377 nasm_free(combine);
378 pPrevPath = pp_get_include_path_ptr(pPrevPath);
379 if (pPrevPath == NULL)
380 break;
381 prefix = *pPrevPath;
382 }
383
384 if (fp == NULL)
385 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
386 fname);
387 else if (fseek(fp, 0L, SEEK_END) < 0)
388 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
389 fname);
390 else {
391 static char buf[2048];
392 int32_t t = instruction->times;
393 int32_t base = 0;
394
395 len = ftell(fp);
396 if (instruction->eops->next) {
397 base = instruction->eops->next->offset;
398 len -= base;
399 if (instruction->eops->next->next &&
400 len > instruction->eops->next->next->offset)
401 len = instruction->eops->next->next->offset;
402 }
403 /*
404 * Dummy call to list->output to give the offset to the
405 * listing module.
406 */
407 list->output(offset, NULL, OUT_RAWDATA, 0);
408 list->uplevel(LIST_INCBIN);
409 while (t--) {
410 int32_t l;
411
412 fseek(fp, base, SEEK_SET);
413 l = len;
414 while (l > 0) {
415 int32_t m =
416 fread(buf, 1, (l > (int32_t) sizeof(buf) ? (int32_t) sizeof(buf) : l),
417 fp);
418 if (!m) {
419 /*
420 * This shouldn't happen unless the file
421 * actually changes while we are reading
422 * it.
423 */
424 error(ERR_NONFATAL,
425 "`incbin': unexpected EOF while"
426 " reading file `%s'", fname);
427 t = 0; /* Try to exit cleanly */
428 break;
429 }
430 out(offset, segment, buf, OUT_RAWDATA, m,
431 NO_SEG, NO_SEG);
432 l -= m;
433 }
434 }
435 list->downlevel(LIST_INCBIN);
436 if (instruction->times > 1) {
437 /*
438 * Dummy call to list->output to give the offset to the
439 * listing module.
440 */
441 list->output(offset, NULL, OUT_RAWDATA, 0);
442 list->uplevel(LIST_TIMES);
443 list->downlevel(LIST_TIMES);
444 }
445 fclose(fp);
446 return instruction->times * len;
447 }
448 return 0; /* if we're here, there's an error */
449 }
450
451 /* Check to see if we need an address-size prefix */
452 add_asp(instruction, bits);
453
454 size_prob = false;
455
456 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++){
457 int m = matches(temp, instruction, bits);
458
459 if (m == 99)
460 m += jmp_match(segment, offset, bits, instruction, temp->code);
461
462 if (m == 100) { /* matches! */
463 const char *codes = temp->code;
464 int64_t insn_size = calcsize(segment, offset, bits,
465 instruction, codes);
466 itimes = instruction->times;
467 if (insn_size < 0) /* shouldn't be, on pass two */
468 error(ERR_PANIC, "errors made it through from pass one");
469 else
470 while (itimes--) {
471 for (j = 0; j < MAXPREFIX; j++) {
472 uint8_t c = 0;
473 switch (instruction->prefixes[j]) {
474 case P_LOCK:
475 c = 0xF0;
476 break;
477 case P_REPNE:
478 case P_REPNZ:
479 c = 0xF2;
480 break;
481 case P_REPE:
482 case P_REPZ:
483 case P_REP:
484 c = 0xF3;
485 break;
486 case R_CS:
487 if (bits == 64) {
488 error(ERR_WARNING,
489 "cs segment base generated, but will be ignored in 64-bit mode");
490 }
491 c = 0x2E;
492 break;
493 case R_DS:
494 if (bits == 64) {
495 error(ERR_WARNING,
496 "ds segment base generated, but will be ignored in 64-bit mode");
497 }
498 c = 0x3E;
499 break;
500 case R_ES:
501 if (bits == 64) {
502 error(ERR_WARNING,
503 "es segment base generated, but will be ignored in 64-bit mode");
504 }
505 c = 0x26;
506 break;
507 case R_FS:
508 c = 0x64;
509 break;
510 case R_GS:
511 c = 0x65;
512 break;
513 case R_SS:
514 if (bits == 64) {
515 error(ERR_WARNING,
516 "ss segment base generated, but will be ignored in 64-bit mode");
517 }
518 c = 0x36;
519 break;
520 case R_SEGR6:
521 case R_SEGR7:
522 error(ERR_NONFATAL,
523 "segr6 and segr7 cannot be used as prefixes");
524 break;
525 case P_A16:
526 if (bits == 64) {
527 error(ERR_NONFATAL,
528 "16-bit addressing is not supported "
529 "in 64-bit mode");
530 } else if (bits != 16)
531 c = 0x67;
532 break;
533 case P_A32:
534 if (bits != 32)
535 c = 0x67;
536 break;
537 case P_A64:
538 if (bits != 64) {
539 error(ERR_NONFATAL,
540 "64-bit addressing is only supported "
541 "in 64-bit mode");
542 }
543 break;
544 case P_ASP:
545 c = 0x67;
546 break;
547 case P_O16:
548 if (bits != 16)
549 c = 0x66;
550 break;
551 case P_O32:
552 if (bits == 16)
553 c = 0x66;
554 break;
555 case P_O64:
556 /* REX.W */
557 break;
558 case P_OSP:
559 c = 0x66;
560 break;
561 case P_none:
562 break;
563 default:
564 error(ERR_PANIC, "invalid instruction prefix");
565 }
566 if (c != 0) {
567 out(offset, segment, &c, OUT_RAWDATA, 1,
568 NO_SEG, NO_SEG);
569 offset++;
570 }
571 }
572 insn_end = offset + insn_size;
573 gencode(segment, offset, bits, instruction, codes,
574 insn_end);
575 offset += insn_size;
576 if (itimes > 0 && itimes == instruction->times - 1) {
577 /*
578 * Dummy call to list->output to give the offset to the
579 * listing module.
580 */
581 list->output(offset, NULL, OUT_RAWDATA, 0);
582 list->uplevel(LIST_TIMES);
583 }
584 }
585 if (instruction->times > 1)
586 list->downlevel(LIST_TIMES);
587 return offset - start;
588 } else if (m > 0 && m > size_prob) {
589 size_prob = m;
590 }
591 // temp++;
592 }
593
594 if (temp->opcode == -1) { /* didn't match any instruction */
595 switch (size_prob) {
596 case 1:
597 error(ERR_NONFATAL, "operation size not specified");
598 break;
599 case 2:
600 error(ERR_NONFATAL, "mismatch in operand sizes");
601 break;
602 case 3:
603 error(ERR_NONFATAL, "no instruction for this cpu level");
604 break;
605 case 4:
606 error(ERR_NONFATAL, "instruction not supported in 64-bit mode");
607 break;
608 default:
609 error(ERR_NONFATAL,
610 "invalid combination of opcode and operands");
611 break;
612 }
613 }
614 return 0;
615 }
616
617 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
618 insn * instruction, efunc error)
619 {
620 const struct itemplate *temp;
621
622 errfunc = error; /* to pass to other functions */
623 cpu = cp;
624
625 if (instruction->opcode == -1)
626 return 0;
627
628 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
629 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
630 instruction->opcode == I_DT || instruction->opcode == I_DO) {
631 extop *e;
632 int32_t isize, osize, wsize = 0; /* placate gcc */
633
634 isize = 0;
635 switch (instruction->opcode) {
636 case I_DB:
637 wsize = 1;
638 break;
639 case I_DW:
640 wsize = 2;
641 break;
642 case I_DD:
643 wsize = 4;
644 break;
645 case I_DQ:
646 wsize = 8;
647 break;
648 case I_DT:
649 wsize = 10;
650 break;
651 case I_DO:
652 wsize = 16;
653 break;
654 default:
655 break;
656 }
657
658 for (e = instruction->eops; e; e = e->next) {
659 int32_t align;
660
661 osize = 0;
662 if (e->type == EOT_DB_NUMBER)
663 osize = 1;
664 else if (e->type == EOT_DB_STRING)
665 osize = e->stringlen;
666
667 align = (-osize) % wsize;
668 if (align < 0)
669 align += wsize;
670 isize += osize + align;
671 }
672 return isize * instruction->times;
673 }
674
675 if (instruction->opcode == I_INCBIN) {
676 char fname[FILENAME_MAX];
677 FILE *fp;
678 int32_t len;
679 char *prefix = "", *combine;
680 char **pPrevPath = NULL;
681
682 len = FILENAME_MAX - 1;
683 if (len > instruction->eops->stringlen)
684 len = instruction->eops->stringlen;
685 strncpy(fname, instruction->eops->stringval, len);
686 fname[len] = '\0';
687
688 /* added by alexfru: 'incbin' uses include paths */
689 while (1) {
690 combine = nasm_malloc(strlen(prefix) + len + 1);
691 strcpy(combine, prefix);
692 strcat(combine, fname);
693
694 if ((fp = fopen(combine, "rb")) != NULL) {
695 nasm_free(combine);
696 break;
697 }
698
699 nasm_free(combine);
700 pPrevPath = pp_get_include_path_ptr(pPrevPath);
701 if (pPrevPath == NULL)
702 break;
703 prefix = *pPrevPath;
704 }
705
706 if (fp == NULL)
707 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
708 fname);
709 else if (fseek(fp, 0L, SEEK_END) < 0)
710 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
711 fname);
712 else {
713 len = ftell(fp);
714 fclose(fp);
715 if (instruction->eops->next) {
716 len -= instruction->eops->next->offset;
717 if (instruction->eops->next->next &&
718 len > instruction->eops->next->next->offset) {
719 len = instruction->eops->next->next->offset;
720 }
721 }
722 return instruction->times * len;
723 }
724 return 0; /* if we're here, there's an error */
725 }
726
727 /* Check to see if we need an address-size prefix */
728 add_asp(instruction, bits);
729
730 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++) {
731 int m = matches(temp, instruction, bits);
732 if (m == 99)
733 m += jmp_match(segment, offset, bits, instruction, temp->code);
734
735 if (m == 100) {
736 /* we've matched an instruction. */
737 int64_t isize;
738 const char *codes = temp->code;
739 int j;
740
741 isize = calcsize(segment, offset, bits, instruction, codes);
742 if (isize < 0)
743 return -1;
744 for (j = 0; j < MAXPREFIX; j++) {
745 switch (instruction->prefixes[j]) {
746 case P_A16:
747 if (bits != 16)
748 isize++;
749 break;
750 case P_A32:
751 if (bits != 32)
752 isize++;
753 break;
754 case P_O16:
755 if (bits != 16)
756 isize++;
757 break;
758 case P_O32:
759 if (bits == 16)
760 isize++;
761 break;
762 case P_A64:
763 case P_O64:
764 case P_none:
765 break;
766 default:
767 isize++;
768 break;
769 }
770 }
771 return isize * instruction->times;
772 }
773 }
774 return -1; /* didn't match any instruction */
775 }
776
777 static bool possible_sbyte(insn * ins, int op)
778 {
779 return !(ins->forw_ref && ins->oprs[op].opflags) &&
780 optimizing >= 0 &&
781 !(ins->oprs[op].type & STRICT) &&
782 ins->oprs[op].wrt == NO_SEG && ins->oprs[op].segment == NO_SEG;
783 }
784
785 /* check that opn[op] is a signed byte of size 16 or 32 */
786 static bool is_sbyte16(insn * ins, int op)
787 {
788 int16_t v;
789
790 if (!possible_sbyte(ins, op))
791 return false;
792
793 v = ins->oprs[op].offset;
794 return v >= -128 && v <= 127;
795 }
796
797 static bool is_sbyte32(insn * ins, int op)
798 {
799 int32_t v;
800
801 if (!possible_sbyte(ins, op))
802 return false;
803
804 v = ins->oprs[op].offset;
805 return v >= -128 && v <= 127;
806 }
807
808 /* check that opn[op] is a signed byte of size 32; warn if this is not
809 the original value when extended to 64 bits */
810 static bool is_sbyte64(insn * ins, int op)
811 {
812 int64_t v64;
813 int32_t v32;
814
815 /* dead in the water on forward reference or External */
816 if (!possible_sbyte(ins, op))
817 return false;
818
819 v64 = ins->oprs[op].offset;
820 v32 = (int32_t)v64;
821
822 warn_overflow(32, v64);
823
824 return v32 >= -128 && v32 <= 127;
825 }
826 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
827 insn * ins, const char *codes)
828 {
829 int64_t length = 0;
830 uint8_t c;
831 int rex_mask = ~0;
832 struct operand *opx;
833
834 ins->rex = 0; /* Ensure REX is reset */
835
836 if (ins->prefixes[PPS_OSIZE] == P_O64)
837 ins->rex |= REX_W;
838
839 (void)segment; /* Don't warn that this parameter is unused */
840 (void)offset; /* Don't warn that this parameter is unused */
841
842 while (*codes) {
843 c = *codes++;
844 opx = &ins->oprs[c & 3];
845 switch (c) {
846 case 01:
847 case 02:
848 case 03:
849 codes += c, length += c;
850 break;
851 case 04:
852 case 05:
853 case 06:
854 case 07:
855 length++;
856 break;
857 case 010:
858 case 011:
859 case 012:
860 case 013:
861 ins->rex |=
862 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
863 codes++, length++;
864 break;
865 case 014:
866 case 015:
867 case 016:
868 case 017:
869 length++;
870 break;
871 case 020:
872 case 021:
873 case 022:
874 case 023:
875 length++;
876 break;
877 case 024:
878 case 025:
879 case 026:
880 case 027:
881 length++;
882 break;
883 case 030:
884 case 031:
885 case 032:
886 case 033:
887 length += 2;
888 break;
889 case 034:
890 case 035:
891 case 036:
892 case 037:
893 if (opx->type & (BITS16 | BITS32 | BITS64))
894 length += (opx->type & BITS16) ? 2 : 4;
895 else
896 length += (bits == 16) ? 2 : 4;
897 break;
898 case 040:
899 case 041:
900 case 042:
901 case 043:
902 length += 4;
903 break;
904 case 044:
905 case 045:
906 case 046:
907 case 047:
908 length += ins->addr_size >> 3;
909 break;
910 case 050:
911 case 051:
912 case 052:
913 case 053:
914 length++;
915 break;
916 case 054:
917 case 055:
918 case 056:
919 case 057:
920 length += 8; /* MOV reg64/imm */
921 break;
922 case 060:
923 case 061:
924 case 062:
925 case 063:
926 length += 2;
927 break;
928 case 064:
929 case 065:
930 case 066:
931 case 067:
932 if (opx->type & (BITS16 | BITS32 | BITS64))
933 length += (opx->type & BITS16) ? 2 : 4;
934 else
935 length += (bits == 16) ? 2 : 4;
936 break;
937 case 070:
938 case 071:
939 case 072:
940 case 073:
941 length += 4;
942 break;
943 case 074:
944 case 075:
945 case 076:
946 case 077:
947 length += 2;
948 break;
949 case 0140:
950 case 0141:
951 case 0142:
952 case 0143:
953 length += is_sbyte16(ins, c & 3) ? 1 : 2;
954 break;
955 case 0144:
956 case 0145:
957 case 0146:
958 case 0147:
959 codes++;
960 length++;
961 break;
962 case 0150:
963 case 0151:
964 case 0152:
965 case 0153:
966 length += is_sbyte32(ins, c & 3) ? 1 : 4;
967 break;
968 case 0154:
969 case 0155:
970 case 0156:
971 case 0157:
972 codes++;
973 length++;
974 break;
975 case 0160:
976 case 0161:
977 case 0162:
978 case 0163:
979 length++;
980 ins->rex |= REX_D;
981 ins->drexdst = regval(opx);
982 break;
983 case 0164:
984 case 0165:
985 case 0166:
986 case 0167:
987 length++;
988 ins->rex |= REX_D|REX_OC;
989 ins->drexdst = regval(opx);
990 break;
991 case 0170:
992 length++;
993 break;
994 case 0171:
995 break;
996 case 0172:
997 codes++;
998 length++;
999 break;
1000 case 0250:
1001 case 0251:
1002 case 0252:
1003 case 0253:
1004 length += is_sbyte64(ins, c & 3) ? 1 : 4;
1005 break;
1006 case 0260:
1007 case 0261:
1008 case 0262:
1009 case 0263:
1010 length += 2;
1011 ins->rex |= REX_V;
1012 ins->drexdst = regval(opx);
1013 ins->vex_m = *codes++;
1014 ins->vex_wlp = *codes++;
1015 break;
1016 case 0270:
1017 length += 2;
1018 ins->rex |= REX_V;
1019 ins->drexdst = 0;
1020 ins->vex_m = *codes++;
1021 ins->vex_wlp = *codes++;
1022 break;
1023 case 0300:
1024 case 0301:
1025 case 0302:
1026 case 0303:
1027 break;
1028 case 0310:
1029 if (bits == 64)
1030 return -1;
1031 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1032 break;
1033 case 0311:
1034 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1035 break;
1036 case 0312:
1037 break;
1038 case 0313:
1039 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1040 has_prefix(ins, PPS_ASIZE, P_A32))
1041 return -1;
1042 break;
1043 case 0314:
1044 case 0315:
1045 case 0316:
1046 case 0317:
1047 break;
1048 case 0320:
1049 length += (bits != 16);
1050 break;
1051 case 0321:
1052 length += (bits == 16);
1053 break;
1054 case 0322:
1055 break;
1056 case 0323:
1057 rex_mask &= ~REX_W;
1058 break;
1059 case 0324:
1060 ins->rex |= REX_W;
1061 break;
1062 case 0330:
1063 codes++, length++;
1064 break;
1065 case 0331:
1066 break;
1067 case 0332:
1068 case 0333:
1069 length++;
1070 break;
1071 case 0334:
1072 ins->rex |= REX_L;
1073 break;
1074 case 0335:
1075 break;
1076 case 0340:
1077 if (ins->oprs[0].segment != NO_SEG)
1078 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1079 " quantity of BSS space");
1080 else
1081 length += ins->oprs[0].offset;
1082 break;
1083 case 0364:
1084 case 0365:
1085 break;
1086 case 0366:
1087 case 0367:
1088 length++;
1089 break;
1090 case 0370:
1091 case 0371:
1092 case 0372:
1093 break;
1094 case 0373:
1095 length++;
1096 break;
1097 default: /* can't do it by 'case' statements */
1098 if (c >= 0100 && c <= 0277) { /* it's an EA */
1099 ea ea_data;
1100 int rfield;
1101 int32_t rflags;
1102 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1103
1104 if (c <= 0177) {
1105 /* pick rfield from operand b */
1106 rflags = regflag(&ins->oprs[c & 7]);
1107 rfield = regvals[ins->oprs[c & 7].basereg];
1108 } else {
1109 rflags = 0;
1110 rfield = c & 7;
1111 }
1112
1113 if (!process_ea
1114 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1115 ins->addr_size, rfield, rflags, ins->forw_ref)) {
1116 errfunc(ERR_NONFATAL, "invalid effective address");
1117 return -1;
1118 } else {
1119 ins->rex |= ea_data.rex;
1120 length += ea_data.size;
1121 }
1122 } else {
1123 errfunc(ERR_PANIC, "internal instruction table corrupt"
1124 ": instruction code 0x%02X given", c);
1125 }
1126 }
1127 }
1128
1129 ins->rex &= rex_mask;
1130
1131 if (ins->rex & REX_V) {
1132 int bad32 = REX_R|REX_W|REX_X|REX_B;
1133
1134 if (ins->rex & REX_H) {
1135 errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
1136 return -1;
1137 }
1138 switch (ins->vex_wlp & 030) {
1139 case 000:
1140 ins->rex &= ~REX_W;
1141 break;
1142 case 010:
1143 ins->rex |= REX_W;
1144 bad32 &= ~REX_W;
1145 break;
1146 default:
1147 /* Follow REX_W */
1148 break;
1149 }
1150
1151 if (bits != 64 && ((ins->rex & bad32) || ins->drexdst > 7)) {
1152 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1153 return -1;
1154 }
1155 if (ins->vex_m != 1 || (ins->rex & (REX_W|REX_R|REX_B)))
1156 length += 3;
1157 else
1158 length += 2;
1159 } else if (ins->rex & REX_D) {
1160 if (ins->rex & REX_H) {
1161 errfunc(ERR_NONFATAL, "cannot use high register in drex instruction");
1162 return -1;
1163 }
1164 if (bits != 64 && ((ins->rex & (REX_R|REX_W|REX_X|REX_B)) ||
1165 ins->drexdst > 7)) {
1166 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1167 return -1;
1168 }
1169 length++;
1170 } else if (ins->rex & REX_REAL) {
1171 if (ins->rex & REX_H) {
1172 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1173 return -1;
1174 } else if (bits == 64) {
1175 length++;
1176 } else if ((ins->rex & REX_L) &&
1177 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1178 cpu >= IF_X86_64) {
1179 /* LOCK-as-REX.R */
1180 assert_no_prefix(ins, PPS_LREP);
1181 length++;
1182 } else {
1183 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1184 return -1;
1185 }
1186 }
1187
1188 return length;
1189 }
1190
1191 #define EMIT_REX() \
1192 if (!(ins->rex & (REX_D|REX_V)) && (ins->rex & REX_REAL) && (bits == 64)) { \
1193 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1194 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1195 ins->rex = 0; \
1196 offset += 1; \
1197 }
1198
1199 static void gencode(int32_t segment, int64_t offset, int bits,
1200 insn * ins, const char *codes, int64_t insn_end)
1201 {
1202 static char condval[] = { /* conditional opcodes */
1203 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1204 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1205 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1206 };
1207 uint8_t c;
1208 uint8_t bytes[4];
1209 int64_t size;
1210 int64_t data;
1211 struct operand *opx;
1212
1213 while (*codes) {
1214 c = *codes++;
1215 opx = &ins->oprs[c & 3];
1216 switch (c) {
1217 case 01:
1218 case 02:
1219 case 03:
1220 EMIT_REX();
1221 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1222 codes += c;
1223 offset += c;
1224 break;
1225
1226 case 04:
1227 case 06:
1228 switch (ins->oprs[0].basereg) {
1229 case R_CS:
1230 bytes[0] = 0x0E + (c == 0x04 ? 1 : 0);
1231 break;
1232 case R_DS:
1233 bytes[0] = 0x1E + (c == 0x04 ? 1 : 0);
1234 break;
1235 case R_ES:
1236 bytes[0] = 0x06 + (c == 0x04 ? 1 : 0);
1237 break;
1238 case R_SS:
1239 bytes[0] = 0x16 + (c == 0x04 ? 1 : 0);
1240 break;
1241 default:
1242 errfunc(ERR_PANIC,
1243 "bizarre 8086 segment register received");
1244 }
1245 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1246 offset++;
1247 break;
1248
1249 case 05:
1250 case 07:
1251 switch (ins->oprs[0].basereg) {
1252 case R_FS:
1253 bytes[0] = 0xA0 + (c == 0x05 ? 1 : 0);
1254 break;
1255 case R_GS:
1256 bytes[0] = 0xA8 + (c == 0x05 ? 1 : 0);
1257 break;
1258 default:
1259 errfunc(ERR_PANIC,
1260 "bizarre 386 segment register received");
1261 }
1262 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1263 offset++;
1264 break;
1265
1266 case 010:
1267 case 011:
1268 case 012:
1269 case 013:
1270 EMIT_REX();
1271 bytes[0] = *codes++ + ((regval(opx)) & 7);
1272 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1273 offset += 1;
1274 break;
1275
1276 case 014:
1277 case 015:
1278 case 016:
1279 case 017:
1280 /* XXX: warns for legitimate optimizer actions */
1281 if (opx->offset < -128 || opx->offset > 127) {
1282 errfunc(ERR_WARNING | ERR_WARN_NOV,
1283 "signed byte value exceeds bounds");
1284 }
1285
1286 if (opx->segment != NO_SEG) {
1287 data = opx->offset;
1288 out(offset, segment, &data, OUT_ADDRESS, 1,
1289 opx->segment, opx->wrt);
1290 } else {
1291 bytes[0] = opx->offset;
1292 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1293 NO_SEG);
1294 }
1295 offset += 1;
1296 break;
1297
1298 case 020:
1299 case 021:
1300 case 022:
1301 case 023:
1302 if (opx->offset < -256 || opx->offset > 255) {
1303 errfunc(ERR_WARNING | ERR_WARN_NOV,
1304 "byte value exceeds bounds");
1305 }
1306 if (opx->segment != NO_SEG) {
1307 data = opx->offset;
1308 out(offset, segment, &data, OUT_ADDRESS, 1,
1309 opx->segment, opx->wrt);
1310 } else {
1311 bytes[0] = opx->offset;
1312 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1313 NO_SEG);
1314 }
1315 offset += 1;
1316 break;
1317
1318 case 024:
1319 case 025:
1320 case 026:
1321 case 027:
1322 if (opx->offset < 0 || opx->offset > 255)
1323 errfunc(ERR_WARNING | ERR_WARN_NOV,
1324 "unsigned byte value exceeds bounds");
1325 if (opx->segment != NO_SEG) {
1326 data = opx->offset;
1327 out(offset, segment, &data, OUT_ADDRESS, 1,
1328 opx->segment, opx->wrt);
1329 } else {
1330 bytes[0] = opx->offset;
1331 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1332 NO_SEG);
1333 }
1334 offset += 1;
1335 break;
1336
1337 case 030:
1338 case 031:
1339 case 032:
1340 case 033:
1341 data = opx->offset;
1342 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1343 warn_overflow(2, data);
1344 out(offset, segment, &data, OUT_ADDRESS, 2,
1345 opx->segment, opx->wrt);
1346 offset += 2;
1347 break;
1348
1349 case 034:
1350 case 035:
1351 case 036:
1352 case 037:
1353 if (opx->type & (BITS16 | BITS32))
1354 size = (opx->type & BITS16) ? 2 : 4;
1355 else
1356 size = (bits == 16) ? 2 : 4;
1357 data = opx->offset;
1358 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1359 warn_overflow(size, data);
1360 out(offset, segment, &data, OUT_ADDRESS, size,
1361 opx->segment, opx->wrt);
1362 offset += size;
1363 break;
1364
1365 case 040:
1366 case 041:
1367 case 042:
1368 case 043:
1369 data = opx->offset;
1370 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1371 warn_overflow(4, data);
1372 out(offset, segment, &data, OUT_ADDRESS, 4,
1373 opx->segment, opx->wrt);
1374 offset += 4;
1375 break;
1376
1377 case 044:
1378 case 045:
1379 case 046:
1380 case 047:
1381 data = opx->offset;
1382 size = ins->addr_size >> 3;
1383 if (opx->segment == NO_SEG &&
1384 opx->wrt == NO_SEG)
1385 warn_overflow(size, data);
1386 out(offset, segment, &data, OUT_ADDRESS, size,
1387 opx->segment, opx->wrt);
1388 offset += size;
1389 break;
1390
1391 case 050:
1392 case 051:
1393 case 052:
1394 case 053:
1395 if (opx->segment != segment)
1396 errfunc(ERR_NONFATAL,
1397 "short relative jump outside segment");
1398 data = opx->offset - insn_end;
1399 if (data > 127 || data < -128)
1400 errfunc(ERR_NONFATAL, "short jump is out of range");
1401 bytes[0] = data;
1402 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1403 offset += 1;
1404 break;
1405
1406 case 054:
1407 case 055:
1408 case 056:
1409 case 057:
1410 data = (int64_t)opx->offset;
1411 out(offset, segment, &data, OUT_ADDRESS, 8,
1412 opx->segment, opx->wrt);
1413 offset += 8;
1414 break;
1415
1416 case 060:
1417 case 061:
1418 case 062:
1419 case 063:
1420 if (opx->segment != segment) {
1421 data = opx->offset;
1422 out(offset, segment, &data,
1423 OUT_REL2ADR, insn_end - offset,
1424 opx->segment, opx->wrt);
1425 } else {
1426 data = opx->offset - insn_end;
1427 out(offset, segment, &data,
1428 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1429 }
1430 offset += 2;
1431 break;
1432
1433 case 064:
1434 case 065:
1435 case 066:
1436 case 067:
1437 if (opx->type & (BITS16 | BITS32 | BITS64))
1438 size = (opx->type & BITS16) ? 2 : 4;
1439 else
1440 size = (bits == 16) ? 2 : 4;
1441 if (opx->segment != segment) {
1442 data = opx->offset;
1443 out(offset, segment, &data,
1444 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1445 insn_end - offset, opx->segment, opx->wrt);
1446 } else {
1447 data = opx->offset - insn_end;
1448 out(offset, segment, &data,
1449 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1450 }
1451 offset += size;
1452 break;
1453
1454 case 070:
1455 case 071:
1456 case 072:
1457 case 073:
1458 if (opx->segment != segment) {
1459 data = opx->offset;
1460 out(offset, segment, &data,
1461 OUT_REL4ADR, insn_end - offset,
1462 opx->segment, opx->wrt);
1463 } else {
1464 data = opx->offset - insn_end;
1465 out(offset, segment, &data,
1466 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1467 }
1468 offset += 4;
1469 break;
1470
1471 case 074:
1472 case 075:
1473 case 076:
1474 case 077:
1475 if (opx->segment == NO_SEG)
1476 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1477 " relocatable");
1478 data = 0L;
1479 out(offset, segment, &data, OUT_ADDRESS, 2,
1480 outfmt->segbase(1 + opx->segment),
1481 opx->wrt);
1482 offset += 2;
1483 break;
1484
1485 case 0140:
1486 case 0141:
1487 case 0142:
1488 case 0143:
1489 data = opx->offset;
1490 if (is_sbyte16(ins, c & 3)) {
1491 bytes[0] = data;
1492 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1493 NO_SEG);
1494 offset++;
1495 } else {
1496 if (opx->segment == NO_SEG &&
1497 opx->wrt == NO_SEG)
1498 warn_overflow(2, data);
1499 out(offset, segment, &data, OUT_ADDRESS, 2,
1500 opx->segment, opx->wrt);
1501 offset += 2;
1502 }
1503 break;
1504
1505 case 0144:
1506 case 0145:
1507 case 0146:
1508 case 0147:
1509 EMIT_REX();
1510 bytes[0] = *codes++;
1511 if (is_sbyte16(ins, c & 3))
1512 bytes[0] |= 2; /* s-bit */
1513 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1514 offset++;
1515 break;
1516
1517 case 0150:
1518 case 0151:
1519 case 0152:
1520 case 0153:
1521 data = opx->offset;
1522 if (is_sbyte32(ins, c & 3)) {
1523 bytes[0] = data;
1524 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1525 NO_SEG);
1526 offset++;
1527 } else {
1528 out(offset, segment, &data, OUT_ADDRESS, 4,
1529 opx->segment, opx->wrt);
1530 offset += 4;
1531 }
1532 break;
1533
1534 case 0154:
1535 case 0155:
1536 case 0156:
1537 case 0157:
1538 EMIT_REX();
1539 bytes[0] = *codes++;
1540 if (is_sbyte32(ins, c & 3))
1541 bytes[0] |= 2; /* s-bit */
1542 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1543 offset++;
1544 break;
1545
1546 case 0160:
1547 case 0161:
1548 case 0162:
1549 case 0163:
1550 case 0164:
1551 case 0165:
1552 case 0166:
1553 case 0167:
1554 break;
1555
1556 case 0170:
1557 EMIT_REX();
1558 bytes[0] = 0;
1559 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1560 offset += 1;
1561 break;
1562
1563 case 0171:
1564 bytes[0] =
1565 (ins->drexdst << 4) |
1566 (ins->rex & REX_OC ? 0x08 : 0) |
1567 (ins->rex & (REX_R|REX_X|REX_B));
1568 ins->rex = 0;
1569 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1570 offset++;
1571 break;
1572
1573 case 0172:
1574 c = *codes++;
1575 opx = &ins->oprs[c >> 3];
1576 bytes[0] = regvals[opx->basereg] << 4;
1577 opx = &ins->oprs[c & 7];
1578 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1579 errfunc(ERR_NONFATAL,
1580 "non-absolute expression not permitted as argument %d",
1581 c & 7);
1582 } else {
1583 if (opx->offset & ~15) {
1584 errfunc(ERR_WARNING | ERR_WARN_NOV,
1585 "four-bit argument exceeds bounds");
1586 }
1587 bytes[0] |= opx->offset & 15;
1588 }
1589 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1590 offset++;
1591 break;
1592
1593 case 0250:
1594 case 0251:
1595 case 0252:
1596 case 0253:
1597 data = opx->offset;
1598 /* is_sbyte32() is right here, we have already warned */
1599 if (is_sbyte32(ins, c & 3)) {
1600 bytes[0] = data;
1601 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1602 NO_SEG);
1603 offset++;
1604 } else {
1605 out(offset, segment, &data, OUT_ADDRESS, 4,
1606 opx->segment, opx->wrt);
1607 offset += 4;
1608 }
1609 break;
1610
1611 case 0260:
1612 case 0261:
1613 case 0262:
1614 case 0263:
1615 case 0270:
1616 codes += 2;
1617 if (ins->vex_m != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1618 bytes[0] = 0xc4;
1619 bytes[1] = ins->vex_m | ((ins->rex & 7) << 5);
1620 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1621 (ins->drexdst << 3) | (ins->vex_wlp & 07);
1622 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1623 offset += 3;
1624 } else {
1625 bytes[0] = 0xc5;
1626 bytes[1] = ((ins->rex & REX_R) << (7-2)) |
1627 (ins->drexdst << 3) | (ins->vex_wlp & 07);
1628 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1629 offset += 2;
1630 }
1631 break;
1632
1633 case 0300:
1634 case 0301:
1635 case 0302:
1636 case 0303:
1637 break;
1638
1639 case 0310:
1640 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1641 *bytes = 0x67;
1642 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1643 offset += 1;
1644 } else
1645 offset += 0;
1646 break;
1647
1648 case 0311:
1649 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1650 *bytes = 0x67;
1651 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1652 offset += 1;
1653 } else
1654 offset += 0;
1655 break;
1656
1657 case 0312:
1658 break;
1659
1660 case 0313:
1661 ins->rex = 0;
1662 break;
1663
1664 case 0314:
1665 case 0315:
1666 case 0316:
1667 case 0317:
1668 break;
1669
1670 case 0320:
1671 if (bits != 16) {
1672 *bytes = 0x66;
1673 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1674 offset += 1;
1675 } else
1676 offset += 0;
1677 break;
1678
1679 case 0321:
1680 if (bits == 16) {
1681 *bytes = 0x66;
1682 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1683 offset += 1;
1684 } else
1685 offset += 0;
1686 break;
1687
1688 case 0322:
1689 case 0323:
1690 break;
1691
1692 case 0324:
1693 ins->rex |= REX_W;
1694 break;
1695
1696 case 0330:
1697 *bytes = *codes++ ^ condval[ins->condition];
1698 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1699 offset += 1;
1700 break;
1701
1702 case 0331:
1703 break;
1704
1705 case 0332:
1706 case 0333:
1707 *bytes = c - 0332 + 0xF2;
1708 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1709 offset += 1;
1710 break;
1711
1712 case 0334:
1713 if (ins->rex & REX_R) {
1714 *bytes = 0xF0;
1715 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1716 offset += 1;
1717 }
1718 ins->rex &= ~(REX_L|REX_R);
1719 break;
1720
1721 case 0335:
1722 break;
1723
1724 case 0340:
1725 if (ins->oprs[0].segment != NO_SEG)
1726 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1727 else {
1728 int64_t size = ins->oprs[0].offset;
1729 if (size > 0)
1730 out(offset, segment, NULL,
1731 OUT_RESERVE, size, NO_SEG, NO_SEG);
1732 offset += size;
1733 }
1734 break;
1735
1736 case 0364:
1737 case 0365:
1738 break;
1739
1740 case 0366:
1741 case 0367:
1742 *bytes = c - 0366 + 0x66;
1743 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1744 offset += 1;
1745 break;
1746
1747 case 0370:
1748 case 0371:
1749 case 0372:
1750 break;
1751
1752 case 0373:
1753 *bytes = bits == 16 ? 3 : 5;
1754 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1755 offset += 1;
1756 break;
1757
1758 default: /* can't do it by 'case' statements */
1759 if (c >= 0100 && c <= 0277) { /* it's an EA */
1760 ea ea_data;
1761 int rfield;
1762 int32_t rflags;
1763 uint8_t *p;
1764 int32_t s;
1765
1766 if (c <= 0177) {
1767 /* pick rfield from operand b */
1768 rflags = regflag(&ins->oprs[c & 7]);
1769 rfield = regvals[ins->oprs[c & 7].basereg];
1770 } else {
1771 /* rfield is constant */
1772 rflags = 0;
1773 rfield = c & 7;
1774 }
1775
1776 if (!process_ea
1777 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1778 ins->addr_size, rfield, rflags, ins->forw_ref)) {
1779 errfunc(ERR_NONFATAL, "invalid effective address");
1780 }
1781
1782
1783 p = bytes;
1784 *p++ = ea_data.modrm;
1785 if (ea_data.sib_present)
1786 *p++ = ea_data.sib;
1787
1788 /* DREX suffixes come between the SIB and the displacement */
1789 if (ins->rex & REX_D) {
1790 *p++ =
1791 (ins->drexdst << 4) |
1792 (ins->rex & REX_OC ? 0x08 : 0) |
1793 (ins->rex & (REX_R|REX_X|REX_B));
1794 ins->rex = 0;
1795 }
1796
1797 s = p - bytes;
1798 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1799
1800 switch (ea_data.bytes) {
1801 case 0:
1802 break;
1803 case 1:
1804 if (ins->oprs[(c >> 3) & 7].segment != NO_SEG) {
1805 data = ins->oprs[(c >> 3) & 7].offset;
1806 out(offset, segment, &data, OUT_ADDRESS, 1,
1807 ins->oprs[(c >> 3) & 7].segment,
1808 ins->oprs[(c >> 3) & 7].wrt);
1809 } else {
1810 *bytes = ins->oprs[(c >> 3) & 7].offset;
1811 out(offset, segment, bytes, OUT_RAWDATA, 1,
1812 NO_SEG, NO_SEG);
1813 }
1814 s++;
1815 break;
1816 case 8:
1817 case 2:
1818 case 4:
1819 data = ins->oprs[(c >> 3) & 7].offset;
1820 warn_overflow(ea_data.bytes, data);
1821 out(offset, segment, &data,
1822 ea_data.rip ? OUT_REL4ADR : OUT_ADDRESS,
1823 ea_data.bytes,
1824 ins->oprs[(c >> 3) & 7].segment,
1825 ins->oprs[(c >> 3) & 7].wrt);
1826 s += ea_data.bytes;
1827 break;
1828 }
1829 offset += s;
1830 } else {
1831 errfunc(ERR_PANIC, "internal instruction table corrupt"
1832 ": instruction code 0x%02X given", c);
1833 }
1834 }
1835 }
1836 }
1837
1838 static int32_t regflag(const operand * o)
1839 {
1840 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1841 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1842 }
1843 return reg_flags[o->basereg];
1844 }
1845
1846 static int32_t regval(const operand * o)
1847 {
1848 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1849 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1850 }
1851 return regvals[o->basereg];
1852 }
1853
1854 static int op_rexflags(const operand * o, int mask)
1855 {
1856 int32_t flags;
1857 int val;
1858
1859 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1860 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1861 }
1862
1863 flags = reg_flags[o->basereg];
1864 val = regvals[o->basereg];
1865
1866 return rexflags(val, flags, mask);
1867 }
1868
1869 static int rexflags(int val, int32_t flags, int mask)
1870 {
1871 int rex = 0;
1872
1873 if (val >= 8)
1874 rex |= REX_B|REX_X|REX_R;
1875 if (flags & BITS64)
1876 rex |= REX_W;
1877 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1878 rex |= REX_H;
1879 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1880 rex |= REX_P;
1881
1882 return rex & mask;
1883 }
1884
1885 static int matches(const struct itemplate *itemp, insn * instruction, int bits)
1886 {
1887 int i, size[MAX_OPERANDS], asize, oprs, ret;
1888
1889 ret = 100;
1890
1891 /*
1892 * Check the opcode
1893 */
1894 if (itemp->opcode != instruction->opcode)
1895 return 0;
1896
1897 /*
1898 * Count the operands
1899 */
1900 if (itemp->operands != instruction->operands)
1901 return 0;
1902
1903 /*
1904 * Check that no spurious colons or TOs are present
1905 */
1906 for (i = 0; i < itemp->operands; i++)
1907 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1908 return 0;
1909
1910 /*
1911 * Process size flags
1912 */
1913 if (itemp->flags & IF_ARMASK) {
1914 memset(size, 0, sizeof size);
1915
1916 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
1917
1918 switch (itemp->flags & IF_SMASK) {
1919 case IF_SB:
1920 size[i] = BITS8;
1921 break;
1922 case IF_SW:
1923 size[i] = BITS16;
1924 break;
1925 case IF_SD:
1926 size[i] = BITS32;
1927 break;
1928 case IF_SQ:
1929 size[i] = BITS64;
1930 break;
1931 case IF_SO:
1932 size[i] = BITS128;
1933 break;
1934 case IF_SZ:
1935 switch (bits) {
1936 case 16:
1937 size[i] = BITS16;
1938 break;
1939 case 32:
1940 size[i] = BITS32;
1941 break;
1942 case 64:
1943 size[i] = BITS64;
1944 break;
1945 }
1946 break;
1947 default:
1948 break;
1949 }
1950 } else {
1951 asize = 0;
1952 switch (itemp->flags & IF_SMASK) {
1953 case IF_SB:
1954 asize = BITS8;
1955 break;
1956 case IF_SW:
1957 asize = BITS16;
1958 break;
1959 case IF_SD:
1960 asize = BITS32;
1961 break;
1962 case IF_SQ:
1963 asize = BITS64;
1964 break;
1965 case IF_SO:
1966 asize = BITS128;
1967 break;
1968 case IF_SZ:
1969 switch (bits) {
1970 case 16:
1971 asize = BITS16;
1972 break;
1973 case 32:
1974 asize = BITS32;
1975 break;
1976 case 64:
1977 asize = BITS64;
1978 break;
1979 }
1980 break;
1981 default:
1982 break;
1983 }
1984 for (i = 0; i < MAX_OPERANDS; i++)
1985 size[i] = asize;
1986 }
1987
1988 /*
1989 * Check that the operand flags all match up
1990 */
1991 for (i = 0; i < itemp->operands; i++) {
1992 int32_t type = instruction->oprs[i].type;
1993 if (!(type & SIZE_MASK))
1994 type |= size[i];
1995
1996 if (itemp->opd[i] & SAME_AS) {
1997 int j = itemp->opd[i] & ~SAME_AS;
1998 if (type != instruction->oprs[j].type ||
1999 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
2000 return 0;
2001 } else if (itemp->opd[i] & ~type ||
2002 ((itemp->opd[i] & SIZE_MASK) &&
2003 ((itemp->opd[i] ^ type) & SIZE_MASK))) {
2004 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2005 (type & SIZE_MASK))
2006 return 0;
2007 else
2008 return 1;
2009 }
2010 }
2011
2012 /*
2013 * Check operand sizes
2014 */
2015 if (itemp->flags & (IF_SM | IF_SM2)) {
2016 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2017 asize = 0;
2018 for (i = 0; i < oprs; i++) {
2019 if ((asize = itemp->opd[i] & SIZE_MASK) != 0) {
2020 int j;
2021 for (j = 0; j < oprs; j++)
2022 size[j] = asize;
2023 break;
2024 }
2025 }
2026 } else {
2027 oprs = itemp->operands;
2028 }
2029
2030 for (i = 0; i < itemp->operands; i++) {
2031 if (!(itemp->opd[i] & SIZE_MASK) &&
2032 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2033 return 2;
2034 }
2035
2036 /*
2037 * Check template is okay at the set cpu level
2038 */
2039 if (((itemp->flags & IF_PLEVEL) > cpu))
2040 return 3;
2041
2042 /*
2043 * Check if instruction is available in long mode
2044 */
2045 if ((itemp->flags & IF_NOLONG) && (bits == 64))
2046 return 4;
2047
2048 /*
2049 * Check if special handling needed for Jumps
2050 */
2051 if ((uint8_t)(itemp->code[0]) >= 0370)
2052 return 99;
2053
2054 return ret;
2055 }
2056
2057 static ea *process_ea(operand * input, ea * output, int bits,
2058 int addrbits, int rfield, int32_t rflags, int forw_ref)
2059 {
2060 output->rip = false;
2061
2062 /* REX flags for the rfield operand */
2063 output->rex |= rexflags(rfield, rflags, REX_R|REX_P|REX_W|REX_H);
2064
2065 if (!(REGISTER & ~input->type)) { /* register direct */
2066 int i;
2067 int32_t f;
2068
2069 if (input->basereg < EXPR_REG_START /* Verify as Register */
2070 || input->basereg >= REG_ENUM_LIMIT)
2071 return NULL;
2072 f = regflag(input);
2073 i = regvals[input->basereg];
2074
2075 if (REG_EA & ~f)
2076 return NULL; /* Invalid EA register */
2077
2078 output->rex |= op_rexflags(input, REX_B|REX_P|REX_W|REX_H);
2079
2080 output->sib_present = false; /* no SIB necessary */
2081 output->bytes = 0; /* no offset necessary either */
2082 output->modrm = 0xC0 | ((rfield & 7) << 3) | (i & 7);
2083 } else { /* it's a memory reference */
2084 if (input->basereg == -1
2085 && (input->indexreg == -1 || input->scale == 0)) {
2086 /* it's a pure offset */
2087 if (bits == 64 && (~input->type & IP_REL)) {
2088 int scale, index, base;
2089 output->sib_present = true;
2090 scale = 0;
2091 index = 4;
2092 base = 5;
2093 output->sib = (scale << 6) | (index << 3) | base;
2094 output->bytes = 4;
2095 output->modrm = 4 | ((rfield & 7) << 3);
2096 output->rip = false;
2097 } else {
2098 output->sib_present = false;
2099 output->bytes = (addrbits != 16 ? 4 : 2);
2100 output->modrm = (addrbits != 16 ? 5 : 6) | ((rfield & 7) << 3);
2101 output->rip = bits == 64;
2102 }
2103 } else { /* it's an indirection */
2104 int i = input->indexreg, b = input->basereg, s = input->scale;
2105 int32_t o = input->offset, seg = input->segment;
2106 int hb = input->hintbase, ht = input->hinttype;
2107 int t;
2108 int it, bt;
2109 int32_t ix, bx; /* register flags */
2110
2111 if (s == 0)
2112 i = -1; /* make this easy, at least */
2113
2114 if (i >= EXPR_REG_START && i < REG_ENUM_LIMIT) {
2115 it = regvals[i];
2116 ix = reg_flags[i];
2117 } else {
2118 it = -1;
2119 ix = 0;
2120 }
2121
2122 if (b >= EXPR_REG_START && b < REG_ENUM_LIMIT) {
2123 bt = regvals[b];
2124 bx = reg_flags[b];
2125 } else {
2126 bt = -1;
2127 bx = 0;
2128 }
2129
2130 /* check for a 32/64-bit memory reference... */
2131 if ((ix|bx) & (BITS32|BITS64)) {
2132 /* it must be a 32/64-bit memory reference. Firstly we have
2133 * to check that all registers involved are type E/Rxx. */
2134 int32_t sok = BITS32|BITS64;
2135
2136 if (it != -1) {
2137 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2138 sok &= ix;
2139 else
2140 return NULL;
2141 }
2142
2143 if (bt != -1) {
2144 if (REG_GPR & ~bx)
2145 return NULL; /* Invalid register */
2146 if (~sok & bx & SIZE_MASK)
2147 return NULL; /* Invalid size */
2148 sok &= bx;
2149 }
2150
2151 /* While we're here, ensure the user didn't specify
2152 WORD or QWORD. */
2153 if (input->disp_size == 16 || input->disp_size == 64)
2154 return NULL;
2155
2156 if (addrbits == 16 ||
2157 (addrbits == 32 && !(sok & BITS32)) ||
2158 (addrbits == 64 && !(sok & BITS64)))
2159 return NULL;
2160
2161 /* now reorganize base/index */
2162 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2163 ((hb == b && ht == EAH_NOTBASE)
2164 || (hb == i && ht == EAH_MAKEBASE))) {
2165 /* swap if hints say so */
2166 t = bt, bt = it, it = t;
2167 t = bx, bx = ix, ix = t;
2168 }
2169 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2170 bt = -1, bx = 0, s++;
2171 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2172 /* make single reg base, unless hint */
2173 bt = it, bx = ix, it = -1, ix = 0;
2174 }
2175 if (((s == 2 && it != REG_NUM_ESP
2176 && !(input->eaflags & EAF_TIMESTWO)) || s == 3
2177 || s == 5 || s == 9) && bt == -1)
2178 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2179 if (it == -1 && (bt & 7) != REG_NUM_ESP
2180 && (input->eaflags & EAF_TIMESTWO))
2181 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2182 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2183 if (s == 1 && it == REG_NUM_ESP) {
2184 /* swap ESP into base if scale is 1 */
2185 t = it, it = bt, bt = t;
2186 t = ix, ix = bx, bx = t;
2187 }
2188 if (it == REG_NUM_ESP
2189 || (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2190 return NULL; /* wrong, for various reasons */
2191
2192 output->rex |= rexflags(it, ix, REX_X);
2193 output->rex |= rexflags(bt, bx, REX_B);
2194
2195 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2196 /* no SIB needed */
2197 int mod, rm;
2198
2199 if (bt == -1) {
2200 rm = 5;
2201 mod = 0;
2202 } else {
2203 rm = (bt & 7);
2204 if (rm != REG_NUM_EBP && o == 0 &&
2205 seg == NO_SEG && !forw_ref &&
2206 !(input->eaflags &
2207 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2208 mod = 0;
2209 else if (input->eaflags & EAF_BYTEOFFS ||
2210 (o >= -128 && o <= 127 && seg == NO_SEG
2211 && !forw_ref
2212 && !(input->eaflags & EAF_WORDOFFS)))
2213 mod = 1;
2214 else
2215 mod = 2;
2216 }
2217
2218 output->sib_present = false;
2219 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2220 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2221 } else {
2222 /* we need a SIB */
2223 int mod, scale, index, base;
2224
2225 if (it == -1)
2226 index = 4, s = 1;
2227 else
2228 index = (it & 7);
2229
2230 switch (s) {
2231 case 1:
2232 scale = 0;
2233 break;
2234 case 2:
2235 scale = 1;
2236 break;
2237 case 4:
2238 scale = 2;
2239 break;
2240 case 8:
2241 scale = 3;
2242 break;
2243 default: /* then what the smeg is it? */
2244 return NULL; /* panic */
2245 }
2246
2247 if (bt == -1) {
2248 base = 5;
2249 mod = 0;
2250 } else {
2251 base = (bt & 7);
2252 if (base != REG_NUM_EBP && o == 0 &&
2253 seg == NO_SEG && !forw_ref &&
2254 !(input->eaflags &
2255 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2256 mod = 0;
2257 else if (input->eaflags & EAF_BYTEOFFS ||
2258 (o >= -128 && o <= 127 && seg == NO_SEG
2259 && !forw_ref
2260 && !(input->eaflags & EAF_WORDOFFS)))
2261 mod = 1;
2262 else
2263 mod = 2;
2264 }
2265
2266 output->sib_present = true;
2267 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2268 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2269 output->sib = (scale << 6) | (index << 3) | base;
2270 }
2271 } else { /* it's 16-bit */
2272 int mod, rm;
2273
2274 /* check for 64-bit long mode */
2275 if (addrbits == 64)
2276 return NULL;
2277
2278 /* check all registers are BX, BP, SI or DI */
2279 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI
2280 && b != R_DI) || (i != -1 && i != R_BP && i != R_BX
2281 && i != R_SI && i != R_DI))
2282 return NULL;
2283
2284 /* ensure the user didn't specify DWORD/QWORD */
2285 if (input->disp_size == 32 || input->disp_size == 64)
2286 return NULL;
2287
2288 if (s != 1 && i != -1)
2289 return NULL; /* no can do, in 16-bit EA */
2290 if (b == -1 && i != -1) {
2291 int tmp = b;
2292 b = i;
2293 i = tmp;
2294 } /* swap */
2295 if ((b == R_SI || b == R_DI) && i != -1) {
2296 int tmp = b;
2297 b = i;
2298 i = tmp;
2299 }
2300 /* have BX/BP as base, SI/DI index */
2301 if (b == i)
2302 return NULL; /* shouldn't ever happen, in theory */
2303 if (i != -1 && b != -1 &&
2304 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2305 return NULL; /* invalid combinations */
2306 if (b == -1) /* pure offset: handled above */
2307 return NULL; /* so if it gets to here, panic! */
2308
2309 rm = -1;
2310 if (i != -1)
2311 switch (i * 256 + b) {
2312 case R_SI * 256 + R_BX:
2313 rm = 0;
2314 break;
2315 case R_DI * 256 + R_BX:
2316 rm = 1;
2317 break;
2318 case R_SI * 256 + R_BP:
2319 rm = 2;
2320 break;
2321 case R_DI * 256 + R_BP:
2322 rm = 3;
2323 break;
2324 } else
2325 switch (b) {
2326 case R_SI:
2327 rm = 4;
2328 break;
2329 case R_DI:
2330 rm = 5;
2331 break;
2332 case R_BP:
2333 rm = 6;
2334 break;
2335 case R_BX:
2336 rm = 7;
2337 break;
2338 }
2339 if (rm == -1) /* can't happen, in theory */
2340 return NULL; /* so panic if it does */
2341
2342 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2343 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2344 mod = 0;
2345 else if (input->eaflags & EAF_BYTEOFFS ||
2346 (o >= -128 && o <= 127 && seg == NO_SEG
2347 && !forw_ref
2348 && !(input->eaflags & EAF_WORDOFFS)))
2349 mod = 1;
2350 else
2351 mod = 2;
2352
2353 output->sib_present = false; /* no SIB - it's 16-bit */
2354 output->bytes = mod; /* bytes of offset needed */
2355 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2356 }
2357 }
2358 }
2359
2360 output->size = 1 + output->sib_present + output->bytes;
2361 return output;
2362 }
2363
2364 static void add_asp(insn *ins, int addrbits)
2365 {
2366 int j, valid;
2367 int defdisp;
2368
2369 valid = (addrbits == 64) ? 64|32 : 32|16;
2370
2371 switch (ins->prefixes[PPS_ASIZE]) {
2372 case P_A16:
2373 valid &= 16;
2374 break;
2375 case P_A32:
2376 valid &= 32;
2377 break;
2378 case P_A64:
2379 valid &= 64;
2380 break;
2381 case P_ASP:
2382 valid &= (addrbits == 32) ? 16 : 32;
2383 break;
2384 default:
2385 break;
2386 }
2387
2388 for (j = 0; j < ins->operands; j++) {
2389 if (!(MEMORY & ~ins->oprs[j].type)) {
2390 int32_t i, b;
2391
2392 /* Verify as Register */
2393 if (ins->oprs[j].indexreg < EXPR_REG_START
2394 || ins->oprs[j].indexreg >= REG_ENUM_LIMIT)
2395 i = 0;
2396 else
2397 i = reg_flags[ins->oprs[j].indexreg];
2398
2399 /* Verify as Register */
2400 if (ins->oprs[j].basereg < EXPR_REG_START
2401 || ins->oprs[j].basereg >= REG_ENUM_LIMIT)
2402 b = 0;
2403 else
2404 b = reg_flags[ins->oprs[j].basereg];
2405
2406 if (ins->oprs[j].scale == 0)
2407 i = 0;
2408
2409 if (!i && !b) {
2410 int ds = ins->oprs[j].disp_size;
2411 if ((addrbits != 64 && ds > 8) ||
2412 (addrbits == 64 && ds == 16))
2413 valid &= ds;
2414 } else {
2415 if (!(REG16 & ~b))
2416 valid &= 16;
2417 if (!(REG32 & ~b))
2418 valid &= 32;
2419 if (!(REG64 & ~b))
2420 valid &= 64;
2421
2422 if (!(REG16 & ~i))
2423 valid &= 16;
2424 if (!(REG32 & ~i))
2425 valid &= 32;
2426 if (!(REG64 & ~i))
2427 valid &= 64;
2428 }
2429 }
2430 }
2431
2432 if (valid & addrbits) {
2433 ins->addr_size = addrbits;
2434 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2435 /* Add an address size prefix */
2436 enum prefixes pref = (addrbits == 32) ? P_A16 : P_A32;
2437 ins->prefixes[PPS_ASIZE] = pref;
2438 ins->addr_size = (addrbits == 32) ? 16 : 32;
2439 } else {
2440 /* Impossible... */
2441 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2442 ins->addr_size = addrbits; /* Error recovery */
2443 }
2444
2445 defdisp = ins->addr_size == 16 ? 16 : 32;
2446
2447 for (j = 0; j < ins->operands; j++) {
2448 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2449 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp)
2450 != ins->addr_size) {
2451 /* mem_offs sizes must match the address size; if not,
2452 strip the MEM_OFFS bit and match only EA instructions */
2453 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2454 }
2455 }
2456 }
The Netwide Assembler