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x86-host-specific performance improvement
[nasm.git] / assemble.c
blob2d24e8d71c8fa0fb9c21292b45ee15a8a010c8ee
1 /* assemble.c code generation for the Netwide Assembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the licence given in the file "Licence"
6 * distributed in the NASM archive.
7 *
8 * the actual codes (C syntax, i.e. octal):
9 * \0 - terminates the code. (Unless it's a literal of course.)
10 * \1, \2, \3 - that many literal bytes follow in the code stream
11 * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
12 * (POP is never used for CS) depending on operand 0
13 * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
14 * on operand 0
15 * \10..\13 - a literal byte follows in the code stream, to be added
16 * to the register value of operand 0..3
17 * \14..\17 - a signed byte immediate operand, from operand 0..3
18 * \20..\23 - a byte immediate operand, from operand 0..3
19 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
20 * \30..\33 - a word immediate operand, from operand 0..3
21 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
22 * assembly mode or the operand-size override on the operand
23 * \40..\43 - a long immediate operand, from operand 0..3
24 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
25 * depending on the address size of the instruction.
26 * \50..\53 - a byte relative operand, from operand 0..3
27 * \54..\57 - a qword immediate operand, from operand 0..3
28 * \60..\63 - a word relative operand, from operand 0..3
29 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
30 * assembly mode or the operand-size override on the operand
31 * \70..\73 - a long relative operand, from operand 0..3
32 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
33 * \1ab - a ModRM, calculated on EA in operand a, with the spare
34 * field the register value of operand b.
35 * \140..\143 - an immediate word or signed byte for operand 0..3
36 * \144..\147 - or 2 (s-field) into next opcode byte if operand 0..3
37 * is a signed byte rather than a word.
38 * \150..\153 - an immediate dword or signed byte for operand 0..3
39 * \154..\157 - or 2 (s-field) into next opcode byte if operand 0..3
40 * is a signed byte rather than a dword.
41 * \160..\163 - this instruction uses DREX rather than REX, with the
42 * OC0 field set to 0, and the dest field taken from
43 * operand 0..3.
44 * \164..\167 - this instruction uses DREX rather than REX, with the
45 * OC0 field set to 1, and the dest field taken from
46 * operand 0..3.
47 * \170 - encodes the literal byte 0. (Some compilers don't take
48 * kindly to a zero byte in the _middle_ of a compile time
49 * string constant, so I had to put this hack in.)
50 * \171 - placement of DREX suffix in the absence of an EA
51 * \2ab - a ModRM, calculated on EA in operand a, with the spare
52 * field equal to digit b.
53 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
54 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
55 * \312 - (disassembler only) marker on LOOP, LOOPxx instructions.
56 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
57 * \314 - (disassembler only) invalid with REX.B
58 * \315 - (disassembler only) invalid with REX.X
59 * \316 - (disassembler only) invalid with REX.R
60 * \317 - (disassembler only) invalid with REX.W
61 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
62 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
63 * \322 - indicates that this instruction is only valid when the
64 * operand size is the default (instruction to disassembler,
65 * generates no code in the assembler)
66 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
67 * \324 - indicates 64-bit operand size requiring REX prefix.
68 * \330 - a literal byte follows in the code stream, to be added
69 * to the condition code value of the instruction.
70 * \331 - instruction not valid with REP prefix. Hint for
71 * disassembler only; for SSE instructions.
72 * \332 - REP prefix (0xF2 byte) used as opcode extension.
73 * \333 - REP prefix (0xF3 byte) used as opcode extension.
74 * \334 - LOCK prefix used instead of REX.R
75 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
76 * \340 - reserve <operand 0> bytes of uninitialized storage.
77 * Operand 0 had better be a segmentless constant.
78 * \364 - operand-size prefix (0x66) not permitted
79 * \365 - address-size prefix (0x67) not permitted
80 * \366 - operand-size prefix (0x66) used as opcode extension
81 * \367 - address-size prefix (0x67) used as opcode extension
82 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
83 * 370 is used for Jcc, 371 is used for JMP.
84 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
85 * used for conditional jump over longer jump
86 */
87
88 #include "compiler.h"
89
90 #include <stdio.h>
91 #include <string.h>
92 #include <inttypes.h>
93
94 #include "nasm.h"
95 #include "nasmlib.h"
96 #include "assemble.h"
97 #include "insns.h"
98 #include "preproc.h"
99 #include "regflags.c"
100 #include "regvals.c"
101
102 typedef struct {
103 int sib_present; /* is a SIB byte necessary? */
104 int bytes; /* # of bytes of offset needed */
105 int size; /* lazy - this is sib+bytes+1 */
106 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
107 } ea;
108
109 static uint32_t cpu; /* cpu level received from nasm.c */
110 static efunc errfunc;
111 static struct ofmt *outfmt;
112 static ListGen *list;
113
114 static int64_t calcsize(int32_t, int64_t, int, insn *, const char *);
115 static void gencode(int32_t, int64_t, int, insn *, const char *, int64_t);
116 static int matches(const struct itemplate *, insn *, int bits);
117 static int32_t regflag(const operand *);
118 static int32_t regval(const operand *);
119 static int rexflags(int, int32_t, int);
120 static int op_rexflags(const operand *, int);
121 static ea *process_ea(operand *, ea *, int, int, int, int32_t, int);
122 static void add_asp(insn *, int);
123
124 static int has_prefix(insn * ins, enum prefix_pos pos, enum prefixes prefix)
125 {
126 return ins->prefixes[pos] == prefix;
127 }
128
129 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
130 {
131 if (ins->prefixes[pos])
132 errfunc(ERR_NONFATAL, "invalid %s prefix",
133 prefix_name(ins->prefixes[pos]));
134 }
135
136 static const char *size_name(int size)
137 {
138 switch (size) {
139 case 1:
140 return "byte";
141 case 2:
142 return "word";
143 case 4:
144 return "dword";
145 case 8:
146 return "qword";
147 case 10:
148 return "tword";
149 case 16:
150 return "oword";
151 default:
152 return "???";
153 }
154 }
155
156 static void warn_overflow(int size, int64_t data)
157 {
158 if (size < 8) {
159 int64_t lim = ((int64_t)1 << (size*8))-1;
160
161 if (data < ~lim || data > lim)
162 errfunc(ERR_WARNING, "%s data exceeds bounds", size_name(size));
163 }
164 }
165 /*
166 * This routine wrappers the real output format's output routine,
167 * in order to pass a copy of the data off to the listing file
168 * generator at the same time.
169 */
170 static void out(int64_t offset, int32_t segto, const void *data,
171 enum out_type type, uint64_t size,
172 int32_t segment, int32_t wrt)
173 {
174 static int32_t lineno = 0; /* static!!! */
175 static char *lnfname = NULL;
176 uint8_t p[8];
177
178 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
179 /*
180 * This is a non-relocated address, and we're going to
181 * convert it into RAWDATA format.
182 */
183 uint8_t *q = p;
184
185 if (size > 8) {
186 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
187 return;
188 }
189
190 WRITEADDR(q, *(int64_t *)data, size);
191 data = p;
192 type = OUT_RAWDATA;
193 }
194
195 list->output(offset, data, type, size);
196
197 /*
198 * this call to src_get determines when we call the
199 * debug-format-specific "linenum" function
200 * it updates lineno and lnfname to the current values
201 * returning 0 if "same as last time", -2 if lnfname
202 * changed, and the amount by which lineno changed,
203 * if it did. thus, these variables must be static
204 */
205
206 if (src_get(&lineno, &lnfname)) {
207 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
208 }
209
210 outfmt->output(segto, data, type, size, segment, wrt);
211 }
212
213 static int jmp_match(int32_t segment, int64_t offset, int bits,
214 insn * ins, const char *code)
215 {
216 int64_t isize;
217 uint8_t c = code[0];
218
219 if (c != 0370 && c != 0371)
220 return 0;
221 if (ins->oprs[0].opflags & OPFLAG_FORWARD) {
222 if ((optimizing < 0 || (ins->oprs[0].type & STRICT))
223 && c == 0370)
224 return 1;
225 else
226 return (pass0 == 0); /* match a forward reference */
227 }
228 isize = calcsize(segment, offset, bits, ins, code);
229 if (ins->oprs[0].segment != segment)
230 return 0;
231 isize = ins->oprs[0].offset - offset - isize; /* isize is now the delta */
232 if (isize >= -128L && isize <= 127L)
233 return 1; /* it is byte size */
234
235 return 0;
236 }
237
238 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
239 insn * instruction, struct ofmt *output, efunc error,
240 ListGen * listgen)
241 {
242 const struct itemplate *temp;
243 int j;
244 int size_prob;
245 int64_t insn_end;
246 int32_t itimes;
247 int64_t start = offset;
248 int64_t wsize = 0; /* size for DB etc. */
249
250 errfunc = error; /* to pass to other functions */
251 cpu = cp;
252 outfmt = output; /* likewise */
253 list = listgen; /* and again */
254
255 switch (instruction->opcode) {
256 case -1:
257 return 0;
258 case I_DB:
259 wsize = 1;
260 break;
261 case I_DW:
262 wsize = 2;
263 break;
264 case I_DD:
265 wsize = 4;
266 break;
267 case I_DQ:
268 wsize = 8;
269 break;
270 case I_DT:
271 wsize = 10;
272 break;
273 case I_DO:
274 wsize = 16;
275 break;
276 default:
277 break;
278 }
279
280 if (wsize) {
281 extop *e;
282 int32_t t = instruction->times;
283 if (t < 0)
284 errfunc(ERR_PANIC,
285 "instruction->times < 0 (%ld) in assemble()", t);
286
287 while (t--) { /* repeat TIMES times */
288 for (e = instruction->eops; e; e = e->next) {
289 if (e->type == EOT_DB_NUMBER) {
290 if (wsize == 1) {
291 if (e->segment != NO_SEG)
292 errfunc(ERR_NONFATAL,
293 "one-byte relocation attempted");
294 else {
295 uint8_t out_byte = e->offset;
296 out(offset, segment, &out_byte,
297 OUT_RAWDATA, 1, NO_SEG, NO_SEG);
298 }
299 } else if (wsize > 8) {
300 errfunc(ERR_NONFATAL, "integer supplied to a DT or DO"
301 " instruction");
302 } else
303 out(offset, segment, &e->offset,
304 OUT_ADDRESS, wsize, e->segment, e->wrt);
305 offset += wsize;
306 } else if (e->type == EOT_DB_STRING) {
307 int align;
308
309 out(offset, segment, e->stringval,
310 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
311 align = e->stringlen % wsize;
312
313 if (align) {
314 align = wsize - align;
315 out(offset, segment, "\0\0\0\0\0\0\0\0",
316 OUT_RAWDATA, align, NO_SEG, NO_SEG);
317 }
318 offset += e->stringlen + align;
319 }
320 }
321 if (t > 0 && t == instruction->times - 1) {
322 /*
323 * Dummy call to list->output to give the offset to the
324 * listing module.
325 */
326 list->output(offset, NULL, OUT_RAWDATA, 0);
327 list->uplevel(LIST_TIMES);
328 }
329 }
330 if (instruction->times > 1)
331 list->downlevel(LIST_TIMES);
332 return offset - start;
333 }
334
335 if (instruction->opcode == I_INCBIN) {
336 static char fname[FILENAME_MAX];
337 FILE *fp;
338 int32_t len;
339 char *prefix = "", *combine;
340 char **pPrevPath = NULL;
341
342 len = FILENAME_MAX - 1;
343 if (len > instruction->eops->stringlen)
344 len = instruction->eops->stringlen;
345 strncpy(fname, instruction->eops->stringval, len);
346 fname[len] = '\0';
347
348 while (1) { /* added by alexfru: 'incbin' uses include paths */
349 combine = nasm_malloc(strlen(prefix) + len + 1);
350 strcpy(combine, prefix);
351 strcat(combine, fname);
352
353 if ((fp = fopen(combine, "rb")) != NULL) {
354 nasm_free(combine);
355 break;
356 }
357
358 nasm_free(combine);
359 pPrevPath = pp_get_include_path_ptr(pPrevPath);
360 if (pPrevPath == NULL)
361 break;
362 prefix = *pPrevPath;
363 }
364
365 if (fp == NULL)
366 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
367 fname);
368 else if (fseek(fp, 0L, SEEK_END) < 0)
369 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
370 fname);
371 else {
372 static char buf[2048];
373 int32_t t = instruction->times;
374 int32_t base = 0;
375
376 len = ftell(fp);
377 if (instruction->eops->next) {
378 base = instruction->eops->next->offset;
379 len -= base;
380 if (instruction->eops->next->next &&
381 len > instruction->eops->next->next->offset)
382 len = instruction->eops->next->next->offset;
383 }
384 /*
385 * Dummy call to list->output to give the offset to the
386 * listing module.
387 */
388 list->output(offset, NULL, OUT_RAWDATA, 0);
389 list->uplevel(LIST_INCBIN);
390 while (t--) {
391 int32_t l;
392
393 fseek(fp, base, SEEK_SET);
394 l = len;
395 while (l > 0) {
396 int32_t m =
397 fread(buf, 1, (l > (int32_t) sizeof(buf) ? (int32_t) sizeof(buf) : l),
398 fp);
399 if (!m) {
400 /*
401 * This shouldn't happen unless the file
402 * actually changes while we are reading
403 * it.
404 */
405 error(ERR_NONFATAL,
406 "`incbin': unexpected EOF while"
407 " reading file `%s'", fname);
408 t = 0; /* Try to exit cleanly */
409 break;
410 }
411 out(offset, segment, buf, OUT_RAWDATA, m,
412 NO_SEG, NO_SEG);
413 l -= m;
414 }
415 }
416 list->downlevel(LIST_INCBIN);
417 if (instruction->times > 1) {
418 /*
419 * Dummy call to list->output to give the offset to the
420 * listing module.
421 */
422 list->output(offset, NULL, OUT_RAWDATA, 0);
423 list->uplevel(LIST_TIMES);
424 list->downlevel(LIST_TIMES);
425 }
426 fclose(fp);
427 return instruction->times * len;
428 }
429 return 0; /* if we're here, there's an error */
430 }
431
432 /* Check to see if we need an address-size prefix */
433 add_asp(instruction, bits);
434
435 size_prob = false;
436
437 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++){
438 int m = matches(temp, instruction, bits);
439
440 if (m == 99)
441 m += jmp_match(segment, offset, bits, instruction, temp->code);
442
443 if (m == 100) { /* matches! */
444 const char *codes = temp->code;
445 int64_t insn_size = calcsize(segment, offset, bits,
446 instruction, codes);
447 itimes = instruction->times;
448 if (insn_size < 0) /* shouldn't be, on pass two */
449 error(ERR_PANIC, "errors made it through from pass one");
450 else
451 while (itimes--) {
452 for (j = 0; j < MAXPREFIX; j++) {
453 uint8_t c = 0;
454 switch (instruction->prefixes[j]) {
455 case P_LOCK:
456 c = 0xF0;
457 break;
458 case P_REPNE:
459 case P_REPNZ:
460 c = 0xF2;
461 break;
462 case P_REPE:
463 case P_REPZ:
464 case P_REP:
465 c = 0xF3;
466 break;
467 case R_CS:
468 if (bits == 64) {
469 error(ERR_WARNING,
470 "cs segment base generated, but will be ignored in 64-bit mode");
471 }
472 c = 0x2E;
473 break;
474 case R_DS:
475 if (bits == 64) {
476 error(ERR_WARNING,
477 "ds segment base generated, but will be ignored in 64-bit mode");
478 }
479 c = 0x3E;
480 break;
481 case R_ES:
482 if (bits == 64) {
483 error(ERR_WARNING,
484 "es segment base generated, but will be ignored in 64-bit mode");
485 }
486 c = 0x26;
487 break;
488 case R_FS:
489 c = 0x64;
490 break;
491 case R_GS:
492 c = 0x65;
493 break;
494 case R_SS:
495 if (bits == 64) {
496 error(ERR_WARNING,
497 "ss segment base generated, but will be ignored in 64-bit mode");
498 }
499 c = 0x36;
500 break;
501 case R_SEGR6:
502 case R_SEGR7:
503 error(ERR_NONFATAL,
504 "segr6 and segr7 cannot be used as prefixes");
505 break;
506 case P_A16:
507 if (bits == 64) {
508 error(ERR_NONFATAL,
509 "16-bit addressing is not supported "
510 "in 64-bit mode");
511 } else if (bits != 16)
512 c = 0x67;
513 break;
514 case P_A32:
515 if (bits != 32)
516 c = 0x67;
517 break;
518 case P_A64:
519 if (bits != 64) {
520 error(ERR_NONFATAL,
521 "64-bit addressing is only supported "
522 "in 64-bit mode");
523 }
524 break;
525 case P_ASP:
526 c = 0x67;
527 break;
528 case P_O16:
529 if (bits != 16)
530 c = 0x66;
531 break;
532 case P_O32:
533 if (bits == 16)
534 c = 0x66;
535 break;
536 case P_O64:
537 /* REX.W */
538 break;
539 case P_OSP:
540 c = 0x66;
541 break;
542 case P_none:
543 break;
544 default:
545 error(ERR_PANIC, "invalid instruction prefix");
546 }
547 if (c != 0) {
548 out(offset, segment, &c, OUT_RAWDATA, 1,
549 NO_SEG, NO_SEG);
550 offset++;
551 }
552 }
553 insn_end = offset + insn_size;
554 gencode(segment, offset, bits, instruction, codes,
555 insn_end);
556 offset += insn_size;
557 if (itimes > 0 && itimes == instruction->times - 1) {
558 /*
559 * Dummy call to list->output to give the offset to the
560 * listing module.
561 */
562 list->output(offset, NULL, OUT_RAWDATA, 0);
563 list->uplevel(LIST_TIMES);
564 }
565 }
566 if (instruction->times > 1)
567 list->downlevel(LIST_TIMES);
568 return offset - start;
569 } else if (m > 0 && m > size_prob) {
570 size_prob = m;
571 }
572 // temp++;
573 }
574
575 if (temp->opcode == -1) { /* didn't match any instruction */
576 switch (size_prob) {
577 case 1:
578 error(ERR_NONFATAL, "operation size not specified");
579 break;
580 case 2:
581 error(ERR_NONFATAL, "mismatch in operand sizes");
582 break;
583 case 3:
584 error(ERR_NONFATAL, "no instruction for this cpu level");
585 break;
586 case 4:
587 error(ERR_NONFATAL, "instruction not supported in 64-bit mode");
588 break;
589 default:
590 error(ERR_NONFATAL,
591 "invalid combination of opcode and operands");
592 break;
593 }
594 }
595 return 0;
596 }
597
598 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
599 insn * instruction, efunc error)
600 {
601 const struct itemplate *temp;
602
603 errfunc = error; /* to pass to other functions */
604 cpu = cp;
605
606 if (instruction->opcode == -1)
607 return 0;
608
609 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
610 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
611 instruction->opcode == I_DT || instruction->opcode == I_DO) {
612 extop *e;
613 int32_t isize, osize, wsize = 0; /* placate gcc */
614
615 isize = 0;
616 switch (instruction->opcode) {
617 case I_DB:
618 wsize = 1;
619 break;
620 case I_DW:
621 wsize = 2;
622 break;
623 case I_DD:
624 wsize = 4;
625 break;
626 case I_DQ:
627 wsize = 8;
628 break;
629 case I_DT:
630 wsize = 10;
631 break;
632 case I_DO:
633 wsize = 16;
634 break;
635 default:
636 break;
637 }
638
639 for (e = instruction->eops; e; e = e->next) {
640 int32_t align;
641
642 osize = 0;
643 if (e->type == EOT_DB_NUMBER)
644 osize = 1;
645 else if (e->type == EOT_DB_STRING)
646 osize = e->stringlen;
647
648 align = (-osize) % wsize;
649 if (align < 0)
650 align += wsize;
651 isize += osize + align;
652 }
653 return isize * instruction->times;
654 }
655
656 if (instruction->opcode == I_INCBIN) {
657 char fname[FILENAME_MAX];
658 FILE *fp;
659 int32_t len;
660 char *prefix = "", *combine;
661 char **pPrevPath = NULL;
662
663 len = FILENAME_MAX - 1;
664 if (len > instruction->eops->stringlen)
665 len = instruction->eops->stringlen;
666 strncpy(fname, instruction->eops->stringval, len);
667 fname[len] = '\0';
668
669 /* added by alexfru: 'incbin' uses include paths */
670 while (1) {
671 combine = nasm_malloc(strlen(prefix) + len + 1);
672 strcpy(combine, prefix);
673 strcat(combine, fname);
674
675 if ((fp = fopen(combine, "rb")) != NULL) {
676 nasm_free(combine);
677 break;
678 }
679
680 nasm_free(combine);
681 pPrevPath = pp_get_include_path_ptr(pPrevPath);
682 if (pPrevPath == NULL)
683 break;
684 prefix = *pPrevPath;
685 }
686
687 if (fp == NULL)
688 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
689 fname);
690 else if (fseek(fp, 0L, SEEK_END) < 0)
691 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
692 fname);
693 else {
694 len = ftell(fp);
695 fclose(fp);
696 if (instruction->eops->next) {
697 len -= instruction->eops->next->offset;
698 if (instruction->eops->next->next &&
699 len > instruction->eops->next->next->offset) {
700 len = instruction->eops->next->next->offset;
701 }
702 }
703 return instruction->times * len;
704 }
705 return 0; /* if we're here, there's an error */
706 }
707
708 /* Check to see if we need an address-size prefix */
709 add_asp(instruction, bits);
710
711 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++) {
712 int m = matches(temp, instruction, bits);
713 if (m == 99)
714 m += jmp_match(segment, offset, bits, instruction, temp->code);
715
716 if (m == 100) {
717 /* we've matched an instruction. */
718 int64_t isize;
719 const char *codes = temp->code;
720 int j;
721
722 isize = calcsize(segment, offset, bits, instruction, codes);
723 if (isize < 0)
724 return -1;
725 for (j = 0; j < MAXPREFIX; j++) {
726 switch (instruction->prefixes[j]) {
727 case P_A16:
728 if (bits != 16)
729 isize++;
730 break;
731 case P_A32:
732 if (bits != 32)
733 isize++;
734 break;
735 case P_O16:
736 if (bits != 16)
737 isize++;
738 break;
739 case P_O32:
740 if (bits == 16)
741 isize++;
742 break;
743 case P_A64:
744 case P_O64:
745 case P_none:
746 break;
747 default:
748 isize++;
749 break;
750 }
751 }
752 return isize * instruction->times;
753 }
754 }
755 return -1; /* didn't match any instruction */
756 }
757
758 /* check that opn[op] is a signed byte of size 16 or 32,
759 and return the signed value*/
760 static int is_sbyte(insn * ins, int op, int size)
761 {
762 int32_t v;
763 int ret;
764
765 ret = !(ins->forw_ref && ins->oprs[op].opflags) && /* dead in the water on forward reference or External */
766 optimizing >= 0 &&
767 !(ins->oprs[op].type & STRICT) &&
768 ins->oprs[op].wrt == NO_SEG && ins->oprs[op].segment == NO_SEG;
769
770 v = ins->oprs[op].offset;
771 if (size == 16)
772 v = (int16_t)v; /* sign extend if 16 bits */
773
774 return ret && v >= -128L && v <= 127L;
775 }
776
777 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
778 insn * ins, const char *codes)
779 {
780 int64_t length = 0;
781 uint8_t c;
782 int rex_mask = ~0;
783 struct operand *opx;
784
785 ins->rex = 0; /* Ensure REX is reset */
786
787 if (ins->prefixes[PPS_OSIZE] == P_O64)
788 ins->rex |= REX_W;
789
790 (void)segment; /* Don't warn that this parameter is unused */
791 (void)offset; /* Don't warn that this parameter is unused */
792
793 while (*codes) {
794 c = *codes++;
795 opx = &ins->oprs[c & 3];
796 switch (c) {
797 case 01:
798 case 02:
799 case 03:
800 codes += c, length += c;
801 break;
802 case 04:
803 case 05:
804 case 06:
805 case 07:
806 length++;
807 break;
808 case 010:
809 case 011:
810 case 012:
811 case 013:
812 ins->rex |=
813 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
814 codes++, length++;
815 break;
816 case 014:
817 case 015:
818 case 016:
819 case 017:
820 length++;
821 break;
822 case 020:
823 case 021:
824 case 022:
825 case 023:
826 length++;
827 break;
828 case 024:
829 case 025:
830 case 026:
831 case 027:
832 length++;
833 break;
834 case 030:
835 case 031:
836 case 032:
837 case 033:
838 length += 2;
839 break;
840 case 034:
841 case 035:
842 case 036:
843 case 037:
844 if (opx->type & (BITS16 | BITS32 | BITS64))
845 length += (opx->type & BITS16) ? 2 : 4;
846 else
847 length += (bits == 16) ? 2 : 4;
848 break;
849 case 040:
850 case 041:
851 case 042:
852 case 043:
853 length += 4;
854 break;
855 case 044:
856 case 045:
857 case 046:
858 case 047:
859 length += ins->addr_size >> 3;
860 break;
861 case 050:
862 case 051:
863 case 052:
864 case 053:
865 length++;
866 break;
867 case 054:
868 case 055:
869 case 056:
870 case 057:
871 length += 8; /* MOV reg64/imm */
872 break;
873 case 060:
874 case 061:
875 case 062:
876 case 063:
877 length += 2;
878 break;
879 case 064:
880 case 065:
881 case 066:
882 case 067:
883 if (opx->type & (BITS16 | BITS32 | BITS64))
884 length += (opx->type & BITS16) ? 2 : 4;
885 else
886 length += (bits == 16) ? 2 : 4;
887 break;
888 case 070:
889 case 071:
890 case 072:
891 case 073:
892 length += 4;
893 break;
894 case 074:
895 case 075:
896 case 076:
897 case 077:
898 length += 2;
899 break;
900 case 0140:
901 case 0141:
902 case 0142:
903 case 0143:
904 length += is_sbyte(ins, c & 3, 16) ? 1 : 2;
905 break;
906 case 0144:
907 case 0145:
908 case 0146:
909 case 0147:
910 codes += 2;
911 length++;
912 break;
913 case 0150:
914 case 0151:
915 case 0152:
916 case 0153:
917 length += is_sbyte(ins, c & 3, 32) ? 1 : 4;
918 break;
919 case 0154:
920 case 0155:
921 case 0156:
922 case 0157:
923 codes += 2;
924 length++;
925 break;
926 case 0160:
927 case 0161:
928 case 0162:
929 case 0163:
930 length++;
931 ins->rex |= REX_D;
932 ins->drexdst = regval(&ins->oprs[c & 3]);
933 break;
934 case 0164:
935 case 0165:
936 case 0166:
937 case 0167:
938 length++;
939 ins->rex |= REX_D|REX_OC;
940 ins->drexdst = regval(&ins->oprs[c & 3]);
941 break;
942 case 0170:
943 length++;
944 break;
945 case 0171:
946 break;
947 case 0300:
948 case 0301:
949 case 0302:
950 case 0303:
951 break;
952 case 0310:
953 if (bits == 64)
954 return -1;
955 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
956 break;
957 case 0311:
958 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
959 break;
960 case 0312:
961 break;
962 case 0313:
963 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
964 has_prefix(ins, PPS_ASIZE, P_A32))
965 return -1;
966 break;
967 case 0314:
968 case 0315:
969 case 0316:
970 case 0317:
971 break;
972 case 0320:
973 length += (bits != 16);
974 break;
975 case 0321:
976 length += (bits == 16);
977 break;
978 case 0322:
979 break;
980 case 0323:
981 rex_mask &= ~REX_W;
982 break;
983 case 0324:
984 ins->rex |= REX_W;
985 break;
986 case 0330:
987 codes++, length++;
988 break;
989 case 0331:
990 break;
991 case 0332:
992 case 0333:
993 length++;
994 break;
995 case 0334:
996 ins->rex |= REX_L;
997 break;
998 case 0335:
999 break;
1000 case 0340:
1001 case 0341:
1002 case 0342:
1003 if (ins->oprs[0].segment != NO_SEG)
1004 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1005 " quantity of BSS space");
1006 else
1007 length += ins->oprs[0].offset << (c & 3);
1008 break;
1009 case 0364:
1010 case 0365:
1011 break;
1012 case 0366:
1013 case 0367:
1014 length++;
1015 break;
1016 case 0370:
1017 case 0371:
1018 case 0372:
1019 break;
1020 case 0373:
1021 length++;
1022 break;
1023 default: /* can't do it by 'case' statements */
1024 if (c >= 0100 && c <= 0277) { /* it's an EA */
1025 ea ea_data;
1026 int rfield;
1027 int32_t rflags;
1028 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1029
1030 if (c <= 0177) {
1031 /* pick rfield from operand b */
1032 rflags = regflag(&ins->oprs[c & 7]);
1033 rfield = regvals[ins->oprs[c & 7].basereg];
1034 } else {
1035 rflags = 0;
1036 rfield = c & 7;
1037 }
1038
1039 if (!process_ea
1040 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1041 ins->addr_size, rfield, rflags, ins->forw_ref)) {
1042 errfunc(ERR_NONFATAL, "invalid effective address");
1043 return -1;
1044 } else {
1045 ins->rex |= ea_data.rex;
1046 length += ea_data.size;
1047 }
1048 } else {
1049 errfunc(ERR_PANIC, "internal instruction table corrupt"
1050 ": instruction code 0x%02X given", c);
1051 }
1052 }
1053 }
1054
1055 ins->rex &= rex_mask;
1056
1057 if (ins->rex & REX_D) {
1058 if (ins->rex & REX_H) {
1059 errfunc(ERR_NONFATAL, "cannot use high register in drex instruction");
1060 return -1;
1061 }
1062 if (bits != 64 && ((ins->rex & (REX_W|REX_X|REX_B)) ||
1063 ins->drexdst > 7)) {
1064 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1065 return -1;
1066 }
1067 length++;
1068 } else if (ins->rex & REX_REAL) {
1069 if (ins->rex & REX_H) {
1070 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1071 return -1;
1072 } else if (bits == 64) {
1073 length++;
1074 } else if ((ins->rex & REX_L) &&
1075 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1076 cpu >= IF_X86_64) {
1077 /* LOCK-as-REX.R */
1078 assert_no_prefix(ins, PPS_LREP);
1079 length++;
1080 } else {
1081 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1082 return -1;
1083 }
1084 }
1085
1086 return length;
1087 }
1088
1089 #define EMIT_REX() \
1090 if (!(ins->rex & REX_D) && (ins->rex & REX_REAL) && (bits == 64)) { \
1091 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1092 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1093 ins->rex = 0; \
1094 offset += 1; \
1095 }
1096
1097 static void gencode(int32_t segment, int64_t offset, int bits,
1098 insn * ins, const char *codes, int64_t insn_end)
1099 {
1100 static char condval[] = { /* conditional opcodes */
1101 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1102 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1103 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1104 };
1105 uint8_t c;
1106 uint8_t bytes[4];
1107 int64_t size;
1108 int64_t data;
1109 struct operand *opx;
1110
1111 while (*codes) {
1112 c = *codes++;
1113 opx = &ins->oprs[c & 3];
1114 switch (c) {
1115 case 01:
1116 case 02:
1117 case 03:
1118 EMIT_REX();
1119 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1120 codes += c;
1121 offset += c;
1122 break;
1123
1124 case 04:
1125 case 06:
1126 switch (ins->oprs[0].basereg) {
1127 case R_CS:
1128 bytes[0] = 0x0E + (c == 0x04 ? 1 : 0);
1129 break;
1130 case R_DS:
1131 bytes[0] = 0x1E + (c == 0x04 ? 1 : 0);
1132 break;
1133 case R_ES:
1134 bytes[0] = 0x06 + (c == 0x04 ? 1 : 0);
1135 break;
1136 case R_SS:
1137 bytes[0] = 0x16 + (c == 0x04 ? 1 : 0);
1138 break;
1139 default:
1140 errfunc(ERR_PANIC,
1141 "bizarre 8086 segment register received");
1142 }
1143 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1144 offset++;
1145 break;
1146
1147 case 05:
1148 case 07:
1149 switch (ins->oprs[0].basereg) {
1150 case R_FS:
1151 bytes[0] = 0xA0 + (c == 0x05 ? 1 : 0);
1152 break;
1153 case R_GS:
1154 bytes[0] = 0xA8 + (c == 0x05 ? 1 : 0);
1155 break;
1156 default:
1157 errfunc(ERR_PANIC,
1158 "bizarre 386 segment register received");
1159 }
1160 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1161 offset++;
1162 break;
1163
1164 case 010:
1165 case 011:
1166 case 012:
1167 case 013:
1168 EMIT_REX();
1169 bytes[0] = *codes++ + ((regval(opx)) & 7);
1170 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1171 offset += 1;
1172 break;
1173
1174 case 014:
1175 case 015:
1176 case 016:
1177 case 017:
1178 if (opx->offset < -128 || opx->offset > 127) {
1179 errfunc(ERR_WARNING, "signed byte value exceeds bounds");
1180 }
1181
1182 if (opx->segment != NO_SEG) {
1183 data = opx->offset;
1184 out(offset, segment, &data, OUT_ADDRESS, 1,
1185 opx->segment, opx->wrt);
1186 } else {
1187 bytes[0] = opx->offset;
1188 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1189 NO_SEG);
1190 }
1191 offset += 1;
1192 break;
1193
1194 case 020:
1195 case 021:
1196 case 022:
1197 case 023:
1198 if (opx->offset < -256 || opx->offset > 255) {
1199 errfunc(ERR_WARNING, "byte value exceeds bounds");
1200 }
1201 if (opx->segment != NO_SEG) {
1202 data = opx->offset;
1203 out(offset, segment, &data, OUT_ADDRESS, 1,
1204 opx->segment, opx->wrt);
1205 } else {
1206 bytes[0] = opx->offset;
1207 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1208 NO_SEG);
1209 }
1210 offset += 1;
1211 break;
1212
1213 case 024:
1214 case 025:
1215 case 026:
1216 case 027:
1217 if (opx->offset < 0 || opx->offset > 255)
1218 errfunc(ERR_WARNING, "unsigned byte value exceeds bounds");
1219 if (opx->segment != NO_SEG) {
1220 data = opx->offset;
1221 out(offset, segment, &data, OUT_ADDRESS, 1,
1222 opx->segment, opx->wrt);
1223 } else {
1224 bytes[0] = opx->offset;
1225 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1226 NO_SEG);
1227 }
1228 offset += 1;
1229 break;
1230
1231 case 030:
1232 case 031:
1233 case 032:
1234 case 033:
1235 data = opx->offset;
1236 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1237 warn_overflow(2, data);
1238 out(offset, segment, &data, OUT_ADDRESS, 2,
1239 opx->segment, opx->wrt);
1240 offset += 2;
1241 break;
1242
1243 case 034:
1244 case 035:
1245 case 036:
1246 case 037:
1247 if (opx->type & (BITS16 | BITS32))
1248 size = (opx->type & BITS16) ? 2 : 4;
1249 else
1250 size = (bits == 16) ? 2 : 4;
1251 data = opx->offset;
1252 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1253 warn_overflow(size, data);
1254 out(offset, segment, &data, OUT_ADDRESS, size,
1255 opx->segment, opx->wrt);
1256 offset += size;
1257 break;
1258
1259 case 040:
1260 case 041:
1261 case 042:
1262 case 043:
1263 data = opx->offset;
1264 out(offset, segment, &data, OUT_ADDRESS, 4,
1265 opx->segment, opx->wrt);
1266 offset += 4;
1267 break;
1268
1269 case 044:
1270 case 045:
1271 case 046:
1272 case 047:
1273 data = opx->offset;
1274 size = ins->addr_size >> 3;
1275 if (opx->segment == NO_SEG &&
1276 opx->wrt == NO_SEG)
1277 warn_overflow(size, data);
1278 out(offset, segment, &data, OUT_ADDRESS, size,
1279 opx->segment, opx->wrt);
1280 offset += size;
1281 break;
1282
1283 case 050:
1284 case 051:
1285 case 052:
1286 case 053:
1287 if (opx->segment != segment)
1288 errfunc(ERR_NONFATAL,
1289 "short relative jump outside segment");
1290 data = opx->offset - insn_end;
1291 if (data > 127 || data < -128)
1292 errfunc(ERR_NONFATAL, "short jump is out of range");
1293 bytes[0] = data;
1294 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1295 offset += 1;
1296 break;
1297
1298 case 054:
1299 case 055:
1300 case 056:
1301 case 057:
1302 data = (int64_t)opx->offset;
1303 out(offset, segment, &data, OUT_ADDRESS, 8,
1304 opx->segment, opx->wrt);
1305 offset += 8;
1306 break;
1307
1308 case 060:
1309 case 061:
1310 case 062:
1311 case 063:
1312 if (opx->segment != segment) {
1313 data = opx->offset;
1314 out(offset, segment, &data,
1315 OUT_REL2ADR, insn_end - offset,
1316 opx->segment, opx->wrt);
1317 } else {
1318 data = opx->offset - insn_end;
1319 out(offset, segment, &data,
1320 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1321 }
1322 offset += 2;
1323 break;
1324
1325 case 064:
1326 case 065:
1327 case 066:
1328 case 067:
1329 if (opx->type & (BITS16 | BITS32 | BITS64))
1330 size = (opx->type & BITS16) ? 2 : 4;
1331 else
1332 size = (bits == 16) ? 2 : 4;
1333 if (opx->segment != segment) {
1334 data = opx->offset;
1335 out(offset, segment, &data,
1336 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1337 insn_end - offset, opx->segment, opx->wrt);
1338 } else {
1339 data = opx->offset - insn_end;
1340 out(offset, segment, &data,
1341 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1342 }
1343 offset += size;
1344 break;
1345
1346 case 070:
1347 case 071:
1348 case 072:
1349 case 073:
1350 if (opx->segment != segment) {
1351 data = opx->offset;
1352 out(offset, segment, &data,
1353 OUT_REL4ADR, insn_end - offset,
1354 opx->segment, opx->wrt);
1355 } else {
1356 data = opx->offset - insn_end;
1357 out(offset, segment, &data,
1358 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1359 }
1360 offset += 4;
1361 break;
1362
1363 case 074:
1364 case 075:
1365 case 076:
1366 case 077:
1367 if (opx->segment == NO_SEG)
1368 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1369 " relocatable");
1370 data = 0L;
1371 out(offset, segment, &data, OUT_ADDRESS, 2,
1372 outfmt->segbase(1 + opx->segment),
1373 opx->wrt);
1374 offset += 2;
1375 break;
1376
1377 case 0140:
1378 case 0141:
1379 case 0142:
1380 case 0143:
1381 data = opx->offset;
1382 if (is_sbyte(ins, c & 3, 16)) {
1383 bytes[0] = data;
1384 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1385 NO_SEG);
1386 offset++;
1387 } else {
1388 if (opx->segment == NO_SEG &&
1389 opx->wrt == NO_SEG)
1390 warn_overflow(2, data);
1391 out(offset, segment, &data, OUT_ADDRESS, 2,
1392 opx->segment, opx->wrt);
1393 offset += 2;
1394 }
1395 break;
1396
1397 case 0144:
1398 case 0145:
1399 case 0146:
1400 case 0147:
1401 EMIT_REX();
1402 codes++;
1403 bytes[0] = *codes++;
1404 if (is_sbyte(ins, c & 3, 16))
1405 bytes[0] |= 2; /* s-bit */
1406 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1407 offset++;
1408 break;
1409
1410 case 0150:
1411 case 0151:
1412 case 0152:
1413 case 0153:
1414 data = opx->offset;
1415 if (is_sbyte(ins, c & 3, 32)) {
1416 bytes[0] = data;
1417 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1418 NO_SEG);
1419 offset++;
1420 } else {
1421 out(offset, segment, &data, OUT_ADDRESS, 4,
1422 opx->segment, opx->wrt);
1423 offset += 4;
1424 }
1425 break;
1426
1427 case 0154:
1428 case 0155:
1429 case 0156:
1430 case 0157:
1431 EMIT_REX();
1432 codes++;
1433 bytes[0] = *codes++;
1434 if (is_sbyte(ins, c & 3, 32))
1435 bytes[0] |= 2; /* s-bit */
1436 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1437 offset++;
1438 break;
1439
1440 case 0160:
1441 case 0161:
1442 case 0162:
1443 case 0163:
1444 case 0164:
1445 case 0165:
1446 case 0166:
1447 case 0167:
1448 break;
1449
1450 case 0170:
1451 EMIT_REX();
1452 bytes[0] = 0;
1453 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1454 offset += 1;
1455 break;
1456
1457 case 0171:
1458 bytes[0] =
1459 (ins->drexdst << 4) |
1460 (ins->rex & REX_OC ? 0x08 : 0) |
1461 (ins->rex & (REX_R|REX_X|REX_B));
1462 ins->rex = 0;
1463 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1464 offset++;
1465 break;
1466
1467 case 0300:
1468 case 0301:
1469 case 0302:
1470 case 0303:
1471 break;
1472
1473 case 0310:
1474 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1475 *bytes = 0x67;
1476 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1477 offset += 1;
1478 } else
1479 offset += 0;
1480 break;
1481
1482 case 0311:
1483 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1484 *bytes = 0x67;
1485 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1486 offset += 1;
1487 } else
1488 offset += 0;
1489 break;
1490
1491 case 0312:
1492 break;
1493
1494 case 0313:
1495 ins->rex = 0;
1496 break;
1497
1498 case 0314:
1499 case 0315:
1500 case 0316:
1501 case 0317:
1502 break;
1503
1504 case 0320:
1505 if (bits != 16) {
1506 *bytes = 0x66;
1507 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1508 offset += 1;
1509 } else
1510 offset += 0;
1511 break;
1512
1513 case 0321:
1514 if (bits == 16) {
1515 *bytes = 0x66;
1516 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1517 offset += 1;
1518 } else
1519 offset += 0;
1520 break;
1521
1522 case 0322:
1523 case 0323:
1524 break;
1525
1526 case 0324:
1527 ins->rex |= REX_W;
1528 break;
1529
1530 case 0330:
1531 *bytes = *codes++ ^ condval[ins->condition];
1532 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1533 offset += 1;
1534 break;
1535
1536 case 0331:
1537 break;
1538
1539 case 0332:
1540 case 0333:
1541 *bytes = c - 0332 + 0xF2;
1542 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1543 offset += 1;
1544 break;
1545
1546 case 0334:
1547 if (ins->rex & REX_R) {
1548 *bytes = 0xF0;
1549 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1550 offset += 1;
1551 }
1552 ins->rex &= ~(REX_L|REX_R);
1553 break;
1554
1555 case 0335:
1556 break;
1557
1558 case 0340:
1559 case 0341:
1560 case 0342:
1561 if (ins->oprs[0].segment != NO_SEG)
1562 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1563 else {
1564 int64_t size = ins->oprs[0].offset << (c & 3);
1565 if (size > 0)
1566 out(offset, segment, NULL,
1567 OUT_RESERVE, size, NO_SEG, NO_SEG);
1568 offset += size;
1569 }
1570 break;
1571
1572 case 0364:
1573 case 0365:
1574 break;
1575
1576 case 0366:
1577 case 0367:
1578 *bytes = c - 0366 + 0x66;
1579 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1580 offset += 1;
1581 break;
1582
1583 case 0370:
1584 case 0371:
1585 case 0372:
1586 break;
1587
1588 case 0373:
1589 *bytes = bits == 16 ? 3 : 5;
1590 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1591 offset += 1;
1592 break;
1593
1594 default: /* can't do it by 'case' statements */
1595 if (c >= 0100 && c <= 0277) { /* it's an EA */
1596 ea ea_data;
1597 int rfield;
1598 int32_t rflags;
1599 uint8_t *p;
1600 int32_t s;
1601
1602 if (c <= 0177) {
1603 /* pick rfield from operand b */
1604 rflags = regflag(&ins->oprs[c & 7]);
1605 rfield = regvals[ins->oprs[c & 7].basereg];
1606 } else {
1607 /* rfield is constant */
1608 rflags = 0;
1609 rfield = c & 7;
1610 }
1611
1612 if (!process_ea
1613 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1614 ins->addr_size, rfield, rflags, ins->forw_ref)) {
1615 errfunc(ERR_NONFATAL, "invalid effective address");
1616 }
1617
1618
1619 p = bytes;
1620 *p++ = ea_data.modrm;
1621 if (ea_data.sib_present)
1622 *p++ = ea_data.sib;
1623
1624 /* DREX suffixes come between the SIB and the displacement */
1625 if (ins->rex & REX_D) {
1626 *p++ =
1627 (ins->drexdst << 4) |
1628 (ins->rex & REX_OC ? 0x08 : 0) |
1629 (ins->rex & (REX_R|REX_X|REX_B));
1630 ins->rex = 0;
1631 }
1632
1633 s = p - bytes;
1634 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1635
1636 switch (ea_data.bytes) {
1637 case 0:
1638 break;
1639 case 1:
1640 if (ins->oprs[(c >> 3) & 7].segment != NO_SEG) {
1641 data = ins->oprs[(c >> 3) & 7].offset;
1642 out(offset, segment, &data, OUT_ADDRESS, 1,
1643 ins->oprs[(c >> 3) & 7].segment,
1644 ins->oprs[(c >> 3) & 7].wrt);
1645 } else {
1646 *bytes = ins->oprs[(c >> 3) & 7].offset;
1647 out(offset, segment, bytes, OUT_RAWDATA, 1,
1648 NO_SEG, NO_SEG);
1649 }
1650 s++;
1651 break;
1652 case 8:
1653 case 2:
1654 case 4:
1655 data = ins->oprs[(c >> 3) & 7].offset;
1656 warn_overflow(ea_data.bytes, data);
1657 out(offset, segment, &data,
1658 ea_data.rip ? OUT_REL4ADR : OUT_ADDRESS,
1659 ea_data.bytes,
1660 ins->oprs[(c >> 3) & 7].segment,
1661 ins->oprs[(c >> 3) & 7].wrt);
1662 s += ea_data.bytes;
1663 break;
1664 }
1665 offset += s;
1666 } else {
1667 errfunc(ERR_PANIC, "internal instruction table corrupt"
1668 ": instruction code 0x%02X given", c);
1669 }
1670 }
1671 }
1672 }
1673
1674 static int32_t regflag(const operand * o)
1675 {
1676 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1677 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1678 }
1679 return reg_flags[o->basereg];
1680 }
1681
1682 static int32_t regval(const operand * o)
1683 {
1684 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1685 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1686 }
1687 return regvals[o->basereg];
1688 }
1689
1690 static int op_rexflags(const operand * o, int mask)
1691 {
1692 int32_t flags;
1693 int val;
1694
1695 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1696 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1697 }
1698
1699 flags = reg_flags[o->basereg];
1700 val = regvals[o->basereg];
1701
1702 return rexflags(val, flags, mask);
1703 }
1704
1705 static int rexflags(int val, int32_t flags, int mask)
1706 {
1707 int rex = 0;
1708
1709 if (val >= 8)
1710 rex |= REX_B|REX_X|REX_R;
1711 if (flags & BITS64)
1712 rex |= REX_W;
1713 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1714 rex |= REX_H;
1715 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1716 rex |= REX_P;
1717
1718 return rex & mask;
1719 }
1720
1721 static int matches(const struct itemplate *itemp, insn * instruction, int bits)
1722 {
1723 int i, size[MAX_OPERANDS], asize, oprs, ret;
1724
1725 ret = 100;
1726
1727 /*
1728 * Check the opcode
1729 */
1730 if (itemp->opcode != instruction->opcode)
1731 return 0;
1732
1733 /*
1734 * Count the operands
1735 */
1736 if (itemp->operands != instruction->operands)
1737 return 0;
1738
1739 /*
1740 * Check that no spurious colons or TOs are present
1741 */
1742 for (i = 0; i < itemp->operands; i++)
1743 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1744 return 0;
1745
1746 /*
1747 * Check that the operand flags all match up
1748 */
1749 for (i = 0; i < itemp->operands; i++) {
1750 if (itemp->opd[i] & SAME_AS) {
1751 int j = itemp->opd[i] & ~SAME_AS;
1752 if (instruction->oprs[i].type != instruction->oprs[j].type ||
1753 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
1754 return 0;
1755 } else if (itemp->opd[i] & ~instruction->oprs[i].type ||
1756 ((itemp->opd[i] & SIZE_MASK) &&
1757 ((itemp->opd[i] ^ instruction->oprs[i].type) & SIZE_MASK))) {
1758 if ((itemp->opd[i] & ~instruction->oprs[i].type & ~SIZE_MASK) ||
1759 (instruction->oprs[i].type & SIZE_MASK))
1760 return 0;
1761 else
1762 return 1;
1763 }
1764 }
1765
1766 /*
1767 * Check operand sizes
1768 */
1769 if (itemp->flags & IF_ARMASK) {
1770 memset(size, 0, sizeof size);
1771
1772 switch (itemp->flags & IF_ARMASK) {
1773 case IF_AR0:
1774 i = 0;
1775 break;
1776 case IF_AR1:
1777 i = 1;
1778 break;
1779 case IF_AR2:
1780 i = 2;
1781 break;
1782 case IF_AR3:
1783 i = 3;
1784 break;
1785 default:
1786 break; /* Shouldn't happen */
1787 }
1788 switch (itemp->flags & IF_SMASK) {
1789 case IF_SB:
1790 size[i] = BITS8;
1791 break;
1792 case IF_SW:
1793 size[i] = BITS16;
1794 break;
1795 case IF_SD:
1796 size[i] = BITS32;
1797 break;
1798 case IF_SQ:
1799 size[i] = BITS64;
1800 break;
1801 case IF_SO:
1802 size[i] = BITS128;
1803 break;
1804 default:
1805 break;
1806 }
1807 } else {
1808 asize = 0;
1809 switch (itemp->flags & IF_SMASK) {
1810 case IF_SB:
1811 asize = BITS8;
1812 oprs = itemp->operands;
1813 break;
1814 case IF_SW:
1815 asize = BITS16;
1816 oprs = itemp->operands;
1817 break;
1818 case IF_SD:
1819 asize = BITS32;
1820 oprs = itemp->operands;
1821 break;
1822 case IF_SQ:
1823 asize = BITS64;
1824 oprs = itemp->operands;
1825 break;
1826 case IF_SO:
1827 asize = BITS128;
1828 oprs = itemp->operands;
1829 break;
1830 default:
1831 break;
1832 }
1833 for (i = 0; i < MAX_OPERANDS; i++)
1834 size[i] = asize;
1835 }
1836
1837 if (itemp->flags & (IF_SM | IF_SM2)) {
1838 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
1839 asize = 0;
1840 for (i = 0; i < oprs; i++) {
1841 if ((asize = itemp->opd[i] & SIZE_MASK) != 0) {
1842 int j;
1843 for (j = 0; j < oprs; j++)
1844 size[j] = asize;
1845 break;
1846 }
1847 }
1848 } else {
1849 oprs = itemp->operands;
1850 }
1851
1852 for (i = 0; i < itemp->operands; i++) {
1853 if (!(itemp->opd[i] & SIZE_MASK) &&
1854 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
1855 return 2;
1856 }
1857
1858 /*
1859 * Check template is okay at the set cpu level
1860 */
1861 if (((itemp->flags & IF_PLEVEL) > cpu))
1862 return 3;
1863
1864 /*
1865 * Check if instruction is available in long mode
1866 */
1867 if ((itemp->flags & IF_NOLONG) && (bits == 64))
1868 return 4;
1869
1870 /*
1871 * Check if special handling needed for Jumps
1872 */
1873 if ((uint8_t)(itemp->code[0]) >= 0370)
1874 return 99;
1875
1876 return ret;
1877 }
1878
1879 static ea *process_ea(operand * input, ea * output, int bits,
1880 int addrbits, int rfield, int32_t rflags, int forw_ref)
1881 {
1882 output->rip = false;
1883
1884 /* REX flags for the rfield operand */
1885 output->rex |= rexflags(rfield, rflags, REX_R|REX_P|REX_W|REX_H);
1886
1887 if (!(REGISTER & ~input->type)) { /* register direct */
1888 int i;
1889 int32_t f;
1890
1891 if (input->basereg < EXPR_REG_START /* Verify as Register */
1892 || input->basereg >= REG_ENUM_LIMIT)
1893 return NULL;
1894 f = regflag(input);
1895 i = regvals[input->basereg];
1896
1897 if (REG_EA & ~f)
1898 return NULL; /* Invalid EA register */
1899
1900 output->rex |= op_rexflags(input, REX_B|REX_P|REX_W|REX_H);
1901
1902 output->sib_present = false; /* no SIB necessary */
1903 output->bytes = 0; /* no offset necessary either */
1904 output->modrm = 0xC0 | ((rfield & 7) << 3) | (i & 7);
1905 } else { /* it's a memory reference */
1906 if (input->basereg == -1
1907 && (input->indexreg == -1 || input->scale == 0)) {
1908 /* it's a pure offset */
1909 if (bits == 64 && (~input->type & IP_REL)) {
1910 int scale, index, base;
1911 output->sib_present = true;
1912 scale = 0;
1913 index = 4;
1914 base = 5;
1915 output->sib = (scale << 6) | (index << 3) | base;
1916 output->bytes = 4;
1917 output->modrm = 4 | ((rfield & 7) << 3);
1918 output->rip = false;
1919 } else {
1920 output->sib_present = false;
1921 output->bytes = (addrbits != 16 ? 4 : 2);
1922 output->modrm = (addrbits != 16 ? 5 : 6) | ((rfield & 7) << 3);
1923 output->rip = bits == 64;
1924 }
1925 } else { /* it's an indirection */
1926 int i = input->indexreg, b = input->basereg, s = input->scale;
1927 int32_t o = input->offset, seg = input->segment;
1928 int hb = input->hintbase, ht = input->hinttype;
1929 int t;
1930 int it, bt;
1931 int32_t ix, bx; /* register flags */
1932
1933 if (s == 0)
1934 i = -1; /* make this easy, at least */
1935
1936 if (i >= EXPR_REG_START && i < REG_ENUM_LIMIT) {
1937 it = regvals[i];
1938 ix = reg_flags[i];
1939 } else {
1940 it = -1;
1941 ix = 0;
1942 }
1943
1944 if (b >= EXPR_REG_START && b < REG_ENUM_LIMIT) {
1945 bt = regvals[b];
1946 bx = reg_flags[b];
1947 } else {
1948 bt = -1;
1949 bx = 0;
1950 }
1951
1952 /* check for a 32/64-bit memory reference... */
1953 if ((ix|bx) & (BITS32|BITS64)) {
1954 /* it must be a 32/64-bit memory reference. Firstly we have
1955 * to check that all registers involved are type E/Rxx. */
1956 int32_t sok = BITS32|BITS64;
1957
1958 if (it != -1) {
1959 if (!(REG64 & ~ix) || !(REG32 & ~ix))
1960 sok &= ix;
1961 else
1962 return NULL;
1963 }
1964
1965 if (bt != -1) {
1966 if (REG_GPR & ~bx)
1967 return NULL; /* Invalid register */
1968 if (~sok & bx & SIZE_MASK)
1969 return NULL; /* Invalid size */
1970 sok &= bx;
1971 }
1972
1973 /* While we're here, ensure the user didn't specify
1974 WORD or QWORD. */
1975 if (input->disp_size == 16 || input->disp_size == 64)
1976 return NULL;
1977
1978 if (addrbits == 16 ||
1979 (addrbits == 32 && !(sok & BITS32)) ||
1980 (addrbits == 64 && !(sok & BITS64)))
1981 return NULL;
1982
1983 /* now reorganize base/index */
1984 if (s == 1 && bt != it && bt != -1 && it != -1 &&
1985 ((hb == b && ht == EAH_NOTBASE)
1986 || (hb == i && ht == EAH_MAKEBASE))) {
1987 /* swap if hints say so */
1988 t = bt, bt = it, it = t;
1989 t = bx, bx = ix, ix = t;
1990 }
1991 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
1992 bt = -1, bx = 0, s++;
1993 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
1994 /* make single reg base, unless hint */
1995 bt = it, bx = ix, it = -1, ix = 0;
1996 }
1997 if (((s == 2 && it != REG_NUM_ESP
1998 && !(input->eaflags & EAF_TIMESTWO)) || s == 3
1999 || s == 5 || s == 9) && bt == -1)
2000 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2001 if (it == -1 && (bt & 7) != REG_NUM_ESP
2002 && (input->eaflags & EAF_TIMESTWO))
2003 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2004 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2005 if (s == 1 && it == REG_NUM_ESP) {
2006 /* swap ESP into base if scale is 1 */
2007 t = it, it = bt, bt = t;
2008 t = ix, ix = bx, bx = t;
2009 }
2010 if (it == REG_NUM_ESP
2011 || (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2012 return NULL; /* wrong, for various reasons */
2013
2014 output->rex |= rexflags(it, ix, REX_X);
2015 output->rex |= rexflags(bt, bx, REX_B);
2016
2017 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2018 /* no SIB needed */
2019 int mod, rm;
2020
2021 if (bt == -1) {
2022 rm = 5;
2023 mod = 0;
2024 } else {
2025 rm = (bt & 7);
2026 if (rm != REG_NUM_EBP && o == 0 &&
2027 seg == NO_SEG && !forw_ref &&
2028 !(input->eaflags &
2029 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2030 mod = 0;
2031 else if (input->eaflags & EAF_BYTEOFFS ||
2032 (o >= -128 && o <= 127 && seg == NO_SEG
2033 && !forw_ref
2034 && !(input->eaflags & EAF_WORDOFFS)))
2035 mod = 1;
2036 else
2037 mod = 2;
2038 }
2039
2040 output->sib_present = false;
2041 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2042 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2043 } else {
2044 /* we need a SIB */
2045 int mod, scale, index, base;
2046
2047 if (it == -1)
2048 index = 4, s = 1;
2049 else
2050 index = (it & 7);
2051
2052 switch (s) {
2053 case 1:
2054 scale = 0;
2055 break;
2056 case 2:
2057 scale = 1;
2058 break;
2059 case 4:
2060 scale = 2;
2061 break;
2062 case 8:
2063 scale = 3;
2064 break;
2065 default: /* then what the smeg is it? */
2066 return NULL; /* panic */
2067 }
2068
2069 if (bt == -1) {
2070 base = 5;
2071 mod = 0;
2072 } else {
2073 base = (bt & 7);
2074 if (base != REG_NUM_EBP && o == 0 &&
2075 seg == NO_SEG && !forw_ref &&
2076 !(input->eaflags &
2077 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2078 mod = 0;
2079 else if (input->eaflags & EAF_BYTEOFFS ||
2080 (o >= -128 && o <= 127 && seg == NO_SEG
2081 && !forw_ref
2082 && !(input->eaflags & EAF_WORDOFFS)))
2083 mod = 1;
2084 else
2085 mod = 2;
2086 }
2087
2088 output->sib_present = true;
2089 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2090 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2091 output->sib = (scale << 6) | (index << 3) | base;
2092 }
2093 } else { /* it's 16-bit */
2094 int mod, rm;
2095
2096 /* check for 64-bit long mode */
2097 if (addrbits == 64)
2098 return NULL;
2099
2100 /* check all registers are BX, BP, SI or DI */
2101 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI
2102 && b != R_DI) || (i != -1 && i != R_BP && i != R_BX
2103 && i != R_SI && i != R_DI))
2104 return NULL;
2105
2106 /* ensure the user didn't specify DWORD/QWORD */
2107 if (input->disp_size == 32 || input->disp_size == 64)
2108 return NULL;
2109
2110 if (s != 1 && i != -1)
2111 return NULL; /* no can do, in 16-bit EA */
2112 if (b == -1 && i != -1) {
2113 int tmp = b;
2114 b = i;
2115 i = tmp;
2116 } /* swap */
2117 if ((b == R_SI || b == R_DI) && i != -1) {
2118 int tmp = b;
2119 b = i;
2120 i = tmp;
2121 }
2122 /* have BX/BP as base, SI/DI index */
2123 if (b == i)
2124 return NULL; /* shouldn't ever happen, in theory */
2125 if (i != -1 && b != -1 &&
2126 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2127 return NULL; /* invalid combinations */
2128 if (b == -1) /* pure offset: handled above */
2129 return NULL; /* so if it gets to here, panic! */
2130
2131 rm = -1;
2132 if (i != -1)
2133 switch (i * 256 + b) {
2134 case R_SI * 256 + R_BX:
2135 rm = 0;
2136 break;
2137 case R_DI * 256 + R_BX:
2138 rm = 1;
2139 break;
2140 case R_SI * 256 + R_BP:
2141 rm = 2;
2142 break;
2143 case R_DI * 256 + R_BP:
2144 rm = 3;
2145 break;
2146 } else
2147 switch (b) {
2148 case R_SI:
2149 rm = 4;
2150 break;
2151 case R_DI:
2152 rm = 5;
2153 break;
2154 case R_BP:
2155 rm = 6;
2156 break;
2157 case R_BX:
2158 rm = 7;
2159 break;
2160 }
2161 if (rm == -1) /* can't happen, in theory */
2162 return NULL; /* so panic if it does */
2163
2164 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2165 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2166 mod = 0;
2167 else if (input->eaflags & EAF_BYTEOFFS ||
2168 (o >= -128 && o <= 127 && seg == NO_SEG
2169 && !forw_ref
2170 && !(input->eaflags & EAF_WORDOFFS)))
2171 mod = 1;
2172 else
2173 mod = 2;
2174
2175 output->sib_present = false; /* no SIB - it's 16-bit */
2176 output->bytes = mod; /* bytes of offset needed */
2177 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2178 }
2179 }
2180 }
2181
2182 output->size = 1 + output->sib_present + output->bytes;
2183 return output;
2184 }
2185
2186 static void add_asp(insn *ins, int addrbits)
2187 {
2188 int j, valid;
2189 int defdisp;
2190
2191 valid = (addrbits == 64) ? 64|32 : 32|16;
2192
2193 switch (ins->prefixes[PPS_ASIZE]) {
2194 case P_A16:
2195 valid &= 16;
2196 break;
2197 case P_A32:
2198 valid &= 32;
2199 break;
2200 case P_A64:
2201 valid &= 64;
2202 break;
2203 case P_ASP:
2204 valid &= (addrbits == 32) ? 16 : 32;
2205 break;
2206 default:
2207 break;
2208 }
2209
2210 for (j = 0; j < ins->operands; j++) {
2211 if (!(MEMORY & ~ins->oprs[j].type)) {
2212 int32_t i, b;
2213
2214 /* Verify as Register */
2215 if (ins->oprs[j].indexreg < EXPR_REG_START
2216 || ins->oprs[j].indexreg >= REG_ENUM_LIMIT)
2217 i = 0;
2218 else
2219 i = reg_flags[ins->oprs[j].indexreg];
2220
2221 /* Verify as Register */
2222 if (ins->oprs[j].basereg < EXPR_REG_START
2223 || ins->oprs[j].basereg >= REG_ENUM_LIMIT)
2224 b = 0;
2225 else
2226 b = reg_flags[ins->oprs[j].basereg];
2227
2228 if (ins->oprs[j].scale == 0)
2229 i = 0;
2230
2231 if (!i && !b) {
2232 int ds = ins->oprs[j].disp_size;
2233 if ((addrbits != 64 && ds > 8) ||
2234 (addrbits == 64 && ds == 16))
2235 valid &= ds;
2236 } else {
2237 if (!(REG16 & ~b))
2238 valid &= 16;
2239 if (!(REG32 & ~b))
2240 valid &= 32;
2241 if (!(REG64 & ~b))
2242 valid &= 64;
2243
2244 if (!(REG16 & ~i))
2245 valid &= 16;
2246 if (!(REG32 & ~i))
2247 valid &= 32;
2248 if (!(REG64 & ~i))
2249 valid &= 64;
2250 }
2251 }
2252 }
2253
2254 if (valid & addrbits) {
2255 ins->addr_size = addrbits;
2256 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2257 /* Add an address size prefix */
2258 enum prefixes pref = (addrbits == 32) ? P_A16 : P_A32;
2259 ins->prefixes[PPS_ASIZE] = pref;
2260 ins->addr_size = (addrbits == 32) ? 16 : 32;
2261 } else {
2262 /* Impossible... */
2263 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2264 ins->addr_size = addrbits; /* Error recovery */
2265 }
2266
2267 defdisp = ins->addr_size == 16 ? 16 : 32;
2268
2269 for (j = 0; j < ins->operands; j++) {
2270 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2271 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp)
2272 != ins->addr_size) {
2273 /* mem_offs sizes must match the address size; if not,
2274 strip the MEM_OFFS bit and match only EA instructions */
2275 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2276 }
2277 }
2278 }
The Netwide Assembler