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Automatically make a specfile
[nasm.git] / disasm.c
blobacc6e3f8c1265a8fcd3b81b4224675a56d8125c0
1 /* disasm.c where all the _work_ gets done in the Netwide Disassembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the licence given in the file "Licence"
6 * distributed in the NASM archive.
7 *
8 * initial version 27/iii/95 by Simon Tatham
9 */
10
11 #include <stdio.h>
12 #include <string.h>
13
14 #include "nasm.h"
15 #include "disasm.h"
16 #include "sync.h"
17 #include "insns.h"
18
19 #include "names.c"
20
21 extern struct itemplate **itable[];
22
23 /*
24 * Flags that go into the `segment' field of `insn' structures
25 * during disassembly.
26 */
27 #define SEG_RELATIVE 1
28 #define SEG_32BIT 2
29 #define SEG_RMREG 4
30 #define SEG_DISP8 8
31 #define SEG_DISP16 16
32 #define SEG_DISP32 32
33 #define SEG_NODISP 64
34 #define SEG_SIGNED 128
35
36 static int whichreg(long regflags, int regval)
37 {
38 static int reg32[] = {
39 R_EAX, R_ECX, R_EDX, R_EBX, R_ESP, R_EBP, R_ESI, R_EDI };
40 static int reg16[] = {
41 R_AX, R_CX, R_DX, R_BX, R_SP, R_BP, R_SI, R_DI };
42 static int reg8[] = {
43 R_AL, R_CL, R_DL, R_BL, R_AH, R_CH, R_DH, R_BH };
44 static int sreg[] = {
45 R_ES, R_CS, R_SS, R_DS, R_FS, R_GS, 0, 0 };
46 static int creg[] = {
47 R_CR0, 0, R_CR2, R_CR3, R_CR4, 0, 0, 0 };
48 static int dreg[] = {
49 R_DR0, R_DR1, R_DR2, R_DR3, 0, 0, R_DR6, R_DR7 };
50 static int treg[] = {
51 0, 0, 0, R_TR3, R_TR4, R_TR5, R_TR6, R_TR7 };
52 static int fpureg[] = {
53 R_ST0, R_ST1, R_ST2, R_ST3, R_ST4, R_ST5, R_ST6, R_ST7 };
54 static int mmxreg[] = {
55 R_MM0, R_MM1, R_MM2, R_MM3, R_MM4, R_MM5, R_MM6, R_MM7 };
56 static int xmmreg[] = {
57 R_XMM0, R_XMM1, R_XMM2, R_XMM3, R_XMM4, R_XMM5, R_XMM6, R_XMM7 };
58
59 if (!(REG_AL & ~regflags))
60 return R_AL;
61 if (!(REG_AX & ~regflags))
62 return R_AX;
63 if (!(REG_EAX & ~regflags))
64 return R_EAX;
65 if (!(REG_DX & ~regflags))
66 return R_DX;
67 if (!(REG_CL & ~regflags))
68 return R_CL;
69 if (!(REG_CX & ~regflags))
70 return R_CX;
71 if (!(REG_ECX & ~regflags))
72 return R_ECX;
73 if (!(REG_CR4 & ~regflags))
74 return R_CR4;
75 if (!(FPU0 & ~regflags))
76 return R_ST0;
77 if (!(REG_CS & ~regflags))
78 return R_CS;
79 if (!(REG_DESS & ~regflags))
80 return (regval == 0 || regval == 2 || regval == 3 ? sreg[regval] : 0);
81 if (!(REG_FSGS & ~regflags))
82 return (regval == 4 || regval == 5 ? sreg[regval] : 0);
83 if (!((REGMEM|BITS8) & ~regflags))
84 return reg8[regval];
85 if (!((REGMEM|BITS16) & ~regflags))
86 return reg16[regval];
87 if (!((REGMEM|BITS32) & ~regflags))
88 return reg32[regval];
89 if (!(REG_SREG & ~regflags))
90 return sreg[regval];
91 if (!(REG_CREG & ~regflags))
92 return creg[regval];
93 if (!(REG_DREG & ~regflags))
94 return dreg[regval];
95 if (!(REG_TREG & ~regflags))
96 return treg[regval];
97 if (!(FPUREG & ~regflags))
98 return fpureg[regval];
99 if (!(MMXREG & ~regflags))
100 return mmxreg[regval];
101 if (!(XMMREG & ~regflags))
102 return xmmreg[regval];
103 return 0;
104 }
105
106 static char *whichcond(int condval)
107 {
108 static int conds[] = {
109 C_O, C_NO, C_C, C_NC, C_Z, C_NZ, C_NA, C_A,
110 C_S, C_NS, C_PE, C_PO, C_L, C_NL, C_NG, C_G
111 };
112 return conditions[conds[condval]];
113 }
114
115 /*
116 * Process an effective address (ModRM) specification.
117 */
118 static unsigned char *do_ea (unsigned char *data, int modrm, int asize,
119 int segsize, operand *op)
120 {
121 int mod, rm, scale, index, base;
122
123 mod = (modrm >> 6) & 03;
124 rm = modrm & 07;
125
126 if (mod == 3) { /* pure register version */
127 op->basereg = rm;
128 op->segment |= SEG_RMREG;
129 return data;
130 }
131
132 op->addr_size = 0;
133
134 if (asize == 16) {
135 /*
136 * <mod> specifies the displacement size (none, byte or
137 * word), and <rm> specifies the register combination.
138 * Exception: mod=0,rm=6 does not specify [BP] as one might
139 * expect, but instead specifies [disp16].
140 */
141 op->indexreg = op->basereg = -1;
142 op->scale = 1; /* always, in 16 bits */
143 switch (rm) {
144 case 0: op->basereg = R_BX; op->indexreg = R_SI; break;
145 case 1: op->basereg = R_BX; op->indexreg = R_DI; break;
146 case 2: op->basereg = R_BP; op->indexreg = R_SI; break;
147 case 3: op->basereg = R_BP; op->indexreg = R_DI; break;
148 case 4: op->basereg = R_SI; break;
149 case 5: op->basereg = R_DI; break;
150 case 6: op->basereg = R_BP; break;
151 case 7: op->basereg = R_BX; break;
152 }
153 if (rm == 6 && mod == 0) { /* special case */
154 op->basereg = -1;
155 if (segsize != 16)
156 op->addr_size = 16;
157 mod = 2; /* fake disp16 */
158 }
159 switch (mod) {
160 case 0:
161 op->segment |= SEG_NODISP;
162 break;
163 case 1:
164 op->segment |= SEG_DISP8;
165 op->offset = (signed char) *data++;
166 break;
167 case 2:
168 op->segment |= SEG_DISP16;
169 op->offset = *data++;
170 op->offset |= (*data++) << 8;
171 break;
172 }
173 return data;
174 } else {
175 /*
176 * Once again, <mod> specifies displacement size (this time
177 * none, byte or *dword*), while <rm> specifies the base
178 * register. Again, [EBP] is missing, replaced by a pure
179 * disp32 (this time that's mod=0,rm=*5*). However, rm=4
180 * indicates not a single base register, but instead the
181 * presence of a SIB byte...
182 */
183 op->indexreg = -1;
184 switch (rm) {
185 case 0: op->basereg = R_EAX; break;
186 case 1: op->basereg = R_ECX; break;
187 case 2: op->basereg = R_EDX; break;
188 case 3: op->basereg = R_EBX; break;
189 case 5: op->basereg = R_EBP; break;
190 case 6: op->basereg = R_ESI; break;
191 case 7: op->basereg = R_EDI; break;
192 }
193 if (rm == 5 && mod == 0) {
194 op->basereg = -1;
195 if (segsize != 32)
196 op->addr_size = 32;
197 mod = 2; /* fake disp32 */
198 }
199 if (rm == 4) { /* process SIB */
200 scale = (*data >> 6) & 03;
201 index = (*data >> 3) & 07;
202 base = *data & 07;
203 data++;
204
205 op->scale = 1 << scale;
206 switch (index) {
207 case 0: op->indexreg = R_EAX; break;
208 case 1: op->indexreg = R_ECX; break;
209 case 2: op->indexreg = R_EDX; break;
210 case 3: op->indexreg = R_EBX; break;
211 case 4: op->indexreg = -1; break;
212 case 5: op->indexreg = R_EBP; break;
213 case 6: op->indexreg = R_ESI; break;
214 case 7: op->indexreg = R_EDI; break;
215 }
216
217 switch (base) {
218 case 0: op->basereg = R_EAX; break;
219 case 1: op->basereg = R_ECX; break;
220 case 2: op->basereg = R_EDX; break;
221 case 3: op->basereg = R_EBX; break;
222 case 4: op->basereg = R_ESP; break;
223 case 6: op->basereg = R_ESI; break;
224 case 7: op->basereg = R_EDI; break;
225 case 5:
226 if (mod == 0) {
227 mod = 2;
228 op->basereg = -1;
229 } else
230 op->basereg = R_EBP;
231 break;
232 }
233 }
234 switch (mod) {
235 case 0:
236 op->segment |= SEG_NODISP;
237 break;
238 case 1:
239 op->segment |= SEG_DISP8;
240 op->offset = (signed char) *data++;
241 break;
242 case 2:
243 op->segment |= SEG_DISP32;
244 op->offset = *data++;
245 op->offset |= (*data++) << 8;
246 op->offset |= ((long) *data++) << 16;
247 op->offset |= ((long) *data++) << 24;
248 break;
249 }
250 return data;
251 }
252 }
253
254 /*
255 * Determine whether the instruction template in t corresponds to the data
256 * stream in data. Return the number of bytes matched if so.
257 */
258 static int matches (struct itemplate *t, unsigned char *data, int asize,
259 int osize, int segsize, int rep, insn *ins)
260 {
261 unsigned char * r = (unsigned char *)(t->code);
262 unsigned char * origdata = data;
263 int a_used = FALSE, o_used = FALSE;
264 int drep = 0;
265
266 if ( rep == 0xF2 )
267 drep = P_REPNE;
268 else if ( rep == 0xF3 )
269 drep = P_REP;
270
271 while (*r)
272 {
273 int c = *r++;
274 if (c >= 01 && c <= 03) {
275 while (c--)
276 if (*r++ != *data++)
277 return FALSE;
278 }
279 if (c == 04) {
280 switch (*data++) {
281 case 0x07: ins->oprs[0].basereg = 0; break;
282 case 0x17: ins->oprs[0].basereg = 2; break;
283 case 0x1F: ins->oprs[0].basereg = 3; break;
284 default: return FALSE;
285 }
286 }
287 if (c == 05) {
288 switch (*data++) {
289 case 0xA1: ins->oprs[0].basereg = 4; break;
290 case 0xA9: ins->oprs[0].basereg = 5; break;
291 default: return FALSE;
292 }
293 }
294 if (c == 06) {
295 switch (*data++) {
296 case 0x06: ins->oprs[0].basereg = 0; break;
297 case 0x0E: ins->oprs[0].basereg = 1; break;
298 case 0x16: ins->oprs[0].basereg = 2; break;
299 case 0x1E: ins->oprs[0].basereg = 3; break;
300 default: return FALSE;
301 }
302 }
303 if (c == 07) {
304 switch (*data++) {
305 case 0xA0: ins->oprs[0].basereg = 4; break;
306 case 0xA8: ins->oprs[0].basereg = 5; break;
307 default: return FALSE;
308 }
309 }
310 if (c >= 010 && c <= 012) {
311 int t = *r++, d = *data++;
312 if (d < t || d > t+7)
313 return FALSE;
314 else {
315 ins->oprs[c-010].basereg = d-t;
316 ins->oprs[c-010].segment |= SEG_RMREG;
317 }
318 }
319 if (c == 017)
320 if (*data++)
321 return FALSE;
322 if (c >= 014 && c <= 016) {
323 ins->oprs[c-014].offset = (signed char) *data++;
324 ins->oprs[c-014].segment |= SEG_SIGNED;
325 }
326 if (c >= 020 && c <= 022)
327 ins->oprs[c-020].offset = *data++;
328 if (c >= 024 && c <= 026)
329 ins->oprs[c-024].offset = *data++;
330 if (c >= 030 && c <= 032) {
331 ins->oprs[c-030].offset = *data++;
332 ins->oprs[c-030].offset |= (*data++ << 8);
333 }
334 if (c >= 034 && c <= 036) {
335 ins->oprs[c-034].offset = *data++;
336 ins->oprs[c-034].offset |= (*data++ << 8);
337 if (asize == 32) {
338 ins->oprs[c-034].offset |= (((long) *data++) << 16);
339 ins->oprs[c-034].offset |= (((long) *data++) << 24);
340 }
341 if (segsize != asize)
342 ins->oprs[c-034].addr_size = asize;
343 }
344 if (c >= 040 && c <= 042) {
345 ins->oprs[c-040].offset = *data++;
346 ins->oprs[c-040].offset |= (*data++ << 8);
347 ins->oprs[c-040].offset |= (((long) *data++) << 16);
348 ins->oprs[c-040].offset |= (((long) *data++) << 24);
349 }
350 if (c >= 050 && c <= 052) {
351 ins->oprs[c-050].offset = (signed char) *data++;
352 ins->oprs[c-050].segment |= SEG_RELATIVE;
353 }
354 if (c >= 060 && c <= 062) {
355 ins->oprs[c-060].offset = *data++;
356 ins->oprs[c-060].offset |= (*data++ << 8);
357 ins->oprs[c-060].segment |= SEG_RELATIVE;
358 ins->oprs[c-060].segment &= ~SEG_32BIT;
359 }
360 if (c >= 064 && c <= 066) {
361 ins->oprs[c-064].offset = *data++;
362 ins->oprs[c-064].offset |= (*data++ << 8);
363 if (osize == 32) {
364 ins->oprs[c-064].offset |= (((long) *data++) << 16);
365 ins->oprs[c-064].offset |= (((long) *data++) << 24);
366 ins->oprs[c-064].segment |= SEG_32BIT;
367 } else
368 ins->oprs[c-064].segment &= ~SEG_32BIT;
369 ins->oprs[c-064].segment |= SEG_RELATIVE;
370 if (segsize != osize) {
371 ins->oprs[c-064].type =
372 (ins->oprs[c-064].type & NON_SIZE)
373 | ((osize == 16) ? BITS16 : BITS32);
374 }
375 }
376 if (c >= 070 && c <= 072) {
377 ins->oprs[c-070].offset = *data++;
378 ins->oprs[c-070].offset |= (*data++ << 8);
379 ins->oprs[c-070].offset |= (((long) *data++) << 16);
380 ins->oprs[c-070].offset |= (((long) *data++) << 24);
381 ins->oprs[c-070].segment |= SEG_32BIT | SEG_RELATIVE;
382 }
383 if (c >= 0100 && c < 0130) {
384 int modrm = *data++;
385 ins->oprs[c & 07].basereg = (modrm >> 3) & 07;
386 ins->oprs[c & 07].segment |= SEG_RMREG;
387 data = do_ea (data, modrm, asize, segsize,
388 &ins->oprs[(c >> 3) & 07]);
389 }
390 if (c >= 0130 && c <= 0132) {
391 ins->oprs[c-0130].offset = *data++;
392 ins->oprs[c-0130].offset |= (*data++ << 8);
393 }
394 if (c >= 0140 && c <= 0142) {
395 ins->oprs[c-0140].offset = *data++;
396 ins->oprs[c-0140].offset |= (*data++ << 8);
397 ins->oprs[c-0140].offset |= (((long) *data++) << 16);
398 ins->oprs[c-0140].offset |= (((long) *data++) << 24);
399 }
400 if (c >= 0200 && c <= 0277) {
401 int modrm = *data++;
402 if (((modrm >> 3) & 07) != (c & 07))
403 return FALSE; /* spare field doesn't match up */
404 data = do_ea (data, modrm, asize, segsize,
405 &ins->oprs[(c >> 3) & 07]);
406 }
407 if (c >= 0300 && c <= 0302) {
408 if (asize)
409 ins->oprs[c-0300].segment |= SEG_32BIT;
410 else
411 ins->oprs[c-0300].segment &= ~SEG_32BIT;
412 a_used = TRUE;
413 }
414 if (c == 0310) {
415 if (asize == 32)
416 return FALSE;
417 else
418 a_used = TRUE;
419 }
420 if (c == 0311) {
421 if (asize == 16)
422 return FALSE;
423 else
424 a_used = TRUE;
425 }
426 if (c == 0312) {
427 if (asize != segsize)
428 return FALSE;
429 else
430 a_used = TRUE;
431 }
432 if (c == 0320) {
433 if (osize == 32)
434 return FALSE;
435 else
436 o_used = TRUE;
437 }
438 if (c == 0321) {
439 if (osize == 16)
440 return FALSE;
441 else
442 o_used = TRUE;
443 }
444 if (c == 0322) {
445 if (osize != segsize)
446 return FALSE;
447 else
448 o_used = TRUE;
449 }
450 if (c == 0330) {
451 int t = *r++, d = *data++;
452 if (d < t || d > t+15)
453 return FALSE;
454 else
455 ins->condition = d - t;
456 }
457 if (c == 0331) {
458 if ( rep )
459 return FALSE;
460 }
461 if (c == 0332) {
462 if (drep == P_REP)
463 drep = P_REPE;
464 }
465 if (c == 0333) {
466 if ( rep != 0xF3 )
467 return FALSE;
468 drep = 0;
469 }
470 }
471
472 /*
473 * Check for unused rep or a/o prefixes.
474 */
475 ins->nprefix = 0;
476 if (drep)
477 ins->prefixes[ins->nprefix++] = drep;
478 if (!a_used && asize != segsize)
479 ins->prefixes[ins->nprefix++] = (asize == 16 ? P_A16 : P_A32);
480 if (!o_used && osize != segsize)
481 ins->prefixes[ins->nprefix++] = (osize == 16 ? P_O16 : P_O32);
482
483 return data - origdata;
484 }
485
486 long disasm (unsigned char *data, char *output, int segsize, long offset,
487 int autosync, unsigned long prefer)
488 {
489 struct itemplate **p, **best_p;
490 int length, best_length = 0;
491 char *segover;
492 int rep, lock, asize, osize, i, slen, colon;
493 unsigned char *origdata;
494 int works;
495 insn tmp_ins, ins;
496 unsigned long goodness, best;
497
498 /*
499 * Scan for prefixes.
500 */
501 asize = osize = segsize;
502 segover = NULL;
503 rep = lock = 0;
504 origdata = data;
505 for (;;) {
506 if (*data == 0xF3 || *data == 0xF2)
507 rep = *data++;
508 else if (*data == 0xF0)
509 lock = *data++;
510 else if (*data == 0x2E || *data == 0x36 || *data == 0x3E ||
511 *data == 0x26 || *data == 0x64 || *data == 0x65) {
512 switch (*data++) {
513 case 0x2E: segover = "cs"; break;
514 case 0x36: segover = "ss"; break;
515 case 0x3E: segover = "ds"; break;
516 case 0x26: segover = "es"; break;
517 case 0x64: segover = "fs"; break;
518 case 0x65: segover = "gs"; break;
519 }
520 } else if (*data == 0x66)
521 osize = 48 - segsize, data++;
522 else if (*data == 0x67)
523 asize = 48 - segsize, data++;
524 else
525 break;
526 }
527
528 tmp_ins.oprs[0].segment = tmp_ins.oprs[1].segment =
529 tmp_ins.oprs[2].segment =
530 tmp_ins.oprs[0].addr_size = tmp_ins.oprs[1].addr_size =
531 tmp_ins.oprs[2].addr_size = (segsize == 16 ? 0 : SEG_32BIT);
532 tmp_ins.condition = -1;
533 best = ~0UL; /* Worst possible */
534 best_p = NULL;
535 for (p = itable[*data]; *p; p++) {
536 if ( (length = matches(*p, data, asize, osize,
537 segsize, rep, &tmp_ins)) ) {
538 works = TRUE;
539 /*
540 * Final check to make sure the types of r/m match up.
541 */
542 for (i = 0; i < (*p)->operands; i++) {
543 if (
544 /* If it's a mem-only EA but we have a register, die. */
545 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
546 !(MEMORY & ~(*p)->opd[i])) ||
547
548 /* If it's a reg-only EA but we have a memory ref, die. */
549 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
550 !(REGNORM & ~(*p)->opd[i]) &&
551 !((*p)->opd[i] & REG_SMASK)) ||
552
553 /* Register type mismatch (eg FS vs REG_DESS): die. */
554 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
555 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
556 !whichreg ((*p)->opd[i], tmp_ins.oprs[i].basereg))) {
557 works = FALSE;
558 break;
559 }
560 }
561
562 if (works) {
563 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
564 if ( goodness < best ) {
565 /* This is the best one found so far */
566 best = goodness;
567 best_p = p;
568 best_length = length;
569 ins = tmp_ins;
570 }
571 }
572 }
573 }
574
575 if (!best_p)
576 return 0; /* no instruction was matched */
577
578 /* Pick the best match */
579 p = best_p;
580 length = best_length;
581
582 slen = 0;
583
584 if (lock)
585 slen += sprintf(output+slen, "lock ");
586 for (i = 0; i < ins.nprefix; i++)
587 switch (ins.prefixes[i]) {
588 case P_REP: slen += sprintf(output+slen, "rep "); break;
589 case P_REPE: slen += sprintf(output+slen, "repe "); break;
590 case P_REPNE: slen += sprintf(output+slen, "repne "); break;
591 case P_A16: slen += sprintf(output+slen, "a16 "); break;
592 case P_A32: slen += sprintf(output+slen, "a32 "); break;
593 case P_O16: slen += sprintf(output+slen, "o16 "); break;
594 case P_O32: slen += sprintf(output+slen, "o32 "); break;
595 }
596
597 for (i = 0; i < elements(ico); i++)
598 if ((*p)->opcode == ico[i]) {
599 slen += sprintf(output+slen, "%s%s", icn[i],
600 whichcond(ins.condition));
601 break;
602 }
603 if (i >= elements(ico))
604 slen += sprintf(output+slen, "%s", insn_names[(*p)->opcode]);
605 colon = FALSE;
606 length += data - origdata; /* fix up for prefixes */
607 for (i=0; i<(*p)->operands; i++) {
608 output[slen++] = (colon ? ':' : i==0 ? ' ' : ',');
609
610 if (ins.oprs[i].segment & SEG_RELATIVE) {
611 ins.oprs[i].offset += offset + length;
612 /*
613 * sort out wraparound
614 */
615 if (!(ins.oprs[i].segment & SEG_32BIT))
616 ins.oprs[i].offset &= 0xFFFF;
617 /*
618 * add sync marker, if autosync is on
619 */
620 if (autosync)
621 add_sync (ins.oprs[i].offset, 0L);
622 }
623
624 if ((*p)->opd[i] & COLON)
625 colon = TRUE;
626 else
627 colon = FALSE;
628
629 if (((*p)->opd[i] & (REGISTER | FPUREG)) ||
630 (ins.oprs[i].segment & SEG_RMREG))
631 {
632 ins.oprs[i].basereg = whichreg ((*p)->opd[i],
633 ins.oprs[i].basereg);
634 if ( (*p)->opd[i] & TO )
635 slen += sprintf(output+slen, "to ");
636 slen += sprintf(output+slen, "%s",
637 reg_names[ins.oprs[i].basereg-EXPR_REG_START]);
638 } else if (!(UNITY & ~(*p)->opd[i])) {
639 output[slen++] = '1';
640 } else if ( (*p)->opd[i] & IMMEDIATE ) {
641 if ( (*p)->opd[i] & BITS8 ) {
642 slen += sprintf(output+slen, "byte ");
643 if (ins.oprs[i].segment & SEG_SIGNED) {
644 if (ins.oprs[i].offset < 0) {
645 ins.oprs[i].offset *= -1;
646 output[slen++] = '-';
647 } else
648 output[slen++] = '+';
649 }
650 } else if ( (*p)->opd[i] & BITS16 ) {
651 slen += sprintf(output+slen, "word ");
652 } else if ( (*p)->opd[i] & BITS32 ) {
653 slen += sprintf(output+slen, "dword ");
654 } else if ( (*p)->opd[i] & NEAR ) {
655 slen += sprintf(output+slen, "near ");
656 } else if ( (*p)->opd[i] & SHORT ) {
657 slen += sprintf(output+slen, "short ");
658 }
659 slen += sprintf(output+slen, "0x%lx", ins.oprs[i].offset);
660 } else if ( !(MEM_OFFS & ~(*p)->opd[i]) ) {
661 slen += sprintf(output+slen, "[%s%s%s0x%lx]",
662 (segover ? segover : ""),
663 (segover ? ":" : ""),
664 (ins.oprs[i].addr_size == 32 ? "dword " :
665 ins.oprs[i].addr_size == 16 ? "word " : ""),
666 ins.oprs[i].offset);
667 segover = NULL;
668 } else if ( !(REGMEM & ~(*p)->opd[i]) ) {
669 int started = FALSE;
670 if ( (*p)->opd[i] & BITS8 )
671 slen += sprintf(output+slen, "byte ");
672 if ( (*p)->opd[i] & BITS16 )
673 slen += sprintf(output+slen, "word ");
674 if ( (*p)->opd[i] & BITS32 )
675 slen += sprintf(output+slen, "dword ");
676 if ( (*p)->opd[i] & BITS64 )
677 slen += sprintf(output+slen, "qword ");
678 if ( (*p)->opd[i] & BITS80 )
679 slen += sprintf(output+slen, "tword ");
680 if ( (*p)->opd[i] & FAR )
681 slen += sprintf(output+slen, "far ");
682 if ( (*p)->opd[i] & NEAR )
683 slen += sprintf(output+slen, "near ");
684 output[slen++] = '[';
685 if (ins.oprs[i].addr_size)
686 slen += sprintf(output+slen, "%s",
687 (ins.oprs[i].addr_size == 32 ? "dword " :
688 ins.oprs[i].addr_size == 16 ? "word " : ""));
689 if (segover) {
690 slen += sprintf(output+slen, "%s:", segover);
691 segover = NULL;
692 }
693 if (ins.oprs[i].basereg != -1) {
694 slen += sprintf(output+slen, "%s",
695 reg_names[(ins.oprs[i].basereg -
696 EXPR_REG_START)]);
697 started = TRUE;
698 }
699 if (ins.oprs[i].indexreg != -1) {
700 if (started)
701 output[slen++] = '+';
702 slen += sprintf(output+slen, "%s",
703 reg_names[(ins.oprs[i].indexreg -
704 EXPR_REG_START)]);
705 if (ins.oprs[i].scale > 1)
706 slen += sprintf(output+slen, "*%d", ins.oprs[i].scale);
707 started = TRUE;
708 }
709 if (ins.oprs[i].segment & SEG_DISP8) {
710 int sign = '+';
711 if (ins.oprs[i].offset & 0x80) {
712 ins.oprs[i].offset = - (signed char) ins.oprs[i].offset;
713 sign = '-';
714 }
715 slen += sprintf(output+slen, "%c0x%lx", sign,
716 ins.oprs[i].offset);
717 } else if (ins.oprs[i].segment & SEG_DISP16) {
718 if (started)
719 output[slen++] = '+';
720 slen += sprintf(output+slen, "0x%lx", ins.oprs[i].offset);
721 } else if (ins.oprs[i].segment & SEG_DISP32) {
722 if (started)
723 output[slen++] = '+';
724 slen += sprintf(output+slen, "0x%lx", ins.oprs[i].offset);
725 }
726 output[slen++] = ']';
727 } else {
728 slen += sprintf(output+slen, "<operand%d>", i);
729 }
730 }
731 output[slen] = '\0';
732 if (segover) { /* unused segment override */
733 char *p = output;
734 int count = slen+1;
735 while (count--)
736 p[count+3] = p[count];
737 strncpy (output, segover, 2);
738 output[2] = ' ';
739 }
740 return length;
741 }
742
743 long eatbyte (unsigned char *data, char *output)
744 {
745 sprintf(output, "db 0x%02X", *data);
746 return 1;
747 }
The Netwide Assembler