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.gitignore file doesn't need to be in the release file
[nasm.git] / assemble.c
blob5d9d1d00c6a935881196147ede2e0c82cb30f379
1 /* assemble.c code generation for the Netwide Assembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the licence given in the file "Licence"
6 * distributed in the NASM archive.
7 *
8 * the actual codes (C syntax, i.e. octal):
9 * \0 - terminates the code. (Unless it's a literal of course.)
10 * \1, \2, \3 - that many literal bytes follow in the code stream
11 * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
12 * (POP is never used for CS) depending on operand 0
13 * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
14 * on operand 0
15 * \10..\13 - a literal byte follows in the code stream, to be added
16 * to the register value of operand 0..3
17 * \14..\17 - a signed byte immediate operand, from operand 0..3
18 * \20..\23 - a byte immediate operand, from operand 0..3
19 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
20 * \30..\33 - a word immediate operand, from operand 0..3
21 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
22 * assembly mode or the operand-size override on the operand
23 * \40..\43 - a long immediate operand, from operand 0..3
24 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
25 * depending on assembly mode or the address-size override
26 * on the operand.
27 * \50..\53 - a byte relative operand, from operand 0..3
28 * \54..\57 - a qword immediate operand, from operand 0..3
29 * \60..\63 - a word relative operand, from operand 0..3
30 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
31 * assembly mode or the operand-size override on the operand
32 * \70..\73 - a long relative operand, from operand 0..3
33 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
34 * \1ab - a ModRM, calculated on EA in operand a, with the spare
35 * field the register value of operand b.
36 * \140..\143 - an immediate word or signed byte for operand 0..3
37 * \144..\147 - or 2 (s-field) into next opcode byte if operand 0..3
38 * is a signed byte rather than a word.
39 * \150..\153 - an immediate dword or signed byte for operand 0..3
40 * \154..\157 - or 2 (s-field) into next opcode byte if operand 0..3
41 * is a signed byte rather than a dword.
42 * \160..\163 - this instruction uses DREX rather than REX, with the
43 * OC0 field set to 0, and the dest field taken from
44 * operand 0..3.
45 * \164..\167 - this instruction uses DREX rather than REX, with the
46 * OC0 field set to 1, and the dest field taken from
47 * operand 0..3.
48 * \170 - encodes the literal byte 0. (Some compilers don't take
49 * kindly to a zero byte in the _middle_ of a compile time
50 * string constant, so I had to put this hack in.)
51 * \171 - placement of DREX suffix in the absence of an EA
52 * \2ab - a ModRM, calculated on EA in operand a, with the spare
53 * field equal to digit b.
54 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
55 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
56 * \312 - (disassembler only) marker on LOOP, LOOPxx instructions.
57 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
58 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
59 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
60 * \322 - indicates that this instruction is only valid when the
61 * operand size is the default (instruction to disassembler,
62 * generates no code in the assembler)
63 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
64 * \324 - indicates 64-bit operand size requiring REX prefix.
65 * \330 - a literal byte follows in the code stream, to be added
66 * to the condition code value of the instruction.
67 * \331 - instruction not valid with REP prefix. Hint for
68 * disassembler only; for SSE instructions.
69 * \332 - REP prefix (0xF2 byte) used as opcode extension.
70 * \333 - REP prefix (0xF3 byte) used as opcode extension.
71 * \334 - LOCK prefix used instead of REX.R
72 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
73 * \340 - reserve <operand 0> bytes of uninitialized storage.
74 * Operand 0 had better be a segmentless constant.
75 * \364 - operand-size prefix (0x66) not permitted
76 * \365 - address-size prefix (0x67) not permitted
77 * \366 - operand-size prefix (0x66) used as opcode extension
78 * \367 - address-size prefix (0x67) used as opcode extension
79 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
80 * 370 is used for Jcc, 371 is used for JMP.
81 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
82 * used for conditional jump over longer jump
83 */
84
85 #include "compiler.h"
86
87 #include <stdio.h>
88 #include <string.h>
89 #include <inttypes.h>
90
91 #include "nasm.h"
92 #include "nasmlib.h"
93 #include "assemble.h"
94 #include "insns.h"
95 #include "preproc.h"
96 #include "regflags.c"
97 #include "regvals.c"
98
99 typedef struct {
100 int sib_present; /* is a SIB byte necessary? */
101 int bytes; /* # of bytes of offset needed */
102 int size; /* lazy - this is sib+bytes+1 */
103 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
104 } ea;
105
106 static uint32_t cpu; /* cpu level received from nasm.c */
107 static efunc errfunc;
108 static struct ofmt *outfmt;
109 static ListGen *list;
110
111 static int32_t calcsize(int32_t, int32_t, int, insn *, const char *);
112 static void gencode(int32_t, int32_t, int, insn *, const char *, int32_t);
113 static int matches(const struct itemplate *, insn *, int bits);
114 static int32_t regflag(const operand *);
115 static int32_t regval(const operand *);
116 static int rexflags(int, int32_t, int);
117 static int op_rexflags(const operand *, int);
118 static ea *process_ea(operand *, ea *, int, int, int32_t, int);
119 static void add_asp(insn *, int);
120
121 static int has_prefix(insn * ins, enum prefixes prefix)
122 {
123 int j;
124 for (j = 0; j < ins->nprefix; j++) {
125 if (ins->prefixes[j] == prefix)
126 return 1;
127 }
128 return 0;
129 }
130
131 static void assert_no_prefix(insn * ins, enum prefixes prefix)
132 {
133 if (has_prefix(ins, prefix))
134 errfunc(ERR_NONFATAL, "invalid %s prefix", prefix_name(prefix));
135 }
136
137 /*
138 * This routine wrappers the real output format's output routine,
139 * in order to pass a copy of the data off to the listing file
140 * generator at the same time.
141 */
142 static void out(int32_t offset, int32_t segto, const void *data,
143 uint32_t type, int32_t segment, int32_t wrt)
144 {
145 static int32_t lineno = 0; /* static!!! */
146 static char *lnfname = NULL;
147
148 if ((type & OUT_TYPMASK) == OUT_ADDRESS) {
149 if (segment != NO_SEG || wrt != NO_SEG) {
150 /*
151 * This address is relocated. We must write it as
152 * OUT_ADDRESS, so there's no work to be done here.
153 */
154 list->output(offset, data, type);
155 } else {
156 uint8_t p[8], *q = p;
157 /*
158 * This is a non-relocated address, and we're going to
159 * convert it into RAWDATA format.
160 */
161 if ((type & OUT_SIZMASK) == 4) {
162 WRITELONG(q, *(int32_t *)data);
163 list->output(offset, p, OUT_RAWDATA + 4);
164 } else if ((type & OUT_SIZMASK) == 8) {
165 WRITEDLONG(q, *(int64_t *)data);
166 list->output(offset, p, OUT_RAWDATA + 8);
167 } else {
168 WRITESHORT(q, *(int32_t *)data);
169 list->output(offset, p, OUT_RAWDATA + 2);
170 }
171 }
172 } else if ((type & OUT_TYPMASK) == OUT_RAWDATA) {
173 list->output(offset, data, type);
174 } else if ((type & OUT_TYPMASK) == OUT_RESERVE) {
175 list->output(offset, NULL, type);
176 } else if ((type & OUT_TYPMASK) == OUT_REL2ADR ||
177 (type & OUT_TYPMASK) == OUT_REL4ADR) {
178 list->output(offset, data, type);
179 }
180
181 /*
182 * this call to src_get determines when we call the
183 * debug-format-specific "linenum" function
184 * it updates lineno and lnfname to the current values
185 * returning 0 if "same as last time", -2 if lnfname
186 * changed, and the amount by which lineno changed,
187 * if it did. thus, these variables must be static
188 */
189
190 if (src_get(&lineno, &lnfname)) {
191 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
192 }
193
194 outfmt->output(segto, data, type, segment, wrt);
195 }
196
197 static int jmp_match(int32_t segment, int32_t offset, int bits,
198 insn * ins, const char *code)
199 {
200 int32_t isize;
201 uint8_t c = code[0];
202
203 if (c != 0370 && c != 0371)
204 return 0;
205 if (ins->oprs[0].opflags & OPFLAG_FORWARD) {
206 if ((optimizing < 0 || (ins->oprs[0].type & STRICT))
207 && c == 0370)
208 return 1;
209 else
210 return (pass0 == 0); /* match a forward reference */
211 }
212 isize = calcsize(segment, offset, bits, ins, code);
213 if (ins->oprs[0].segment != segment)
214 return 0;
215 isize = ins->oprs[0].offset - offset - isize; /* isize is now the delta */
216 if (isize >= -128L && isize <= 127L)
217 return 1; /* it is byte size */
218
219 return 0;
220 }
221
222 int32_t assemble(int32_t segment, int32_t offset, int bits, uint32_t cp,
223 insn * instruction, struct ofmt *output, efunc error,
224 ListGen * listgen)
225 {
226 const struct itemplate *temp;
227 int j;
228 int size_prob;
229 int32_t insn_end;
230 int32_t itimes;
231 int32_t start = offset;
232 int32_t wsize = 0; /* size for DB etc. */
233
234 errfunc = error; /* to pass to other functions */
235 cpu = cp;
236 outfmt = output; /* likewise */
237 list = listgen; /* and again */
238
239 switch (instruction->opcode) {
240 case -1:
241 return 0;
242 case I_DB:
243 wsize = 1;
244 break;
245 case I_DW:
246 wsize = 2;
247 break;
248 case I_DD:
249 wsize = 4;
250 break;
251 case I_DQ:
252 wsize = 8;
253 break;
254 case I_DT:
255 wsize = 10;
256 break;
257 case I_DO:
258 wsize = 16;
259 break;
260 default:
261 break;
262 }
263
264 if (wsize) {
265 extop *e;
266 int32_t t = instruction->times;
267 if (t < 0)
268 errfunc(ERR_PANIC,
269 "instruction->times < 0 (%ld) in assemble()", t);
270
271 while (t--) { /* repeat TIMES times */
272 for (e = instruction->eops; e; e = e->next) {
273 if (e->type == EOT_DB_NUMBER) {
274 if (wsize == 1) {
275 if (e->segment != NO_SEG)
276 errfunc(ERR_NONFATAL,
277 "one-byte relocation attempted");
278 else {
279 uint8_t out_byte = e->offset;
280 out(offset, segment, &out_byte,
281 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
282 }
283 } else if (wsize > 8) {
284 errfunc(ERR_NONFATAL, "integer supplied to a DT or DO"
285 " instruction");
286 } else
287 out(offset, segment, &e->offset,
288 OUT_ADDRESS + wsize, e->segment, e->wrt);
289 offset += wsize;
290 } else if (e->type == EOT_DB_STRING) {
291 int align;
292
293 out(offset, segment, e->stringval,
294 OUT_RAWDATA + e->stringlen, NO_SEG, NO_SEG);
295 align = e->stringlen % wsize;
296
297 if (align) {
298 align = wsize - align;
299 out(offset, segment, "\0\0\0\0\0\0\0\0",
300 OUT_RAWDATA + align, NO_SEG, NO_SEG);
301 }
302 offset += e->stringlen + align;
303 }
304 }
305 if (t > 0 && t == instruction->times - 1) {
306 /*
307 * Dummy call to list->output to give the offset to the
308 * listing module.
309 */
310 list->output(offset, NULL, OUT_RAWDATA);
311 list->uplevel(LIST_TIMES);
312 }
313 }
314 if (instruction->times > 1)
315 list->downlevel(LIST_TIMES);
316 return offset - start;
317 }
318
319 if (instruction->opcode == I_INCBIN) {
320 static char fname[FILENAME_MAX];
321 FILE *fp;
322 int32_t len;
323 char *prefix = "", *combine;
324 char **pPrevPath = NULL;
325
326 len = FILENAME_MAX - 1;
327 if (len > instruction->eops->stringlen)
328 len = instruction->eops->stringlen;
329 strncpy(fname, instruction->eops->stringval, len);
330 fname[len] = '\0';
331
332 while (1) { /* added by alexfru: 'incbin' uses include paths */
333 combine = nasm_malloc(strlen(prefix) + len + 1);
334 strcpy(combine, prefix);
335 strcat(combine, fname);
336
337 if ((fp = fopen(combine, "rb")) != NULL) {
338 nasm_free(combine);
339 break;
340 }
341
342 nasm_free(combine);
343 pPrevPath = pp_get_include_path_ptr(pPrevPath);
344 if (pPrevPath == NULL)
345 break;
346 prefix = *pPrevPath;
347 }
348
349 if (fp == NULL)
350 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
351 fname);
352 else if (fseek(fp, 0L, SEEK_END) < 0)
353 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
354 fname);
355 else {
356 static char buf[2048];
357 int32_t t = instruction->times;
358 int32_t base = 0;
359
360 len = ftell(fp);
361 if (instruction->eops->next) {
362 base = instruction->eops->next->offset;
363 len -= base;
364 if (instruction->eops->next->next &&
365 len > instruction->eops->next->next->offset)
366 len = instruction->eops->next->next->offset;
367 }
368 /*
369 * Dummy call to list->output to give the offset to the
370 * listing module.
371 */
372 list->output(offset, NULL, OUT_RAWDATA);
373 list->uplevel(LIST_INCBIN);
374 while (t--) {
375 int32_t l;
376
377 fseek(fp, base, SEEK_SET);
378 l = len;
379 while (l > 0) {
380 int32_t m =
381 fread(buf, 1, (l > sizeof(buf) ? sizeof(buf) : l),
382 fp);
383 if (!m) {
384 /*
385 * This shouldn't happen unless the file
386 * actually changes while we are reading
387 * it.
388 */
389 error(ERR_NONFATAL,
390 "`incbin': unexpected EOF while"
391 " reading file `%s'", fname);
392 t = 0; /* Try to exit cleanly */
393 break;
394 }
395 out(offset, segment, buf, OUT_RAWDATA + m,
396 NO_SEG, NO_SEG);
397 l -= m;
398 }
399 }
400 list->downlevel(LIST_INCBIN);
401 if (instruction->times > 1) {
402 /*
403 * Dummy call to list->output to give the offset to the
404 * listing module.
405 */
406 list->output(offset, NULL, OUT_RAWDATA);
407 list->uplevel(LIST_TIMES);
408 list->downlevel(LIST_TIMES);
409 }
410 fclose(fp);
411 return instruction->times * len;
412 }
413 return 0; /* if we're here, there's an error */
414 }
415
416 /* Check to see if we need an address-size prefix */
417 add_asp(instruction, bits);
418
419 size_prob = false;
420
421 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++){
422 int m = matches(temp, instruction, bits);
423
424 if (m == 99)
425 m += jmp_match(segment, offset, bits, instruction, temp->code);
426
427 if (m == 100) { /* matches! */
428 const char *codes = temp->code;
429 int32_t insn_size = calcsize(segment, offset, bits,
430 instruction, codes);
431 itimes = instruction->times;
432 if (insn_size < 0) /* shouldn't be, on pass two */
433 error(ERR_PANIC, "errors made it through from pass one");
434 else
435 while (itimes--) {
436 for (j = 0; j < instruction->nprefix; j++) {
437 uint8_t c = 0;
438 switch (instruction->prefixes[j]) {
439 case P_LOCK:
440 c = 0xF0;
441 break;
442 case P_REPNE:
443 case P_REPNZ:
444 c = 0xF2;
445 break;
446 case P_REPE:
447 case P_REPZ:
448 case P_REP:
449 c = 0xF3;
450 break;
451 case R_CS:
452 if (bits == 64) {
453 error(ERR_WARNING,
454 "cs segment base ignored in 64-bit mode");
455 }
456 c = 0x2E;
457 break;
458 case R_DS:
459 if (bits == 64) {
460 error(ERR_WARNING,
461 "ds segment base ignored in 64-bit mode");
462 }
463 c = 0x3E;
464 break;
465 case R_ES:
466 if (bits == 64) {
467 error(ERR_WARNING,
468 "es segment base ignored in 64-bit mode");
469 }
470 c = 0x26;
471 break;
472 case R_FS:
473 c = 0x64;
474 break;
475 case R_GS:
476 c = 0x65;
477 break;
478 case R_SS:
479 if (bits == 64) {
480 error(ERR_WARNING,
481 "ss segment base ignored in 64-bit mode");
482 }
483 c = 0x36;
484 break;
485 case R_SEGR6:
486 case R_SEGR7:
487 error(ERR_NONFATAL,
488 "segr6 and segr7 cannot be used as prefixes");
489 break;
490 case P_A16:
491 if (bits == 64) {
492 error(ERR_NONFATAL,
493 "16-bit addressing is not supported "
494 "in 64-bit mode");
495 break;
496 }
497 if (bits != 16)
498 c = 0x67;
499 break;
500 case P_A32:
501 if (bits != 32)
502 c = 0x67;
503 break;
504 case P_O16:
505 if (bits != 16)
506 c = 0x66;
507 break;
508 case P_O32:
509 if (bits == 16)
510 c = 0x66;
511 break;
512 default:
513 error(ERR_PANIC, "invalid instruction prefix");
514 }
515 if (c != 0) {
516 out(offset, segment, &c, OUT_RAWDATA + 1,
517 NO_SEG, NO_SEG);
518 offset++;
519 }
520 }
521 insn_end = offset + insn_size;
522 gencode(segment, offset, bits, instruction, codes,
523 insn_end);
524 offset += insn_size;
525 if (itimes > 0 && itimes == instruction->times - 1) {
526 /*
527 * Dummy call to list->output to give the offset to the
528 * listing module.
529 */
530 list->output(offset, NULL, OUT_RAWDATA);
531 list->uplevel(LIST_TIMES);
532 }
533 }
534 if (instruction->times > 1)
535 list->downlevel(LIST_TIMES);
536 return offset - start;
537 } else if (m > 0 && m > size_prob) {
538 size_prob = m;
539 }
540 // temp++;
541 }
542
543 if (temp->opcode == -1) { /* didn't match any instruction */
544 switch (size_prob) {
545 case 1:
546 error(ERR_NONFATAL, "operation size not specified");
547 break;
548 case 2:
549 error(ERR_NONFATAL, "mismatch in operand sizes");
550 break;
551 case 3:
552 error(ERR_NONFATAL, "no instruction for this cpu level");
553 break;
554 case 4:
555 error(ERR_NONFATAL, "instruction not supported in 64-bit mode");
556 break;
557 default:
558 error(ERR_NONFATAL,
559 "invalid combination of opcode and operands");
560 break;
561 }
562 }
563 return 0;
564 }
565
566 int32_t insn_size(int32_t segment, int32_t offset, int bits, uint32_t cp,
567 insn * instruction, efunc error)
568 {
569 const struct itemplate *temp;
570
571 errfunc = error; /* to pass to other functions */
572 cpu = cp;
573
574 if (instruction->opcode == -1)
575 return 0;
576
577 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
578 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
579 instruction->opcode == I_DT || instruction->opcode == I_DO) {
580 extop *e;
581 int32_t isize, osize, wsize = 0; /* placate gcc */
582
583 isize = 0;
584 switch (instruction->opcode) {
585 case I_DB:
586 wsize = 1;
587 break;
588 case I_DW:
589 wsize = 2;
590 break;
591 case I_DD:
592 wsize = 4;
593 break;
594 case I_DQ:
595 wsize = 8;
596 break;
597 case I_DT:
598 wsize = 10;
599 break;
600 case I_DO:
601 wsize = 16;
602 break;
603 default:
604 break;
605 }
606
607 for (e = instruction->eops; e; e = e->next) {
608 int32_t align;
609
610 osize = 0;
611 if (e->type == EOT_DB_NUMBER)
612 osize = 1;
613 else if (e->type == EOT_DB_STRING)
614 osize = e->stringlen;
615
616 align = (-osize) % wsize;
617 if (align < 0)
618 align += wsize;
619 isize += osize + align;
620 }
621 return isize * instruction->times;
622 }
623
624 if (instruction->opcode == I_INCBIN) {
625 char fname[FILENAME_MAX];
626 FILE *fp;
627 int32_t len;
628 char *prefix = "", *combine;
629 char **pPrevPath = NULL;
630
631 len = FILENAME_MAX - 1;
632 if (len > instruction->eops->stringlen)
633 len = instruction->eops->stringlen;
634 strncpy(fname, instruction->eops->stringval, len);
635 fname[len] = '\0';
636
637 while (1) { /* added by alexfru: 'incbin' uses include paths */
638 combine = nasm_malloc(strlen(prefix) + len + 1);
639 strcpy(combine, prefix);
640 strcat(combine, fname);
641
642 if ((fp = fopen(combine, "rb")) != NULL) {
643 nasm_free(combine);
644 break;
645 }
646
647 nasm_free(combine);
648 pPrevPath = pp_get_include_path_ptr(pPrevPath);
649 if (pPrevPath == NULL)
650 break;
651 prefix = *pPrevPath;
652 }
653
654 if (fp == NULL)
655 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
656 fname);
657 else if (fseek(fp, 0L, SEEK_END) < 0)
658 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
659 fname);
660 else {
661 len = ftell(fp);
662 fclose(fp);
663 if (instruction->eops->next) {
664 len -= instruction->eops->next->offset;
665 if (instruction->eops->next->next &&
666 len > instruction->eops->next->next->offset) {
667 len = instruction->eops->next->next->offset;
668 }
669 }
670 return instruction->times * len;
671 }
672 return 0; /* if we're here, there's an error */
673 }
674
675 /* Check to see if we need an address-size prefix */
676 add_asp(instruction, bits);
677
678 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++) {
679 int m = matches(temp, instruction, bits);
680 if (m == 99)
681 m += jmp_match(segment, offset, bits, instruction, temp->code);
682
683 if (m == 100) {
684 /* we've matched an instruction. */
685 int32_t isize;
686 const char *codes = temp->code;
687 int j;
688
689 isize = calcsize(segment, offset, bits, instruction, codes);
690 if (isize < 0)
691 return -1;
692 for (j = 0; j < instruction->nprefix; j++) {
693 switch (instruction->prefixes[j]) {
694 case P_A16:
695 if (bits != 16)
696 isize++;
697 break;
698 case P_A32:
699 if (bits != 32)
700 isize++;
701 break;
702 case P_O16:
703 if (bits != 16)
704 isize++;
705 break;
706 case P_O32:
707 if (bits == 16)
708 isize++;
709 break;
710 default:
711 isize++;
712 break;
713 }
714 }
715 return isize * instruction->times;
716 }
717 }
718 return -1; /* didn't match any instruction */
719 }
720
721 /* check that opn[op] is a signed byte of size 16 or 32,
722 and return the signed value*/
723 static int is_sbyte(insn * ins, int op, int size)
724 {
725 int32_t v;
726 int ret;
727
728 ret = !(ins->forw_ref && ins->oprs[op].opflags) && /* dead in the water on forward reference or External */
729 optimizing >= 0 &&
730 !(ins->oprs[op].type & STRICT) &&
731 ins->oprs[op].wrt == NO_SEG && ins->oprs[op].segment == NO_SEG;
732
733 v = ins->oprs[op].offset;
734 if (size == 16)
735 v = (int16_t)v; /* sign extend if 16 bits */
736
737 return ret && v >= -128L && v <= 127L;
738 }
739
740 static int32_t calcsize(int32_t segment, int32_t offset, int bits,
741 insn * ins, const char *codes)
742 {
743 int32_t length = 0;
744 uint8_t c;
745 int rex_mask = ~0;
746 ins->rex = 0; /* Ensure REX is reset */
747
748 (void)segment; /* Don't warn that this parameter is unused */
749 (void)offset; /* Don't warn that this parameter is unused */
750
751 while (*codes)
752 switch (c = *codes++) {
753 case 01:
754 case 02:
755 case 03:
756 codes += c, length += c;
757 break;
758 case 04:
759 case 05:
760 case 06:
761 case 07:
762 length++;
763 break;
764 case 010:
765 case 011:
766 case 012:
767 case 013:
768 ins->rex |=
769 op_rexflags(&ins->oprs[c - 010], REX_B|REX_H|REX_P|REX_W);
770 codes++, length++;
771 break;
772 case 014:
773 case 015:
774 case 016:
775 case 017:
776 length++;
777 break;
778 case 020:
779 case 021:
780 case 022:
781 case 023:
782 length++;
783 break;
784 case 024:
785 case 025:
786 case 026:
787 case 027:
788 length++;
789 break;
790 case 030:
791 case 031:
792 case 032:
793 case 033:
794 length += 2;
795 break;
796 case 034:
797 case 035:
798 case 036:
799 case 037:
800 if (ins->oprs[c - 034].type & (BITS16 | BITS32 | BITS64))
801 length += (ins->oprs[c - 034].type & BITS16) ? 2 : 4;
802 else
803 length += (bits == 16) ? 2 : 4;
804 break;
805 case 040:
806 case 041:
807 case 042:
808 case 043:
809 length += 4;
810 break;
811 case 044:
812 case 045:
813 case 046:
814 case 047:
815 length += ((ins->oprs[c - 044].addr_size ?
816 ins->oprs[c - 044].addr_size : bits) >> 3);
817 break;
818 case 050:
819 case 051:
820 case 052:
821 case 053:
822 length++;
823 break;
824 case 054:
825 case 055:
826 case 056:
827 case 057:
828 length += 8; /* MOV reg64/imm */
829 break;
830 case 060:
831 case 061:
832 case 062:
833 case 063:
834 length += 2;
835 break;
836 case 064:
837 case 065:
838 case 066:
839 case 067:
840 if (ins->oprs[c - 064].type & (BITS16 | BITS32 | BITS64))
841 length += (ins->oprs[c - 064].type & BITS16) ? 2 : 4;
842 else
843 length += (bits == 16) ? 2 : 4;
844 break;
845 case 070:
846 case 071:
847 case 072:
848 case 073:
849 length += 4;
850 break;
851 case 074:
852 case 075:
853 case 076:
854 case 077:
855 length += 2;
856 break;
857 case 0140:
858 case 0141:
859 case 0142:
860 case 0143:
861 length += is_sbyte(ins, c - 0140, 16) ? 1 : 2;
862 break;
863 case 0144:
864 case 0145:
865 case 0146:
866 case 0147:
867 codes += 2;
868 length++;
869 break;
870 case 0150:
871 case 0151:
872 case 0152:
873 case 0153:
874 length += is_sbyte(ins, c - 0150, 32) ? 1 : 4;
875 break;
876 case 0154:
877 case 0155:
878 case 0156:
879 case 0157:
880 codes += 2;
881 length++;
882 break;
883 case 0160:
884 case 0161:
885 case 0162:
886 case 0163:
887 length++;
888 ins->rex |= REX_D;
889 ins->drexdst = regval(&ins->oprs[c & 3]);
890 break;
891 case 0164:
892 case 0165:
893 case 0166:
894 case 0167:
895 length++;
896 ins->rex |= REX_D|REX_OC;
897 ins->drexdst = regval(&ins->oprs[c & 3]);
898 break;
899 case 0170:
900 length++;
901 break;
902 case 0171:
903 break;
904 case 0300:
905 case 0301:
906 case 0302:
907 case 0303:
908 break;
909 case 0310:
910 if (bits == 64)
911 return -1;
912 length += (bits != 16) && !has_prefix(ins,P_A16);
913 break;
914 case 0311:
915 length += (bits != 32) && !has_prefix(ins,P_A32);
916 break;
917 case 0312:
918 break;
919 case 0313:
920 if (bits != 64 || has_prefix(ins,P_A16) || has_prefix(ins,P_A32))
921 return -1;
922 break;
923 case 0320:
924 length += (bits != 16);
925 break;
926 case 0321:
927 length += (bits == 16);
928 break;
929 case 0322:
930 break;
931 case 0323:
932 rex_mask &= ~REX_W;
933 break;
934 case 0324:
935 ins->rex |= REX_W;
936 break;
937 case 0330:
938 codes++, length++;
939 break;
940 case 0331:
941 break;
942 case 0332:
943 case 0333:
944 length++;
945 break;
946 case 0334:
947 assert_no_prefix(ins, P_LOCK);
948 ins->rex |= REX_L;
949 break;
950 case 0335:
951 break;
952 case 0340:
953 case 0341:
954 case 0342:
955 if (ins->oprs[0].segment != NO_SEG)
956 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
957 " quantity of BSS space");
958 else
959 length += ins->oprs[0].offset << (c - 0340);
960 break;
961 case 0364:
962 case 0365:
963 break;
964 case 0366:
965 case 0367:
966 length++;
967 break;
968 case 0370:
969 case 0371:
970 case 0372:
971 break;
972 case 0373:
973 length++;
974 break;
975 default: /* can't do it by 'case' statements */
976 if (c >= 0100 && c <= 0277) { /* it's an EA */
977 ea ea_data;
978 int rfield;
979 int32_t rflags;
980 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
981
982 if (c <= 0177) {
983 /* pick rfield from operand b */
984 rflags = regflag(&ins->oprs[c & 7]);
985 rfield = regvals[ins->oprs[c & 7].basereg];
986 } else {
987 rflags = 0;
988 rfield = c & 7;
989 }
990
991 if (!process_ea
992 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
993 rfield, rflags, ins->forw_ref)) {
994 errfunc(ERR_NONFATAL, "invalid effective address");
995 return -1;
996 } else {
997 ins->rex |= ea_data.rex;
998 length += ea_data.size;
999 }
1000 } else
1001 errfunc(ERR_PANIC, "internal instruction table corrupt"
1002 ": instruction code 0x%02X given", c);
1003 }
1004
1005 ins->rex &= rex_mask;
1006
1007 if (ins->rex & REX_D) {
1008 if (ins->rex & REX_H) {
1009 errfunc(ERR_NONFATAL, "cannot use high register in drex instruction");
1010 return -1;
1011 }
1012 if (bits != 64 && ((ins->rex & (REX_W|REX_X|REX_B)) ||
1013 ins->drexdst > 7)) {
1014 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1015 return -1;
1016 }
1017 length++;
1018 } else if (ins->rex & REX_REAL) {
1019 if (ins->rex & REX_H) {
1020 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1021 return -1;
1022 } else if (bits == 64 ||
1023 ((ins->rex & REX_L) &&
1024 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1025 cpu >= IF_X86_64)) {
1026 length++;
1027 } else {
1028 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1029 return -1;
1030 }
1031 }
1032
1033 return length;
1034 }
1035
1036 #define EMIT_REX() \
1037 if (!(ins->rex & REX_D) && (ins->rex & REX_REAL) && (bits == 64)) { \
1038 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1039 out(offset, segment, &ins->rex, OUT_RAWDATA+1, NO_SEG, NO_SEG); \
1040 ins->rex = 0; \
1041 offset += 1; \
1042 }
1043
1044 static void gencode(int32_t segment, int32_t offset, int bits,
1045 insn * ins, const char *codes, int32_t insn_end)
1046 {
1047 static char condval[] = { /* conditional opcodes */
1048 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1049 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1050 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1051 };
1052 uint8_t c;
1053 uint8_t bytes[4];
1054 int32_t size;
1055 int64_t data;
1056
1057 while (*codes)
1058 switch (c = *codes++) {
1059 case 01:
1060 case 02:
1061 case 03:
1062 EMIT_REX();
1063 out(offset, segment, codes, OUT_RAWDATA + c, NO_SEG, NO_SEG);
1064 codes += c;
1065 offset += c;
1066 break;
1067
1068 case 04:
1069 case 06:
1070 switch (ins->oprs[0].basereg) {
1071 case R_CS:
1072 bytes[0] = 0x0E + (c == 0x04 ? 1 : 0);
1073 break;
1074 case R_DS:
1075 bytes[0] = 0x1E + (c == 0x04 ? 1 : 0);
1076 break;
1077 case R_ES:
1078 bytes[0] = 0x06 + (c == 0x04 ? 1 : 0);
1079 break;
1080 case R_SS:
1081 bytes[0] = 0x16 + (c == 0x04 ? 1 : 0);
1082 break;
1083 default:
1084 errfunc(ERR_PANIC,
1085 "bizarre 8086 segment register received");
1086 }
1087 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1088 offset++;
1089 break;
1090
1091 case 05:
1092 case 07:
1093 switch (ins->oprs[0].basereg) {
1094 case R_FS:
1095 bytes[0] = 0xA0 + (c == 0x05 ? 1 : 0);
1096 break;
1097 case R_GS:
1098 bytes[0] = 0xA8 + (c == 0x05 ? 1 : 0);
1099 break;
1100 default:
1101 errfunc(ERR_PANIC,
1102 "bizarre 386 segment register received");
1103 }
1104 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1105 offset++;
1106 break;
1107
1108 case 010:
1109 case 011:
1110 case 012:
1111 case 013:
1112 EMIT_REX();
1113 bytes[0] = *codes++ + ((regval(&ins->oprs[c - 010])) & 7);
1114 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1115 offset += 1;
1116 break;
1117
1118 case 014:
1119 case 015:
1120 case 016:
1121 case 017:
1122 if (ins->oprs[c - 014].offset < -128
1123 || ins->oprs[c - 014].offset > 127) {
1124 errfunc(ERR_WARNING, "signed byte value exceeds bounds");
1125 }
1126
1127 if (ins->oprs[c - 014].segment != NO_SEG) {
1128 data = ins->oprs[c - 014].offset;
1129 out(offset, segment, &data, OUT_ADDRESS + 1,
1130 ins->oprs[c - 014].segment, ins->oprs[c - 014].wrt);
1131 } else {
1132 bytes[0] = ins->oprs[c - 014].offset;
1133 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1134 NO_SEG);
1135 }
1136 offset += 1;
1137 break;
1138
1139 case 020:
1140 case 021:
1141 case 022:
1142 case 023:
1143 if (ins->oprs[c - 020].offset < -256
1144 || ins->oprs[c - 020].offset > 255) {
1145 errfunc(ERR_WARNING, "byte value exceeds bounds");
1146 }
1147 if (ins->oprs[c - 020].segment != NO_SEG) {
1148 data = ins->oprs[c - 020].offset;
1149 out(offset, segment, &data, OUT_ADDRESS + 1,
1150 ins->oprs[c - 020].segment, ins->oprs[c - 020].wrt);
1151 } else {
1152 bytes[0] = ins->oprs[c - 020].offset;
1153 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1154 NO_SEG);
1155 }
1156 offset += 1;
1157 break;
1158
1159 case 024:
1160 case 025:
1161 case 026:
1162 case 027:
1163 if (ins->oprs[c - 024].offset < 0
1164 || ins->oprs[c - 024].offset > 255)
1165 errfunc(ERR_WARNING, "unsigned byte value exceeds bounds");
1166 if (ins->oprs[c - 024].segment != NO_SEG) {
1167 data = ins->oprs[c - 024].offset;
1168 out(offset, segment, &data, OUT_ADDRESS + 1,
1169 ins->oprs[c - 024].segment, ins->oprs[c - 024].wrt);
1170 } else {
1171 bytes[0] = ins->oprs[c - 024].offset;
1172 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1173 NO_SEG);
1174 }
1175 offset += 1;
1176 break;
1177
1178 case 030:
1179 case 031:
1180 case 032:
1181 case 033:
1182 if (ins->oprs[c - 030].segment == NO_SEG &&
1183 ins->oprs[c - 030].wrt == NO_SEG &&
1184 (ins->oprs[c - 030].offset < -65536L ||
1185 ins->oprs[c - 030].offset > 65535L)) {
1186 errfunc(ERR_WARNING, "word value exceeds bounds");
1187 }
1188 data = ins->oprs[c - 030].offset;
1189 out(offset, segment, &data, OUT_ADDRESS + 2,
1190 ins->oprs[c - 030].segment, ins->oprs[c - 030].wrt);
1191 offset += 2;
1192 break;
1193
1194 case 034:
1195 case 035:
1196 case 036:
1197 case 037:
1198 if (ins->oprs[c - 034].type & (BITS16 | BITS32))
1199 size = (ins->oprs[c - 034].type & BITS16) ? 2 : 4;
1200 else
1201 size = (bits == 16) ? 2 : 4;
1202 data = ins->oprs[c - 034].offset;
1203 if (size == 2 && (data < -65536L || data > 65535L))
1204 errfunc(ERR_WARNING, "word value exceeds bounds");
1205 out(offset, segment, &data, OUT_ADDRESS + size,
1206 ins->oprs[c - 034].segment, ins->oprs[c - 034].wrt);
1207 offset += size;
1208 break;
1209
1210 case 040:
1211 case 041:
1212 case 042:
1213 case 043:
1214 data = ins->oprs[c - 040].offset;
1215 out(offset, segment, &data, OUT_ADDRESS + 4,
1216 ins->oprs[c - 040].segment, ins->oprs[c - 040].wrt);
1217 offset += 4;
1218 break;
1219
1220 case 044:
1221 case 045:
1222 case 046:
1223 case 047:
1224 data = ins->oprs[c - 044].offset;
1225 size = ((ins->oprs[c - 044].addr_size ?
1226 ins->oprs[c - 044].addr_size : bits) >> 3);
1227 if (size == 2 && (data < -65536L || data > 65535L))
1228 errfunc(ERR_WARNING, "word value exceeds bounds");
1229 out(offset, segment, &data, OUT_ADDRESS + size,
1230 ins->oprs[c - 044].segment, ins->oprs[c - 044].wrt);
1231 offset += size;
1232 break;
1233
1234 case 050:
1235 case 051:
1236 case 052:
1237 case 053:
1238 if (ins->oprs[c - 050].segment != segment)
1239 errfunc(ERR_NONFATAL,
1240 "short relative jump outside segment");
1241 data = ins->oprs[c - 050].offset - insn_end;
1242 if (data > 127 || data < -128)
1243 errfunc(ERR_NONFATAL, "short jump is out of range");
1244 bytes[0] = data;
1245 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1246 offset += 1;
1247 break;
1248
1249 case 054:
1250 case 055:
1251 case 056:
1252 case 057:
1253 data = (int64_t)ins->oprs[c - 054].offset;
1254 out(offset, segment, &data, OUT_ADDRESS + 8,
1255 ins->oprs[c - 054].segment, ins->oprs[c - 054].wrt);
1256 offset += 8;
1257 break;
1258
1259 case 060:
1260 case 061:
1261 case 062:
1262 case 063:
1263 if (ins->oprs[c - 060].segment != segment) {
1264 data = ins->oprs[c - 060].offset;
1265 out(offset, segment, &data,
1266 OUT_REL2ADR + insn_end - offset,
1267 ins->oprs[c - 060].segment, ins->oprs[c - 060].wrt);
1268 } else {
1269 data = ins->oprs[c - 060].offset - insn_end;
1270 out(offset, segment, &data,
1271 OUT_ADDRESS + 2, NO_SEG, NO_SEG);
1272 }
1273 offset += 2;
1274 break;
1275
1276 case 064:
1277 case 065:
1278 case 066:
1279 case 067:
1280 if (ins->oprs[c - 064].type & (BITS16 | BITS32 | BITS64))
1281 size = (ins->oprs[c - 064].type & BITS16) ? 2 : 4;
1282 else
1283 size = (bits == 16) ? 2 : 4;
1284 if (ins->oprs[c - 064].segment != segment) {
1285 int32_t reltype = (size == 2 ? OUT_REL2ADR : OUT_REL4ADR);
1286 data = ins->oprs[c - 064].offset;
1287 out(offset, segment, &data, reltype + insn_end - offset,
1288 ins->oprs[c - 064].segment, ins->oprs[c - 064].wrt);
1289 } else {
1290 data = ins->oprs[c - 064].offset - insn_end;
1291 out(offset, segment, &data,
1292 OUT_ADDRESS + size, NO_SEG, NO_SEG);
1293 }
1294 offset += size;
1295 break;
1296
1297 case 070:
1298 case 071:
1299 case 072:
1300 case 073:
1301 if (ins->oprs[c - 070].segment != segment) {
1302 data = ins->oprs[c - 070].offset;
1303 out(offset, segment, &data,
1304 OUT_REL4ADR + insn_end - offset,
1305 ins->oprs[c - 070].segment, ins->oprs[c - 070].wrt);
1306 } else {
1307 data = ins->oprs[c - 070].offset - insn_end;
1308 out(offset, segment, &data,
1309 OUT_ADDRESS + 4, NO_SEG, NO_SEG);
1310 }
1311 offset += 4;
1312 break;
1313
1314 case 074:
1315 case 075:
1316 case 076:
1317 case 077:
1318 if (ins->oprs[c - 074].segment == NO_SEG)
1319 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1320 " relocatable");
1321 data = 0L;
1322 out(offset, segment, &data, OUT_ADDRESS + 2,
1323 outfmt->segbase(1 + ins->oprs[c - 074].segment),
1324 ins->oprs[c - 074].wrt);
1325 offset += 2;
1326 break;
1327
1328 case 0140:
1329 case 0141:
1330 case 0142:
1331 case 0143:
1332 data = ins->oprs[c - 0140].offset;
1333 if (is_sbyte(ins, c - 0140, 16)) {
1334 bytes[0] = data;
1335 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1336 NO_SEG);
1337 offset++;
1338 } else {
1339 if (ins->oprs[c - 0140].segment == NO_SEG &&
1340 ins->oprs[c - 0140].wrt == NO_SEG &&
1341 (data < -65536L || data > 65535L)) {
1342 errfunc(ERR_WARNING, "word value exceeds bounds");
1343 }
1344 out(offset, segment, &data, OUT_ADDRESS + 2,
1345 ins->oprs[c - 0140].segment, ins->oprs[c - 0140].wrt);
1346 offset += 2;
1347 }
1348 break;
1349
1350 case 0144:
1351 case 0145:
1352 case 0146:
1353 case 0147:
1354 EMIT_REX();
1355 codes++;
1356 bytes[0] = *codes++;
1357 if (is_sbyte(ins, c - 0144, 16))
1358 bytes[0] |= 2; /* s-bit */
1359 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1360 offset++;
1361 break;
1362
1363 case 0150:
1364 case 0151:
1365 case 0152:
1366 case 0153:
1367 data = ins->oprs[c - 0150].offset;
1368 if (is_sbyte(ins, c - 0150, 32)) {
1369 bytes[0] = data;
1370 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG,
1371 NO_SEG);
1372 offset++;
1373 } else {
1374 out(offset, segment, &data, OUT_ADDRESS + 4,
1375 ins->oprs[c - 0150].segment, ins->oprs[c - 0150].wrt);
1376 offset += 4;
1377 }
1378 break;
1379
1380 case 0154:
1381 case 0155:
1382 case 0156:
1383 case 0157:
1384 EMIT_REX();
1385 codes++;
1386 bytes[0] = *codes++;
1387 if (is_sbyte(ins, c - 0154, 32))
1388 bytes[0] |= 2; /* s-bit */
1389 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1390 offset++;
1391 break;
1392
1393 case 0160:
1394 case 0161:
1395 case 0162:
1396 case 0163:
1397 case 0164:
1398 case 0165:
1399 case 0166:
1400 case 0167:
1401 break;
1402
1403 case 0170:
1404 EMIT_REX();
1405 bytes[0] = 0;
1406 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1407 offset += 1;
1408 break;
1409
1410 case 0171:
1411 bytes[0] =
1412 (ins->drexdst << 4) |
1413 (ins->rex & REX_OC ? 0x08 : 0) |
1414 (ins->rex & (REX_R|REX_X|REX_B));
1415 ins->rex = 0;
1416 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1417 offset++;
1418 break;
1419
1420 case 0300:
1421 case 0301:
1422 case 0302:
1423 case 0303:
1424 break;
1425
1426 case 0310:
1427 if (bits == 32 && !has_prefix(ins,P_A16)) {
1428 *bytes = 0x67;
1429 out(offset, segment, bytes,
1430 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1431 offset += 1;
1432 } else
1433 offset += 0;
1434 break;
1435
1436 case 0311:
1437 if (bits != 32 && !has_prefix(ins,P_A32)) {
1438 *bytes = 0x67;
1439 out(offset, segment, bytes,
1440 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1441 offset += 1;
1442 } else
1443 offset += 0;
1444 break;
1445
1446 case 0312:
1447 break;
1448
1449 case 0313:
1450 ins->rex = 0;
1451 break;
1452
1453 case 0320:
1454 if (bits != 16) {
1455 *bytes = 0x66;
1456 out(offset, segment, bytes,
1457 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1458 offset += 1;
1459 } else
1460 offset += 0;
1461 break;
1462
1463 case 0321:
1464 if (bits == 16) {
1465 *bytes = 0x66;
1466 out(offset, segment, bytes,
1467 OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1468 offset += 1;
1469 } else
1470 offset += 0;
1471 break;
1472
1473 case 0322:
1474 case 0323:
1475 break;
1476
1477 case 0324:
1478 ins->rex |= REX_W;
1479 break;
1480
1481 case 0330:
1482 *bytes = *codes++ ^ condval[ins->condition];
1483 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1484 offset += 1;
1485 break;
1486
1487 case 0331:
1488 break;
1489
1490 case 0332:
1491 case 0333:
1492 *bytes = c - 0332 + 0xF2;
1493 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1494 offset += 1;
1495 break;
1496
1497 case 0334:
1498 if (ins->rex & REX_R) {
1499 *bytes = 0xF0;
1500 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1501 offset += 1;
1502 }
1503 ins->rex &= ~(REX_L|REX_R);
1504 break;
1505
1506 case 0335:
1507 break;
1508
1509 case 0340:
1510 case 0341:
1511 case 0342:
1512 if (ins->oprs[0].segment != NO_SEG)
1513 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1514 else {
1515 int32_t size = ins->oprs[0].offset << (c - 0340);
1516 if (size > 0)
1517 out(offset, segment, NULL,
1518 OUT_RESERVE + size, NO_SEG, NO_SEG);
1519 offset += size;
1520 }
1521 break;
1522
1523 case 0364:
1524 case 0365:
1525 break;
1526
1527 case 0366:
1528 case 0367:
1529 *bytes = c - 0366 + 0x66;
1530 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1531 offset += 1;
1532 break;
1533
1534 case 0370:
1535 case 0371:
1536 case 0372:
1537 break;
1538
1539 case 0373:
1540 *bytes = bits == 16 ? 3 : 5;
1541 out(offset, segment, bytes, OUT_RAWDATA + 1, NO_SEG, NO_SEG);
1542 offset += 1;
1543 break;
1544
1545 default: /* can't do it by 'case' statements */
1546 if (c >= 0100 && c <= 0277) { /* it's an EA */
1547 ea ea_data;
1548 int rfield;
1549 int32_t rflags;
1550 uint8_t *p;
1551 int32_t s;
1552
1553 if (c <= 0177) {
1554 /* pick rfield from operand b */
1555 rflags = regflag(&ins->oprs[c & 7]);
1556 rfield = regvals[ins->oprs[c & 7].basereg];
1557 } else {
1558 /* rfield is constant */
1559 rflags = 0;
1560 rfield = c & 7;
1561 }
1562
1563 if (!process_ea
1564 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1565 rfield, rflags, ins->forw_ref)) {
1566 errfunc(ERR_NONFATAL, "invalid effective address");
1567 }
1568
1569 p = bytes;
1570 *p++ = ea_data.modrm;
1571 if (ea_data.sib_present)
1572 *p++ = ea_data.sib;
1573
1574 /* DREX suffixes come between the SIB and the displacement */
1575 if (ins->rex & REX_D) {
1576 *p++ =
1577 (ins->drexdst << 4) |
1578 (ins->rex & REX_OC ? 0x08 : 0) |
1579 (ins->rex & (REX_R|REX_X|REX_B));
1580 ins->rex = 0;
1581 }
1582
1583 s = p - bytes;
1584 out(offset, segment, bytes, OUT_RAWDATA + s,
1585 NO_SEG, NO_SEG);
1586
1587 switch (ea_data.bytes) {
1588 case 0:
1589 break;
1590 case 1:
1591 if (ins->oprs[(c >> 3) & 7].segment != NO_SEG) {
1592 data = ins->oprs[(c >> 3) & 7].offset;
1593 out(offset, segment, &data, OUT_ADDRESS + 1,
1594 ins->oprs[(c >> 3) & 7].segment,
1595 ins->oprs[(c >> 3) & 7].wrt);
1596 } else {
1597 *bytes = ins->oprs[(c >> 3) & 7].offset;
1598 out(offset, segment, bytes, OUT_RAWDATA + 1,
1599 NO_SEG, NO_SEG);
1600 }
1601 s++;
1602 break;
1603 case 8:
1604 case 2:
1605 case 4:
1606 data = ins->oprs[(c >> 3) & 7].offset;
1607 out(offset, segment, &data,
1608 (ea_data.rip ? OUT_REL4ADR : OUT_ADDRESS)
1609 + ea_data.bytes,
1610 ins->oprs[(c >> 3) & 7].segment,
1611 ins->oprs[(c >> 3) & 7].wrt);
1612 s += ea_data.bytes;
1613 break;
1614 }
1615 offset += s;
1616 } else
1617 errfunc(ERR_PANIC, "internal instruction table corrupt"
1618 ": instruction code 0x%02X given", c);
1619 }
1620 }
1621
1622 static int32_t regflag(const operand * o)
1623 {
1624 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1625 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1626 }
1627 return reg_flags[o->basereg];
1628 }
1629
1630 static int32_t regval(const operand * o)
1631 {
1632 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1633 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1634 }
1635 return regvals[o->basereg];
1636 }
1637
1638 static int op_rexflags(const operand * o, int mask)
1639 {
1640 int32_t flags;
1641 int val;
1642
1643 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1644 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1645 }
1646
1647 flags = reg_flags[o->basereg];
1648 val = regvals[o->basereg];
1649
1650 return rexflags(val, flags, mask);
1651 }
1652
1653 static int rexflags(int val, int32_t flags, int mask)
1654 {
1655 int rex = 0;
1656
1657 if (val >= 8)
1658 rex |= REX_B|REX_X|REX_R;
1659 if (flags & BITS64)
1660 rex |= REX_W;
1661 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1662 rex |= REX_H;
1663 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1664 rex |= REX_P;
1665
1666 return rex & mask;
1667 }
1668
1669 static int matches(const struct itemplate *itemp, insn * instruction, int bits)
1670 {
1671 int i, size[MAX_OPERANDS], asize, oprs, ret;
1672
1673 ret = 100;
1674
1675 /*
1676 * Check the opcode
1677 */
1678 if (itemp->opcode != instruction->opcode)
1679 return 0;
1680
1681 /*
1682 * Count the operands
1683 */
1684 if (itemp->operands != instruction->operands)
1685 return 0;
1686
1687 /*
1688 * Check that no spurious colons or TOs are present
1689 */
1690 for (i = 0; i < itemp->operands; i++)
1691 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1692 return 0;
1693
1694 /*
1695 * Check that the operand flags all match up
1696 */
1697 for (i = 0; i < itemp->operands; i++) {
1698 if (itemp->opd[i] & SAME_AS) {
1699 int j = itemp->opd[i] & ~SAME_AS;
1700 if (instruction->oprs[i].type != instruction->oprs[j].type ||
1701 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
1702 return 0;
1703 } else if (itemp->opd[i] & ~instruction->oprs[i].type ||
1704 ((itemp->opd[i] & SIZE_MASK) &&
1705 ((itemp->opd[i] ^ instruction->oprs[i].type) & SIZE_MASK))) {
1706 if ((itemp->opd[i] & ~instruction->oprs[i].type & ~SIZE_MASK) ||
1707 (instruction->oprs[i].type & SIZE_MASK))
1708 return 0;
1709 else
1710 return 1;
1711 }
1712 }
1713
1714 /*
1715 * Check operand sizes
1716 */
1717 if (itemp->flags & IF_ARMASK) {
1718 memset(size, 0, sizeof size);
1719
1720 switch (itemp->flags & IF_ARMASK) {
1721 case IF_AR0:
1722 i = 0;
1723 break;
1724 case IF_AR1:
1725 i = 1;
1726 break;
1727 case IF_AR2:
1728 i = 2;
1729 break;
1730 case IF_AR3:
1731 i = 3;
1732 break;
1733 default:
1734 break; /* Shouldn't happen */
1735 }
1736 switch (itemp->flags & IF_SMASK) {
1737 case IF_SB:
1738 size[i] = BITS8;
1739 break;
1740 case IF_SW:
1741 size[i] = BITS16;
1742 break;
1743 case IF_SD:
1744 size[i] = BITS32;
1745 break;
1746 case IF_SQ:
1747 size[i] = BITS64;
1748 break;
1749 case IF_SO:
1750 size[i] = BITS128;
1751 break;
1752 default:
1753 break;
1754 }
1755 } else {
1756 asize = 0;
1757 switch (itemp->flags & IF_SMASK) {
1758 case IF_SB:
1759 asize = BITS8;
1760 oprs = itemp->operands;
1761 break;
1762 case IF_SW:
1763 asize = BITS16;
1764 oprs = itemp->operands;
1765 break;
1766 case IF_SD:
1767 asize = BITS32;
1768 oprs = itemp->operands;
1769 break;
1770 case IF_SQ:
1771 asize = BITS64;
1772 oprs = itemp->operands;
1773 break;
1774 case IF_SO:
1775 asize = BITS128;
1776 oprs = itemp->operands;
1777 break;
1778 default:
1779 break;
1780 }
1781 for (i = 0; i < MAX_OPERANDS; i++)
1782 size[i] = asize;
1783 }
1784
1785 if (itemp->flags & (IF_SM | IF_SM2)) {
1786 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
1787 asize = 0;
1788 for (i = 0; i < oprs; i++) {
1789 if ((asize = itemp->opd[i] & SIZE_MASK) != 0) {
1790 int j;
1791 for (j = 0; j < oprs; j++)
1792 size[j] = asize;
1793 break;
1794 }
1795 }
1796 } else {
1797 oprs = itemp->operands;
1798 }
1799
1800 for (i = 0; i < itemp->operands; i++) {
1801 if (!(itemp->opd[i] & SIZE_MASK) &&
1802 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
1803 return 2;
1804 }
1805
1806 /*
1807 * Check template is okay at the set cpu level
1808 */
1809 if (((itemp->flags & IF_PLEVEL) > cpu))
1810 return 3;
1811
1812 /*
1813 * Check if instruction is available in long mode
1814 */
1815 if ((itemp->flags & IF_NOLONG) && (bits == 64))
1816 return 4;
1817
1818 /*
1819 * Check if special handling needed for Jumps
1820 */
1821 if ((uint8_t)(itemp->code[0]) >= 0370)
1822 return 99;
1823
1824 return ret;
1825 }
1826
1827 static ea *process_ea(operand * input, ea * output, int addrbits,
1828 int rfield, int32_t rflags, int forw_ref)
1829 {
1830 output->rip = false;
1831
1832 /* REX flags for the rfield operand */
1833 output->rex |= rexflags(rfield, rflags, REX_R|REX_P|REX_W|REX_H);
1834
1835 if (!(REGISTER & ~input->type)) { /* register direct */
1836 int i;
1837 int32_t f;
1838
1839 if (input->basereg < EXPR_REG_START /* Verify as Register */
1840 || input->basereg >= REG_ENUM_LIMIT)
1841 return NULL;
1842 f = regflag(input);
1843 i = regvals[input->basereg];
1844
1845 if (REG_EA & ~f)
1846 return NULL; /* Invalid EA register */
1847
1848 output->rex |= op_rexflags(input, REX_B|REX_P|REX_W|REX_H);
1849
1850 output->sib_present = false; /* no SIB necessary */
1851 output->bytes = 0; /* no offset necessary either */
1852 output->modrm = 0xC0 | ((rfield & 7) << 3) | (i & 7);
1853 } else { /* it's a memory reference */
1854 if (input->basereg == -1
1855 && (input->indexreg == -1 || input->scale == 0)) {
1856 /* it's a pure offset */
1857 if (input->addr_size)
1858 addrbits = input->addr_size;
1859
1860 if (globalbits == 64 && (~input->type & IP_REL)) {
1861 int scale, index, base;
1862 output->sib_present = true;
1863 scale = 0;
1864 index = 4;
1865 base = 5;
1866 output->sib = (scale << 6) | (index << 3) | base;
1867 output->bytes = 4;
1868 output->modrm = 4 | ((rfield & 7) << 3);
1869 output->rip = false;
1870 } else {
1871 output->sib_present = false;
1872 output->bytes = (addrbits != 16 ? 4 : 2);
1873 output->modrm = (addrbits != 16 ? 5 : 6) | ((rfield & 7) << 3);
1874 output->rip = globalbits == 64;
1875 }
1876 } else { /* it's an indirection */
1877 int i = input->indexreg, b = input->basereg, s = input->scale;
1878 int32_t o = input->offset, seg = input->segment;
1879 int hb = input->hintbase, ht = input->hinttype;
1880 int t;
1881 int it, bt;
1882 int32_t ix, bx; /* register flags */
1883
1884 if (s == 0)
1885 i = -1; /* make this easy, at least */
1886
1887 if (i >= EXPR_REG_START && i < REG_ENUM_LIMIT) {
1888 it = regvals[i];
1889 ix = reg_flags[i];
1890 } else {
1891 it = -1;
1892 ix = 0;
1893 }
1894
1895 if (b != -1 && b >= EXPR_REG_START && b < REG_ENUM_LIMIT) {
1896 bt = regvals[b];
1897 bx = reg_flags[b];
1898 } else {
1899 bt = -1;
1900 bx = 0;
1901 }
1902
1903 /* check for a 32/64-bit memory reference... */
1904 if ((ix|bx) & (BITS32|BITS64)) {
1905 /* it must be a 32/64-bit memory reference. Firstly we have
1906 * to check that all registers involved are type E/Rxx. */
1907 int32_t sok = BITS32|BITS64;
1908
1909 if (it != -1) {
1910 if (!(REG64 & ~ix) || !(REG32 & ~ix))
1911 sok &= ix;
1912 else
1913 return NULL;
1914 }
1915
1916 if (bt != -1) {
1917 if (REG_GPR & ~bx)
1918 return NULL; /* Invalid register */
1919 if (~sok & bx & SIZE_MASK)
1920 return NULL; /* Invalid size */
1921 sok &= ~bx;
1922 }
1923
1924 /* While we're here, ensure the user didn't specify WORD. */
1925 if (input->addr_size == 16 ||
1926 (input->addr_size == 32 && !(sok & BITS32)) ||
1927 (input->addr_size == 64 && !(sok & BITS64)))
1928 return NULL;
1929
1930 /* now reorganize base/index */
1931 if (s == 1 && bt != it && bt != -1 && it != -1 &&
1932 ((hb == b && ht == EAH_NOTBASE)
1933 || (hb == i && ht == EAH_MAKEBASE))) {
1934 /* swap if hints say so */
1935 t = bt, bt = it, it = t;
1936 t = bx, bx = ix, ix = t;
1937 }
1938 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
1939 bt = -1, bx = 0, s++;
1940 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
1941 /* make single reg base, unless hint */
1942 bt = it, bx = ix, it = -1, ix = 0;
1943 }
1944 if (((s == 2 && it != REG_NUM_ESP
1945 && !(input->eaflags & EAF_TIMESTWO)) || s == 3
1946 || s == 5 || s == 9) && bt == -1)
1947 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
1948 if (it == -1 && (bt & 7) != REG_NUM_ESP
1949 && (input->eaflags & EAF_TIMESTWO))
1950 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
1951 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
1952 if (s == 1 && it == REG_NUM_ESP) {
1953 /* swap ESP into base if scale is 1 */
1954 t = it, it = bt, bt = t;
1955 t = ix, ix = bx, bx = t;
1956 }
1957 if (it == REG_NUM_ESP
1958 || (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
1959 return NULL; /* wrong, for various reasons */
1960
1961 output->rex |= rexflags(it, ix, REX_X);
1962 output->rex |= rexflags(bt, bx, REX_B);
1963
1964 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
1965 /* no SIB needed */
1966 int mod, rm;
1967
1968 if (bt == -1) {
1969 rm = 5;
1970 mod = 0;
1971 } else {
1972 rm = (bt & 7);
1973 if (rm != REG_NUM_EBP && o == 0 &&
1974 seg == NO_SEG && !forw_ref &&
1975 !(input->eaflags &
1976 (EAF_BYTEOFFS | EAF_WORDOFFS)))
1977 mod = 0;
1978 else if (input->eaflags & EAF_BYTEOFFS ||
1979 (o >= -128 && o <= 127 && seg == NO_SEG
1980 && !forw_ref
1981 && !(input->eaflags & EAF_WORDOFFS)))
1982 mod = 1;
1983 else
1984 mod = 2;
1985 }
1986
1987 output->sib_present = false;
1988 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
1989 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
1990 } else {
1991 /* we need a SIB */
1992 int mod, scale, index, base;
1993
1994 if (it == -1)
1995 index = 4, s = 1;
1996 else
1997 index = (it & 7);
1998
1999 switch (s) {
2000 case 1:
2001 scale = 0;
2002 break;
2003 case 2:
2004 scale = 1;
2005 break;
2006 case 4:
2007 scale = 2;
2008 break;
2009 case 8:
2010 scale = 3;
2011 break;
2012 default: /* then what the smeg is it? */
2013 return NULL; /* panic */
2014 }
2015
2016 if (bt == -1) {
2017 base = 5;
2018 mod = 0;
2019 } else {
2020 base = (bt & 7);
2021 if (base != REG_NUM_EBP && o == 0 &&
2022 seg == NO_SEG && !forw_ref &&
2023 !(input->eaflags &
2024 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2025 mod = 0;
2026 else if (input->eaflags & EAF_BYTEOFFS ||
2027 (o >= -128 && o <= 127 && seg == NO_SEG
2028 && !forw_ref
2029 && !(input->eaflags & EAF_WORDOFFS)))
2030 mod = 1;
2031 else
2032 mod = 2;
2033 }
2034
2035 output->sib_present = true;
2036 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2037 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2038 output->sib = (scale << 6) | (index << 3) | base;
2039 }
2040 } else { /* it's 16-bit */
2041 int mod, rm;
2042
2043 /* check for 64-bit long mode */
2044 if (addrbits == 64)
2045 return NULL;
2046
2047 /* check all registers are BX, BP, SI or DI */
2048 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI
2049 && b != R_DI) || (i != -1 && i != R_BP && i != R_BX
2050 && i != R_SI && i != R_DI))
2051 return NULL;
2052
2053 /* ensure the user didn't specify DWORD/QWORD */
2054 if (input->addr_size == 32 || input->addr_size == 64)
2055 return NULL;
2056
2057 if (s != 1 && i != -1)
2058 return NULL; /* no can do, in 16-bit EA */
2059 if (b == -1 && i != -1) {
2060 int tmp = b;
2061 b = i;
2062 i = tmp;
2063 } /* swap */
2064 if ((b == R_SI || b == R_DI) && i != -1) {
2065 int tmp = b;
2066 b = i;
2067 i = tmp;
2068 }
2069 /* have BX/BP as base, SI/DI index */
2070 if (b == i)
2071 return NULL; /* shouldn't ever happen, in theory */
2072 if (i != -1 && b != -1 &&
2073 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2074 return NULL; /* invalid combinations */
2075 if (b == -1) /* pure offset: handled above */
2076 return NULL; /* so if it gets to here, panic! */
2077
2078 rm = -1;
2079 if (i != -1)
2080 switch (i * 256 + b) {
2081 case R_SI * 256 + R_BX:
2082 rm = 0;
2083 break;
2084 case R_DI * 256 + R_BX:
2085 rm = 1;
2086 break;
2087 case R_SI * 256 + R_BP:
2088 rm = 2;
2089 break;
2090 case R_DI * 256 + R_BP:
2091 rm = 3;
2092 break;
2093 } else
2094 switch (b) {
2095 case R_SI:
2096 rm = 4;
2097 break;
2098 case R_DI:
2099 rm = 5;
2100 break;
2101 case R_BP:
2102 rm = 6;
2103 break;
2104 case R_BX:
2105 rm = 7;
2106 break;
2107 }
2108 if (rm == -1) /* can't happen, in theory */
2109 return NULL; /* so panic if it does */
2110
2111 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2112 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2113 mod = 0;
2114 else if (input->eaflags & EAF_BYTEOFFS ||
2115 (o >= -128 && o <= 127 && seg == NO_SEG
2116 && !forw_ref
2117 && !(input->eaflags & EAF_WORDOFFS)))
2118 mod = 1;
2119 else
2120 mod = 2;
2121
2122 output->sib_present = false; /* no SIB - it's 16-bit */
2123 output->bytes = mod; /* bytes of offset needed */
2124 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2125 }
2126 }
2127 }
2128
2129 output->size = 1 + output->sib_present + output->bytes;
2130 return output;
2131 }
2132
2133 static void add_asp(insn *instruction, int addrbits)
2134 {
2135 int j, valid;
2136
2137 valid = (addrbits == 64) ? 64|32 : 32|16;
2138
2139 for (j = 0; j < instruction->operands; j++) {
2140 if (!(MEMORY & ~instruction->oprs[j].type)) {
2141 int32_t i, b;
2142
2143 /* Verify as Register */
2144 if (instruction->oprs[j].indexreg < EXPR_REG_START
2145 || instruction->oprs[j].indexreg >= REG_ENUM_LIMIT)
2146 i = 0;
2147 else
2148 i = reg_flags[instruction->oprs[j].indexreg];
2149
2150 /* Verify as Register */
2151 if (instruction->oprs[j].basereg < EXPR_REG_START
2152 || instruction->oprs[j].basereg >= REG_ENUM_LIMIT)
2153 b = 0;
2154 else
2155 b = reg_flags[instruction->oprs[j].basereg];
2156
2157 if (instruction->oprs[j].scale == 0)
2158 i = 0;
2159
2160 if (!i && !b) {
2161 if (instruction->oprs[j].addr_size)
2162 valid &= instruction->oprs[j].addr_size;
2163 } else {
2164 if (!(REG16 & ~b))
2165 valid &= 16;
2166 if (!(REG32 & ~b))
2167 valid &= 32;
2168 if (!(REG64 & ~b))
2169 valid &= 64;
2170
2171 if (!(REG16 & ~i))
2172 valid &= 16;
2173 if (!(REG32 & ~i))
2174 valid &= 32;
2175 if (!(REG64 & ~i))
2176 valid &= 64;
2177 }
2178 }
2179 }
2180
2181 if (valid & addrbits) {
2182 /* Don't do anything */
2183 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2184 /* Add an instruction size prefix */
2185 enum prefixes pref = (addrbits == 32) ? P_A16 : P_A32;
2186 for (j = 0; j < instruction->nprefix; j++) {
2187 if (instruction->prefixes[j] == pref)
2188 return; /* Already there */
2189 }
2190 instruction->prefixes[j] = pref;
2191 instruction->nprefix++;
2192 } else {
2193 /* Impossible... */
2194 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2195 }
2196 }
The Netwide Assembler