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process_ea: Drop redundant variable
[nasm.git] / assemble.c
blobf0253606d8590b54e4c498840a8b54b7ba4b3052
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2012 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \20..\23 - a byte immediate operand, from operand 0..3
46 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
47 * \30..\33 - a word immediate operand, from operand 0..3
48 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
49 * assembly mode or the operand-size override on the operand
50 * \40..\43 - a long immediate operand, from operand 0..3
51 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
52 * depending on the address size of the instruction.
53 * \50..\53 - a byte relative operand, from operand 0..3
54 * \54..\57 - a qword immediate operand, from operand 0..3
55 * \60..\63 - a word relative operand, from operand 0..3
56 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
57 * assembly mode or the operand-size override on the operand
58 * \70..\73 - a long relative operand, from operand 0..3
59 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
60 * \1ab - a ModRM, calculated on EA in operand a, with the spare
61 * field the register value of operand b.
62 * \172\ab - the register number from operand a in bits 7..4, with
63 * the 4-bit immediate from operand b in bits 3..0.
64 * \173\xab - the register number from operand a in bits 7..4, with
65 * the value b in bits 3..0.
66 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
67 * an arbitrary value in bits 3..0 (assembled as zero.)
68 * \2ab - a ModRM, calculated on EA in operand a, with the spare
69 * field equal to digit b.
70 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
71 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
72 * V field taken from operand 0..3.
73 * \270 - this instruction uses VEX/XOP rather than REX, with the
74 * V field set to 1111b.
75 *
76 * VEX/XOP prefixes are followed by the sequence:
77 * \tmm\wlp where mm is the M field; and wlp is:
78 * 00 wwl lpp
79 * [l0] ll = 0 for L = 0 (.128, .lz)
80 * [l1] ll = 1 for L = 1 (.256)
81 * [lig] ll = 2 for L don't care (always assembled as 0)
82 *
83 * [w0] ww = 0 for W = 0
84 * [w1 ] ww = 1 for W = 1
85 * [wig] ww = 2 for W don't care (always assembled as 0)
86 * [ww] ww = 3 for W used as REX.W
87 *
88 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
89 *
90 * \271 - instruction takes XRELEASE (F3) with or without lock
91 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
92 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
93 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
94 * to the operand size (if o16/o32/o64 present) or the bit size
95 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
96 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
97 * \312 - (disassembler only) invalid with non-default address size.
98 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
99 * \314 - (disassembler only) invalid with REX.B
100 * \315 - (disassembler only) invalid with REX.X
101 * \316 - (disassembler only) invalid with REX.R
102 * \317 - (disassembler only) invalid with REX.W
103 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
104 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
105 * \322 - indicates that this instruction is only valid when the
106 * operand size is the default (instruction to disassembler,
107 * generates no code in the assembler)
108 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
109 * \324 - indicates 64-bit operand size requiring REX prefix.
110 * \325 - instruction which always uses spl/bpl/sil/dil
111 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
112 disassembler only; for SSE instructions.
113 * \330 - a literal byte follows in the code stream, to be added
114 * to the condition code value of the instruction.
115 * \331 - instruction not valid with REP prefix. Hint for
116 * disassembler only; for SSE instructions.
117 * \332 - REP prefix (0xF2 byte) used as opcode extension.
118 * \333 - REP prefix (0xF3 byte) used as opcode extension.
119 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
120 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
121 * \336 - force a REP(E) prefix (0xF3) even if not specified.
122 * \337 - force a REPNE prefix (0xF2) even if not specified.
123 * \336-\337 are still listed as prefixes in the disassembler.
124 * \340 - reserve <operand 0> bytes of uninitialized storage.
125 * Operand 0 had better be a segmentless constant.
126 * \341 - this instruction needs a WAIT "prefix"
127 * \344,\345 - the PUSH/POP (respectively) codes for CS, DS, ES, SS
128 * (POP is never used for CS) depending on operand 0
129 * \346,\347 - the second byte of PUSH/POP codes for FS, GS, depending
130 * on operand 0
131 * \360 - no SSE prefix (== \364\331)
132 * \361 - 66 SSE prefix (== \366\331)
133 * \362 - F2 SSE prefix (== \364\332)
134 * \363 - F3 SSE prefix (== \364\333)
135 * \364 - operand-size prefix (0x66) not permitted
136 * \365 - address-size prefix (0x67) not permitted
137 * \366 - operand-size prefix (0x66) used as opcode extension
138 * \367 - address-size prefix (0x67) used as opcode extension
139 * \370,\371 - match only if operand 0 meets byte jump criteria.
140 * 370 is used for Jcc, 371 is used for JMP.
141 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
142 * used for conditional jump over longer jump
143 * \374 - this instruction takes an XMM VSIB memory EA
144 * \375 - this instruction takes an YMM VSIB memory EA
145 */
146
147 #include "compiler.h"
148
149 #include <stdio.h>
150 #include <string.h>
151 #include <inttypes.h>
152
153 #include "nasm.h"
154 #include "nasmlib.h"
155 #include "assemble.h"
156 #include "insns.h"
157 #include "tables.h"
158
159 enum match_result {
160 /*
161 * Matching errors. These should be sorted so that more specific
162 * errors come later in the sequence.
163 */
164 MERR_INVALOP,
165 MERR_OPSIZEMISSING,
166 MERR_OPSIZEMISMATCH,
167 MERR_BADCPU,
168 MERR_BADMODE,
169 MERR_BADHLE,
170 /*
171 * Matching success; the conditional ones first
172 */
173 MOK_JUMP, /* Matching OK but needs jmp_match() */
174 MOK_GOOD /* Matching unconditionally OK */
175 };
176
177 typedef struct {
178 enum ea_type type; /* what kind of EA is this? */
179 int sib_present; /* is a SIB byte necessary? */
180 int bytes; /* # of bytes of offset needed */
181 int size; /* lazy - this is sib+bytes+1 */
182 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
183 } ea;
184
185 #define GEN_SIB(scale, index, base) \
186 (((scale) << 6) | ((index) << 3) | ((base)))
187
188 #define GEN_MODRM(mod, reg, rm) \
189 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
190
191 static uint32_t cpu; /* cpu level received from nasm.c */
192 static efunc errfunc;
193 static struct ofmt *outfmt;
194 static ListGen *list;
195
196 static int64_t calcsize(int32_t, int64_t, int, insn *,
197 const struct itemplate *);
198 static void gencode(int32_t segment, int64_t offset, int bits,
199 insn * ins, const struct itemplate *temp,
200 int64_t insn_end);
201 static enum match_result find_match(const struct itemplate **tempp,
202 insn *instruction,
203 int32_t segment, int64_t offset, int bits);
204 static enum match_result matches(const struct itemplate *, insn *, int bits);
205 static opflags_t regflag(const operand *);
206 static int32_t regval(const operand *);
207 static int rexflags(int, opflags_t, int);
208 static int op_rexflags(const operand *, int);
209 static void add_asp(insn *, int);
210
211 static enum ea_type process_ea(operand *, ea *, int, int, int, opflags_t);
212
213 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
214 {
215 return ins->prefixes[pos] == prefix;
216 }
217
218 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
219 {
220 if (ins->prefixes[pos])
221 errfunc(ERR_NONFATAL, "invalid %s prefix",
222 prefix_name(ins->prefixes[pos]));
223 }
224
225 static const char *size_name(int size)
226 {
227 switch (size) {
228 case 1:
229 return "byte";
230 case 2:
231 return "word";
232 case 4:
233 return "dword";
234 case 8:
235 return "qword";
236 case 10:
237 return "tword";
238 case 16:
239 return "oword";
240 case 32:
241 return "yword";
242 default:
243 return "???";
244 }
245 }
246
247 static void warn_overflow(int pass, int size)
248 {
249 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
250 "%s data exceeds bounds", size_name(size));
251 }
252
253 static void warn_overflow_const(int64_t data, int size)
254 {
255 if (overflow_general(data, size))
256 warn_overflow(ERR_PASS1, size);
257 }
258
259 static void warn_overflow_opd(const struct operand *o, int size)
260 {
261 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
262 if (overflow_general(o->offset, size))
263 warn_overflow(ERR_PASS2, size);
264 }
265 }
266
267 /*
268 * This routine wrappers the real output format's output routine,
269 * in order to pass a copy of the data off to the listing file
270 * generator at the same time.
271 */
272 static void out(int64_t offset, int32_t segto, const void *data,
273 enum out_type type, uint64_t size,
274 int32_t segment, int32_t wrt)
275 {
276 static int32_t lineno = 0; /* static!!! */
277 static char *lnfname = NULL;
278 uint8_t p[8];
279
280 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
281 /*
282 * This is a non-relocated address, and we're going to
283 * convert it into RAWDATA format.
284 */
285 uint8_t *q = p;
286
287 if (size > 8) {
288 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
289 return;
290 }
291
292 WRITEADDR(q, *(int64_t *)data, size);
293 data = p;
294 type = OUT_RAWDATA;
295 }
296
297 list->output(offset, data, type, size);
298
299 /*
300 * this call to src_get determines when we call the
301 * debug-format-specific "linenum" function
302 * it updates lineno and lnfname to the current values
303 * returning 0 if "same as last time", -2 if lnfname
304 * changed, and the amount by which lineno changed,
305 * if it did. thus, these variables must be static
306 */
307
308 if (src_get(&lineno, &lnfname))
309 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
310
311 outfmt->output(segto, data, type, size, segment, wrt);
312 }
313
314 static void out_imm8(int64_t offset, int32_t segment, struct operand *opx)
315 {
316 if (opx->segment != NO_SEG) {
317 uint64_t data = opx->offset;
318 out(offset, segment, &data, OUT_ADDRESS, 1, opx->segment, opx->wrt);
319 } else {
320 uint8_t byte = opx->offset;
321 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
322 }
323 }
324
325 static bool jmp_match(int32_t segment, int64_t offset, int bits,
326 insn * ins, const struct itemplate *temp)
327 {
328 int64_t isize;
329 const uint8_t *code = temp->code;
330 uint8_t c = code[0];
331
332 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
333 return false;
334 if (!optimizing)
335 return false;
336 if (optimizing < 0 && c == 0371)
337 return false;
338
339 isize = calcsize(segment, offset, bits, ins, temp);
340
341 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
342 /* Be optimistic in pass 1 */
343 return true;
344
345 if (ins->oprs[0].segment != segment)
346 return false;
347
348 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
349 return (isize >= -128 && isize <= 127); /* is it byte size? */
350 }
351
352 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
353 insn * instruction, struct ofmt *output, efunc error,
354 ListGen * listgen)
355 {
356 const struct itemplate *temp;
357 int j;
358 enum match_result m;
359 int64_t insn_end;
360 int32_t itimes;
361 int64_t start = offset;
362 int64_t wsize; /* size for DB etc. */
363
364 errfunc = error; /* to pass to other functions */
365 cpu = cp;
366 outfmt = output; /* likewise */
367 list = listgen; /* and again */
368
369 wsize = idata_bytes(instruction->opcode);
370 if (wsize == -1)
371 return 0;
372
373 if (wsize) {
374 extop *e;
375 int32_t t = instruction->times;
376 if (t < 0)
377 errfunc(ERR_PANIC,
378 "instruction->times < 0 (%ld) in assemble()", t);
379
380 while (t--) { /* repeat TIMES times */
381 list_for_each(e, instruction->eops) {
382 if (e->type == EOT_DB_NUMBER) {
383 if (wsize > 8) {
384 errfunc(ERR_NONFATAL,
385 "integer supplied to a DT, DO or DY"
386 " instruction");
387 } else {
388 out(offset, segment, &e->offset,
389 OUT_ADDRESS, wsize, e->segment, e->wrt);
390 offset += wsize;
391 }
392 } else if (e->type == EOT_DB_STRING ||
393 e->type == EOT_DB_STRING_FREE) {
394 int align;
395
396 out(offset, segment, e->stringval,
397 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
398 align = e->stringlen % wsize;
399
400 if (align) {
401 align = wsize - align;
402 out(offset, segment, zero_buffer,
403 OUT_RAWDATA, align, NO_SEG, NO_SEG);
404 }
405 offset += e->stringlen + align;
406 }
407 }
408 if (t > 0 && t == instruction->times - 1) {
409 /*
410 * Dummy call to list->output to give the offset to the
411 * listing module.
412 */
413 list->output(offset, NULL, OUT_RAWDATA, 0);
414 list->uplevel(LIST_TIMES);
415 }
416 }
417 if (instruction->times > 1)
418 list->downlevel(LIST_TIMES);
419 return offset - start;
420 }
421
422 if (instruction->opcode == I_INCBIN) {
423 const char *fname = instruction->eops->stringval;
424 FILE *fp;
425
426 fp = fopen(fname, "rb");
427 if (!fp) {
428 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
429 fname);
430 } else if (fseek(fp, 0L, SEEK_END) < 0) {
431 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
432 fname);
433 } else {
434 static char buf[4096];
435 size_t t = instruction->times;
436 size_t base = 0;
437 size_t len;
438
439 len = ftell(fp);
440 if (instruction->eops->next) {
441 base = instruction->eops->next->offset;
442 len -= base;
443 if (instruction->eops->next->next &&
444 len > (size_t)instruction->eops->next->next->offset)
445 len = (size_t)instruction->eops->next->next->offset;
446 }
447 /*
448 * Dummy call to list->output to give the offset to the
449 * listing module.
450 */
451 list->output(offset, NULL, OUT_RAWDATA, 0);
452 list->uplevel(LIST_INCBIN);
453 while (t--) {
454 size_t l;
455
456 fseek(fp, base, SEEK_SET);
457 l = len;
458 while (l > 0) {
459 int32_t m;
460 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
461 if (!m) {
462 /*
463 * This shouldn't happen unless the file
464 * actually changes while we are reading
465 * it.
466 */
467 error(ERR_NONFATAL,
468 "`incbin': unexpected EOF while"
469 " reading file `%s'", fname);
470 t = 0; /* Try to exit cleanly */
471 break;
472 }
473 out(offset, segment, buf, OUT_RAWDATA, m,
474 NO_SEG, NO_SEG);
475 l -= m;
476 }
477 }
478 list->downlevel(LIST_INCBIN);
479 if (instruction->times > 1) {
480 /*
481 * Dummy call to list->output to give the offset to the
482 * listing module.
483 */
484 list->output(offset, NULL, OUT_RAWDATA, 0);
485 list->uplevel(LIST_TIMES);
486 list->downlevel(LIST_TIMES);
487 }
488 fclose(fp);
489 return instruction->times * len;
490 }
491 return 0; /* if we're here, there's an error */
492 }
493
494 /* Check to see if we need an address-size prefix */
495 add_asp(instruction, bits);
496
497 m = find_match(&temp, instruction, segment, offset, bits);
498
499 if (m == MOK_GOOD) {
500 /* Matches! */
501 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
502 itimes = instruction->times;
503 if (insn_size < 0) /* shouldn't be, on pass two */
504 error(ERR_PANIC, "errors made it through from pass one");
505 else
506 while (itimes--) {
507 for (j = 0; j < MAXPREFIX; j++) {
508 uint8_t c = 0;
509 switch (instruction->prefixes[j]) {
510 case P_WAIT:
511 c = 0x9B;
512 break;
513 case P_LOCK:
514 c = 0xF0;
515 break;
516 case P_REPNE:
517 case P_REPNZ:
518 case P_XACQUIRE:
519 c = 0xF2;
520 break;
521 case P_REPE:
522 case P_REPZ:
523 case P_REP:
524 case P_XRELEASE:
525 c = 0xF3;
526 break;
527 case R_CS:
528 if (bits == 64) {
529 error(ERR_WARNING | ERR_PASS2,
530 "cs segment base generated, but will be ignored in 64-bit mode");
531 }
532 c = 0x2E;
533 break;
534 case R_DS:
535 if (bits == 64) {
536 error(ERR_WARNING | ERR_PASS2,
537 "ds segment base generated, but will be ignored in 64-bit mode");
538 }
539 c = 0x3E;
540 break;
541 case R_ES:
542 if (bits == 64) {
543 error(ERR_WARNING | ERR_PASS2,
544 "es segment base generated, but will be ignored in 64-bit mode");
545 }
546 c = 0x26;
547 break;
548 case R_FS:
549 c = 0x64;
550 break;
551 case R_GS:
552 c = 0x65;
553 break;
554 case R_SS:
555 if (bits == 64) {
556 error(ERR_WARNING | ERR_PASS2,
557 "ss segment base generated, but will be ignored in 64-bit mode");
558 }
559 c = 0x36;
560 break;
561 case R_SEGR6:
562 case R_SEGR7:
563 error(ERR_NONFATAL,
564 "segr6 and segr7 cannot be used as prefixes");
565 break;
566 case P_A16:
567 if (bits == 64) {
568 error(ERR_NONFATAL,
569 "16-bit addressing is not supported "
570 "in 64-bit mode");
571 } else if (bits != 16)
572 c = 0x67;
573 break;
574 case P_A32:
575 if (bits != 32)
576 c = 0x67;
577 break;
578 case P_A64:
579 if (bits != 64) {
580 error(ERR_NONFATAL,
581 "64-bit addressing is only supported "
582 "in 64-bit mode");
583 }
584 break;
585 case P_ASP:
586 c = 0x67;
587 break;
588 case P_O16:
589 if (bits != 16)
590 c = 0x66;
591 break;
592 case P_O32:
593 if (bits == 16)
594 c = 0x66;
595 break;
596 case P_O64:
597 /* REX.W */
598 break;
599 case P_OSP:
600 c = 0x66;
601 break;
602 case P_none:
603 break;
604 default:
605 error(ERR_PANIC, "invalid instruction prefix");
606 }
607 if (c != 0) {
608 out(offset, segment, &c, OUT_RAWDATA, 1,
609 NO_SEG, NO_SEG);
610 offset++;
611 }
612 }
613 insn_end = offset + insn_size;
614 gencode(segment, offset, bits, instruction,
615 temp, insn_end);
616 offset += insn_size;
617 if (itimes > 0 && itimes == instruction->times - 1) {
618 /*
619 * Dummy call to list->output to give the offset to the
620 * listing module.
621 */
622 list->output(offset, NULL, OUT_RAWDATA, 0);
623 list->uplevel(LIST_TIMES);
624 }
625 }
626 if (instruction->times > 1)
627 list->downlevel(LIST_TIMES);
628 return offset - start;
629 } else {
630 /* No match */
631 switch (m) {
632 case MERR_OPSIZEMISSING:
633 error(ERR_NONFATAL, "operation size not specified");
634 break;
635 case MERR_OPSIZEMISMATCH:
636 error(ERR_NONFATAL, "mismatch in operand sizes");
637 break;
638 case MERR_BADCPU:
639 error(ERR_NONFATAL, "no instruction for this cpu level");
640 break;
641 case MERR_BADMODE:
642 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
643 bits);
644 break;
645 default:
646 error(ERR_NONFATAL,
647 "invalid combination of opcode and operands");
648 break;
649 }
650 }
651 return 0;
652 }
653
654 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
655 insn * instruction, efunc error)
656 {
657 const struct itemplate *temp;
658 enum match_result m;
659
660 errfunc = error; /* to pass to other functions */
661 cpu = cp;
662
663 if (instruction->opcode == I_none)
664 return 0;
665
666 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
667 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
668 instruction->opcode == I_DT || instruction->opcode == I_DO ||
669 instruction->opcode == I_DY) {
670 extop *e;
671 int32_t isize, osize, wsize;
672
673 isize = 0;
674 wsize = idata_bytes(instruction->opcode);
675
676 list_for_each(e, instruction->eops) {
677 int32_t align;
678
679 osize = 0;
680 if (e->type == EOT_DB_NUMBER) {
681 osize = 1;
682 warn_overflow_const(e->offset, wsize);
683 } else if (e->type == EOT_DB_STRING ||
684 e->type == EOT_DB_STRING_FREE)
685 osize = e->stringlen;
686
687 align = (-osize) % wsize;
688 if (align < 0)
689 align += wsize;
690 isize += osize + align;
691 }
692 return isize * instruction->times;
693 }
694
695 if (instruction->opcode == I_INCBIN) {
696 const char *fname = instruction->eops->stringval;
697 FILE *fp;
698 int64_t val = 0;
699 size_t len;
700
701 fp = fopen(fname, "rb");
702 if (!fp)
703 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
704 fname);
705 else if (fseek(fp, 0L, SEEK_END) < 0)
706 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
707 fname);
708 else {
709 len = ftell(fp);
710 if (instruction->eops->next) {
711 len -= instruction->eops->next->offset;
712 if (instruction->eops->next->next &&
713 len > (size_t)instruction->eops->next->next->offset) {
714 len = (size_t)instruction->eops->next->next->offset;
715 }
716 }
717 val = instruction->times * len;
718 }
719 if (fp)
720 fclose(fp);
721 return val;
722 }
723
724 /* Check to see if we need an address-size prefix */
725 add_asp(instruction, bits);
726
727 m = find_match(&temp, instruction, segment, offset, bits);
728 if (m == MOK_GOOD) {
729 /* we've matched an instruction. */
730 int64_t isize;
731 int j;
732
733 isize = calcsize(segment, offset, bits, instruction, temp);
734 if (isize < 0)
735 return -1;
736 for (j = 0; j < MAXPREFIX; j++) {
737 switch (instruction->prefixes[j]) {
738 case P_A16:
739 if (bits != 16)
740 isize++;
741 break;
742 case P_A32:
743 if (bits != 32)
744 isize++;
745 break;
746 case P_O16:
747 if (bits != 16)
748 isize++;
749 break;
750 case P_O32:
751 if (bits == 16)
752 isize++;
753 break;
754 case P_A64:
755 case P_O64:
756 case P_none:
757 break;
758 default:
759 isize++;
760 break;
761 }
762 }
763 return isize * instruction->times;
764 } else {
765 return -1; /* didn't match any instruction */
766 }
767 }
768
769 static void bad_hle_warn(const insn * ins, uint8_t hleok)
770 {
771 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
772 enum whatwarn { w_none, w_lock, w_inval } ww;
773 static const enum whatwarn warn[2][4] =
774 {
775 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
776 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
777 };
778 unsigned int n;
779
780 n = (unsigned int)rep_pfx - P_XACQUIRE;
781 if (n > 1)
782 return; /* Not XACQUIRE/XRELEASE */
783
784 ww = warn[n][hleok];
785 if (!is_class(MEMORY, ins->oprs[0].type))
786 ww = w_inval; /* HLE requires operand 0 to be memory */
787
788 switch (ww) {
789 case w_none:
790 break;
791
792 case w_lock:
793 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
794 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
795 "%s with this instruction requires lock",
796 prefix_name(rep_pfx));
797 }
798 break;
799
800 case w_inval:
801 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
802 "%s invalid with this instruction",
803 prefix_name(rep_pfx));
804 break;
805 }
806 }
807
808 /* Common construct */
809 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
810
811 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
812 insn * ins, const struct itemplate *temp)
813 {
814 const uint8_t *codes = temp->code;
815 int64_t length = 0;
816 uint8_t c;
817 int rex_mask = ~0;
818 int op1, op2;
819 struct operand *opx;
820 uint8_t opex = 0;
821 enum ea_type eat;
822 uint8_t hleok = 0;
823 bool lockcheck = true;
824
825 ins->rex = 0; /* Ensure REX is reset */
826 eat = EA_SCALAR; /* Expect a scalar EA */
827
828 if (ins->prefixes[PPS_OSIZE] == P_O64)
829 ins->rex |= REX_W;
830
831 (void)segment; /* Don't warn that this parameter is unused */
832 (void)offset; /* Don't warn that this parameter is unused */
833
834 while (*codes) {
835 c = *codes++;
836 op1 = (c & 3) + ((opex & 1) << 2);
837 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
838 opx = &ins->oprs[op1];
839 opex = 0; /* For the next iteration */
840
841 switch (c) {
842 case 01:
843 case 02:
844 case 03:
845 case 04:
846 codes += c, length += c;
847 break;
848
849 case 05:
850 case 06:
851 case 07:
852 opex = c;
853 break;
854
855 case4(010):
856 ins->rex |=
857 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
858 codes++, length++;
859 break;
860
861 case4(020):
862 case4(024):
863 length++;
864 break;
865
866 case4(030):
867 length += 2;
868 break;
869
870 case4(034):
871 if (opx->type & (BITS16 | BITS32 | BITS64))
872 length += (opx->type & BITS16) ? 2 : 4;
873 else
874 length += (bits == 16) ? 2 : 4;
875 break;
876
877 case4(040):
878 length += 4;
879 break;
880
881 case4(044):
882 length += ins->addr_size >> 3;
883 break;
884
885 case4(050):
886 length++;
887 break;
888
889 case4(054):
890 length += 8; /* MOV reg64/imm */
891 break;
892
893 case4(060):
894 length += 2;
895 break;
896
897 case4(064):
898 if (opx->type & (BITS16 | BITS32 | BITS64))
899 length += (opx->type & BITS16) ? 2 : 4;
900 else
901 length += (bits == 16) ? 2 : 4;
902 break;
903
904 case4(070):
905 length += 4;
906 break;
907
908 case4(074):
909 length += 2;
910 break;
911
912 case 0172:
913 case 0173:
914 codes++;
915 length++;
916 break;
917
918 case4(0174):
919 length++;
920 break;
921
922 case4(0254):
923 length += 4;
924 break;
925
926 case4(0260):
927 ins->rex |= REX_V;
928 ins->vexreg = regval(opx);
929 ins->vex_cm = *codes++;
930 ins->vex_wlp = *codes++;
931 break;
932
933 case 0270:
934 ins->rex |= REX_V;
935 ins->vexreg = 0;
936 ins->vex_cm = *codes++;
937 ins->vex_wlp = *codes++;
938 break;
939
940 case 0271:
941 case 0272:
942 case 0273:
943 hleok = c & 3;
944 break;
945
946 case4(0274):
947 length++;
948 break;
949
950 case4(0300):
951 break;
952
953 case 0310:
954 if (bits == 64)
955 return -1;
956 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
957 break;
958
959 case 0311:
960 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
961 break;
962
963 case 0312:
964 break;
965
966 case 0313:
967 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
968 has_prefix(ins, PPS_ASIZE, P_A32))
969 return -1;
970 break;
971
972 case4(0314):
973 break;
974
975 case 0320:
976 {
977 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
978 if (pfx == P_O16)
979 break;
980 if (pfx != P_none)
981 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
982 else
983 ins->prefixes[PPS_OSIZE] = P_O16;
984 break;
985 }
986
987 case 0321:
988 {
989 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
990 if (pfx == P_O32)
991 break;
992 if (pfx != P_none)
993 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
994 else
995 ins->prefixes[PPS_OSIZE] = P_O32;
996 break;
997 }
998
999 case 0322:
1000 break;
1001
1002 case 0323:
1003 rex_mask &= ~REX_W;
1004 break;
1005
1006 case 0324:
1007 ins->rex |= REX_W;
1008 break;
1009
1010 case 0325:
1011 ins->rex |= REX_NH;
1012 break;
1013
1014 case 0326:
1015 break;
1016
1017 case 0330:
1018 codes++, length++;
1019 break;
1020
1021 case 0331:
1022 break;
1023
1024 case 0332:
1025 case 0333:
1026 length++;
1027 break;
1028
1029 case 0334:
1030 ins->rex |= REX_L;
1031 break;
1032
1033 case 0335:
1034 break;
1035
1036 case 0336:
1037 if (!ins->prefixes[PPS_REP])
1038 ins->prefixes[PPS_REP] = P_REP;
1039 break;
1040
1041 case 0337:
1042 if (!ins->prefixes[PPS_REP])
1043 ins->prefixes[PPS_REP] = P_REPNE;
1044 break;
1045
1046 case 0340:
1047 if (ins->oprs[0].segment != NO_SEG)
1048 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1049 " quantity of BSS space");
1050 else
1051 length += ins->oprs[0].offset;
1052 break;
1053
1054 case 0341:
1055 if (!ins->prefixes[PPS_WAIT])
1056 ins->prefixes[PPS_WAIT] = P_WAIT;
1057 break;
1058
1059 case4(0344):
1060 length++;
1061 break;
1062
1063 case 0360:
1064 break;
1065
1066 case 0361:
1067 case 0362:
1068 case 0363:
1069 length++;
1070 break;
1071
1072 case 0364:
1073 case 0365:
1074 break;
1075
1076 case 0366:
1077 case 0367:
1078 length++;
1079 break;
1080
1081 case 0370:
1082 case 0371:
1083 case 0372:
1084 break;
1085
1086 case 0373:
1087 length++;
1088 break;
1089
1090 case 0374:
1091 eat = EA_XMMVSIB;
1092 break;
1093
1094 case 0375:
1095 eat = EA_YMMVSIB;
1096 break;
1097
1098 case4(0100):
1099 case4(0110):
1100 case4(0120):
1101 case4(0130):
1102 case4(0200):
1103 case4(0204):
1104 case4(0210):
1105 case4(0214):
1106 case4(0220):
1107 case4(0224):
1108 case4(0230):
1109 case4(0234):
1110 {
1111 ea ea_data;
1112 int rfield;
1113 opflags_t rflags;
1114 struct operand *opy = &ins->oprs[op2];
1115
1116 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1117
1118 if (c <= 0177) {
1119 /* pick rfield from operand b (opx) */
1120 rflags = regflag(opx);
1121 rfield = nasm_regvals[opx->basereg];
1122 } else {
1123 rflags = 0;
1124 rfield = c & 7;
1125 }
1126 if (process_ea(opy, &ea_data, bits,ins->addr_size,
1127 rfield, rflags) != eat) {
1128 errfunc(ERR_NONFATAL, "invalid effective address");
1129 return -1;
1130 } else {
1131 ins->rex |= ea_data.rex;
1132 length += ea_data.size;
1133 }
1134 }
1135 break;
1136
1137 default:
1138 errfunc(ERR_PANIC, "internal instruction table corrupt"
1139 ": instruction code \\%o (0x%02X) given", c, c);
1140 break;
1141 }
1142 }
1143
1144 ins->rex &= rex_mask;
1145
1146 if (ins->rex & REX_NH) {
1147 if (ins->rex & REX_H) {
1148 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1149 return -1;
1150 }
1151 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1152 }
1153
1154 if (ins->rex & REX_V) {
1155 int bad32 = REX_R|REX_W|REX_X|REX_B;
1156
1157 if (ins->rex & REX_H) {
1158 errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
1159 return -1;
1160 }
1161 switch (ins->vex_wlp & 060) {
1162 case 000:
1163 case 040:
1164 ins->rex &= ~REX_W;
1165 break;
1166 case 020:
1167 ins->rex |= REX_W;
1168 bad32 &= ~REX_W;
1169 break;
1170 case 060:
1171 /* Follow REX_W */
1172 break;
1173 }
1174
1175 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1176 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1177 return -1;
1178 }
1179 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1180 length += 3;
1181 else
1182 length += 2;
1183 } else if (ins->rex & REX_REAL) {
1184 if (ins->rex & REX_H) {
1185 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1186 return -1;
1187 } else if (bits == 64) {
1188 length++;
1189 } else if ((ins->rex & REX_L) &&
1190 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1191 cpu >= IF_X86_64) {
1192 /* LOCK-as-REX.R */
1193 assert_no_prefix(ins, PPS_LOCK);
1194 lockcheck = false; /* Already errored, no need for warning */
1195 length++;
1196 } else {
1197 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1198 return -1;
1199 }
1200 }
1201
1202 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1203 (!(temp->flags & IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1204 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1205 "instruction is not lockable");
1206 }
1207
1208 bad_hle_warn(ins, hleok);
1209
1210 return length;
1211 }
1212
1213 #define EMIT_REX() \
1214 if (!(ins->rex & REX_V) && (ins->rex & REX_REAL) && (bits == 64)) { \
1215 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1216 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1217 ins->rex = 0; \
1218 offset += 1; \
1219 }
1220
1221 static void gencode(int32_t segment, int64_t offset, int bits,
1222 insn * ins, const struct itemplate *temp,
1223 int64_t insn_end)
1224 {
1225 static const char condval[] = { /* conditional opcodes */
1226 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1227 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1228 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1229 };
1230 uint8_t c;
1231 uint8_t bytes[4];
1232 int64_t size;
1233 int64_t data;
1234 int op1, op2;
1235 struct operand *opx;
1236 const uint8_t *codes = temp->code;
1237 uint8_t opex = 0;
1238 enum ea_type eat = EA_SCALAR;
1239
1240 while (*codes) {
1241 c = *codes++;
1242 op1 = (c & 3) + ((opex & 1) << 2);
1243 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1244 opx = &ins->oprs[op1];
1245 opex = 0; /* For the next iteration */
1246
1247 switch (c) {
1248 case 01:
1249 case 02:
1250 case 03:
1251 case 04:
1252 EMIT_REX();
1253 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1254 codes += c;
1255 offset += c;
1256 break;
1257
1258 case 05:
1259 case 06:
1260 case 07:
1261 opex = c;
1262 break;
1263
1264 case4(010):
1265 EMIT_REX();
1266 bytes[0] = *codes++ + (regval(opx) & 7);
1267 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1268 offset += 1;
1269 break;
1270
1271 case4(020):
1272 if (opx->offset < -256 || opx->offset > 255) {
1273 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1274 "byte value exceeds bounds");
1275 }
1276 out_imm8(offset, segment, opx);
1277 offset += 1;
1278 break;
1279
1280 case4(024):
1281 if (opx->offset < 0 || opx->offset > 255)
1282 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1283 "unsigned byte value exceeds bounds");
1284 out_imm8(offset, segment, opx);
1285 offset += 1;
1286 break;
1287
1288 case4(030):
1289 warn_overflow_opd(opx, 2);
1290 data = opx->offset;
1291 out(offset, segment, &data, OUT_ADDRESS, 2,
1292 opx->segment, opx->wrt);
1293 offset += 2;
1294 break;
1295
1296 case4(034):
1297 if (opx->type & (BITS16 | BITS32))
1298 size = (opx->type & BITS16) ? 2 : 4;
1299 else
1300 size = (bits == 16) ? 2 : 4;
1301 warn_overflow_opd(opx, size);
1302 data = opx->offset;
1303 out(offset, segment, &data, OUT_ADDRESS, size,
1304 opx->segment, opx->wrt);
1305 offset += size;
1306 break;
1307
1308 case4(040):
1309 warn_overflow_opd(opx, 4);
1310 data = opx->offset;
1311 out(offset, segment, &data, OUT_ADDRESS, 4,
1312 opx->segment, opx->wrt);
1313 offset += 4;
1314 break;
1315
1316 case4(044):
1317 data = opx->offset;
1318 size = ins->addr_size >> 3;
1319 warn_overflow_opd(opx, size);
1320 out(offset, segment, &data, OUT_ADDRESS, size,
1321 opx->segment, opx->wrt);
1322 offset += size;
1323 break;
1324
1325 case4(050):
1326 if (opx->segment != segment) {
1327 data = opx->offset;
1328 out(offset, segment, &data,
1329 OUT_REL1ADR, insn_end - offset,
1330 opx->segment, opx->wrt);
1331 } else {
1332 data = opx->offset - insn_end;
1333 if (data > 127 || data < -128)
1334 errfunc(ERR_NONFATAL, "short jump is out of range");
1335 out(offset, segment, &data,
1336 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1337 }
1338 offset += 1;
1339 break;
1340
1341 case4(054):
1342 data = (int64_t)opx->offset;
1343 out(offset, segment, &data, OUT_ADDRESS, 8,
1344 opx->segment, opx->wrt);
1345 offset += 8;
1346 break;
1347
1348 case4(060):
1349 if (opx->segment != segment) {
1350 data = opx->offset;
1351 out(offset, segment, &data,
1352 OUT_REL2ADR, insn_end - offset,
1353 opx->segment, opx->wrt);
1354 } else {
1355 data = opx->offset - insn_end;
1356 out(offset, segment, &data,
1357 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1358 }
1359 offset += 2;
1360 break;
1361
1362 case4(064):
1363 if (opx->type & (BITS16 | BITS32 | BITS64))
1364 size = (opx->type & BITS16) ? 2 : 4;
1365 else
1366 size = (bits == 16) ? 2 : 4;
1367 if (opx->segment != segment) {
1368 data = opx->offset;
1369 out(offset, segment, &data,
1370 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1371 insn_end - offset, opx->segment, opx->wrt);
1372 } else {
1373 data = opx->offset - insn_end;
1374 out(offset, segment, &data,
1375 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1376 }
1377 offset += size;
1378 break;
1379
1380 case4(070):
1381 if (opx->segment != segment) {
1382 data = opx->offset;
1383 out(offset, segment, &data,
1384 OUT_REL4ADR, insn_end - offset,
1385 opx->segment, opx->wrt);
1386 } else {
1387 data = opx->offset - insn_end;
1388 out(offset, segment, &data,
1389 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1390 }
1391 offset += 4;
1392 break;
1393
1394 case4(074):
1395 if (opx->segment == NO_SEG)
1396 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1397 " relocatable");
1398 data = 0;
1399 out(offset, segment, &data, OUT_ADDRESS, 2,
1400 outfmt->segbase(1 + opx->segment),
1401 opx->wrt);
1402 offset += 2;
1403 break;
1404
1405 case 0172:
1406 c = *codes++;
1407 opx = &ins->oprs[c >> 3];
1408 bytes[0] = nasm_regvals[opx->basereg] << 4;
1409 opx = &ins->oprs[c & 7];
1410 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1411 errfunc(ERR_NONFATAL,
1412 "non-absolute expression not permitted as argument %d",
1413 c & 7);
1414 } else {
1415 if (opx->offset & ~15) {
1416 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1417 "four-bit argument exceeds bounds");
1418 }
1419 bytes[0] |= opx->offset & 15;
1420 }
1421 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1422 offset++;
1423 break;
1424
1425 case 0173:
1426 c = *codes++;
1427 opx = &ins->oprs[c >> 4];
1428 bytes[0] = nasm_regvals[opx->basereg] << 4;
1429 bytes[0] |= c & 15;
1430 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1431 offset++;
1432 break;
1433
1434 case4(0174):
1435 bytes[0] = nasm_regvals[opx->basereg] << 4;
1436 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1437 offset++;
1438 break;
1439
1440 case4(0254):
1441 data = opx->offset;
1442 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1443 (int32_t)data != (int64_t)data) {
1444 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1445 "signed dword immediate exceeds bounds");
1446 }
1447 out(offset, segment, &data, OUT_ADDRESS, 4,
1448 opx->segment, opx->wrt);
1449 offset += 4;
1450 break;
1451
1452 case4(0260):
1453 case 0270:
1454 codes += 2;
1455 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1456 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1457 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1458 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1459 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1460 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1461 offset += 3;
1462 } else {
1463 bytes[0] = 0xc5;
1464 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1465 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1466 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1467 offset += 2;
1468 }
1469 break;
1470
1471 case 0271:
1472 case 0272:
1473 case 0273:
1474 break;
1475
1476 case4(0274):
1477 {
1478 uint64_t uv, um;
1479 int s;
1480
1481 if (ins->rex & REX_W)
1482 s = 64;
1483 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1484 s = 16;
1485 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1486 s = 32;
1487 else
1488 s = bits;
1489
1490 um = (uint64_t)2 << (s-1);
1491 uv = opx->offset;
1492
1493 if (uv > 127 && uv < (uint64_t)-128 &&
1494 (uv < um-128 || uv > um-1)) {
1495 /* If this wasn't explicitly byte-sized, warn as though we
1496 * had fallen through to the imm16/32/64 case.
1497 */
1498 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1499 "%s value exceeds bounds",
1500 (opx->type & BITS8) ? "signed byte" :
1501 s == 16 ? "word" :
1502 s == 32 ? "dword" :
1503 "signed dword");
1504 }
1505 if (opx->segment != NO_SEG) {
1506 data = uv;
1507 out(offset, segment, &data, OUT_ADDRESS, 1,
1508 opx->segment, opx->wrt);
1509 } else {
1510 bytes[0] = uv;
1511 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1512 NO_SEG);
1513 }
1514 offset += 1;
1515 break;
1516 }
1517
1518 case4(0300):
1519 break;
1520
1521 case 0310:
1522 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1523 *bytes = 0x67;
1524 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1525 offset += 1;
1526 } else
1527 offset += 0;
1528 break;
1529
1530 case 0311:
1531 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1532 *bytes = 0x67;
1533 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1534 offset += 1;
1535 } else
1536 offset += 0;
1537 break;
1538
1539 case 0312:
1540 break;
1541
1542 case 0313:
1543 ins->rex = 0;
1544 break;
1545
1546 case4(0314):
1547 break;
1548
1549 case 0320:
1550 case 0321:
1551 break;
1552
1553 case 0322:
1554 case 0323:
1555 break;
1556
1557 case 0324:
1558 ins->rex |= REX_W;
1559 break;
1560
1561 case 0325:
1562 break;
1563
1564 case 0326:
1565 break;
1566
1567 case 0330:
1568 *bytes = *codes++ ^ condval[ins->condition];
1569 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1570 offset += 1;
1571 break;
1572
1573 case 0331:
1574 break;
1575
1576 case 0332:
1577 case 0333:
1578 *bytes = c - 0332 + 0xF2;
1579 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1580 offset += 1;
1581 break;
1582
1583 case 0334:
1584 if (ins->rex & REX_R) {
1585 *bytes = 0xF0;
1586 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1587 offset += 1;
1588 }
1589 ins->rex &= ~(REX_L|REX_R);
1590 break;
1591
1592 case 0335:
1593 break;
1594
1595 case 0336:
1596 case 0337:
1597 break;
1598
1599 case 0340:
1600 if (ins->oprs[0].segment != NO_SEG)
1601 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1602 else {
1603 int64_t size = ins->oprs[0].offset;
1604 if (size > 0)
1605 out(offset, segment, NULL,
1606 OUT_RESERVE, size, NO_SEG, NO_SEG);
1607 offset += size;
1608 }
1609 break;
1610
1611 case 0341:
1612 break;
1613
1614 case 0344:
1615 case 0345:
1616 bytes[0] = c & 1;
1617 switch (ins->oprs[0].basereg) {
1618 case R_CS:
1619 bytes[0] += 0x0E;
1620 break;
1621 case R_DS:
1622 bytes[0] += 0x1E;
1623 break;
1624 case R_ES:
1625 bytes[0] += 0x06;
1626 break;
1627 case R_SS:
1628 bytes[0] += 0x16;
1629 break;
1630 default:
1631 errfunc(ERR_PANIC,
1632 "bizarre 8086 segment register received");
1633 }
1634 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1635 offset++;
1636 break;
1637
1638 case 0346:
1639 case 0347:
1640 bytes[0] = c & 1;
1641 switch (ins->oprs[0].basereg) {
1642 case R_FS:
1643 bytes[0] += 0xA0;
1644 break;
1645 case R_GS:
1646 bytes[0] += 0xA8;
1647 break;
1648 default:
1649 errfunc(ERR_PANIC,
1650 "bizarre 386 segment register received");
1651 }
1652 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1653 offset++;
1654 break;
1655
1656 case 0360:
1657 break;
1658
1659 case 0361:
1660 bytes[0] = 0x66;
1661 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1662 offset += 1;
1663 break;
1664
1665 case 0362:
1666 case 0363:
1667 bytes[0] = c - 0362 + 0xf2;
1668 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1669 offset += 1;
1670 break;
1671
1672 case 0364:
1673 case 0365:
1674 break;
1675
1676 case 0366:
1677 case 0367:
1678 *bytes = c - 0366 + 0x66;
1679 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1680 offset += 1;
1681 break;
1682
1683 case 0370:
1684 case 0371:
1685 break;
1686
1687 case 0373:
1688 *bytes = bits == 16 ? 3 : 5;
1689 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1690 offset += 1;
1691 break;
1692
1693 case 0374:
1694 eat = EA_XMMVSIB;
1695 break;
1696
1697 case 0375:
1698 eat = EA_YMMVSIB;
1699 break;
1700
1701 case4(0100):
1702 case4(0110):
1703 case4(0120):
1704 case4(0130):
1705 case4(0200):
1706 case4(0204):
1707 case4(0210):
1708 case4(0214):
1709 case4(0220):
1710 case4(0224):
1711 case4(0230):
1712 case4(0234):
1713 {
1714 ea ea_data;
1715 int rfield;
1716 opflags_t rflags;
1717 uint8_t *p;
1718 int32_t s;
1719 struct operand *opy = &ins->oprs[op2];
1720
1721 if (c <= 0177) {
1722 /* pick rfield from operand b (opx) */
1723 rflags = regflag(opx);
1724 rfield = nasm_regvals[opx->basereg];
1725 } else {
1726 /* rfield is constant */
1727 rflags = 0;
1728 rfield = c & 7;
1729 }
1730
1731 if (process_ea(opy, &ea_data, bits, ins->addr_size,
1732 rfield, rflags) != eat)
1733 errfunc(ERR_NONFATAL, "invalid effective address");
1734
1735 p = bytes;
1736 *p++ = ea_data.modrm;
1737 if (ea_data.sib_present)
1738 *p++ = ea_data.sib;
1739
1740 s = p - bytes;
1741 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1742
1743 /*
1744 * Make sure the address gets the right offset in case
1745 * the line breaks in the .lst file (BR 1197827)
1746 */
1747 offset += s;
1748 s = 0;
1749
1750 switch (ea_data.bytes) {
1751 case 0:
1752 break;
1753 case 1:
1754 case 2:
1755 case 4:
1756 case 8:
1757 data = opy->offset;
1758 s += ea_data.bytes;
1759 if (ea_data.rip) {
1760 if (opy->segment == segment) {
1761 data -= insn_end;
1762 if (overflow_signed(data, ea_data.bytes))
1763 warn_overflow(ERR_PASS2, ea_data.bytes);
1764 out(offset, segment, &data, OUT_ADDRESS,
1765 ea_data.bytes, NO_SEG, NO_SEG);
1766 } else {
1767 /* overflow check in output/linker? */
1768 out(offset, segment, &data, OUT_REL4ADR,
1769 insn_end - offset, opy->segment, opy->wrt);
1770 }
1771 } else {
1772 if (overflow_general(opy->offset, ins->addr_size >> 3) ||
1773 signed_bits(opy->offset, ins->addr_size) !=
1774 signed_bits(opy->offset, ea_data.bytes * 8))
1775 warn_overflow(ERR_PASS2, ea_data.bytes);
1776
1777 out(offset, segment, &data, OUT_ADDRESS,
1778 ea_data.bytes, opy->segment, opy->wrt);
1779 }
1780 break;
1781 default:
1782 /* Impossible! */
1783 errfunc(ERR_PANIC,
1784 "Invalid amount of bytes (%d) for offset?!",
1785 ea_data.bytes);
1786 break;
1787 }
1788 offset += s;
1789 }
1790 break;
1791
1792 default:
1793 errfunc(ERR_PANIC, "internal instruction table corrupt"
1794 ": instruction code \\%o (0x%02X) given", c, c);
1795 break;
1796 }
1797 }
1798 }
1799
1800 static opflags_t regflag(const operand * o)
1801 {
1802 if (!is_register(o->basereg))
1803 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1804 return nasm_reg_flags[o->basereg];
1805 }
1806
1807 static int32_t regval(const operand * o)
1808 {
1809 if (!is_register(o->basereg))
1810 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1811 return nasm_regvals[o->basereg];
1812 }
1813
1814 static int op_rexflags(const operand * o, int mask)
1815 {
1816 opflags_t flags;
1817 int val;
1818
1819 if (!is_register(o->basereg))
1820 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1821
1822 flags = nasm_reg_flags[o->basereg];
1823 val = nasm_regvals[o->basereg];
1824
1825 return rexflags(val, flags, mask);
1826 }
1827
1828 static int rexflags(int val, opflags_t flags, int mask)
1829 {
1830 int rex = 0;
1831
1832 if (val >= 8)
1833 rex |= REX_B|REX_X|REX_R;
1834 if (flags & BITS64)
1835 rex |= REX_W;
1836 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1837 rex |= REX_H;
1838 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1839 rex |= REX_P;
1840
1841 return rex & mask;
1842 }
1843
1844 static enum match_result find_match(const struct itemplate **tempp,
1845 insn *instruction,
1846 int32_t segment, int64_t offset, int bits)
1847 {
1848 const struct itemplate *temp;
1849 enum match_result m, merr;
1850 opflags_t xsizeflags[MAX_OPERANDS];
1851 bool opsizemissing = false;
1852 int i;
1853
1854 for (i = 0; i < instruction->operands; i++)
1855 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1856
1857 merr = MERR_INVALOP;
1858
1859 for (temp = nasm_instructions[instruction->opcode];
1860 temp->opcode != I_none; temp++) {
1861 m = matches(temp, instruction, bits);
1862 if (m == MOK_JUMP) {
1863 if (jmp_match(segment, offset, bits, instruction, temp))
1864 m = MOK_GOOD;
1865 else
1866 m = MERR_INVALOP;
1867 } else if (m == MERR_OPSIZEMISSING &&
1868 (temp->flags & IF_SMASK) != IF_SX) {
1869 /*
1870 * Missing operand size and a candidate for fuzzy matching...
1871 */
1872 for (i = 0; i < temp->operands; i++) {
1873 if ((temp->opd[i] & SAME_AS) == 0)
1874 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
1875 }
1876 opsizemissing = true;
1877 }
1878 if (m > merr)
1879 merr = m;
1880 if (merr == MOK_GOOD)
1881 goto done;
1882 }
1883
1884 /* No match, but see if we can get a fuzzy operand size match... */
1885 if (!opsizemissing)
1886 goto done;
1887
1888 for (i = 0; i < instruction->operands; i++) {
1889 /*
1890 * We ignore extrinsic operand sizes on registers, so we should
1891 * never try to fuzzy-match on them. This also resolves the case
1892 * when we have e.g. "xmmrm128" in two different positions.
1893 */
1894 if (is_class(REGISTER, instruction->oprs[i].type))
1895 continue;
1896
1897 /* This tests if xsizeflags[i] has more than one bit set */
1898 if ((xsizeflags[i] & (xsizeflags[i]-1)))
1899 goto done; /* No luck */
1900
1901 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
1902 }
1903
1904 /* Try matching again... */
1905 for (temp = nasm_instructions[instruction->opcode];
1906 temp->opcode != I_none; temp++) {
1907 m = matches(temp, instruction, bits);
1908 if (m == MOK_JUMP) {
1909 if (jmp_match(segment, offset, bits, instruction, temp))
1910 m = MOK_GOOD;
1911 else
1912 m = MERR_INVALOP;
1913 }
1914 if (m > merr)
1915 merr = m;
1916 if (merr == MOK_GOOD)
1917 goto done;
1918 }
1919
1920 done:
1921 *tempp = temp;
1922 return merr;
1923 }
1924
1925 static enum match_result matches(const struct itemplate *itemp,
1926 insn *instruction, int bits)
1927 {
1928 opflags_t size[MAX_OPERANDS], asize;
1929 bool opsizemissing = false;
1930 int i, oprs;
1931
1932 /*
1933 * Check the opcode
1934 */
1935 if (itemp->opcode != instruction->opcode)
1936 return MERR_INVALOP;
1937
1938 /*
1939 * Count the operands
1940 */
1941 if (itemp->operands != instruction->operands)
1942 return MERR_INVALOP;
1943
1944 /*
1945 * Is it legal?
1946 */
1947 if (!(optimizing > 0) && (itemp->flags & IF_OPT))
1948 return MERR_INVALOP;
1949
1950 /*
1951 * Check that no spurious colons or TOs are present
1952 */
1953 for (i = 0; i < itemp->operands; i++)
1954 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1955 return MERR_INVALOP;
1956
1957 /*
1958 * Process size flags
1959 */
1960 switch (itemp->flags & IF_SMASK) {
1961 case IF_SB:
1962 asize = BITS8;
1963 break;
1964 case IF_SW:
1965 asize = BITS16;
1966 break;
1967 case IF_SD:
1968 asize = BITS32;
1969 break;
1970 case IF_SQ:
1971 asize = BITS64;
1972 break;
1973 case IF_SO:
1974 asize = BITS128;
1975 break;
1976 case IF_SY:
1977 asize = BITS256;
1978 break;
1979 case IF_SZ:
1980 switch (bits) {
1981 case 16:
1982 asize = BITS16;
1983 break;
1984 case 32:
1985 asize = BITS32;
1986 break;
1987 case 64:
1988 asize = BITS64;
1989 break;
1990 default:
1991 asize = 0;
1992 break;
1993 }
1994 break;
1995 default:
1996 asize = 0;
1997 break;
1998 }
1999
2000 if (itemp->flags & IF_ARMASK) {
2001 /* S- flags only apply to a specific operand */
2002 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
2003 memset(size, 0, sizeof size);
2004 size[i] = asize;
2005 } else {
2006 /* S- flags apply to all operands */
2007 for (i = 0; i < MAX_OPERANDS; i++)
2008 size[i] = asize;
2009 }
2010
2011 /*
2012 * Check that the operand flags all match up,
2013 * it's a bit tricky so lets be verbose:
2014 *
2015 * 1) Find out the size of operand. If instruction
2016 * doesn't have one specified -- we're trying to
2017 * guess it either from template (IF_S* flag) or
2018 * from code bits.
2019 *
2020 * 2) If template operand (i) has SAME_AS flag [used for registers only]
2021 * (ie the same operand as was specified somewhere in template, and
2022 * this referred operand index is being achieved via ~SAME_AS)
2023 * we are to be sure that both registers (in template and instruction)
2024 * do exactly match.
2025 *
2026 * 3) If template operand do not match the instruction OR
2027 * template has an operand size specified AND this size differ
2028 * from which instruction has (perhaps we got it from code bits)
2029 * we are:
2030 * a) Check that only size of instruction and operand is differ
2031 * other characteristics do match
2032 * b) Perhaps it's a register specified in instruction so
2033 * for such a case we just mark that operand as "size
2034 * missing" and this will turn on fuzzy operand size
2035 * logic facility (handled by a caller)
2036 */
2037 for (i = 0; i < itemp->operands; i++) {
2038 opflags_t type = instruction->oprs[i].type;
2039 if (!(type & SIZE_MASK))
2040 type |= size[i];
2041
2042 if (itemp->opd[i] & SAME_AS) {
2043 int j = itemp->opd[i] & ~SAME_AS;
2044 if (type != instruction->oprs[j].type ||
2045 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
2046 return MERR_INVALOP;
2047 } else if (itemp->opd[i] & ~type & ~SIZE_MASK) {
2048 return MERR_INVALOP;
2049 } else if ((itemp->opd[i] & SIZE_MASK) &&
2050 (itemp->opd[i] & SIZE_MASK) != (type & SIZE_MASK)) {
2051 if (type & SIZE_MASK) {
2052 return MERR_INVALOP;
2053 } else if (!is_class(REGISTER, type)) {
2054 /*
2055 * Note: we don't honor extrinsic operand sizes for registers,
2056 * so "missing operand size" for a register should be
2057 * considered a wildcard match rather than an error.
2058 */
2059 opsizemissing = true;
2060 }
2061 }
2062 }
2063
2064 if (opsizemissing)
2065 return MERR_OPSIZEMISSING;
2066
2067 /*
2068 * Check operand sizes
2069 */
2070 if (itemp->flags & (IF_SM | IF_SM2)) {
2071 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2072 for (i = 0; i < oprs; i++) {
2073 asize = itemp->opd[i] & SIZE_MASK;
2074 if (asize) {
2075 for (i = 0; i < oprs; i++)
2076 size[i] = asize;
2077 break;
2078 }
2079 }
2080 } else {
2081 oprs = itemp->operands;
2082 }
2083
2084 for (i = 0; i < itemp->operands; i++) {
2085 if (!(itemp->opd[i] & SIZE_MASK) &&
2086 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2087 return MERR_OPSIZEMISMATCH;
2088 }
2089
2090 /*
2091 * Check template is okay at the set cpu level
2092 */
2093 if (((itemp->flags & IF_PLEVEL) > cpu))
2094 return MERR_BADCPU;
2095
2096 /*
2097 * Verify the appropriate long mode flag.
2098 */
2099 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2100 return MERR_BADMODE;
2101
2102 /*
2103 * If we have a HLE prefix, look for the NOHLE flag
2104 */
2105 if ((itemp->flags & IF_NOHLE) &&
2106 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2107 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2108 return MERR_BADHLE;
2109
2110 /*
2111 * Check if special handling needed for Jumps
2112 */
2113 if ((itemp->code[0] & ~1) == 0370)
2114 return MOK_JUMP;
2115
2116 return MOK_GOOD;
2117 }
2118
2119 static enum ea_type process_ea(operand *input, ea *output, int bits,
2120 int addrbits, int rfield, opflags_t rflags)
2121 {
2122 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2123
2124 output->type = EA_SCALAR;
2125 output->rip = false;
2126
2127 /* REX flags for the rfield operand */
2128 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2129
2130 if (is_class(REGISTER, input->type)) {
2131 /*
2132 * It's a direct register.
2133 */
2134 if (!is_register(input->basereg))
2135 goto err;
2136
2137 if (!is_class(REG_EA, regflag(input)))
2138 goto err;
2139
2140 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2141 output->sib_present = false; /* no SIB necessary */
2142 output->bytes = 0; /* no offset necessary either */
2143 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2144 } else {
2145 /*
2146 * It's a memory reference.
2147 */
2148 if (input->basereg == -1 &&
2149 (input->indexreg == -1 || input->scale == 0)) {
2150 /*
2151 * It's a pure offset.
2152 */
2153 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2154 input->segment == NO_SEG) {
2155 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2156 input->type &= ~IP_REL;
2157 input->type |= MEMORY;
2158 }
2159
2160 if (input->eaflags & EAF_BYTEOFFS ||
2161 (input->eaflags & EAF_WORDOFFS &&
2162 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2163 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2164 }
2165
2166 if (bits == 64 && (~input->type & IP_REL)) {
2167 output->sib_present = true;
2168 output->sib = GEN_SIB(0, 4, 5);
2169 output->bytes = 4;
2170 output->modrm = GEN_MODRM(0, rfield, 4);
2171 output->rip = false;
2172 } else {
2173 output->sib_present = false;
2174 output->bytes = (addrbits != 16 ? 4 : 2);
2175 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2176 output->rip = bits == 64;
2177 }
2178 } else {
2179 /*
2180 * It's an indirection.
2181 */
2182 int i = input->indexreg, b = input->basereg, s = input->scale;
2183 int32_t seg = input->segment;
2184 int hb = input->hintbase, ht = input->hinttype;
2185 int t, it, bt; /* register numbers */
2186 opflags_t x, ix, bx; /* register flags */
2187
2188 if (s == 0)
2189 i = -1; /* make this easy, at least */
2190
2191 if (is_register(i)) {
2192 it = nasm_regvals[i];
2193 ix = nasm_reg_flags[i];
2194 } else {
2195 it = -1;
2196 ix = 0;
2197 }
2198
2199 if (is_register(b)) {
2200 bt = nasm_regvals[b];
2201 bx = nasm_reg_flags[b];
2202 } else {
2203 bt = -1;
2204 bx = 0;
2205 }
2206
2207 /* if either one are a vector register... */
2208 if ((ix|bx) & (XMMREG|YMMREG) & ~REG_EA) {
2209 opflags_t sok = BITS32 | BITS64;
2210 int32_t o = input->offset;
2211 int mod, scale, index, base;
2212
2213 /*
2214 * For a vector SIB, one has to be a vector and the other,
2215 * if present, a GPR. The vector must be the index operand.
2216 */
2217 if (it == -1 || (bx & (XMMREG|YMMREG) & ~REG_EA)) {
2218 if (s == 0)
2219 s = 1;
2220 else if (s != 1)
2221 goto err;
2222
2223 t = bt, bt = it, it = t;
2224 x = bx, bx = ix, ix = x;
2225 }
2226
2227 if (bt != -1) {
2228 if (REG_GPR & ~bx)
2229 goto err;
2230 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2231 sok &= bx;
2232 else
2233 goto err;
2234 }
2235
2236 /*
2237 * While we're here, ensure the user didn't specify
2238 * WORD or QWORD
2239 */
2240 if (input->disp_size == 16 || input->disp_size == 64)
2241 goto err;
2242
2243 if (addrbits == 16 ||
2244 (addrbits == 32 && !(sok & BITS32)) ||
2245 (addrbits == 64 && !(sok & BITS64)))
2246 goto err;
2247
2248 output->type = (ix & YMMREG & ~REG_EA)
2249 ? EA_YMMVSIB : EA_XMMVSIB;
2250
2251 output->rex |= rexflags(it, ix, REX_X);
2252 output->rex |= rexflags(bt, bx, REX_B);
2253
2254 index = it & 7; /* it is known to be != -1 */
2255
2256 switch (s) {
2257 case 1:
2258 scale = 0;
2259 break;
2260 case 2:
2261 scale = 1;
2262 break;
2263 case 4:
2264 scale = 2;
2265 break;
2266 case 8:
2267 scale = 3;
2268 break;
2269 default: /* then what the smeg is it? */
2270 goto err; /* panic */
2271 }
2272
2273 if (bt == -1) {
2274 base = 5;
2275 mod = 0;
2276 } else {
2277 base = (bt & 7);
2278 if (base != REG_NUM_EBP && o == 0 &&
2279 seg == NO_SEG && !forw_ref &&
2280 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2281 mod = 0;
2282 else if (input->eaflags & EAF_BYTEOFFS ||
2283 (o >= -128 && o <= 127 &&
2284 seg == NO_SEG && !forw_ref &&
2285 !(input->eaflags & EAF_WORDOFFS)))
2286 mod = 1;
2287 else
2288 mod = 2;
2289 }
2290
2291 output->sib_present = true;
2292 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2293 output->modrm = GEN_MODRM(mod, rfield, 4);
2294 output->sib = GEN_SIB(scale, index, base);
2295 } else if ((ix|bx) & (BITS32|BITS64)) {
2296 /*
2297 * it must be a 32/64-bit memory reference. Firstly we have
2298 * to check that all registers involved are type E/Rxx.
2299 */
2300 opflags_t sok = BITS32 | BITS64;
2301 int32_t o = input->offset;
2302
2303 if (it != -1) {
2304 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2305 sok &= ix;
2306 else
2307 goto err;
2308 }
2309
2310 if (bt != -1) {
2311 if (REG_GPR & ~bx)
2312 goto err; /* Invalid register */
2313 if (~sok & bx & SIZE_MASK)
2314 goto err; /* Invalid size */
2315 sok &= bx;
2316 }
2317
2318 /*
2319 * While we're here, ensure the user didn't specify
2320 * WORD or QWORD
2321 */
2322 if (input->disp_size == 16 || input->disp_size == 64)
2323 goto err;
2324
2325 if (addrbits == 16 ||
2326 (addrbits == 32 && !(sok & BITS32)) ||
2327 (addrbits == 64 && !(sok & BITS64)))
2328 goto err;
2329
2330 /* now reorganize base/index */
2331 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2332 ((hb == b && ht == EAH_NOTBASE) ||
2333 (hb == i && ht == EAH_MAKEBASE))) {
2334 /* swap if hints say so */
2335 t = bt, bt = it, it = t;
2336 x = bx, bx = ix, ix = x;
2337 }
2338 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2339 bt = -1, bx = 0, s++;
2340 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2341 /* make single reg base, unless hint */
2342 bt = it, bx = ix, it = -1, ix = 0;
2343 }
2344 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2345 s == 3 || s == 5 || s == 9) && bt == -1)
2346 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2347 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2348 (input->eaflags & EAF_TIMESTWO))
2349 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2350 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2351 if (s == 1 && it == REG_NUM_ESP) {
2352 /* swap ESP into base if scale is 1 */
2353 t = it, it = bt, bt = t;
2354 x = ix, ix = bx, bx = x;
2355 }
2356 if (it == REG_NUM_ESP ||
2357 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2358 goto err; /* wrong, for various reasons */
2359
2360 output->rex |= rexflags(it, ix, REX_X);
2361 output->rex |= rexflags(bt, bx, REX_B);
2362
2363 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2364 /* no SIB needed */
2365 int mod, rm;
2366
2367 if (bt == -1) {
2368 rm = 5;
2369 mod = 0;
2370 } else {
2371 rm = (bt & 7);
2372 if (rm != REG_NUM_EBP && o == 0 &&
2373 seg == NO_SEG && !forw_ref &&
2374 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2375 mod = 0;
2376 else if (input->eaflags & EAF_BYTEOFFS ||
2377 (o >= -128 && o <= 127 &&
2378 seg == NO_SEG && !forw_ref &&
2379 !(input->eaflags & EAF_WORDOFFS)))
2380 mod = 1;
2381 else
2382 mod = 2;
2383 }
2384
2385 output->sib_present = false;
2386 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2387 output->modrm = GEN_MODRM(mod, rfield, rm);
2388 } else {
2389 /* we need a SIB */
2390 int mod, scale, index, base;
2391
2392 if (it == -1)
2393 index = 4, s = 1;
2394 else
2395 index = (it & 7);
2396
2397 switch (s) {
2398 case 1:
2399 scale = 0;
2400 break;
2401 case 2:
2402 scale = 1;
2403 break;
2404 case 4:
2405 scale = 2;
2406 break;
2407 case 8:
2408 scale = 3;
2409 break;
2410 default: /* then what the smeg is it? */
2411 goto err; /* panic */
2412 }
2413
2414 if (bt == -1) {
2415 base = 5;
2416 mod = 0;
2417 } else {
2418 base = (bt & 7);
2419 if (base != REG_NUM_EBP && o == 0 &&
2420 seg == NO_SEG && !forw_ref &&
2421 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2422 mod = 0;
2423 else if (input->eaflags & EAF_BYTEOFFS ||
2424 (o >= -128 && o <= 127 &&
2425 seg == NO_SEG && !forw_ref &&
2426 !(input->eaflags & EAF_WORDOFFS)))
2427 mod = 1;
2428 else
2429 mod = 2;
2430 }
2431
2432 output->sib_present = true;
2433 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2434 output->modrm = GEN_MODRM(mod, rfield, 4);
2435 output->sib = GEN_SIB(scale, index, base);
2436 }
2437 } else { /* it's 16-bit */
2438 int mod, rm;
2439 int16_t o = input->offset;
2440
2441 /* check for 64-bit long mode */
2442 if (addrbits == 64)
2443 goto err;
2444
2445 /* check all registers are BX, BP, SI or DI */
2446 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2447 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2448 goto err;
2449
2450 /* ensure the user didn't specify DWORD/QWORD */
2451 if (input->disp_size == 32 || input->disp_size == 64)
2452 goto err;
2453
2454 if (s != 1 && i != -1)
2455 goto err; /* no can do, in 16-bit EA */
2456 if (b == -1 && i != -1) {
2457 int tmp = b;
2458 b = i;
2459 i = tmp;
2460 } /* swap */
2461 if ((b == R_SI || b == R_DI) && i != -1) {
2462 int tmp = b;
2463 b = i;
2464 i = tmp;
2465 }
2466 /* have BX/BP as base, SI/DI index */
2467 if (b == i)
2468 goto err; /* shouldn't ever happen, in theory */
2469 if (i != -1 && b != -1 &&
2470 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2471 goto err; /* invalid combinations */
2472 if (b == -1) /* pure offset: handled above */
2473 goto err; /* so if it gets to here, panic! */
2474
2475 rm = -1;
2476 if (i != -1)
2477 switch (i * 256 + b) {
2478 case R_SI * 256 + R_BX:
2479 rm = 0;
2480 break;
2481 case R_DI * 256 + R_BX:
2482 rm = 1;
2483 break;
2484 case R_SI * 256 + R_BP:
2485 rm = 2;
2486 break;
2487 case R_DI * 256 + R_BP:
2488 rm = 3;
2489 break;
2490 } else
2491 switch (b) {
2492 case R_SI:
2493 rm = 4;
2494 break;
2495 case R_DI:
2496 rm = 5;
2497 break;
2498 case R_BP:
2499 rm = 6;
2500 break;
2501 case R_BX:
2502 rm = 7;
2503 break;
2504 }
2505 if (rm == -1) /* can't happen, in theory */
2506 goto err; /* so panic if it does */
2507
2508 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2509 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2510 mod = 0;
2511 else if (input->eaflags & EAF_BYTEOFFS ||
2512 (o >= -128 && o <= 127 && seg == NO_SEG &&
2513 !forw_ref && !(input->eaflags & EAF_WORDOFFS)))
2514 mod = 1;
2515 else
2516 mod = 2;
2517
2518 output->sib_present = false; /* no SIB - it's 16-bit */
2519 output->bytes = mod; /* bytes of offset needed */
2520 output->modrm = GEN_MODRM(mod, rfield, rm);
2521 }
2522 }
2523 }
2524
2525 output->size = 1 + output->sib_present + output->bytes;
2526 return output->type;
2527
2528 err:
2529 return output->type = EA_INVALID;
2530 }
2531
2532 static void add_asp(insn *ins, int addrbits)
2533 {
2534 int j, valid;
2535 int defdisp;
2536
2537 valid = (addrbits == 64) ? 64|32 : 32|16;
2538
2539 switch (ins->prefixes[PPS_ASIZE]) {
2540 case P_A16:
2541 valid &= 16;
2542 break;
2543 case P_A32:
2544 valid &= 32;
2545 break;
2546 case P_A64:
2547 valid &= 64;
2548 break;
2549 case P_ASP:
2550 valid &= (addrbits == 32) ? 16 : 32;
2551 break;
2552 default:
2553 break;
2554 }
2555
2556 for (j = 0; j < ins->operands; j++) {
2557 if (is_class(MEMORY, ins->oprs[j].type)) {
2558 opflags_t i, b;
2559
2560 /* Verify as Register */
2561 if (!is_register(ins->oprs[j].indexreg))
2562 i = 0;
2563 else
2564 i = nasm_reg_flags[ins->oprs[j].indexreg];
2565
2566 /* Verify as Register */
2567 if (!is_register(ins->oprs[j].basereg))
2568 b = 0;
2569 else
2570 b = nasm_reg_flags[ins->oprs[j].basereg];
2571
2572 if (ins->oprs[j].scale == 0)
2573 i = 0;
2574
2575 if (!i && !b) {
2576 int ds = ins->oprs[j].disp_size;
2577 if ((addrbits != 64 && ds > 8) ||
2578 (addrbits == 64 && ds == 16))
2579 valid &= ds;
2580 } else {
2581 if (!(REG16 & ~b))
2582 valid &= 16;
2583 if (!(REG32 & ~b))
2584 valid &= 32;
2585 if (!(REG64 & ~b))
2586 valid &= 64;
2587
2588 if (!(REG16 & ~i))
2589 valid &= 16;
2590 if (!(REG32 & ~i))
2591 valid &= 32;
2592 if (!(REG64 & ~i))
2593 valid &= 64;
2594 }
2595 }
2596 }
2597
2598 if (valid & addrbits) {
2599 ins->addr_size = addrbits;
2600 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2601 /* Add an address size prefix */
2602 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2603 ins->addr_size = (addrbits == 32) ? 16 : 32;
2604 } else {
2605 /* Impossible... */
2606 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2607 ins->addr_size = addrbits; /* Error recovery */
2608 }
2609
2610 defdisp = ins->addr_size == 16 ? 16 : 32;
2611
2612 for (j = 0; j < ins->operands; j++) {
2613 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2614 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2615 /*
2616 * mem_offs sizes must match the address size; if not,
2617 * strip the MEM_OFFS bit and match only EA instructions
2618 */
2619 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2620 }
2621 }
2622 }
The Netwide Assembler