3 # insns.pl produce insnsa.c, insnsd.c, insnsi.h, insnsn.c from insns.dat
5 # The Netwide Assembler is copyright (C) 1996 Simon Tatham and
6 # Julian Hall. All rights reserved. The software is
7 # redistributable under the license given in the file "LICENSE"
8 # distributed in the NASM archive.
10 # Opcode prefixes which need their own opcode tables
11 # LONGER PREFIXES FIRST!
12 @disasm_prefixes = qw(0F24 0F25 0F38 0F3A 0F7A 0FA6 0FA7 0F);
14 # This should match MAX_OPERANDS from nasm.h
17 # Add VEX/XOP prefixes
18 @vex_class = ( 'vex', 'xop' );
19 $vex_classes = scalar(@vex_class);
22 for ($c = 0; $c < $vex_classes; $c++) {
23 $vexmap{$vex_class[$c]} = $c;
24 for ($m = 0; $m < 32; $m++) {
25 for ($lp = 0; $lp < 8; $lp++) {
26 push(@vexlist, sprintf("%s%02X%01X", $vex_class[$c], $m, $lp));
30 @disasm_prefixes = (@vexlist, @disasm_prefixes);
32 @bytecode_count = (0) x
256;
34 print STDERR
"Reading insns.dat...\n";
38 foreach $arg ( @ARGV ) {
39 if ( $arg =~ /^\-/ ) {
40 if ( $arg =~ /^\-([abdin])$/ ) {
43 die "$0: Unknown option: ${arg}\n";
50 $fname = "insns.dat" unless $fname = $args[0];
51 open (F
, $fname) || die "unable to open $fname";
61 next if ( /^\s*(\;.*|)$/ ); # comments or blank lines
63 unless (/^\s*(\S+)\s+(\S+)\s+(\S+|\[.*\])\s+(\S+)\s*$/) {
64 warn "line $line does not contain four fields\n";
67 @fields = ($1, $2, $3, $4);
68 ($formatted, $nd) = format_insn
(@fields);
71 $aname = "aa_$fields[0]";
72 push @
$aname, $formatted;
74 if ( $fields[0] =~ /cc$/ ) {
75 # Conditional instruction
76 $k_opcodes_cc{$fields[0]}++;
78 # Unconditional instruction
79 $k_opcodes{$fields[0]}++;
81 if ($formatted && !$nd) {
82 push @big, $formatted;
83 my @sseq = startseq
($fields[2]);
85 if (!defined($dinstables{$i})) {
88 push(@
{$dinstables{$i}}, $#big);
96 # Generate the bytecode array. At this point, @bytecode_list contains
97 # the full set of bytecodes.
100 # Sort by descending length
101 @bytecode_list = sort { scalar(@
$b) <=> scalar(@
$a) } @bytecode_list;
102 @bytecode_array = ();
105 foreach $bl (@bytecode_list) {
106 my $h = hexstr
(@
$bl);
107 next if (defined($bytecode_pos{$h}));
109 push(@bytecode_array, $bl);
111 $bytecode_pos{$h} = $bytecode_next;
116 undef @bytecode_list;
118 @opcodes = sort keys(%k_opcodes);
119 @opcodes_cc = sort keys(%k_opcodes_cc);
121 if ( !defined($output) || $output eq 'b') {
122 print STDERR
"Writing insnsb.c...\n";
126 print B
"/* This file auto-generated from insns.dat by insns.pl" .
127 " - don't edit it */\n\n";
129 print B
"#include \"nasm.h\"\n";
130 print B
"#include \"insns.h\"\n\n";
132 print B
"const uint8_t nasm_bytecodes[$bytecode_next] = {\n";
135 foreach $bl (@bytecode_array) {
136 printf B
" /* %5d */ ", $p;
147 print B
" * Bytecode frequencies (including reuse):\n";
149 for ($i = 0; $i < 32; $i++) {
151 for ($j = 0; $j < 256; $j += 32) {
152 print B
" |" if ($j);
153 printf B
" %3o:%4d", $i+$j, $bytecode_count[$i+$j];
162 if ( !defined($output) || $output eq 'a' ) {
163 print STDERR
"Writing insnsa.c...\n";
167 print A
"/* This file auto-generated from insns.dat by insns.pl" .
168 " - don't edit it */\n\n";
170 print A
"#include \"nasm.h\"\n";
171 print A
"#include \"insns.h\"\n\n";
173 foreach $i (@opcodes, @opcodes_cc) {
174 print A
"static const struct itemplate instrux_${i}[] = {\n";
176 foreach $j (@
$aname) {
177 print A
" ", codesubst
($j), "\n";
179 print A
" ITEMPLATE_END\n};\n\n";
181 print A
"const struct itemplate * const nasm_instructions[] = {\n";
182 foreach $i (@opcodes, @opcodes_cc) {
183 print A
" instrux_${i},\n";
190 if ( !defined($output) || $output eq 'd' ) {
191 print STDERR
"Writing insnsd.c...\n";
195 print D
"/* This file auto-generated from insns.dat by insns.pl" .
196 " - don't edit it */\n\n";
198 print D
"#include \"nasm.h\"\n";
199 print D
"#include \"insns.h\"\n\n";
201 print D
"static const struct itemplate instrux[] = {\n";
204 printf D
" /* %4d */ %s\n", $n++, codesubst
($j);
208 foreach $h (sort(keys(%dinstables))) {
209 next if ($h eq ''); # Skip pseudo-instructions
210 print D
"\nstatic const struct itemplate * const itable_${h}[] = {\n";
211 foreach $j (@
{$dinstables{$h}}) {
212 print D
" instrux + $j,\n";
218 foreach $h (@disasm_prefixes, '') {
219 for ($c = 0; $c < 256; $c++) {
220 $nn = sprintf("%s%02X", $h, $c);
221 if ($is_prefix{$nn} || defined($dinstables{$nn})) {
222 # At least one entry in this prefix table
223 push(@prefix_list, $h);
230 foreach $h (@prefix_list) {
232 print D
"static " unless ($h eq '');
233 print D
"const struct disasm_index ";
234 print D
($h eq '') ?
'itable' : "itable_$h";
235 print D
"[256] = {\n";
236 for ($c = 0; $c < 256; $c++) {
237 $nn = sprintf("%s%02X", $h, $c);
238 if ($is_prefix{$nn}) {
239 die "$fname: ambiguous decoding of $nn\n"
240 if (defined($dinstables{$nn}));
241 printf D
" { itable_%s, -1 },\n", $nn;
242 } elsif (defined($dinstables{$nn})) {
243 printf D
" { itable_%s, %u },\n",
244 $nn, scalar(@
{$dinstables{$nn}});
246 printf D
" { NULL, 0 },\n";
252 printf D
"\nconst struct disasm_index * const itable_vex[%d][32][8] =\n",
255 for ($c = 0; $c < $vex_classes; $c++) {
257 for ($m = 0; $m < 32; $m++) {
259 for ($lp = 0; $lp < 8; $lp++) {
260 $vp = sprintf("%s%02X%01X", $vex_class[$c], $m, $lp);
261 if ($is_prefix{$vp}) {
262 printf D
" itable_%s,\n", $vp;
276 if ( !defined($output) || $output eq 'i' ) {
277 print STDERR
"Writing insnsi.h...\n";
281 print I
"/* This file is auto-generated from insns.dat by insns.pl" .
282 " - don't edit it */\n\n";
283 print I
"/* This file in included by nasm.h */\n\n";
285 print I
"/* Instruction names */\n\n";
286 print I
"#ifndef NASM_INSNSI_H\n";
287 print I
"#define NASM_INSNSI_H 1\n\n";
288 print I
"enum opcode {\n";
290 foreach $i (@opcodes, @opcodes_cc) {
291 print I
"\tI_${i},\n";
293 $len++ if ( $i =~ /cc$/ ); # Condition codes can be 3 characters long
294 $maxlen = $len if ( $len > $maxlen );
296 print I
"\tI_none = -1\n";
298 print I
"#define MAX_INSLEN ", $maxlen, "\n";
299 print I
"#define FIRST_COND_OPCODE I_", $opcodes_cc[0], "\n\n";
300 print I
"#endif /* NASM_INSNSI_H */\n";
305 if ( !defined($output) || $output eq 'n' ) {
306 print STDERR
"Writing insnsn.c...\n";
310 print N
"/* This file is auto-generated from insns.dat by insns.pl" .
311 " - don't edit it */\n\n";
312 print N
"#include \"tables.h\"\n\n";
314 print N
"const char * const nasm_insn_names[] = {";
316 foreach $i (@opcodes, @opcodes_cc) {
317 print N
"," if ( !$first );
320 $ilower =~ s/cc$//; # Remove conditional cc suffix
321 $ilower =~ tr/A-Z/a-z/; # Change to lower case (Perl 4 compatible)
322 print N
"\n\t\"${ilower}\"";
328 printf STDERR
"Done: %d instructions\n", $insns;
330 # Count primary bytecodes, for statistics
331 sub count_bytecodes
(@
) {
333 foreach my $bc (@_) {
338 $bytecode_count[$bc]++;
339 if ($bc >= 01 && $bc <= 04) {
341 } elsif (($bc & ~03) == 010) {
343 } elsif (($bc & ~013) == 0144) {
345 } elsif ($bc == 0172) {
347 } elsif ($bc >= 0260 && $bc <= 0270) {
349 } elsif ($bc == 0330) {
356 my ($opcode, $operands, $codes, $flags) = @_;
360 return (undef, undef) if $operands eq "ignore";
362 # format the operands
363 $operands =~ s/:/|colon,/g;
364 $operands =~ s/mem(\d+)/mem|bits$1/g;
365 $operands =~ s/mem/memory/g;
366 $operands =~ s/memory_offs/mem_offs/g;
367 $operands =~ s/imm(\d+)/imm|bits$1/g;
368 $operands =~ s/imm/immediate/g;
369 $operands =~ s/rm(\d+)/rm_gpr|bits$1/g;
370 $operands =~ s/(mmx|xmm|ymm)rm/rm_$1/g;
371 $operands =~ s/\=([0-9]+)/same_as|$1/g;
372 if ($operands eq 'void') {
375 @ops = split(/\,/, $operands);
378 while (scalar(@ops) < $MAX_OPERANDS) {
381 $operands = join(',', @ops);
382 $operands =~ tr/a-z/A-Z/;
385 $flags =~ s/,/|IF_/g;
386 $flags =~ s/(\|IF_ND|IF_ND\|)//, $nd = 1 if $flags =~ /IF_ND/;
387 $flags = "IF_" . $flags;
389 @bytecode = (decodify
($codes), 0);
390 push(@bytecode_list, [@bytecode]);
391 $codes = hexstr
(@bytecode);
392 count_bytecodes
(@bytecode);
394 ("{I_$opcode, $num, {$operands}, \@\@CODES-$codes\@\@, $flags},", $nd);
398 # Look for @@CODES-xxx@@ sequences and replace them with the appropriate
399 # offset into nasm_bytecodes
405 while ($s =~ /\@\@CODES-([0-9A-F]+)\@\@/) {
406 my $pos = $bytecode_pos{$1};
407 if (!defined($pos)) {
408 die "$fname: no position assigned to byte code $1\n";
410 $s = $` . "nasm_bytecodes+${pos}" . "$'";
416 my ($prefix, @list) = @_;
421 push(@l, sprintf("%s%02X", $prefix, $x));
428 # Turn a code string into a sequence of bytes
431 # Although these are C-syntax strings, by convention they should have
432 # only octal escapes (for directives) and hexadecimal escapes
433 # (for verbatim bytes)
436 if ($codestr =~ /^\s*\[([^\]]*)\]\s*$/) {
437 return byte_code_compile($1);
444 if ($c =~ /^\\x([0-9a-f]+)(.*)$/i) {
445 push(@codes, hex $1);
448 } elsif ($c =~ /^\\([0-7]{1,3})(.*)$/) {
449 push(@codes, oct $1);
453 die "$fname: unknown code format in \"$codestr\"\n";
460 # Turn a numeric list into a hex string
466 $s .= sprintf("%02X", $c);
471 # Here we determine the range of possible starting bytes for a given
472 # instruction. We need only consider the codes:
473 # \[1234] mean literal bytes, of course
474 # \1[0123] mean byte plus register value
475 # \330 means byte plus condition code
476 # \0 or \340 mean give up and return empty set
477 # \34[4567] mean PUSH/POP of segment registers: special case
478 # \17[234] skip is4 control byte
479 # \26x \270 skip VEX control bytes
488 @codes = decodify($codestr);
490 while ($c0 = shift(@codes)) {
492 if ($c0 >= 01 && $c0 <= 04) {
496 if ($c0 >= 01 && $c0 <= 04) {
498 $fbs .= sprintf("%02X", shift(@codes));
506 foreach $pfx (@disasm_prefixes) {
507 if (substr($fbs, 0, length($pfx)) eq $pfx) {
509 $fbs = substr($fbs, length($pfx));
515 return ($prefix.substr($fbs,0,2));
518 unshift(@codes, $c0);
519 } elsif ($c0 >= 010 && $c0 <= 013) {
520 return addprefix($prefix, $c1..($c1+7));
521 } elsif (($c0 & ~013) == 0144) {
522 return addprefix($prefix, $c1, $c1|2);
523 } elsif ($c0 == 0330) {
524 return addprefix($prefix, $c1..($c1+15));
525 } elsif ($c0 == 0 || $c0 == 0340) {
527 } elsif ($c0 == 0344) {
528 return addprefix($prefix, 0x06, 0x0E, 0x16, 0x1E);
529 } elsif ($c0 == 0345) {
530 return addprefix($prefix, 0x07, 0x17, 0x1F);
531 } elsif ($c0 == 0346) {
532 return addprefix($prefix, 0xA0, 0xA8);
533 } elsif ($c0 == 0347) {
534 return addprefix($prefix, 0xA1, 0xA9);
535 } elsif (($c0 & ~3) == 0260 || $c0 == 0270) {
538 $wlp = shift(@codes);
541 $prefix .= sprintf('%s%02X%01X', $vex_class[$c], $m, $wlp & 7);
542 } elsif ($c0 >= 0172 && $c0 <= 174) {
543 shift(@codes); # Skip is4 control byte
545 # We really need to be able to distinguish "forbidden"
546 # and "ignorable" codes here
553 # This function takes a series of byte codes in a format which is more
554 # typical of the Intel documentation, and encode it.
556 # The format looks like:
558 # [operands: opcodes]
560 # The operands word lists the order of the operands:
562 # r = register field in the modr/m
565 # d = DREX "dst" field
567 # s = register field of is4/imz2 field
568 # - = implicit (unencoded) operand
570 # For an operand that should be filled into more than one field,
571 # enter it as e.g. "r+v".
573 sub byte_code_compile($) {
584 unless ($str =~ /^(([^\s:]*)\:|)\s*(.*\S)\s*$/) {
585 die "$fname: $line: cannot parse: [$str]\n";
591 for ($i = 0; $i < length($opr); $i++) {
592 my $c = substr($opr,$i,1);
601 foreach $op (split(/\s*(?:\s|(?=[\/\\]))/, $opc)) {
604 } elsif ($op eq 'o32') {
606 } elsif ($op eq 'o64') { # 64-bit operand size requiring REX.W
608 } elsif ($op eq 'o64nw') { # Implied 64-bit operand size (no REX.W)
610 } elsif ($op eq 'a16') {
612 } elsif ($op eq 'a32') {
614 } elsif ($op eq 'a64') {
616 } elsif ($op eq '!osp') {
618 } elsif ($op eq '!asp') {
620 } elsif ($op eq 'rex.l') {
622 } elsif ($op eq 'repe') {
624 } elsif ($prefix_ok && $op =~ /^(66|f2|f3|np)$/) {
625 # 66/F2/F3 prefix used as an opcode extension, or np = no prefix
628 } elsif ($op eq 'f2') {
630 } elsif ($op eq 'f3') {
635 } elsif ($op =~ /^[0-9a-f]{2}$/) {
636 if (defined($litix) && $litix+$codes[$litix]+1 == scalar @codes &&
637 $codes[$litix] < 4) {
639 push(@codes, hex $op);
641 $litix = scalar(@codes);
642 push(@codes, 01, hex $op);
645 } elsif ($op eq '/r') {
646 if (!defined($oppos{'r'}) || !defined($oppos{'m'})) {
647 die "$fname: $line: $op requires r and m operands\n";
649 $opex = (($oppos{'m'} & 4) ? 06 : 0) |
650 (($oppos{'r'} & 4) ? 05 : 0);
651 push(@codes, $opex) if ($opex);
652 push(@codes, 0100 + (($oppos{'m'} & 3) << 3) + ($oppos{'r'} & 3));
654 } elsif ($op =~ m:^/([0-7])$:) {
655 if (!defined($oppos{'m'})) {
656 die "$fname: $line: $op requires m operand\n";
658 push(@codes, 06) if ($oppos{'m'} & 4);
659 push(@codes, 0200 + (($oppos{'m'} & 3) << 3) + $1);
661 } elsif ($op =~ /^(vex|xop)(|\..*)$/) {
663 my ($m,$w,$l,$p) = (undef,2,undef,0);
665 my @subops = split(/\./, $op);
666 shift @subops; # Drop prefix
667 foreach $oq (@subops) {
668 if ($oq eq '128' || $oq eq 'l0') {
670 } elsif ($oq eq '256' || $oq eq 'l1') {
672 } elsif ($oq eq 'w0') {
674 } elsif ($oq eq 'w1') {
676 } elsif ($oq eq 'wx') {
678 } elsif ($oq eq 'ww') {
680 } elsif ($oq eq 'p0') {
682 } elsif ($oq eq '66' || $oq eq 'p1') {
684 } elsif ($oq eq 'f3' || $oq eq 'p2') {
686 } elsif ($oq eq 'f2' || $oq eq 'p3') {
688 } elsif ($oq eq '0f') {
690 } elsif ($oq eq '0f38') {
692 } elsif ($oq eq '0f3a') {
694 } elsif ($oq =~ /^m([0-9]+)$/) {
696 } elsif ($oq eq 'nds' || $oq eq 'ndd' || $oq eq 'dds') {
697 if (!defined($oppos{'v'})) {
698 die "$fname: $line: vex.$oq without 'v' operand\n";
702 die "$fname: $line: undefined VEX subcode: $oq\n";
705 if (!defined($m) || !defined($w) || !defined($l) || !defined($p)) {
706 die "$fname: $line: missing fields in VEX specification\n";
708 if (defined($oppos{'v'}) && !$has_nds) {
709 die "$fname: $line: 'v' operand without vex.nds or vex.ndd\n";
711 push(@codes, defined($oppos{'v'}) ? 0260+($oppos{'v'} & 3) : 0270,
712 ($c << 6)+$m, ($w << 3)+($l << 2)+$p);
714 } elsif ($op =~ /^\/drex([01])$/) {
716 if (!defined($oppos{'d'})) {
717 die "$fname: $line: DREX without a 'd' operand\n";
719 # Note the use of *unshift* here, as opposed to *push*.
720 # This is because NASM want this byte code at the start of
721 # the instruction sequence, but the AMD documentation puts
722 # this at (roughly) the position of the drex byte itself.
723 # This allows us to match the AMD documentation and still
724 # do the right thing.
725 unshift(@codes, 0160+($oppos{'d'} & 3)+($oc0 ? 4 : 0));
726 unshift(@codes, 05) if ($oppos{'d'} & 4);
727 } elsif ($op =~ /^(ib\,s|ib|ibx|ib\,w|iw|iwd|id|idx|iwdq|rel|rel8|rel16|rel32|iq|seg|ibw|ibd|ibd,s)$/) {
728 if (!defined($oppos{'i'})) {
729 die "$fname: $line: $op without 'i' operand\n";
731 if ($op eq 'ib,s') { # Signed imm8
732 push(@codes, 05) if ($oppos{'i'} & 4);
733 push(@codes, 014+($oppos{'i'} & 3));
734 } elsif ($op eq 'ib') { # imm8
735 push(@codes, 05) if ($oppos{'i'} & 4);
736 push(@codes, 020+($oppos{'i'} & 3));
737 } elsif ($op eq 'ib,u') { # Unsigned imm8
738 push(@codes, 05) if ($oppos{'i'} & 4);
739 push(@codes, 024+($oppos{'i'} & 3));
740 } elsif ($op eq 'iw') { # imm16
741 push(@codes, 05) if ($oppos{'i'} & 4);
742 push(@codes, 030+($oppos{'i'} & 3));
743 } elsif ($op eq 'ibx') { # imm8 sign-extended to opsize
744 push(@codes, 05) if ($oppos{'i'} & 4);
745 push(@codes, 0274+($oppos{'i'} & 3));
746 } elsif ($op eq 'iwd') { # imm16 or imm32, depending on opsize
747 push(@codes, 05) if ($oppos{'i'} & 4);
748 push(@codes, 034+($oppos{'i'} & 3));
749 } elsif ($op eq 'id') { # imm32
750 push(@codes, 05) if ($oppos{'i'} & 4);
751 push(@codes, 040+($oppos{'i'} & 3));
752 } elsif ($op eq 'idx') { # imm32 extended to 64 bits
753 push(@codes, 05) if ($oppos{'i'} & 4);
754 push(@codes, 0254+($oppos{'i'} & 3));
755 } elsif ($op eq 'iwdq') { # imm16/32/64, depending on opsize
756 push(@codes, 05) if ($oppos{'i'} & 4);
757 push(@codes, 044+($oppos{'i'} & 3));
758 } elsif ($op eq 'rel8') {
759 push(@codes, 05) if ($oppos{'i'} & 4);
760 push(@codes, 050+($oppos{'i'} & 3));
761 } elsif ($op eq 'iq') {
762 push(@codes, 05) if ($oppos{'i'} & 4);
763 push(@codes, 054+($oppos{'i'} & 3));
764 } elsif ($op eq 'rel16') {
765 push(@codes, 05) if ($oppos{'i'} & 4);
766 push(@codes, 060+($oppos{'i'} & 3));
767 } elsif ($op eq 'rel') { # 16 or 32 bit relative operand
768 push(@codes, 05) if ($oppos{'i'} & 4);
769 push(@codes, 064+($oppos{'i'} & 3));
770 } elsif ($op eq 'rel32') {
771 push(@codes, 05) if ($oppos{'i'} & 4);
772 push(@codes, 070+($oppos{'i'} & 3));
773 } elsif ($op eq 'seg') {
774 push(@codes, 05) if ($oppos{'i'} & 4);
775 push(@codes, 074+($oppos{'i'} & 3));
776 } elsif ($op eq 'ibw') { # imm16 that can be bytified
777 if (!defined($s_pos)) {
778 die "$fname: $line: $op without a +s byte\n";
780 $codes[$s_pos] += 0144;
781 push(@codes, 05) if ($oppos{'i'} & 4);
782 push(@codes, 0140+($oppos{'i'} & 3));
783 } elsif ($op eq 'ibd') { # imm32 that can be bytified
784 if (!defined($s_pos)) {
785 die "$fname: $line: $op without a +s byte\n";
787 $codes[$s_pos] += 0154;
788 push(@codes, 05) if ($oppos{'i'} & 4);
789 push(@codes, 0150+($oppos{'i'} & 3));
790 } elsif ($op eq 'ibd,s') {
791 # imm32 that can be bytified, sign extended to 64 bits
792 if (!defined($s_pos)) {
793 die "$fname: $line: $op without a +s byte\n";
795 $codes[$s_pos] += 0154;
796 push(@codes, 05) if ($oppos{'i'} & 4);
797 push(@codes, 0250+($oppos{'i'} & 3));
800 } elsif ($op eq '/is4') {
801 if (!defined($oppos{'s'})) {
802 die "$fname: $line: $op without 's' operand\n";
804 if (defined($oppos{'i'})) {
805 push(@codes, 0172, ($oppos{'s'} << 3)+$oppos{'i'});
807 push(@codes, 0174, $oppos{'s'});
810 } elsif ($op =~ /^\/is4\=([0-9]+)$/) {
812 if (!defined($oppos{'s'})) {
813 die "$fname: $line: $op without 's' operand\n";
815 if ($imm < 0 || $imm > 15) {
816 die "$fname: $line: invalid imm4 value for $op: $imm\n";
818 push(@codes, 0173, ($oppos{'s'} << 4) + $imm);
820 } elsif ($op =~ /^([0-9a-f]{2})\+s$/) {
821 if (!defined($oppos{'i'})) {
822 die "$fname: $line: $op without 'i' operand\n";
824 $s_pos = scalar @codes;
825 push(@codes, 05) if ($oppos{'i'} & 4);
826 push(@codes, $oppos{'i'} & 3, hex $1);
828 } elsif ($op =~ /^([0-9a-f]{2})\+c$/) {
829 push(@codes, 0330, hex $1);
831 } elsif ($op =~ /^\\([0-7]+|x[0-9a-f]{2})$/) {
832 # Escape to enter literal bytecodes
833 push(@codes, oct $1);
835 die "$fname: $line: unknown operation: $op\n";