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NASM 2.04
[nasm.git] / assemble.c
blob16c88615fe70d9834ce712cb67e7130256a6c29a
1 /* assemble.c code generation for the Netwide Assembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
7 *
8 * the actual codes (C syntax, i.e. octal):
9 * \0 - terminates the code. (Unless it's a literal of course.)
10 * \1, \2, \3 - that many literal bytes follow in the code stream
11 * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
12 * (POP is never used for CS) depending on operand 0
13 * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
14 * on operand 0
15 * \10..\13 - a literal byte follows in the code stream, to be added
16 * to the register value of operand 0..3
17 * \14..\17 - a signed byte immediate operand, from operand 0..3
18 * \20..\23 - a byte immediate operand, from operand 0..3
19 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
20 * \30..\33 - a word immediate operand, from operand 0..3
21 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
22 * assembly mode or the operand-size override on the operand
23 * \40..\43 - a long immediate operand, from operand 0..3
24 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
25 * depending on the address size of the instruction.
26 * \50..\53 - a byte relative operand, from operand 0..3
27 * \54..\57 - a qword immediate operand, from operand 0..3
28 * \60..\63 - a word relative operand, from operand 0..3
29 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
30 * assembly mode or the operand-size override on the operand
31 * \70..\73 - a long relative operand, from operand 0..3
32 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
33 * \1ab - a ModRM, calculated on EA in operand a, with the spare
34 * field the register value of operand b.
35 * \140..\143 - an immediate word or signed byte for operand 0..3
36 * \144..\147 - or 2 (s-field) into opcode byte if operand 0..3
37 * is a signed byte rather than a word. Opcode byte follows.
38 * \150..\153 - an immediate dword or signed byte for operand 0..3
39 * \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
40 * is a signed byte rather than a dword. Opcode byte follows.
41 * \160..\163 - this instruction uses DREX rather than REX, with the
42 * OC0 field set to 0, and the dest field taken from
43 * operand 0..3.
44 * \164..\167 - this instruction uses DREX rather than REX, with the
45 * OC0 field set to 1, and the dest field taken from
46 * operand 0..3.
47 * \171 - placement of DREX suffix in the absence of an EA
48 * \172\ab - the register number from operand a in bits 7..4, with
49 * the 4-bit immediate from operand b in bits 3..0.
50 * \173\xab - the register number from operand a in bits 7..4, with
51 * the value b in bits 3..0.
52 * \174\a - the register number from operand a in bits 7..4, and
53 * an arbitrary value in bits 3..0 (assembled as zero.)
54 * \2ab - a ModRM, calculated on EA in operand a, with the spare
55 * field equal to digit b.
56 * \250..\253 - same as \150..\153, except warn if the 64-bit operand
57 * is not equal to the truncated and sign-extended 32-bit
58 * operand; used for 32-bit immediates in 64-bit mode.
59 * \260..\263 - this instruction uses VEX rather than REX, with the
60 * V field taken from operand 0..3.
61 * \270 - this instruction uses VEX rather than REX, with the
62 * V field set to 1111b.
63 *
64 * VEX prefixes are followed by the sequence:
65 * \mm\wlp where mm is the M field; and wlp is:
66 * 00 0ww lpp
67 * [w0] ww = 0 for W = 0
68 * [w1] ww = 1 for W = 1
69 * [wx] ww = 2 for W don't care (always assembled as 0)
70 * [ww] ww = 3 for W used as REX.W
71 *
72 *
73 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
74 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
75 * \312 - (disassembler only) marker on LOOP, LOOPxx instructions.
76 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
77 * \314 - (disassembler only) invalid with REX.B
78 * \315 - (disassembler only) invalid with REX.X
79 * \316 - (disassembler only) invalid with REX.R
80 * \317 - (disassembler only) invalid with REX.W
81 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
82 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
83 * \322 - indicates that this instruction is only valid when the
84 * operand size is the default (instruction to disassembler,
85 * generates no code in the assembler)
86 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
87 * \324 - indicates 64-bit operand size requiring REX prefix.
88 * \330 - a literal byte follows in the code stream, to be added
89 * to the condition code value of the instruction.
90 * \331 - instruction not valid with REP prefix. Hint for
91 * disassembler only; for SSE instructions.
92 * \332 - REP prefix (0xF2 byte) used as opcode extension.
93 * \333 - REP prefix (0xF3 byte) used as opcode extension.
94 * \334 - LOCK prefix used instead of REX.R
95 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
96 * \336 - force a REP(E) prefix (0xF2) even if not specified.
97 * \337 - force a REPNE prefix (0xF3) even if not specified.
98 * \336-\337 are still listed as prefixes in the disassembler.
99 * \340 - reserve <operand 0> bytes of uninitialized storage.
100 * Operand 0 had better be a segmentless constant.
101 * \360 - no SSE prefix (== \364\331)
102 * \361 - 66 SSE prefix (== \366\331)
103 * \362 - F2 SSE prefix (== \364\332)
104 * \363 - F3 SSE prefix (== \364\333)
105 * \364 - operand-size prefix (0x66) not permitted
106 * \365 - address-size prefix (0x67) not permitted
107 * \366 - operand-size prefix (0x66) used as opcode extension
108 * \367 - address-size prefix (0x67) used as opcode extension
109 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
110 * 370 is used for Jcc, 371 is used for JMP.
111 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
112 * used for conditional jump over longer jump
113 */
114
115 #include "compiler.h"
116
117 #include <stdio.h>
118 #include <string.h>
119 #include <inttypes.h>
120
121 #include "nasm.h"
122 #include "nasmlib.h"
123 #include "assemble.h"
124 #include "insns.h"
125 #include "tables.h"
126
127 /* Initialized to zero by the C standard */
128 static const uint8_t const_zero_buf[256];
129
130 typedef struct {
131 int sib_present; /* is a SIB byte necessary? */
132 int bytes; /* # of bytes of offset needed */
133 int size; /* lazy - this is sib+bytes+1 */
134 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
135 } ea;
136
137 static uint32_t cpu; /* cpu level received from nasm.c */
138 static efunc errfunc;
139 static struct ofmt *outfmt;
140 static ListGen *list;
141
142 static int64_t calcsize(int32_t, int64_t, int, insn *, const uint8_t *);
143 static void gencode(int32_t, int64_t, int, insn *, const uint8_t *, int64_t);
144 static int matches(const struct itemplate *, insn *, int bits);
145 static int32_t regflag(const operand *);
146 static int32_t regval(const operand *);
147 static int rexflags(int, int32_t, int);
148 static int op_rexflags(const operand *, int);
149 static ea *process_ea(operand *, ea *, int, int, int, int32_t);
150 static void add_asp(insn *, int);
151
152 static int has_prefix(insn * ins, enum prefix_pos pos, enum prefixes prefix)
153 {
154 return ins->prefixes[pos] == prefix;
155 }
156
157 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
158 {
159 if (ins->prefixes[pos])
160 errfunc(ERR_NONFATAL, "invalid %s prefix",
161 prefix_name(ins->prefixes[pos]));
162 }
163
164 static const char *size_name(int size)
165 {
166 switch (size) {
167 case 1:
168 return "byte";
169 case 2:
170 return "word";
171 case 4:
172 return "dword";
173 case 8:
174 return "qword";
175 case 10:
176 return "tword";
177 case 16:
178 return "oword";
179 case 32:
180 return "yword";
181 default:
182 return "???";
183 }
184 }
185
186 static void warn_overflow(int size, int64_t data)
187 {
188 if (size < 8) {
189 int64_t lim = ((int64_t)1 << (size*8))-1;
190
191 if (data < ~lim || data > lim)
192 errfunc(ERR_WARNING | ERR_WARN_NOV,
193 "%s data exceeds bounds", size_name(size));
194 }
195 }
196 /*
197 * This routine wrappers the real output format's output routine,
198 * in order to pass a copy of the data off to the listing file
199 * generator at the same time.
200 */
201 static void out(int64_t offset, int32_t segto, const void *data,
202 enum out_type type, uint64_t size,
203 int32_t segment, int32_t wrt)
204 {
205 static int32_t lineno = 0; /* static!!! */
206 static char *lnfname = NULL;
207 uint8_t p[8];
208
209 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
210 /*
211 * This is a non-relocated address, and we're going to
212 * convert it into RAWDATA format.
213 */
214 uint8_t *q = p;
215
216 if (size > 8) {
217 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
218 return;
219 }
220
221 WRITEADDR(q, *(int64_t *)data, size);
222 data = p;
223 type = OUT_RAWDATA;
224 }
225
226 list->output(offset, data, type, size);
227
228 /*
229 * this call to src_get determines when we call the
230 * debug-format-specific "linenum" function
231 * it updates lineno and lnfname to the current values
232 * returning 0 if "same as last time", -2 if lnfname
233 * changed, and the amount by which lineno changed,
234 * if it did. thus, these variables must be static
235 */
236
237 if (src_get(&lineno, &lnfname)) {
238 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
239 }
240
241 outfmt->output(segto, data, type, size, segment, wrt);
242 }
243
244 static int jmp_match(int32_t segment, int64_t offset, int bits,
245 insn * ins, const uint8_t *code)
246 {
247 int64_t isize;
248 uint8_t c = code[0];
249
250 if (c != 0370 && c != 0371)
251 return 0;
252 if ((optimizing <= 0 || (ins->oprs[0].type & STRICT)))
253 {
254 return 0;
255 }
256 isize = calcsize(segment, offset, bits, ins, code);
257 if (ins->oprs[0].segment != segment)
258 return 0;
259 isize = ins->oprs[0].offset - offset - isize; /* isize is now the delta */
260 if (isize >= -128L && isize <= 127L)
261 return 1; /* it is byte size */
262
263 return 0;
264 }
265
266 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
267 insn * instruction, struct ofmt *output, efunc error,
268 ListGen * listgen)
269 {
270 const struct itemplate *temp;
271 int j;
272 int size_prob;
273 int64_t insn_end;
274 int32_t itimes;
275 int64_t start = offset;
276 int64_t wsize = 0; /* size for DB etc. */
277
278 errfunc = error; /* to pass to other functions */
279 cpu = cp;
280 outfmt = output; /* likewise */
281 list = listgen; /* and again */
282
283 switch (instruction->opcode) {
284 case -1:
285 return 0;
286 case I_DB:
287 wsize = 1;
288 break;
289 case I_DW:
290 wsize = 2;
291 break;
292 case I_DD:
293 wsize = 4;
294 break;
295 case I_DQ:
296 wsize = 8;
297 break;
298 case I_DT:
299 wsize = 10;
300 break;
301 case I_DO:
302 wsize = 16;
303 break;
304 case I_DY:
305 wsize = 32;
306 break;
307 default:
308 break;
309 }
310
311 if (wsize) {
312 extop *e;
313 int32_t t = instruction->times;
314 if (t < 0)
315 errfunc(ERR_PANIC,
316 "instruction->times < 0 (%ld) in assemble()", t);
317
318 while (t--) { /* repeat TIMES times */
319 for (e = instruction->eops; e; e = e->next) {
320 if (e->type == EOT_DB_NUMBER) {
321 if (wsize == 1) {
322 if (e->segment != NO_SEG)
323 errfunc(ERR_NONFATAL,
324 "one-byte relocation attempted");
325 else {
326 uint8_t out_byte = e->offset;
327 out(offset, segment, &out_byte,
328 OUT_RAWDATA, 1, NO_SEG, NO_SEG);
329 }
330 } else if (wsize > 8) {
331 errfunc(ERR_NONFATAL,
332 "integer supplied to a DT, DO or DY"
333 " instruction");
334 } else
335 out(offset, segment, &e->offset,
336 OUT_ADDRESS, wsize, e->segment, e->wrt);
337 offset += wsize;
338 } else if (e->type == EOT_DB_STRING ||
339 e->type == EOT_DB_STRING_FREE) {
340 int align;
341
342 out(offset, segment, e->stringval,
343 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
344 align = e->stringlen % wsize;
345
346 if (align) {
347 align = wsize - align;
348 out(offset, segment, const_zero_buf,
349 OUT_RAWDATA, align, NO_SEG, NO_SEG);
350 }
351 offset += e->stringlen + align;
352 }
353 }
354 if (t > 0 && t == instruction->times - 1) {
355 /*
356 * Dummy call to list->output to give the offset to the
357 * listing module.
358 */
359 list->output(offset, NULL, OUT_RAWDATA, 0);
360 list->uplevel(LIST_TIMES);
361 }
362 }
363 if (instruction->times > 1)
364 list->downlevel(LIST_TIMES);
365 return offset - start;
366 }
367
368 if (instruction->opcode == I_INCBIN) {
369 const char *fname = instruction->eops->stringval;
370 FILE *fp;
371
372 fp = fopen(fname, "rb");
373 if (!fp) {
374 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
375 fname);
376 } else if (fseek(fp, 0L, SEEK_END) < 0) {
377 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
378 fname);
379 } else {
380 static char buf[4096];
381 size_t t = instruction->times;
382 size_t base = 0;
383 size_t len;
384
385 len = ftell(fp);
386 if (instruction->eops->next) {
387 base = instruction->eops->next->offset;
388 len -= base;
389 if (instruction->eops->next->next &&
390 len > (size_t)instruction->eops->next->next->offset)
391 len = (size_t)instruction->eops->next->next->offset;
392 }
393 /*
394 * Dummy call to list->output to give the offset to the
395 * listing module.
396 */
397 list->output(offset, NULL, OUT_RAWDATA, 0);
398 list->uplevel(LIST_INCBIN);
399 while (t--) {
400 size_t l;
401
402 fseek(fp, base, SEEK_SET);
403 l = len;
404 while (l > 0) {
405 int32_t m =
406 fread(buf, 1, (l > (int32_t) sizeof(buf) ? (int32_t) sizeof(buf) : l),
407 fp);
408 if (!m) {
409 /*
410 * This shouldn't happen unless the file
411 * actually changes while we are reading
412 * it.
413 */
414 error(ERR_NONFATAL,
415 "`incbin': unexpected EOF while"
416 " reading file `%s'", fname);
417 t = 0; /* Try to exit cleanly */
418 break;
419 }
420 out(offset, segment, buf, OUT_RAWDATA, m,
421 NO_SEG, NO_SEG);
422 l -= m;
423 }
424 }
425 list->downlevel(LIST_INCBIN);
426 if (instruction->times > 1) {
427 /*
428 * Dummy call to list->output to give the offset to the
429 * listing module.
430 */
431 list->output(offset, NULL, OUT_RAWDATA, 0);
432 list->uplevel(LIST_TIMES);
433 list->downlevel(LIST_TIMES);
434 }
435 fclose(fp);
436 return instruction->times * len;
437 }
438 return 0; /* if we're here, there's an error */
439 }
440
441 /* Check to see if we need an address-size prefix */
442 add_asp(instruction, bits);
443
444 size_prob = false;
445
446 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++){
447 int m = matches(temp, instruction, bits);
448
449 if (m == 99)
450 m += jmp_match(segment, offset, bits, instruction, temp->code);
451
452 if (m == 100) { /* matches! */
453 const uint8_t *codes = temp->code;
454 int64_t insn_size = calcsize(segment, offset, bits,
455 instruction, codes);
456 itimes = instruction->times;
457 if (insn_size < 0) /* shouldn't be, on pass two */
458 error(ERR_PANIC, "errors made it through from pass one");
459 else
460 while (itimes--) {
461 for (j = 0; j < MAXPREFIX; j++) {
462 uint8_t c = 0;
463 switch (instruction->prefixes[j]) {
464 case P_LOCK:
465 c = 0xF0;
466 break;
467 case P_REPNE:
468 case P_REPNZ:
469 c = 0xF2;
470 break;
471 case P_REPE:
472 case P_REPZ:
473 case P_REP:
474 c = 0xF3;
475 break;
476 case R_CS:
477 if (bits == 64) {
478 error(ERR_WARNING,
479 "cs segment base generated, but will be ignored in 64-bit mode");
480 }
481 c = 0x2E;
482 break;
483 case R_DS:
484 if (bits == 64) {
485 error(ERR_WARNING,
486 "ds segment base generated, but will be ignored in 64-bit mode");
487 }
488 c = 0x3E;
489 break;
490 case R_ES:
491 if (bits == 64) {
492 error(ERR_WARNING,
493 "es segment base generated, but will be ignored in 64-bit mode");
494 }
495 c = 0x26;
496 break;
497 case R_FS:
498 c = 0x64;
499 break;
500 case R_GS:
501 c = 0x65;
502 break;
503 case R_SS:
504 if (bits == 64) {
505 error(ERR_WARNING,
506 "ss segment base generated, but will be ignored in 64-bit mode");
507 }
508 c = 0x36;
509 break;
510 case R_SEGR6:
511 case R_SEGR7:
512 error(ERR_NONFATAL,
513 "segr6 and segr7 cannot be used as prefixes");
514 break;
515 case P_A16:
516 if (bits == 64) {
517 error(ERR_NONFATAL,
518 "16-bit addressing is not supported "
519 "in 64-bit mode");
520 } else if (bits != 16)
521 c = 0x67;
522 break;
523 case P_A32:
524 if (bits != 32)
525 c = 0x67;
526 break;
527 case P_A64:
528 if (bits != 64) {
529 error(ERR_NONFATAL,
530 "64-bit addressing is only supported "
531 "in 64-bit mode");
532 }
533 break;
534 case P_ASP:
535 c = 0x67;
536 break;
537 case P_O16:
538 if (bits != 16)
539 c = 0x66;
540 break;
541 case P_O32:
542 if (bits == 16)
543 c = 0x66;
544 break;
545 case P_O64:
546 /* REX.W */
547 break;
548 case P_OSP:
549 c = 0x66;
550 break;
551 case P_none:
552 break;
553 default:
554 error(ERR_PANIC, "invalid instruction prefix");
555 }
556 if (c != 0) {
557 out(offset, segment, &c, OUT_RAWDATA, 1,
558 NO_SEG, NO_SEG);
559 offset++;
560 }
561 }
562 insn_end = offset + insn_size;
563 gencode(segment, offset, bits, instruction, codes,
564 insn_end);
565 offset += insn_size;
566 if (itimes > 0 && itimes == instruction->times - 1) {
567 /*
568 * Dummy call to list->output to give the offset to the
569 * listing module.
570 */
571 list->output(offset, NULL, OUT_RAWDATA, 0);
572 list->uplevel(LIST_TIMES);
573 }
574 }
575 if (instruction->times > 1)
576 list->downlevel(LIST_TIMES);
577 return offset - start;
578 } else if (m > 0 && m > size_prob) {
579 size_prob = m;
580 }
581 // temp++;
582 }
583
584 if (temp->opcode == -1) { /* didn't match any instruction */
585 switch (size_prob) {
586 case 1:
587 error(ERR_NONFATAL, "operation size not specified");
588 break;
589 case 2:
590 error(ERR_NONFATAL, "mismatch in operand sizes");
591 break;
592 case 3:
593 error(ERR_NONFATAL, "no instruction for this cpu level");
594 break;
595 case 4:
596 error(ERR_NONFATAL, "instruction not supported in 64-bit mode");
597 break;
598 default:
599 error(ERR_NONFATAL,
600 "invalid combination of opcode and operands");
601 break;
602 }
603 }
604 return 0;
605 }
606
607 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
608 insn * instruction, efunc error)
609 {
610 const struct itemplate *temp;
611
612 errfunc = error; /* to pass to other functions */
613 cpu = cp;
614
615 if (instruction->opcode == -1)
616 return 0;
617
618 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
619 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
620 instruction->opcode == I_DT || instruction->opcode == I_DO ||
621 instruction->opcode == I_DY) {
622 extop *e;
623 int32_t isize, osize, wsize = 0; /* placate gcc */
624
625 isize = 0;
626 switch (instruction->opcode) {
627 case I_DB:
628 wsize = 1;
629 break;
630 case I_DW:
631 wsize = 2;
632 break;
633 case I_DD:
634 wsize = 4;
635 break;
636 case I_DQ:
637 wsize = 8;
638 break;
639 case I_DT:
640 wsize = 10;
641 break;
642 case I_DO:
643 wsize = 16;
644 break;
645 case I_DY:
646 wsize = 32;
647 break;
648 default:
649 break;
650 }
651
652 for (e = instruction->eops; e; e = e->next) {
653 int32_t align;
654
655 osize = 0;
656 if (e->type == EOT_DB_NUMBER)
657 osize = 1;
658 else if (e->type == EOT_DB_STRING ||
659 e->type == EOT_DB_STRING_FREE)
660 osize = e->stringlen;
661
662 align = (-osize) % wsize;
663 if (align < 0)
664 align += wsize;
665 isize += osize + align;
666 }
667 return isize * instruction->times;
668 }
669
670 if (instruction->opcode == I_INCBIN) {
671 const char *fname = instruction->eops->stringval;
672 FILE *fp;
673 size_t len;
674
675 fp = fopen(fname, "rb");
676 if (!fp)
677 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
678 fname);
679 else if (fseek(fp, 0L, SEEK_END) < 0)
680 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
681 fname);
682 else {
683 len = ftell(fp);
684 fclose(fp);
685 if (instruction->eops->next) {
686 len -= instruction->eops->next->offset;
687 if (instruction->eops->next->next &&
688 len > (size_t)instruction->eops->next->next->offset) {
689 len = (size_t)instruction->eops->next->next->offset;
690 }
691 }
692 return instruction->times * len;
693 }
694 return 0; /* if we're here, there's an error */
695 }
696
697 /* Check to see if we need an address-size prefix */
698 add_asp(instruction, bits);
699
700 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++) {
701 int m = matches(temp, instruction, bits);
702 if (m == 99)
703 m += jmp_match(segment, offset, bits, instruction, temp->code);
704
705 if (m == 100) {
706 /* we've matched an instruction. */
707 int64_t isize;
708 const uint8_t *codes = temp->code;
709 int j;
710
711 isize = calcsize(segment, offset, bits, instruction, codes);
712 if (isize < 0)
713 return -1;
714 for (j = 0; j < MAXPREFIX; j++) {
715 switch (instruction->prefixes[j]) {
716 case P_A16:
717 if (bits != 16)
718 isize++;
719 break;
720 case P_A32:
721 if (bits != 32)
722 isize++;
723 break;
724 case P_O16:
725 if (bits != 16)
726 isize++;
727 break;
728 case P_O32:
729 if (bits == 16)
730 isize++;
731 break;
732 case P_A64:
733 case P_O64:
734 case P_none:
735 break;
736 default:
737 isize++;
738 break;
739 }
740 }
741 return isize * instruction->times;
742 }
743 }
744 return -1; /* didn't match any instruction */
745 }
746
747 static bool possible_sbyte(operand *o)
748 {
749 return !(o->opflags & OPFLAG_FORWARD) &&
750 optimizing >= 0 && !(o->type & STRICT) &&
751 o->wrt == NO_SEG && o->segment == NO_SEG;
752 }
753
754 /* check that opn[op] is a signed byte of size 16 or 32 */
755 static bool is_sbyte16(operand *o)
756 {
757 int16_t v;
758
759 if (!possible_sbyte(o))
760 return false;
761
762 v = o->offset;
763 return v >= -128 && v <= 127;
764 }
765
766 static bool is_sbyte32(operand *o)
767 {
768 int32_t v;
769
770 if (!possible_sbyte(o))
771 return false;
772
773 v = o->offset;
774 return v >= -128 && v <= 127;
775 }
776
777 /* check that opn[op] is a signed byte of size 32; warn if this is not
778 the original value when extended to 64 bits */
779 static bool is_sbyte64(operand *o)
780 {
781 int64_t v64;
782 int32_t v32;
783
784 /* dead in the water on forward reference or External */
785 if (!possible_sbyte(o))
786 return false;
787
788 v64 = o->offset;
789 v32 = (int32_t)v64;
790
791 warn_overflow(32, v64);
792
793 return v32 >= -128 && v32 <= 127;
794 }
795 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
796 insn * ins, const uint8_t *codes)
797 {
798 int64_t length = 0;
799 uint8_t c;
800 int rex_mask = ~0;
801 struct operand *opx;
802
803 ins->rex = 0; /* Ensure REX is reset */
804
805 if (ins->prefixes[PPS_OSIZE] == P_O64)
806 ins->rex |= REX_W;
807
808 (void)segment; /* Don't warn that this parameter is unused */
809 (void)offset; /* Don't warn that this parameter is unused */
810
811 while (*codes) {
812 c = *codes++;
813 opx = &ins->oprs[c & 3];
814 switch (c) {
815 case 01:
816 case 02:
817 case 03:
818 codes += c, length += c;
819 break;
820 case 04:
821 case 05:
822 case 06:
823 case 07:
824 length++;
825 break;
826 case 010:
827 case 011:
828 case 012:
829 case 013:
830 ins->rex |=
831 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
832 codes++, length++;
833 break;
834 case 014:
835 case 015:
836 case 016:
837 case 017:
838 length++;
839 break;
840 case 020:
841 case 021:
842 case 022:
843 case 023:
844 length++;
845 break;
846 case 024:
847 case 025:
848 case 026:
849 case 027:
850 length++;
851 break;
852 case 030:
853 case 031:
854 case 032:
855 case 033:
856 length += 2;
857 break;
858 case 034:
859 case 035:
860 case 036:
861 case 037:
862 if (opx->type & (BITS16 | BITS32 | BITS64))
863 length += (opx->type & BITS16) ? 2 : 4;
864 else
865 length += (bits == 16) ? 2 : 4;
866 break;
867 case 040:
868 case 041:
869 case 042:
870 case 043:
871 length += 4;
872 break;
873 case 044:
874 case 045:
875 case 046:
876 case 047:
877 length += ins->addr_size >> 3;
878 break;
879 case 050:
880 case 051:
881 case 052:
882 case 053:
883 length++;
884 break;
885 case 054:
886 case 055:
887 case 056:
888 case 057:
889 length += 8; /* MOV reg64/imm */
890 break;
891 case 060:
892 case 061:
893 case 062:
894 case 063:
895 length += 2;
896 break;
897 case 064:
898 case 065:
899 case 066:
900 case 067:
901 if (opx->type & (BITS16 | BITS32 | BITS64))
902 length += (opx->type & BITS16) ? 2 : 4;
903 else
904 length += (bits == 16) ? 2 : 4;
905 break;
906 case 070:
907 case 071:
908 case 072:
909 case 073:
910 length += 4;
911 break;
912 case 074:
913 case 075:
914 case 076:
915 case 077:
916 length += 2;
917 break;
918 case 0140:
919 case 0141:
920 case 0142:
921 case 0143:
922 length += is_sbyte16(opx) ? 1 : 2;
923 break;
924 case 0144:
925 case 0145:
926 case 0146:
927 case 0147:
928 codes++;
929 length++;
930 break;
931 case 0150:
932 case 0151:
933 case 0152:
934 case 0153:
935 length += is_sbyte32(opx) ? 1 : 4;
936 break;
937 case 0154:
938 case 0155:
939 case 0156:
940 case 0157:
941 codes++;
942 length++;
943 break;
944 case 0160:
945 case 0161:
946 case 0162:
947 case 0163:
948 length++;
949 ins->rex |= REX_D;
950 ins->drexdst = regval(opx);
951 break;
952 case 0164:
953 case 0165:
954 case 0166:
955 case 0167:
956 length++;
957 ins->rex |= REX_D|REX_OC;
958 ins->drexdst = regval(opx);
959 break;
960 case 0171:
961 break;
962 case 0172:
963 case 0173:
964 case 0174:
965 codes++;
966 length++;
967 break;
968 case 0250:
969 case 0251:
970 case 0252:
971 case 0253:
972 length += is_sbyte64(opx) ? 1 : 4;
973 break;
974 case 0260:
975 case 0261:
976 case 0262:
977 case 0263:
978 ins->rex |= REX_V;
979 ins->drexdst = regval(opx);
980 ins->vex_m = *codes++;
981 ins->vex_wlp = *codes++;
982 break;
983 case 0270:
984 ins->rex |= REX_V;
985 ins->drexdst = 0;
986 ins->vex_m = *codes++;
987 ins->vex_wlp = *codes++;
988 break;
989 case 0300:
990 case 0301:
991 case 0302:
992 case 0303:
993 break;
994 case 0310:
995 if (bits == 64)
996 return -1;
997 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
998 break;
999 case 0311:
1000 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1001 break;
1002 case 0312:
1003 break;
1004 case 0313:
1005 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1006 has_prefix(ins, PPS_ASIZE, P_A32))
1007 return -1;
1008 break;
1009 case 0314:
1010 case 0315:
1011 case 0316:
1012 case 0317:
1013 break;
1014 case 0320:
1015 length += (bits != 16);
1016 break;
1017 case 0321:
1018 length += (bits == 16);
1019 break;
1020 case 0322:
1021 break;
1022 case 0323:
1023 rex_mask &= ~REX_W;
1024 break;
1025 case 0324:
1026 ins->rex |= REX_W;
1027 break;
1028 case 0330:
1029 codes++, length++;
1030 break;
1031 case 0331:
1032 break;
1033 case 0332:
1034 case 0333:
1035 length++;
1036 break;
1037 case 0334:
1038 ins->rex |= REX_L;
1039 break;
1040 case 0335:
1041 break;
1042 case 0336:
1043 if (!ins->prefixes[PPS_LREP])
1044 ins->prefixes[PPS_LREP] = P_REP;
1045 break;
1046 case 0337:
1047 if (!ins->prefixes[PPS_LREP])
1048 ins->prefixes[PPS_LREP] = P_REPNE;
1049 break;
1050 case 0340:
1051 if (ins->oprs[0].segment != NO_SEG)
1052 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1053 " quantity of BSS space");
1054 else
1055 length += ins->oprs[0].offset;
1056 break;
1057 case 0360:
1058 break;
1059 case 0361:
1060 case 0362:
1061 case 0363:
1062 length++;
1063 break;
1064 case 0364:
1065 case 0365:
1066 break;
1067 case 0366:
1068 case 0367:
1069 length++;
1070 break;
1071 case 0370:
1072 case 0371:
1073 case 0372:
1074 break;
1075 case 0373:
1076 length++;
1077 break;
1078 default: /* can't do it by 'case' statements */
1079 if (c >= 0100 && c <= 0277) { /* it's an EA */
1080 ea ea_data;
1081 int rfield;
1082 int32_t rflags;
1083 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1084
1085 if (c <= 0177) {
1086 /* pick rfield from operand b */
1087 rflags = regflag(&ins->oprs[c & 7]);
1088 rfield = nasm_regvals[ins->oprs[c & 7].basereg];
1089 } else {
1090 rflags = 0;
1091 rfield = c & 7;
1092 }
1093
1094 if (!process_ea
1095 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1096 ins->addr_size, rfield, rflags)) {
1097 errfunc(ERR_NONFATAL, "invalid effective address");
1098 return -1;
1099 } else {
1100 ins->rex |= ea_data.rex;
1101 length += ea_data.size;
1102 }
1103 } else {
1104 errfunc(ERR_PANIC, "internal instruction table corrupt"
1105 ": instruction code 0x%02X given", c);
1106 }
1107 }
1108 }
1109
1110 ins->rex &= rex_mask;
1111
1112 if (ins->rex & REX_V) {
1113 int bad32 = REX_R|REX_W|REX_X|REX_B;
1114
1115 if (ins->rex & REX_H) {
1116 errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
1117 return -1;
1118 }
1119 switch (ins->vex_wlp & 030) {
1120 case 000:
1121 case 020:
1122 ins->rex &= ~REX_W;
1123 break;
1124 case 010:
1125 ins->rex |= REX_W;
1126 bad32 &= ~REX_W;
1127 break;
1128 case 030:
1129 /* Follow REX_W */
1130 break;
1131 }
1132
1133 if (bits != 64 && ((ins->rex & bad32) || ins->drexdst > 7)) {
1134 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1135 return -1;
1136 }
1137 if (ins->vex_m != 1 || (ins->rex & (REX_W|REX_R|REX_B)))
1138 length += 3;
1139 else
1140 length += 2;
1141 } else if (ins->rex & REX_D) {
1142 if (ins->rex & REX_H) {
1143 errfunc(ERR_NONFATAL, "cannot use high register in drex instruction");
1144 return -1;
1145 }
1146 if (bits != 64 && ((ins->rex & (REX_R|REX_W|REX_X|REX_B)) ||
1147 ins->drexdst > 7)) {
1148 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1149 return -1;
1150 }
1151 length++;
1152 } else if (ins->rex & REX_REAL) {
1153 if (ins->rex & REX_H) {
1154 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1155 return -1;
1156 } else if (bits == 64) {
1157 length++;
1158 } else if ((ins->rex & REX_L) &&
1159 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1160 cpu >= IF_X86_64) {
1161 /* LOCK-as-REX.R */
1162 assert_no_prefix(ins, PPS_LREP);
1163 length++;
1164 } else {
1165 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1166 return -1;
1167 }
1168 }
1169
1170 return length;
1171 }
1172
1173 #define EMIT_REX() \
1174 if (!(ins->rex & (REX_D|REX_V)) && (ins->rex & REX_REAL) && (bits == 64)) { \
1175 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1176 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1177 ins->rex = 0; \
1178 offset += 1; \
1179 }
1180
1181 static void gencode(int32_t segment, int64_t offset, int bits,
1182 insn * ins, const uint8_t *codes, int64_t insn_end)
1183 {
1184 static char condval[] = { /* conditional opcodes */
1185 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1186 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1187 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1188 };
1189 uint8_t c;
1190 uint8_t bytes[4];
1191 int64_t size;
1192 int64_t data;
1193 struct operand *opx;
1194
1195 while (*codes) {
1196 c = *codes++;
1197 opx = &ins->oprs[c & 3];
1198 switch (c) {
1199 case 01:
1200 case 02:
1201 case 03:
1202 EMIT_REX();
1203 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1204 codes += c;
1205 offset += c;
1206 break;
1207
1208 case 04:
1209 case 06:
1210 switch (ins->oprs[0].basereg) {
1211 case R_CS:
1212 bytes[0] = 0x0E + (c == 0x04 ? 1 : 0);
1213 break;
1214 case R_DS:
1215 bytes[0] = 0x1E + (c == 0x04 ? 1 : 0);
1216 break;
1217 case R_ES:
1218 bytes[0] = 0x06 + (c == 0x04 ? 1 : 0);
1219 break;
1220 case R_SS:
1221 bytes[0] = 0x16 + (c == 0x04 ? 1 : 0);
1222 break;
1223 default:
1224 errfunc(ERR_PANIC,
1225 "bizarre 8086 segment register received");
1226 }
1227 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1228 offset++;
1229 break;
1230
1231 case 05:
1232 case 07:
1233 switch (ins->oprs[0].basereg) {
1234 case R_FS:
1235 bytes[0] = 0xA0 + (c == 0x05 ? 1 : 0);
1236 break;
1237 case R_GS:
1238 bytes[0] = 0xA8 + (c == 0x05 ? 1 : 0);
1239 break;
1240 default:
1241 errfunc(ERR_PANIC,
1242 "bizarre 386 segment register received");
1243 }
1244 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1245 offset++;
1246 break;
1247
1248 case 010:
1249 case 011:
1250 case 012:
1251 case 013:
1252 EMIT_REX();
1253 bytes[0] = *codes++ + ((regval(opx)) & 7);
1254 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1255 offset += 1;
1256 break;
1257
1258 case 014:
1259 case 015:
1260 case 016:
1261 case 017:
1262 /* XXX: warns for legitimate optimizer actions */
1263 if (opx->offset < -128 || opx->offset > 127) {
1264 errfunc(ERR_WARNING | ERR_WARN_NOV,
1265 "signed byte value exceeds bounds");
1266 }
1267
1268 if (opx->segment != NO_SEG) {
1269 data = opx->offset;
1270 out(offset, segment, &data, OUT_ADDRESS, 1,
1271 opx->segment, opx->wrt);
1272 } else {
1273 bytes[0] = opx->offset;
1274 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1275 NO_SEG);
1276 }
1277 offset += 1;
1278 break;
1279
1280 case 020:
1281 case 021:
1282 case 022:
1283 case 023:
1284 if (opx->offset < -256 || opx->offset > 255) {
1285 errfunc(ERR_WARNING | ERR_WARN_NOV,
1286 "byte value exceeds bounds");
1287 }
1288 if (opx->segment != NO_SEG) {
1289 data = opx->offset;
1290 out(offset, segment, &data, OUT_ADDRESS, 1,
1291 opx->segment, opx->wrt);
1292 } else {
1293 bytes[0] = opx->offset;
1294 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1295 NO_SEG);
1296 }
1297 offset += 1;
1298 break;
1299
1300 case 024:
1301 case 025:
1302 case 026:
1303 case 027:
1304 if (opx->offset < 0 || opx->offset > 255)
1305 errfunc(ERR_WARNING | ERR_WARN_NOV,
1306 "unsigned byte value exceeds bounds");
1307 if (opx->segment != NO_SEG) {
1308 data = opx->offset;
1309 out(offset, segment, &data, OUT_ADDRESS, 1,
1310 opx->segment, opx->wrt);
1311 } else {
1312 bytes[0] = opx->offset;
1313 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1314 NO_SEG);
1315 }
1316 offset += 1;
1317 break;
1318
1319 case 030:
1320 case 031:
1321 case 032:
1322 case 033:
1323 data = opx->offset;
1324 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1325 warn_overflow(2, data);
1326 out(offset, segment, &data, OUT_ADDRESS, 2,
1327 opx->segment, opx->wrt);
1328 offset += 2;
1329 break;
1330
1331 case 034:
1332 case 035:
1333 case 036:
1334 case 037:
1335 if (opx->type & (BITS16 | BITS32))
1336 size = (opx->type & BITS16) ? 2 : 4;
1337 else
1338 size = (bits == 16) ? 2 : 4;
1339 data = opx->offset;
1340 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1341 warn_overflow(size, data);
1342 out(offset, segment, &data, OUT_ADDRESS, size,
1343 opx->segment, opx->wrt);
1344 offset += size;
1345 break;
1346
1347 case 040:
1348 case 041:
1349 case 042:
1350 case 043:
1351 data = opx->offset;
1352 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1353 warn_overflow(4, data);
1354 out(offset, segment, &data, OUT_ADDRESS, 4,
1355 opx->segment, opx->wrt);
1356 offset += 4;
1357 break;
1358
1359 case 044:
1360 case 045:
1361 case 046:
1362 case 047:
1363 data = opx->offset;
1364 size = ins->addr_size >> 3;
1365 if (opx->segment == NO_SEG &&
1366 opx->wrt == NO_SEG)
1367 warn_overflow(size, data);
1368 out(offset, segment, &data, OUT_ADDRESS, size,
1369 opx->segment, opx->wrt);
1370 offset += size;
1371 break;
1372
1373 case 050:
1374 case 051:
1375 case 052:
1376 case 053:
1377 if (opx->segment != segment)
1378 errfunc(ERR_NONFATAL,
1379 "short relative jump outside segment");
1380 data = opx->offset - insn_end;
1381 if (data > 127 || data < -128)
1382 errfunc(ERR_NONFATAL, "short jump is out of range");
1383 bytes[0] = data;
1384 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1385 offset += 1;
1386 break;
1387
1388 case 054:
1389 case 055:
1390 case 056:
1391 case 057:
1392 data = (int64_t)opx->offset;
1393 out(offset, segment, &data, OUT_ADDRESS, 8,
1394 opx->segment, opx->wrt);
1395 offset += 8;
1396 break;
1397
1398 case 060:
1399 case 061:
1400 case 062:
1401 case 063:
1402 if (opx->segment != segment) {
1403 data = opx->offset;
1404 out(offset, segment, &data,
1405 OUT_REL2ADR, insn_end - offset,
1406 opx->segment, opx->wrt);
1407 } else {
1408 data = opx->offset - insn_end;
1409 out(offset, segment, &data,
1410 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1411 }
1412 offset += 2;
1413 break;
1414
1415 case 064:
1416 case 065:
1417 case 066:
1418 case 067:
1419 if (opx->type & (BITS16 | BITS32 | BITS64))
1420 size = (opx->type & BITS16) ? 2 : 4;
1421 else
1422 size = (bits == 16) ? 2 : 4;
1423 if (opx->segment != segment) {
1424 data = opx->offset;
1425 out(offset, segment, &data,
1426 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1427 insn_end - offset, opx->segment, opx->wrt);
1428 } else {
1429 data = opx->offset - insn_end;
1430 out(offset, segment, &data,
1431 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1432 }
1433 offset += size;
1434 break;
1435
1436 case 070:
1437 case 071:
1438 case 072:
1439 case 073:
1440 if (opx->segment != segment) {
1441 data = opx->offset;
1442 out(offset, segment, &data,
1443 OUT_REL4ADR, insn_end - offset,
1444 opx->segment, opx->wrt);
1445 } else {
1446 data = opx->offset - insn_end;
1447 out(offset, segment, &data,
1448 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1449 }
1450 offset += 4;
1451 break;
1452
1453 case 074:
1454 case 075:
1455 case 076:
1456 case 077:
1457 if (opx->segment == NO_SEG)
1458 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1459 " relocatable");
1460 data = 0;
1461 out(offset, segment, &data, OUT_ADDRESS, 2,
1462 outfmt->segbase(1 + opx->segment),
1463 opx->wrt);
1464 offset += 2;
1465 break;
1466
1467 case 0140:
1468 case 0141:
1469 case 0142:
1470 case 0143:
1471 data = opx->offset;
1472 if (is_sbyte16(opx)) {
1473 bytes[0] = data;
1474 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1475 NO_SEG);
1476 offset++;
1477 } else {
1478 if (opx->segment == NO_SEG &&
1479 opx->wrt == NO_SEG)
1480 warn_overflow(2, data);
1481 out(offset, segment, &data, OUT_ADDRESS, 2,
1482 opx->segment, opx->wrt);
1483 offset += 2;
1484 }
1485 break;
1486
1487 case 0144:
1488 case 0145:
1489 case 0146:
1490 case 0147:
1491 EMIT_REX();
1492 bytes[0] = *codes++;
1493 if (is_sbyte16(opx))
1494 bytes[0] |= 2; /* s-bit */
1495 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1496 offset++;
1497 break;
1498
1499 case 0150:
1500 case 0151:
1501 case 0152:
1502 case 0153:
1503 data = opx->offset;
1504 if (is_sbyte32(opx)) {
1505 bytes[0] = data;
1506 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1507 NO_SEG);
1508 offset++;
1509 } else {
1510 out(offset, segment, &data, OUT_ADDRESS, 4,
1511 opx->segment, opx->wrt);
1512 offset += 4;
1513 }
1514 break;
1515
1516 case 0154:
1517 case 0155:
1518 case 0156:
1519 case 0157:
1520 EMIT_REX();
1521 bytes[0] = *codes++;
1522 if (is_sbyte32(opx))
1523 bytes[0] |= 2; /* s-bit */
1524 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1525 offset++;
1526 break;
1527
1528 case 0160:
1529 case 0161:
1530 case 0162:
1531 case 0163:
1532 case 0164:
1533 case 0165:
1534 case 0166:
1535 case 0167:
1536 break;
1537
1538 case 0171:
1539 bytes[0] =
1540 (ins->drexdst << 4) |
1541 (ins->rex & REX_OC ? 0x08 : 0) |
1542 (ins->rex & (REX_R|REX_X|REX_B));
1543 ins->rex = 0;
1544 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1545 offset++;
1546 break;
1547
1548 case 0172:
1549 c = *codes++;
1550 opx = &ins->oprs[c >> 3];
1551 bytes[0] = nasm_regvals[opx->basereg] << 4;
1552 opx = &ins->oprs[c & 7];
1553 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1554 errfunc(ERR_NONFATAL,
1555 "non-absolute expression not permitted as argument %d",
1556 c & 7);
1557 } else {
1558 if (opx->offset & ~15) {
1559 errfunc(ERR_WARNING | ERR_WARN_NOV,
1560 "four-bit argument exceeds bounds");
1561 }
1562 bytes[0] |= opx->offset & 15;
1563 }
1564 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1565 offset++;
1566 break;
1567
1568 case 0173:
1569 c = *codes++;
1570 opx = &ins->oprs[c >> 4];
1571 bytes[0] = nasm_regvals[opx->basereg] << 4;
1572 bytes[0] |= c & 15;
1573 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1574 offset++;
1575 break;
1576
1577 case 0174:
1578 c = *codes++;
1579 opx = &ins->oprs[c];
1580 bytes[0] = nasm_regvals[opx->basereg] << 4;
1581 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1582 offset++;
1583 break;
1584
1585 case 0250:
1586 case 0251:
1587 case 0252:
1588 case 0253:
1589 data = opx->offset;
1590 /* is_sbyte32() is right here, we have already warned */
1591 if (is_sbyte32(opx)) {
1592 bytes[0] = data;
1593 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1594 NO_SEG);
1595 offset++;
1596 } else {
1597 out(offset, segment, &data, OUT_ADDRESS, 4,
1598 opx->segment, opx->wrt);
1599 offset += 4;
1600 }
1601 break;
1602
1603 case 0260:
1604 case 0261:
1605 case 0262:
1606 case 0263:
1607 case 0270:
1608 codes += 2;
1609 if (ins->vex_m != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1610 bytes[0] = 0xc4;
1611 bytes[1] = ins->vex_m | ((~ins->rex & 7) << 5);
1612 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1613 ((~ins->drexdst & 15)<< 3) | (ins->vex_wlp & 07);
1614 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1615 offset += 3;
1616 } else {
1617 bytes[0] = 0xc5;
1618 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1619 ((~ins->drexdst & 15) << 3) | (ins->vex_wlp & 07);
1620 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1621 offset += 2;
1622 }
1623 break;
1624
1625 case 0300:
1626 case 0301:
1627 case 0302:
1628 case 0303:
1629 break;
1630
1631 case 0310:
1632 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1633 *bytes = 0x67;
1634 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1635 offset += 1;
1636 } else
1637 offset += 0;
1638 break;
1639
1640 case 0311:
1641 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1642 *bytes = 0x67;
1643 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1644 offset += 1;
1645 } else
1646 offset += 0;
1647 break;
1648
1649 case 0312:
1650 break;
1651
1652 case 0313:
1653 ins->rex = 0;
1654 break;
1655
1656 case 0314:
1657 case 0315:
1658 case 0316:
1659 case 0317:
1660 break;
1661
1662 case 0320:
1663 if (bits != 16) {
1664 *bytes = 0x66;
1665 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1666 offset += 1;
1667 } else
1668 offset += 0;
1669 break;
1670
1671 case 0321:
1672 if (bits == 16) {
1673 *bytes = 0x66;
1674 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1675 offset += 1;
1676 } else
1677 offset += 0;
1678 break;
1679
1680 case 0322:
1681 case 0323:
1682 break;
1683
1684 case 0324:
1685 ins->rex |= REX_W;
1686 break;
1687
1688 case 0330:
1689 *bytes = *codes++ ^ condval[ins->condition];
1690 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1691 offset += 1;
1692 break;
1693
1694 case 0331:
1695 break;
1696
1697 case 0332:
1698 case 0333:
1699 *bytes = c - 0332 + 0xF2;
1700 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1701 offset += 1;
1702 break;
1703
1704 case 0334:
1705 if (ins->rex & REX_R) {
1706 *bytes = 0xF0;
1707 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1708 offset += 1;
1709 }
1710 ins->rex &= ~(REX_L|REX_R);
1711 break;
1712
1713 case 0335:
1714 break;
1715
1716 case 0336:
1717 case 0337:
1718 break;
1719
1720 case 0340:
1721 if (ins->oprs[0].segment != NO_SEG)
1722 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1723 else {
1724 int64_t size = ins->oprs[0].offset;
1725 if (size > 0)
1726 out(offset, segment, NULL,
1727 OUT_RESERVE, size, NO_SEG, NO_SEG);
1728 offset += size;
1729 }
1730 break;
1731
1732 case 0360:
1733 break;
1734
1735 case 0361:
1736 bytes[0] = 0x66;
1737 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1738 offset += 1;
1739 break;
1740
1741 case 0362:
1742 case 0363:
1743 bytes[0] = c - 0362 + 0xf2;
1744 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1745 offset += 1;
1746 break;
1747
1748 case 0364:
1749 case 0365:
1750 break;
1751
1752 case 0366:
1753 case 0367:
1754 *bytes = c - 0366 + 0x66;
1755 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1756 offset += 1;
1757 break;
1758
1759 case 0370:
1760 case 0371:
1761 case 0372:
1762 break;
1763
1764 case 0373:
1765 *bytes = bits == 16 ? 3 : 5;
1766 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1767 offset += 1;
1768 break;
1769
1770 default: /* can't do it by 'case' statements */
1771 if (c >= 0100 && c <= 0277) { /* it's an EA */
1772 ea ea_data;
1773 int rfield;
1774 int32_t rflags;
1775 uint8_t *p;
1776 int32_t s;
1777
1778 if (c <= 0177) {
1779 /* pick rfield from operand b */
1780 rflags = regflag(&ins->oprs[c & 7]);
1781 rfield = nasm_regvals[ins->oprs[c & 7].basereg];
1782 } else {
1783 /* rfield is constant */
1784 rflags = 0;
1785 rfield = c & 7;
1786 }
1787
1788 if (!process_ea
1789 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1790 ins->addr_size, rfield, rflags)) {
1791 errfunc(ERR_NONFATAL, "invalid effective address");
1792 }
1793
1794
1795 p = bytes;
1796 *p++ = ea_data.modrm;
1797 if (ea_data.sib_present)
1798 *p++ = ea_data.sib;
1799
1800 /* DREX suffixes come between the SIB and the displacement */
1801 if (ins->rex & REX_D) {
1802 *p++ =
1803 (ins->drexdst << 4) |
1804 (ins->rex & REX_OC ? 0x08 : 0) |
1805 (ins->rex & (REX_R|REX_X|REX_B));
1806 ins->rex = 0;
1807 }
1808
1809 s = p - bytes;
1810 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1811
1812 switch (ea_data.bytes) {
1813 case 0:
1814 break;
1815 case 1:
1816 if (ins->oprs[(c >> 3) & 7].segment != NO_SEG) {
1817 data = ins->oprs[(c >> 3) & 7].offset;
1818 out(offset, segment, &data, OUT_ADDRESS, 1,
1819 ins->oprs[(c >> 3) & 7].segment,
1820 ins->oprs[(c >> 3) & 7].wrt);
1821 } else {
1822 *bytes = ins->oprs[(c >> 3) & 7].offset;
1823 out(offset, segment, bytes, OUT_RAWDATA, 1,
1824 NO_SEG, NO_SEG);
1825 }
1826 s++;
1827 break;
1828 case 8:
1829 case 2:
1830 case 4:
1831 data = ins->oprs[(c >> 3) & 7].offset;
1832 warn_overflow(ea_data.bytes, data);
1833 out(offset, segment, &data,
1834 ea_data.rip ? OUT_REL4ADR : OUT_ADDRESS,
1835 ea_data.bytes,
1836 ins->oprs[(c >> 3) & 7].segment,
1837 ins->oprs[(c >> 3) & 7].wrt);
1838 s += ea_data.bytes;
1839 break;
1840 }
1841 offset += s;
1842 } else {
1843 errfunc(ERR_PANIC, "internal instruction table corrupt"
1844 ": instruction code 0x%02X given", c);
1845 }
1846 }
1847 }
1848 }
1849
1850 static int32_t regflag(const operand * o)
1851 {
1852 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1853 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1854 }
1855 return nasm_reg_flags[o->basereg];
1856 }
1857
1858 static int32_t regval(const operand * o)
1859 {
1860 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1861 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1862 }
1863 return nasm_regvals[o->basereg];
1864 }
1865
1866 static int op_rexflags(const operand * o, int mask)
1867 {
1868 int32_t flags;
1869 int val;
1870
1871 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1872 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1873 }
1874
1875 flags = nasm_reg_flags[o->basereg];
1876 val = nasm_regvals[o->basereg];
1877
1878 return rexflags(val, flags, mask);
1879 }
1880
1881 static int rexflags(int val, int32_t flags, int mask)
1882 {
1883 int rex = 0;
1884
1885 if (val >= 8)
1886 rex |= REX_B|REX_X|REX_R;
1887 if (flags & BITS64)
1888 rex |= REX_W;
1889 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1890 rex |= REX_H;
1891 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1892 rex |= REX_P;
1893
1894 return rex & mask;
1895 }
1896
1897 static int matches(const struct itemplate *itemp, insn * instruction, int bits)
1898 {
1899 int i, size[MAX_OPERANDS], asize, oprs, ret;
1900
1901 ret = 100;
1902
1903 /*
1904 * Check the opcode
1905 */
1906 if (itemp->opcode != instruction->opcode)
1907 return 0;
1908
1909 /*
1910 * Count the operands
1911 */
1912 if (itemp->operands != instruction->operands)
1913 return 0;
1914
1915 /*
1916 * Check that no spurious colons or TOs are present
1917 */
1918 for (i = 0; i < itemp->operands; i++)
1919 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1920 return 0;
1921
1922 /*
1923 * Process size flags
1924 */
1925 if (itemp->flags & IF_ARMASK) {
1926 memset(size, 0, sizeof size);
1927
1928 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
1929
1930 switch (itemp->flags & IF_SMASK) {
1931 case IF_SB:
1932 size[i] = BITS8;
1933 break;
1934 case IF_SW:
1935 size[i] = BITS16;
1936 break;
1937 case IF_SD:
1938 size[i] = BITS32;
1939 break;
1940 case IF_SQ:
1941 size[i] = BITS64;
1942 break;
1943 case IF_SO:
1944 size[i] = BITS128;
1945 break;
1946 case IF_SY:
1947 size[i] = BITS256;
1948 break;
1949 case IF_SZ:
1950 switch (bits) {
1951 case 16:
1952 size[i] = BITS16;
1953 break;
1954 case 32:
1955 size[i] = BITS32;
1956 break;
1957 case 64:
1958 size[i] = BITS64;
1959 break;
1960 }
1961 break;
1962 default:
1963 break;
1964 }
1965 } else {
1966 asize = 0;
1967 switch (itemp->flags & IF_SMASK) {
1968 case IF_SB:
1969 asize = BITS8;
1970 break;
1971 case IF_SW:
1972 asize = BITS16;
1973 break;
1974 case IF_SD:
1975 asize = BITS32;
1976 break;
1977 case IF_SQ:
1978 asize = BITS64;
1979 break;
1980 case IF_SO:
1981 asize = BITS128;
1982 break;
1983 case IF_SY:
1984 asize = BITS256;
1985 break;
1986 case IF_SZ:
1987 switch (bits) {
1988 case 16:
1989 asize = BITS16;
1990 break;
1991 case 32:
1992 asize = BITS32;
1993 break;
1994 case 64:
1995 asize = BITS64;
1996 break;
1997 }
1998 break;
1999 default:
2000 break;
2001 }
2002 for (i = 0; i < MAX_OPERANDS; i++)
2003 size[i] = asize;
2004 }
2005
2006 /*
2007 * Check that the operand flags all match up
2008 */
2009 for (i = 0; i < itemp->operands; i++) {
2010 int32_t type = instruction->oprs[i].type;
2011 if (!(type & SIZE_MASK))
2012 type |= size[i];
2013
2014 if (itemp->opd[i] & SAME_AS) {
2015 int j = itemp->opd[i] & ~SAME_AS;
2016 if (type != instruction->oprs[j].type ||
2017 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
2018 return 0;
2019 } else if (itemp->opd[i] & ~type ||
2020 ((itemp->opd[i] & SIZE_MASK) &&
2021 ((itemp->opd[i] ^ type) & SIZE_MASK))) {
2022 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2023 (type & SIZE_MASK))
2024 return 0;
2025 else
2026 return 1;
2027 }
2028 }
2029
2030 /*
2031 * Check operand sizes
2032 */
2033 if (itemp->flags & (IF_SM | IF_SM2)) {
2034 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2035 asize = 0;
2036 for (i = 0; i < oprs; i++) {
2037 if ((asize = itemp->opd[i] & SIZE_MASK) != 0) {
2038 int j;
2039 for (j = 0; j < oprs; j++)
2040 size[j] = asize;
2041 break;
2042 }
2043 }
2044 } else {
2045 oprs = itemp->operands;
2046 }
2047
2048 for (i = 0; i < itemp->operands; i++) {
2049 if (!(itemp->opd[i] & SIZE_MASK) &&
2050 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2051 return 2;
2052 }
2053
2054 /*
2055 * Check template is okay at the set cpu level
2056 */
2057 if (((itemp->flags & IF_PLEVEL) > cpu))
2058 return 3;
2059
2060 /*
2061 * Check if instruction is available in long mode
2062 */
2063 if ((itemp->flags & IF_NOLONG) && (bits == 64))
2064 return 4;
2065
2066 /*
2067 * Check if special handling needed for Jumps
2068 */
2069 if ((uint8_t)(itemp->code[0]) >= 0370)
2070 return 99;
2071
2072 return ret;
2073 }
2074
2075 static ea *process_ea(operand * input, ea * output, int bits,
2076 int addrbits, int rfield, int32_t rflags)
2077 {
2078 bool forw_ref = !!(input->opflags & OPFLAG_FORWARD);
2079
2080 output->rip = false;
2081
2082 /* REX flags for the rfield operand */
2083 output->rex |= rexflags(rfield, rflags, REX_R|REX_P|REX_W|REX_H);
2084
2085 if (!(REGISTER & ~input->type)) { /* register direct */
2086 int i;
2087 int32_t f;
2088
2089 if (input->basereg < EXPR_REG_START /* Verify as Register */
2090 || input->basereg >= REG_ENUM_LIMIT)
2091 return NULL;
2092 f = regflag(input);
2093 i = nasm_regvals[input->basereg];
2094
2095 if (REG_EA & ~f)
2096 return NULL; /* Invalid EA register */
2097
2098 output->rex |= op_rexflags(input, REX_B|REX_P|REX_W|REX_H);
2099
2100 output->sib_present = false; /* no SIB necessary */
2101 output->bytes = 0; /* no offset necessary either */
2102 output->modrm = 0xC0 | ((rfield & 7) << 3) | (i & 7);
2103 } else { /* it's a memory reference */
2104 if (input->basereg == -1
2105 && (input->indexreg == -1 || input->scale == 0)) {
2106 /* it's a pure offset */
2107 if (bits == 64 && (~input->type & IP_REL)) {
2108 int scale, index, base;
2109 output->sib_present = true;
2110 scale = 0;
2111 index = 4;
2112 base = 5;
2113 output->sib = (scale << 6) | (index << 3) | base;
2114 output->bytes = 4;
2115 output->modrm = 4 | ((rfield & 7) << 3);
2116 output->rip = false;
2117 } else {
2118 output->sib_present = false;
2119 output->bytes = (addrbits != 16 ? 4 : 2);
2120 output->modrm = (addrbits != 16 ? 5 : 6) | ((rfield & 7) << 3);
2121 output->rip = bits == 64;
2122 }
2123 } else { /* it's an indirection */
2124 int i = input->indexreg, b = input->basereg, s = input->scale;
2125 int32_t o = input->offset, seg = input->segment;
2126 int hb = input->hintbase, ht = input->hinttype;
2127 int t;
2128 int it, bt;
2129 int32_t ix, bx; /* register flags */
2130
2131 if (s == 0)
2132 i = -1; /* make this easy, at least */
2133
2134 if (i >= EXPR_REG_START && i < REG_ENUM_LIMIT) {
2135 it = nasm_regvals[i];
2136 ix = nasm_reg_flags[i];
2137 } else {
2138 it = -1;
2139 ix = 0;
2140 }
2141
2142 if (b >= EXPR_REG_START && b < REG_ENUM_LIMIT) {
2143 bt = nasm_regvals[b];
2144 bx = nasm_reg_flags[b];
2145 } else {
2146 bt = -1;
2147 bx = 0;
2148 }
2149
2150 /* check for a 32/64-bit memory reference... */
2151 if ((ix|bx) & (BITS32|BITS64)) {
2152 /* it must be a 32/64-bit memory reference. Firstly we have
2153 * to check that all registers involved are type E/Rxx. */
2154 int32_t sok = BITS32|BITS64;
2155
2156 if (it != -1) {
2157 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2158 sok &= ix;
2159 else
2160 return NULL;
2161 }
2162
2163 if (bt != -1) {
2164 if (REG_GPR & ~bx)
2165 return NULL; /* Invalid register */
2166 if (~sok & bx & SIZE_MASK)
2167 return NULL; /* Invalid size */
2168 sok &= bx;
2169 }
2170
2171 /* While we're here, ensure the user didn't specify
2172 WORD or QWORD. */
2173 if (input->disp_size == 16 || input->disp_size == 64)
2174 return NULL;
2175
2176 if (addrbits == 16 ||
2177 (addrbits == 32 && !(sok & BITS32)) ||
2178 (addrbits == 64 && !(sok & BITS64)))
2179 return NULL;
2180
2181 /* now reorganize base/index */
2182 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2183 ((hb == b && ht == EAH_NOTBASE)
2184 || (hb == i && ht == EAH_MAKEBASE))) {
2185 /* swap if hints say so */
2186 t = bt, bt = it, it = t;
2187 t = bx, bx = ix, ix = t;
2188 }
2189 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2190 bt = -1, bx = 0, s++;
2191 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2192 /* make single reg base, unless hint */
2193 bt = it, bx = ix, it = -1, ix = 0;
2194 }
2195 if (((s == 2 && it != REG_NUM_ESP
2196 && !(input->eaflags & EAF_TIMESTWO)) || s == 3
2197 || s == 5 || s == 9) && bt == -1)
2198 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2199 if (it == -1 && (bt & 7) != REG_NUM_ESP
2200 && (input->eaflags & EAF_TIMESTWO))
2201 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2202 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2203 if (s == 1 && it == REG_NUM_ESP) {
2204 /* swap ESP into base if scale is 1 */
2205 t = it, it = bt, bt = t;
2206 t = ix, ix = bx, bx = t;
2207 }
2208 if (it == REG_NUM_ESP
2209 || (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2210 return NULL; /* wrong, for various reasons */
2211
2212 output->rex |= rexflags(it, ix, REX_X);
2213 output->rex |= rexflags(bt, bx, REX_B);
2214
2215 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2216 /* no SIB needed */
2217 int mod, rm;
2218
2219 if (bt == -1) {
2220 rm = 5;
2221 mod = 0;
2222 } else {
2223 rm = (bt & 7);
2224 if (rm != REG_NUM_EBP && o == 0 &&
2225 seg == NO_SEG && !forw_ref &&
2226 !(input->eaflags &
2227 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2228 mod = 0;
2229 else if (input->eaflags & EAF_BYTEOFFS ||
2230 (o >= -128 && o <= 127 && seg == NO_SEG
2231 && !forw_ref
2232 && !(input->eaflags & EAF_WORDOFFS)))
2233 mod = 1;
2234 else
2235 mod = 2;
2236 }
2237
2238 output->sib_present = false;
2239 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2240 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2241 } else {
2242 /* we need a SIB */
2243 int mod, scale, index, base;
2244
2245 if (it == -1)
2246 index = 4, s = 1;
2247 else
2248 index = (it & 7);
2249
2250 switch (s) {
2251 case 1:
2252 scale = 0;
2253 break;
2254 case 2:
2255 scale = 1;
2256 break;
2257 case 4:
2258 scale = 2;
2259 break;
2260 case 8:
2261 scale = 3;
2262 break;
2263 default: /* then what the smeg is it? */
2264 return NULL; /* panic */
2265 }
2266
2267 if (bt == -1) {
2268 base = 5;
2269 mod = 0;
2270 } else {
2271 base = (bt & 7);
2272 if (base != REG_NUM_EBP && o == 0 &&
2273 seg == NO_SEG && !forw_ref &&
2274 !(input->eaflags &
2275 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2276 mod = 0;
2277 else if (input->eaflags & EAF_BYTEOFFS ||
2278 (o >= -128 && o <= 127 && seg == NO_SEG
2279 && !forw_ref
2280 && !(input->eaflags & EAF_WORDOFFS)))
2281 mod = 1;
2282 else
2283 mod = 2;
2284 }
2285
2286 output->sib_present = true;
2287 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2288 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2289 output->sib = (scale << 6) | (index << 3) | base;
2290 }
2291 } else { /* it's 16-bit */
2292 int mod, rm;
2293
2294 /* check for 64-bit long mode */
2295 if (addrbits == 64)
2296 return NULL;
2297
2298 /* check all registers are BX, BP, SI or DI */
2299 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI
2300 && b != R_DI) || (i != -1 && i != R_BP && i != R_BX
2301 && i != R_SI && i != R_DI))
2302 return NULL;
2303
2304 /* ensure the user didn't specify DWORD/QWORD */
2305 if (input->disp_size == 32 || input->disp_size == 64)
2306 return NULL;
2307
2308 if (s != 1 && i != -1)
2309 return NULL; /* no can do, in 16-bit EA */
2310 if (b == -1 && i != -1) {
2311 int tmp = b;
2312 b = i;
2313 i = tmp;
2314 } /* swap */
2315 if ((b == R_SI || b == R_DI) && i != -1) {
2316 int tmp = b;
2317 b = i;
2318 i = tmp;
2319 }
2320 /* have BX/BP as base, SI/DI index */
2321 if (b == i)
2322 return NULL; /* shouldn't ever happen, in theory */
2323 if (i != -1 && b != -1 &&
2324 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2325 return NULL; /* invalid combinations */
2326 if (b == -1) /* pure offset: handled above */
2327 return NULL; /* so if it gets to here, panic! */
2328
2329 rm = -1;
2330 if (i != -1)
2331 switch (i * 256 + b) {
2332 case R_SI * 256 + R_BX:
2333 rm = 0;
2334 break;
2335 case R_DI * 256 + R_BX:
2336 rm = 1;
2337 break;
2338 case R_SI * 256 + R_BP:
2339 rm = 2;
2340 break;
2341 case R_DI * 256 + R_BP:
2342 rm = 3;
2343 break;
2344 } else
2345 switch (b) {
2346 case R_SI:
2347 rm = 4;
2348 break;
2349 case R_DI:
2350 rm = 5;
2351 break;
2352 case R_BP:
2353 rm = 6;
2354 break;
2355 case R_BX:
2356 rm = 7;
2357 break;
2358 }
2359 if (rm == -1) /* can't happen, in theory */
2360 return NULL; /* so panic if it does */
2361
2362 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2363 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2364 mod = 0;
2365 else if (input->eaflags & EAF_BYTEOFFS ||
2366 (o >= -128 && o <= 127 && seg == NO_SEG
2367 && !forw_ref
2368 && !(input->eaflags & EAF_WORDOFFS)))
2369 mod = 1;
2370 else
2371 mod = 2;
2372
2373 output->sib_present = false; /* no SIB - it's 16-bit */
2374 output->bytes = mod; /* bytes of offset needed */
2375 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2376 }
2377 }
2378 }
2379
2380 output->size = 1 + output->sib_present + output->bytes;
2381 return output;
2382 }
2383
2384 static void add_asp(insn *ins, int addrbits)
2385 {
2386 int j, valid;
2387 int defdisp;
2388
2389 valid = (addrbits == 64) ? 64|32 : 32|16;
2390
2391 switch (ins->prefixes[PPS_ASIZE]) {
2392 case P_A16:
2393 valid &= 16;
2394 break;
2395 case P_A32:
2396 valid &= 32;
2397 break;
2398 case P_A64:
2399 valid &= 64;
2400 break;
2401 case P_ASP:
2402 valid &= (addrbits == 32) ? 16 : 32;
2403 break;
2404 default:
2405 break;
2406 }
2407
2408 for (j = 0; j < ins->operands; j++) {
2409 if (!(MEMORY & ~ins->oprs[j].type)) {
2410 int32_t i, b;
2411
2412 /* Verify as Register */
2413 if (ins->oprs[j].indexreg < EXPR_REG_START
2414 || ins->oprs[j].indexreg >= REG_ENUM_LIMIT)
2415 i = 0;
2416 else
2417 i = nasm_reg_flags[ins->oprs[j].indexreg];
2418
2419 /* Verify as Register */
2420 if (ins->oprs[j].basereg < EXPR_REG_START
2421 || ins->oprs[j].basereg >= REG_ENUM_LIMIT)
2422 b = 0;
2423 else
2424 b = nasm_reg_flags[ins->oprs[j].basereg];
2425
2426 if (ins->oprs[j].scale == 0)
2427 i = 0;
2428
2429 if (!i && !b) {
2430 int ds = ins->oprs[j].disp_size;
2431 if ((addrbits != 64 && ds > 8) ||
2432 (addrbits == 64 && ds == 16))
2433 valid &= ds;
2434 } else {
2435 if (!(REG16 & ~b))
2436 valid &= 16;
2437 if (!(REG32 & ~b))
2438 valid &= 32;
2439 if (!(REG64 & ~b))
2440 valid &= 64;
2441
2442 if (!(REG16 & ~i))
2443 valid &= 16;
2444 if (!(REG32 & ~i))
2445 valid &= 32;
2446 if (!(REG64 & ~i))
2447 valid &= 64;
2448 }
2449 }
2450 }
2451
2452 if (valid & addrbits) {
2453 ins->addr_size = addrbits;
2454 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2455 /* Add an address size prefix */
2456 enum prefixes pref = (addrbits == 32) ? P_A16 : P_A32;
2457 ins->prefixes[PPS_ASIZE] = pref;
2458 ins->addr_size = (addrbits == 32) ? 16 : 32;
2459 } else {
2460 /* Impossible... */
2461 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2462 ins->addr_size = addrbits; /* Error recovery */
2463 }
2464
2465 defdisp = ins->addr_size == 16 ? 16 : 32;
2466
2467 for (j = 0; j < ins->operands; j++) {
2468 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2469 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp)
2470 != ins->addr_size) {
2471 /* mem_offs sizes must match the address size; if not,
2472 strip the MEM_OFFS bit and match only EA instructions */
2473 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2474 }
2475 }
2476 }
The Netwide Assembler