1 /* assemble.c code generation for the Netwide Assembler
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the licence given in the file "Licence"
6 * distributed in the NASM archive.
8 * the actual codes (C syntax, i.e. octal):
9 * \0 - terminates the code. (Unless it's a literal of course.)
10 * \1, \2, \3 - that many literal bytes follow in the code stream
11 * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
12 * (POP is never used for CS) depending on operand 0
13 * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
15 * \10..\13 - a literal byte follows in the code stream, to be added
16 * to the register value of operand 0..3
17 * \14..\17 - a signed byte immediate operand, from operand 0..3
18 * \20..\23 - a byte immediate operand, from operand 0..3
19 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
20 * \30..\33 - a word immediate operand, from operand 0..3
21 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
22 * assembly mode or the operand-size override on the operand
23 * \40..\43 - a long immediate operand, from operand 0..3
24 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
25 * depending on the address size of the instruction.
26 * \50..\53 - a byte relative operand, from operand 0..3
27 * \54..\57 - a qword immediate operand, from operand 0..3
28 * \60..\63 - a word relative operand, from operand 0..3
29 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
30 * assembly mode or the operand-size override on the operand
31 * \70..\73 - a long relative operand, from operand 0..3
32 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
33 * \1ab - a ModRM, calculated on EA in operand a, with the spare
34 * field the register value of operand b.
35 * \140..\143 - an immediate word or signed byte for operand 0..3
36 * \144..\147 - or 2 (s-field) into next opcode byte if operand 0..3
37 * is a signed byte rather than a word.
38 * \150..\153 - an immediate dword or signed byte for operand 0..3
39 * \154..\157 - or 2 (s-field) into next opcode byte if operand 0..3
40 * is a signed byte rather than a dword.
41 * \160..\163 - this instruction uses DREX rather than REX, with the
42 * OC0 field set to 0, and the dest field taken from
44 * \164..\167 - this instruction uses DREX rather than REX, with the
45 * OC0 field set to 1, and the dest field taken from
47 * \170 - encodes the literal byte 0. (Some compilers don't take
48 * kindly to a zero byte in the _middle_ of a compile time
49 * string constant, so I had to put this hack in.)
50 * \171 - placement of DREX suffix in the absence of an EA
51 * \2ab - a ModRM, calculated on EA in operand a, with the spare
52 * field equal to digit b.
53 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
54 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
55 * \312 - (disassembler only) marker on LOOP, LOOPxx instructions.
56 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
57 * \314 - (disassembler only) invalid with REX.B
58 * \315 - (disassembler only) invalid with REX.X
59 * \316 - (disassembler only) invalid with REX.R
60 * \317 - (disassembler only) invalid with REX.W
61 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
62 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
63 * \322 - indicates that this instruction is only valid when the
64 * operand size is the default (instruction to disassembler,
65 * generates no code in the assembler)
66 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
67 * \324 - indicates 64-bit operand size requiring REX prefix.
68 * \330 - a literal byte follows in the code stream, to be added
69 * to the condition code value of the instruction.
70 * \331 - instruction not valid with REP prefix. Hint for
71 * disassembler only; for SSE instructions.
72 * \332 - REP prefix (0xF2 byte) used as opcode extension.
73 * \333 - REP prefix (0xF3 byte) used as opcode extension.
74 * \334 - LOCK prefix used instead of REX.R
75 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
76 * \340 - reserve <operand 0> bytes of uninitialized storage.
77 * Operand 0 had better be a segmentless constant.
78 * \364 - operand-size prefix (0x66) not permitted
79 * \365 - address-size prefix (0x67) not permitted
80 * \366 - operand-size prefix (0x66) used as opcode extension
81 * \367 - address-size prefix (0x67) used as opcode extension
82 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
83 * 370 is used for Jcc, 371 is used for JMP.
84 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
85 * used for conditional jump over longer jump
103 int sib_present
; /* is a SIB byte necessary? */
104 int bytes
; /* # of bytes of offset needed */
105 int size
; /* lazy - this is sib+bytes+1 */
106 uint8_t modrm
, sib
, rex
, rip
; /* the bytes themselves */
109 static uint32_t cpu
; /* cpu level received from nasm.c */
110 static efunc errfunc
;
111 static struct ofmt
*outfmt
;
112 static ListGen
*list
;
114 static int64_t calcsize(int32_t, int64_t, int, insn
*, const char *);
115 static void gencode(int32_t, int64_t, int, insn
*, const char *, int64_t);
116 static int matches(const struct itemplate
*, insn
*, int bits
);
117 static int32_t regflag(const operand
*);
118 static int32_t regval(const operand
*);
119 static int rexflags(int, int32_t, int);
120 static int op_rexflags(const operand
*, int);
121 static ea
*process_ea(operand
*, ea
*, int, int, int, int32_t, int);
122 static void add_asp(insn
*, int);
124 static int has_prefix(insn
* ins
, enum prefix_pos pos
, enum prefixes prefix
)
126 return ins
->prefixes
[pos
] == prefix
;
129 static void assert_no_prefix(insn
* ins
, enum prefix_pos pos
)
131 if (ins
->prefixes
[pos
])
132 errfunc(ERR_NONFATAL
, "invalid %s prefix",
133 prefix_name(ins
->prefixes
[pos
]));
136 static const char *size_name(int size
)
156 static void warn_overflow(int size
, int64_t data
)
159 int64_t lim
= ((int64_t)1 << (size
*8))-1;
161 if (data
< ~lim
|| data
> lim
)
162 errfunc(ERR_WARNING
, "%s data exceeds bounds", size_name(size
));
166 * This routine wrappers the real output format's output routine,
167 * in order to pass a copy of the data off to the listing file
168 * generator at the same time.
170 static void out(int64_t offset
, int32_t segto
, const void *data
,
171 enum out_type type
, uint64_t size
,
172 int32_t segment
, int32_t wrt
)
174 static int32_t lineno
= 0; /* static!!! */
175 static char *lnfname
= NULL
;
178 if (type
== OUT_ADDRESS
&& segment
== NO_SEG
&& wrt
== NO_SEG
) {
180 * This is a non-relocated address, and we're going to
181 * convert it into RAWDATA format.
187 WRITESHORT(q
, *(int32_t *)data
);
190 WRITELONG(q
, *(int32_t *)data
);
193 WRITEDLONG(q
, *(int64_t *)data
);
200 list
->output(offset
, data
, type
, size
);
203 * this call to src_get determines when we call the
204 * debug-format-specific "linenum" function
205 * it updates lineno and lnfname to the current values
206 * returning 0 if "same as last time", -2 if lnfname
207 * changed, and the amount by which lineno changed,
208 * if it did. thus, these variables must be static
211 if (src_get(&lineno
, &lnfname
)) {
212 outfmt
->current_dfmt
->linenum(lnfname
, lineno
, segto
);
215 outfmt
->output(segto
, data
, type
, size
, segment
, wrt
);
218 static int jmp_match(int32_t segment
, int64_t offset
, int bits
,
219 insn
* ins
, const char *code
)
224 if (c
!= 0370 && c
!= 0371)
226 if (ins
->oprs
[0].opflags
& OPFLAG_FORWARD
) {
227 if ((optimizing
< 0 || (ins
->oprs
[0].type
& STRICT
))
231 return (pass0
== 0); /* match a forward reference */
233 isize
= calcsize(segment
, offset
, bits
, ins
, code
);
234 if (ins
->oprs
[0].segment
!= segment
)
236 isize
= ins
->oprs
[0].offset
- offset
- isize
; /* isize is now the delta */
237 if (isize
>= -128L && isize
<= 127L)
238 return 1; /* it is byte size */
243 int64_t assemble(int32_t segment
, int64_t offset
, int bits
, uint32_t cp
,
244 insn
* instruction
, struct ofmt
*output
, efunc error
,
247 const struct itemplate
*temp
;
252 int64_t start
= offset
;
253 int64_t wsize
= 0; /* size for DB etc. */
255 errfunc
= error
; /* to pass to other functions */
257 outfmt
= output
; /* likewise */
258 list
= listgen
; /* and again */
260 switch (instruction
->opcode
) {
287 int32_t t
= instruction
->times
;
290 "instruction->times < 0 (%ld) in assemble()", t
);
292 while (t
--) { /* repeat TIMES times */
293 for (e
= instruction
->eops
; e
; e
= e
->next
) {
294 if (e
->type
== EOT_DB_NUMBER
) {
296 if (e
->segment
!= NO_SEG
)
297 errfunc(ERR_NONFATAL
,
298 "one-byte relocation attempted");
300 uint8_t out_byte
= e
->offset
;
301 out(offset
, segment
, &out_byte
,
302 OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
304 } else if (wsize
> 8) {
305 errfunc(ERR_NONFATAL
, "integer supplied to a DT or DO"
308 out(offset
, segment
, &e
->offset
,
309 OUT_ADDRESS
, wsize
, e
->segment
, e
->wrt
);
311 } else if (e
->type
== EOT_DB_STRING
) {
314 out(offset
, segment
, e
->stringval
,
315 OUT_RAWDATA
, e
->stringlen
, NO_SEG
, NO_SEG
);
316 align
= e
->stringlen
% wsize
;
319 align
= wsize
- align
;
320 out(offset
, segment
, "\0\0\0\0\0\0\0\0",
321 OUT_RAWDATA
, align
, NO_SEG
, NO_SEG
);
323 offset
+= e
->stringlen
+ align
;
326 if (t
> 0 && t
== instruction
->times
- 1) {
328 * Dummy call to list->output to give the offset to the
331 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
332 list
->uplevel(LIST_TIMES
);
335 if (instruction
->times
> 1)
336 list
->downlevel(LIST_TIMES
);
337 return offset
- start
;
340 if (instruction
->opcode
== I_INCBIN
) {
341 static char fname
[FILENAME_MAX
];
344 char *prefix
= "", *combine
;
345 char **pPrevPath
= NULL
;
347 len
= FILENAME_MAX
- 1;
348 if (len
> instruction
->eops
->stringlen
)
349 len
= instruction
->eops
->stringlen
;
350 strncpy(fname
, instruction
->eops
->stringval
, len
);
353 while (1) { /* added by alexfru: 'incbin' uses include paths */
354 combine
= nasm_malloc(strlen(prefix
) + len
+ 1);
355 strcpy(combine
, prefix
);
356 strcat(combine
, fname
);
358 if ((fp
= fopen(combine
, "rb")) != NULL
) {
364 pPrevPath
= pp_get_include_path_ptr(pPrevPath
);
365 if (pPrevPath
== NULL
)
371 error(ERR_NONFATAL
, "`incbin': unable to open file `%s'",
373 else if (fseek(fp
, 0L, SEEK_END
) < 0)
374 error(ERR_NONFATAL
, "`incbin': unable to seek on file `%s'",
377 static char buf
[2048];
378 int32_t t
= instruction
->times
;
382 if (instruction
->eops
->next
) {
383 base
= instruction
->eops
->next
->offset
;
385 if (instruction
->eops
->next
->next
&&
386 len
> instruction
->eops
->next
->next
->offset
)
387 len
= instruction
->eops
->next
->next
->offset
;
390 * Dummy call to list->output to give the offset to the
393 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
394 list
->uplevel(LIST_INCBIN
);
398 fseek(fp
, base
, SEEK_SET
);
402 fread(buf
, 1, (l
> (int32_t) sizeof(buf
) ? (int32_t) sizeof(buf
) : l
),
406 * This shouldn't happen unless the file
407 * actually changes while we are reading
411 "`incbin': unexpected EOF while"
412 " reading file `%s'", fname
);
413 t
= 0; /* Try to exit cleanly */
416 out(offset
, segment
, buf
, OUT_RAWDATA
, m
,
421 list
->downlevel(LIST_INCBIN
);
422 if (instruction
->times
> 1) {
424 * Dummy call to list->output to give the offset to the
427 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
428 list
->uplevel(LIST_TIMES
);
429 list
->downlevel(LIST_TIMES
);
432 return instruction
->times
* len
;
434 return 0; /* if we're here, there's an error */
437 /* Check to see if we need an address-size prefix */
438 add_asp(instruction
, bits
);
442 for (temp
= nasm_instructions
[instruction
->opcode
]; temp
->opcode
!= -1; temp
++){
443 int m
= matches(temp
, instruction
, bits
);
446 m
+= jmp_match(segment
, offset
, bits
, instruction
, temp
->code
);
448 if (m
== 100) { /* matches! */
449 const char *codes
= temp
->code
;
450 int64_t insn_size
= calcsize(segment
, offset
, bits
,
452 itimes
= instruction
->times
;
453 if (insn_size
< 0) /* shouldn't be, on pass two */
454 error(ERR_PANIC
, "errors made it through from pass one");
457 for (j
= 0; j
< MAXPREFIX
; j
++) {
459 switch (instruction
->prefixes
[j
]) {
475 "cs segment base generated, but will be ignored in 64-bit mode");
482 "ds segment base generated, but will be ignored in 64-bit mode");
489 "es segment base generated, but will be ignored in 64-bit mode");
502 "ss segment base generated, but will be ignored in 64-bit mode");
509 "segr6 and segr7 cannot be used as prefixes");
514 "16-bit addressing is not supported "
516 } else if (bits
!= 16)
526 "64-bit addressing is only supported "
550 error(ERR_PANIC
, "invalid instruction prefix");
553 out(offset
, segment
, &c
, OUT_RAWDATA
, 1,
558 insn_end
= offset
+ insn_size
;
559 gencode(segment
, offset
, bits
, instruction
, codes
,
562 if (itimes
> 0 && itimes
== instruction
->times
- 1) {
564 * Dummy call to list->output to give the offset to the
567 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
568 list
->uplevel(LIST_TIMES
);
571 if (instruction
->times
> 1)
572 list
->downlevel(LIST_TIMES
);
573 return offset
- start
;
574 } else if (m
> 0 && m
> size_prob
) {
580 if (temp
->opcode
== -1) { /* didn't match any instruction */
583 error(ERR_NONFATAL
, "operation size not specified");
586 error(ERR_NONFATAL
, "mismatch in operand sizes");
589 error(ERR_NONFATAL
, "no instruction for this cpu level");
592 error(ERR_NONFATAL
, "instruction not supported in 64-bit mode");
596 "invalid combination of opcode and operands");
603 int64_t insn_size(int32_t segment
, int64_t offset
, int bits
, uint32_t cp
,
604 insn
* instruction
, efunc error
)
606 const struct itemplate
*temp
;
608 errfunc
= error
; /* to pass to other functions */
611 if (instruction
->opcode
== -1)
614 if (instruction
->opcode
== I_DB
|| instruction
->opcode
== I_DW
||
615 instruction
->opcode
== I_DD
|| instruction
->opcode
== I_DQ
||
616 instruction
->opcode
== I_DT
|| instruction
->opcode
== I_DO
) {
618 int32_t isize
, osize
, wsize
= 0; /* placate gcc */
621 switch (instruction
->opcode
) {
644 for (e
= instruction
->eops
; e
; e
= e
->next
) {
648 if (e
->type
== EOT_DB_NUMBER
)
650 else if (e
->type
== EOT_DB_STRING
)
651 osize
= e
->stringlen
;
653 align
= (-osize
) % wsize
;
656 isize
+= osize
+ align
;
658 return isize
* instruction
->times
;
661 if (instruction
->opcode
== I_INCBIN
) {
662 char fname
[FILENAME_MAX
];
665 char *prefix
= "", *combine
;
666 char **pPrevPath
= NULL
;
668 len
= FILENAME_MAX
- 1;
669 if (len
> instruction
->eops
->stringlen
)
670 len
= instruction
->eops
->stringlen
;
671 strncpy(fname
, instruction
->eops
->stringval
, len
);
674 /* added by alexfru: 'incbin' uses include paths */
676 combine
= nasm_malloc(strlen(prefix
) + len
+ 1);
677 strcpy(combine
, prefix
);
678 strcat(combine
, fname
);
680 if ((fp
= fopen(combine
, "rb")) != NULL
) {
686 pPrevPath
= pp_get_include_path_ptr(pPrevPath
);
687 if (pPrevPath
== NULL
)
693 error(ERR_NONFATAL
, "`incbin': unable to open file `%s'",
695 else if (fseek(fp
, 0L, SEEK_END
) < 0)
696 error(ERR_NONFATAL
, "`incbin': unable to seek on file `%s'",
701 if (instruction
->eops
->next
) {
702 len
-= instruction
->eops
->next
->offset
;
703 if (instruction
->eops
->next
->next
&&
704 len
> instruction
->eops
->next
->next
->offset
) {
705 len
= instruction
->eops
->next
->next
->offset
;
708 return instruction
->times
* len
;
710 return 0; /* if we're here, there's an error */
713 /* Check to see if we need an address-size prefix */
714 add_asp(instruction
, bits
);
716 for (temp
= nasm_instructions
[instruction
->opcode
]; temp
->opcode
!= -1; temp
++) {
717 int m
= matches(temp
, instruction
, bits
);
719 m
+= jmp_match(segment
, offset
, bits
, instruction
, temp
->code
);
722 /* we've matched an instruction. */
724 const char *codes
= temp
->code
;
727 isize
= calcsize(segment
, offset
, bits
, instruction
, codes
);
730 for (j
= 0; j
< MAXPREFIX
; j
++) {
731 switch (instruction
->prefixes
[j
]) {
757 return isize
* instruction
->times
;
760 return -1; /* didn't match any instruction */
763 /* check that opn[op] is a signed byte of size 16 or 32,
764 and return the signed value*/
765 static int is_sbyte(insn
* ins
, int op
, int size
)
770 ret
= !(ins
->forw_ref
&& ins
->oprs
[op
].opflags
) && /* dead in the water on forward reference or External */
772 !(ins
->oprs
[op
].type
& STRICT
) &&
773 ins
->oprs
[op
].wrt
== NO_SEG
&& ins
->oprs
[op
].segment
== NO_SEG
;
775 v
= ins
->oprs
[op
].offset
;
777 v
= (int16_t)v
; /* sign extend if 16 bits */
779 return ret
&& v
>= -128L && v
<= 127L;
782 static int64_t calcsize(int32_t segment
, int64_t offset
, int bits
,
783 insn
* ins
, const char *codes
)
790 ins
->rex
= 0; /* Ensure REX is reset */
792 if (ins
->prefixes
[PPS_OSIZE
] == P_O64
)
795 (void)segment
; /* Don't warn that this parameter is unused */
796 (void)offset
; /* Don't warn that this parameter is unused */
800 opx
= &ins
->oprs
[c
& 3];
805 codes
+= c
, length
+= c
;
818 op_rexflags(opx
, REX_B
|REX_H
|REX_P
|REX_W
);
849 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
850 length
+= (opx
->type
& BITS16
) ? 2 : 4;
852 length
+= (bits
== 16) ? 2 : 4;
864 length
+= ins
->addr_size
>> 3;
876 length
+= 8; /* MOV reg64/imm */
888 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
889 length
+= (opx
->type
& BITS16
) ? 2 : 4;
891 length
+= (bits
== 16) ? 2 : 4;
909 length
+= is_sbyte(ins
, c
& 3, 16) ? 1 : 2;
922 length
+= is_sbyte(ins
, c
& 3, 32) ? 1 : 4;
937 ins
->drexdst
= regval(&ins
->oprs
[c
& 3]);
944 ins
->rex
|= REX_D
|REX_OC
;
945 ins
->drexdst
= regval(&ins
->oprs
[c
& 3]);
960 length
+= (bits
!= 16) && !has_prefix(ins
, PPS_ASIZE
, P_A16
);
963 length
+= (bits
!= 32) && !has_prefix(ins
, PPS_ASIZE
, P_A32
);
968 if (bits
!= 64 || has_prefix(ins
, PPS_ASIZE
, P_A16
) ||
969 has_prefix(ins
, PPS_ASIZE
, P_A32
))
978 length
+= (bits
!= 16);
981 length
+= (bits
== 16);
1008 if (ins
->oprs
[0].segment
!= NO_SEG
)
1009 errfunc(ERR_NONFATAL
, "attempt to reserve non-constant"
1010 " quantity of BSS space");
1012 length
+= ins
->oprs
[0].offset
<< (c
& 3);
1028 default: /* can't do it by 'case' statements */
1029 if (c
>= 0100 && c
<= 0277) { /* it's an EA */
1033 ea_data
.rex
= 0; /* Ensure ea.REX is initially 0 */
1036 /* pick rfield from operand b */
1037 rflags
= regflag(&ins
->oprs
[c
& 7]);
1038 rfield
= regvals
[ins
->oprs
[c
& 7].basereg
];
1045 (&ins
->oprs
[(c
>> 3) & 7], &ea_data
, bits
,
1046 ins
->addr_size
, rfield
, rflags
, ins
->forw_ref
)) {
1047 errfunc(ERR_NONFATAL
, "invalid effective address");
1050 ins
->rex
|= ea_data
.rex
;
1051 length
+= ea_data
.size
;
1054 errfunc(ERR_PANIC
, "internal instruction table corrupt"
1055 ": instruction code 0x%02X given", c
);
1060 ins
->rex
&= rex_mask
;
1062 if (ins
->rex
& REX_D
) {
1063 if (ins
->rex
& REX_H
) {
1064 errfunc(ERR_NONFATAL
, "cannot use high register in drex instruction");
1067 if (bits
!= 64 && ((ins
->rex
& (REX_W
|REX_X
|REX_B
)) ||
1068 ins
->drexdst
> 7)) {
1069 errfunc(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1073 } else if (ins
->rex
& REX_REAL
) {
1074 if (ins
->rex
& REX_H
) {
1075 errfunc(ERR_NONFATAL
, "cannot use high register in rex instruction");
1077 } else if (bits
== 64) {
1079 } else if ((ins
->rex
& REX_L
) &&
1080 !(ins
->rex
& (REX_P
|REX_W
|REX_X
|REX_B
)) &&
1083 assert_no_prefix(ins
, PPS_LREP
);
1086 errfunc(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1094 #define EMIT_REX() \
1095 if (!(ins->rex & REX_D) && (ins->rex & REX_REAL) && (bits == 64)) { \
1096 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1097 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1102 static void gencode(int32_t segment
, int64_t offset
, int bits
,
1103 insn
* ins
, const char *codes
, int64_t insn_end
)
1105 static char condval
[] = { /* conditional opcodes */
1106 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1107 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1108 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1114 struct operand
*opx
;
1118 opx
= &ins
->oprs
[c
& 3];
1124 out(offset
, segment
, codes
, OUT_RAWDATA
, c
, NO_SEG
, NO_SEG
);
1131 switch (ins
->oprs
[0].basereg
) {
1133 bytes
[0] = 0x0E + (c
== 0x04 ? 1 : 0);
1136 bytes
[0] = 0x1E + (c
== 0x04 ? 1 : 0);
1139 bytes
[0] = 0x06 + (c
== 0x04 ? 1 : 0);
1142 bytes
[0] = 0x16 + (c
== 0x04 ? 1 : 0);
1146 "bizarre 8086 segment register received");
1148 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1154 switch (ins
->oprs
[0].basereg
) {
1156 bytes
[0] = 0xA0 + (c
== 0x05 ? 1 : 0);
1159 bytes
[0] = 0xA8 + (c
== 0x05 ? 1 : 0);
1163 "bizarre 386 segment register received");
1165 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1174 bytes
[0] = *codes
++ + ((regval(opx
)) & 7);
1175 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1183 if (opx
->offset
< -128 || opx
->offset
> 127) {
1184 errfunc(ERR_WARNING
, "signed byte value exceeds bounds");
1187 if (opx
->segment
!= NO_SEG
) {
1189 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1190 opx
->segment
, opx
->wrt
);
1192 bytes
[0] = opx
->offset
;
1193 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1203 if (opx
->offset
< -256 || opx
->offset
> 255) {
1204 errfunc(ERR_WARNING
, "byte value exceeds bounds");
1206 if (opx
->segment
!= NO_SEG
) {
1208 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1209 opx
->segment
, opx
->wrt
);
1211 bytes
[0] = opx
->offset
;
1212 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1222 if (opx
->offset
< 0 || opx
->offset
> 255)
1223 errfunc(ERR_WARNING
, "unsigned byte value exceeds bounds");
1224 if (opx
->segment
!= NO_SEG
) {
1226 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1227 opx
->segment
, opx
->wrt
);
1229 bytes
[0] = opx
->offset
;
1230 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1241 if (opx
->segment
== NO_SEG
&& opx
->wrt
== NO_SEG
)
1242 warn_overflow(2, data
);
1243 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1244 opx
->segment
, opx
->wrt
);
1252 if (opx
->type
& (BITS16
| BITS32
))
1253 size
= (opx
->type
& BITS16
) ? 2 : 4;
1255 size
= (bits
== 16) ? 2 : 4;
1257 if (opx
->segment
== NO_SEG
&& opx
->wrt
== NO_SEG
)
1258 warn_overflow(size
, data
);
1259 out(offset
, segment
, &data
, OUT_ADDRESS
, size
,
1260 opx
->segment
, opx
->wrt
);
1269 out(offset
, segment
, &data
, OUT_ADDRESS
, 4,
1270 opx
->segment
, opx
->wrt
);
1279 size
= ins
->addr_size
>> 3;
1280 if (opx
->segment
== NO_SEG
&&
1282 warn_overflow(size
, data
);
1283 out(offset
, segment
, &data
, OUT_ADDRESS
, size
,
1284 opx
->segment
, opx
->wrt
);
1292 if (opx
->segment
!= segment
)
1293 errfunc(ERR_NONFATAL
,
1294 "short relative jump outside segment");
1295 data
= opx
->offset
- insn_end
;
1296 if (data
> 127 || data
< -128)
1297 errfunc(ERR_NONFATAL
, "short jump is out of range");
1299 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1307 data
= (int64_t)opx
->offset
;
1308 out(offset
, segment
, &data
, OUT_ADDRESS
, 8,
1309 opx
->segment
, opx
->wrt
);
1317 if (opx
->segment
!= segment
) {
1319 out(offset
, segment
, &data
,
1320 OUT_REL2ADR
, insn_end
- offset
,
1321 opx
->segment
, opx
->wrt
);
1323 data
= opx
->offset
- insn_end
;
1324 out(offset
, segment
, &data
,
1325 OUT_ADDRESS
, 2, NO_SEG
, NO_SEG
);
1334 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
1335 size
= (opx
->type
& BITS16
) ? 2 : 4;
1337 size
= (bits
== 16) ? 2 : 4;
1338 if (opx
->segment
!= segment
) {
1340 out(offset
, segment
, &data
,
1341 size
== 2 ? OUT_REL2ADR
: OUT_REL4ADR
,
1342 insn_end
- offset
, opx
->segment
, opx
->wrt
);
1344 data
= opx
->offset
- insn_end
;
1345 out(offset
, segment
, &data
,
1346 OUT_ADDRESS
, size
, NO_SEG
, NO_SEG
);
1355 if (opx
->segment
!= segment
) {
1357 out(offset
, segment
, &data
,
1358 OUT_REL4ADR
, insn_end
- offset
,
1359 opx
->segment
, opx
->wrt
);
1361 data
= opx
->offset
- insn_end
;
1362 out(offset
, segment
, &data
,
1363 OUT_ADDRESS
, 4, NO_SEG
, NO_SEG
);
1372 if (opx
->segment
== NO_SEG
)
1373 errfunc(ERR_NONFATAL
, "value referenced by FAR is not"
1376 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1377 outfmt
->segbase(1 + opx
->segment
),
1387 if (is_sbyte(ins
, c
& 3, 16)) {
1389 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1393 if (opx
->segment
== NO_SEG
&&
1395 warn_overflow(2, data
);
1396 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1397 opx
->segment
, opx
->wrt
);
1408 bytes
[0] = *codes
++;
1409 if (is_sbyte(ins
, c
& 3, 16))
1410 bytes
[0] |= 2; /* s-bit */
1411 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1420 if (is_sbyte(ins
, c
& 3, 32)) {
1422 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1426 out(offset
, segment
, &data
, OUT_ADDRESS
, 4,
1427 opx
->segment
, opx
->wrt
);
1438 bytes
[0] = *codes
++;
1439 if (is_sbyte(ins
, c
& 3, 32))
1440 bytes
[0] |= 2; /* s-bit */
1441 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1458 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1464 (ins
->drexdst
<< 4) |
1465 (ins
->rex
& REX_OC
? 0x08 : 0) |
1466 (ins
->rex
& (REX_R
|REX_X
|REX_B
));
1468 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1479 if (bits
== 32 && !has_prefix(ins
, PPS_ASIZE
, P_A16
)) {
1481 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1488 if (bits
!= 32 && !has_prefix(ins
, PPS_ASIZE
, P_A32
)) {
1490 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1512 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1521 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1536 *bytes
= *codes
++ ^ condval
[ins
->condition
];
1537 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1546 *bytes
= c
- 0332 + 0xF2;
1547 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1552 if (ins
->rex
& REX_R
) {
1554 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1557 ins
->rex
&= ~(REX_L
|REX_R
);
1566 if (ins
->oprs
[0].segment
!= NO_SEG
)
1567 errfunc(ERR_PANIC
, "non-constant BSS size in pass two");
1569 int64_t size
= ins
->oprs
[0].offset
<< (c
& 3);
1571 out(offset
, segment
, NULL
,
1572 OUT_RESERVE
, size
, NO_SEG
, NO_SEG
);
1583 *bytes
= c
- 0366 + 0x66;
1584 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1594 *bytes
= bits
== 16 ? 3 : 5;
1595 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1599 default: /* can't do it by 'case' statements */
1600 if (c
>= 0100 && c
<= 0277) { /* it's an EA */
1608 /* pick rfield from operand b */
1609 rflags
= regflag(&ins
->oprs
[c
& 7]);
1610 rfield
= regvals
[ins
->oprs
[c
& 7].basereg
];
1612 /* rfield is constant */
1618 (&ins
->oprs
[(c
>> 3) & 7], &ea_data
, bits
,
1619 ins
->addr_size
, rfield
, rflags
, ins
->forw_ref
)) {
1620 errfunc(ERR_NONFATAL
, "invalid effective address");
1625 *p
++ = ea_data
.modrm
;
1626 if (ea_data
.sib_present
)
1629 /* DREX suffixes come between the SIB and the displacement */
1630 if (ins
->rex
& REX_D
) {
1632 (ins
->drexdst
<< 4) |
1633 (ins
->rex
& REX_OC
? 0x08 : 0) |
1634 (ins
->rex
& (REX_R
|REX_X
|REX_B
));
1639 out(offset
, segment
, bytes
, OUT_RAWDATA
, s
, NO_SEG
, NO_SEG
);
1641 switch (ea_data
.bytes
) {
1645 if (ins
->oprs
[(c
>> 3) & 7].segment
!= NO_SEG
) {
1646 data
= ins
->oprs
[(c
>> 3) & 7].offset
;
1647 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1648 ins
->oprs
[(c
>> 3) & 7].segment
,
1649 ins
->oprs
[(c
>> 3) & 7].wrt
);
1651 *bytes
= ins
->oprs
[(c
>> 3) & 7].offset
;
1652 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1,
1660 data
= ins
->oprs
[(c
>> 3) & 7].offset
;
1661 warn_overflow(ea_data
.bytes
, data
);
1662 out(offset
, segment
, &data
,
1663 ea_data
.rip
? OUT_REL4ADR
: OUT_ADDRESS
,
1665 ins
->oprs
[(c
>> 3) & 7].segment
,
1666 ins
->oprs
[(c
>> 3) & 7].wrt
);
1672 errfunc(ERR_PANIC
, "internal instruction table corrupt"
1673 ": instruction code 0x%02X given", c
);
1679 static int32_t regflag(const operand
* o
)
1681 if (o
->basereg
< EXPR_REG_START
|| o
->basereg
>= REG_ENUM_LIMIT
) {
1682 errfunc(ERR_PANIC
, "invalid operand passed to regflag()");
1684 return reg_flags
[o
->basereg
];
1687 static int32_t regval(const operand
* o
)
1689 if (o
->basereg
< EXPR_REG_START
|| o
->basereg
>= REG_ENUM_LIMIT
) {
1690 errfunc(ERR_PANIC
, "invalid operand passed to regval()");
1692 return regvals
[o
->basereg
];
1695 static int op_rexflags(const operand
* o
, int mask
)
1700 if (o
->basereg
< EXPR_REG_START
|| o
->basereg
>= REG_ENUM_LIMIT
) {
1701 errfunc(ERR_PANIC
, "invalid operand passed to op_rexflags()");
1704 flags
= reg_flags
[o
->basereg
];
1705 val
= regvals
[o
->basereg
];
1707 return rexflags(val
, flags
, mask
);
1710 static int rexflags(int val
, int32_t flags
, int mask
)
1715 rex
|= REX_B
|REX_X
|REX_R
;
1718 if (!(REG_HIGH
& ~flags
)) /* AH, CH, DH, BH */
1720 else if (!(REG8
& ~flags
) && val
>= 4) /* SPL, BPL, SIL, DIL */
1726 static int matches(const struct itemplate
*itemp
, insn
* instruction
, int bits
)
1728 int i
, size
[MAX_OPERANDS
], asize
, oprs
, ret
;
1735 if (itemp
->opcode
!= instruction
->opcode
)
1739 * Count the operands
1741 if (itemp
->operands
!= instruction
->operands
)
1745 * Check that no spurious colons or TOs are present
1747 for (i
= 0; i
< itemp
->operands
; i
++)
1748 if (instruction
->oprs
[i
].type
& ~itemp
->opd
[i
] & (COLON
| TO
))
1752 * Check that the operand flags all match up
1754 for (i
= 0; i
< itemp
->operands
; i
++) {
1755 if (itemp
->opd
[i
] & SAME_AS
) {
1756 int j
= itemp
->opd
[i
] & ~SAME_AS
;
1757 if (instruction
->oprs
[i
].type
!= instruction
->oprs
[j
].type
||
1758 instruction
->oprs
[i
].basereg
!= instruction
->oprs
[j
].basereg
)
1760 } else if (itemp
->opd
[i
] & ~instruction
->oprs
[i
].type
||
1761 ((itemp
->opd
[i
] & SIZE_MASK
) &&
1762 ((itemp
->opd
[i
] ^ instruction
->oprs
[i
].type
) & SIZE_MASK
))) {
1763 if ((itemp
->opd
[i
] & ~instruction
->oprs
[i
].type
& ~SIZE_MASK
) ||
1764 (instruction
->oprs
[i
].type
& SIZE_MASK
))
1772 * Check operand sizes
1774 if (itemp
->flags
& IF_ARMASK
) {
1775 memset(size
, 0, sizeof size
);
1777 switch (itemp
->flags
& IF_ARMASK
) {
1791 break; /* Shouldn't happen */
1793 switch (itemp
->flags
& IF_SMASK
) {
1814 switch (itemp
->flags
& IF_SMASK
) {
1817 oprs
= itemp
->operands
;
1821 oprs
= itemp
->operands
;
1825 oprs
= itemp
->operands
;
1829 oprs
= itemp
->operands
;
1833 oprs
= itemp
->operands
;
1838 for (i
= 0; i
< MAX_OPERANDS
; i
++)
1842 if (itemp
->flags
& (IF_SM
| IF_SM2
)) {
1843 oprs
= (itemp
->flags
& IF_SM2
? 2 : itemp
->operands
);
1845 for (i
= 0; i
< oprs
; i
++) {
1846 if ((asize
= itemp
->opd
[i
] & SIZE_MASK
) != 0) {
1848 for (j
= 0; j
< oprs
; j
++)
1854 oprs
= itemp
->operands
;
1857 for (i
= 0; i
< itemp
->operands
; i
++) {
1858 if (!(itemp
->opd
[i
] & SIZE_MASK
) &&
1859 (instruction
->oprs
[i
].type
& SIZE_MASK
& ~size
[i
]))
1864 * Check template is okay at the set cpu level
1866 if (((itemp
->flags
& IF_PLEVEL
) > cpu
))
1870 * Check if instruction is available in long mode
1872 if ((itemp
->flags
& IF_NOLONG
) && (bits
== 64))
1876 * Check if special handling needed for Jumps
1878 if ((uint8_t)(itemp
->code
[0]) >= 0370)
1884 static ea
*process_ea(operand
* input
, ea
* output
, int bits
,
1885 int addrbits
, int rfield
, int32_t rflags
, int forw_ref
)
1887 output
->rip
= false;
1889 /* REX flags for the rfield operand */
1890 output
->rex
|= rexflags(rfield
, rflags
, REX_R
|REX_P
|REX_W
|REX_H
);
1892 if (!(REGISTER
& ~input
->type
)) { /* register direct */
1896 if (input
->basereg
< EXPR_REG_START
/* Verify as Register */
1897 || input
->basereg
>= REG_ENUM_LIMIT
)
1900 i
= regvals
[input
->basereg
];
1903 return NULL
; /* Invalid EA register */
1905 output
->rex
|= op_rexflags(input
, REX_B
|REX_P
|REX_W
|REX_H
);
1907 output
->sib_present
= false; /* no SIB necessary */
1908 output
->bytes
= 0; /* no offset necessary either */
1909 output
->modrm
= 0xC0 | ((rfield
& 7) << 3) | (i
& 7);
1910 } else { /* it's a memory reference */
1911 if (input
->basereg
== -1
1912 && (input
->indexreg
== -1 || input
->scale
== 0)) {
1913 /* it's a pure offset */
1914 if (bits
== 64 && (~input
->type
& IP_REL
)) {
1915 int scale
, index
, base
;
1916 output
->sib_present
= true;
1920 output
->sib
= (scale
<< 6) | (index
<< 3) | base
;
1922 output
->modrm
= 4 | ((rfield
& 7) << 3);
1923 output
->rip
= false;
1925 output
->sib_present
= false;
1926 output
->bytes
= (addrbits
!= 16 ? 4 : 2);
1927 output
->modrm
= (addrbits
!= 16 ? 5 : 6) | ((rfield
& 7) << 3);
1928 output
->rip
= bits
== 64;
1930 } else { /* it's an indirection */
1931 int i
= input
->indexreg
, b
= input
->basereg
, s
= input
->scale
;
1932 int32_t o
= input
->offset
, seg
= input
->segment
;
1933 int hb
= input
->hintbase
, ht
= input
->hinttype
;
1936 int32_t ix
, bx
; /* register flags */
1939 i
= -1; /* make this easy, at least */
1941 if (i
>= EXPR_REG_START
&& i
< REG_ENUM_LIMIT
) {
1949 if (b
>= EXPR_REG_START
&& b
< REG_ENUM_LIMIT
) {
1957 /* check for a 32/64-bit memory reference... */
1958 if ((ix
|bx
) & (BITS32
|BITS64
)) {
1959 /* it must be a 32/64-bit memory reference. Firstly we have
1960 * to check that all registers involved are type E/Rxx. */
1961 int32_t sok
= BITS32
|BITS64
;
1964 if (!(REG64
& ~ix
) || !(REG32
& ~ix
))
1972 return NULL
; /* Invalid register */
1973 if (~sok
& bx
& SIZE_MASK
)
1974 return NULL
; /* Invalid size */
1978 /* While we're here, ensure the user didn't specify
1980 if (input
->disp_size
== 16 || input
->disp_size
== 64)
1983 if (addrbits
== 16 ||
1984 (addrbits
== 32 && !(sok
& BITS32
)) ||
1985 (addrbits
== 64 && !(sok
& BITS64
)))
1988 /* now reorganize base/index */
1989 if (s
== 1 && bt
!= it
&& bt
!= -1 && it
!= -1 &&
1990 ((hb
== b
&& ht
== EAH_NOTBASE
)
1991 || (hb
== i
&& ht
== EAH_MAKEBASE
))) {
1992 /* swap if hints say so */
1993 t
= bt
, bt
= it
, it
= t
;
1994 t
= bx
, bx
= ix
, ix
= t
;
1996 if (bt
== it
) /* convert EAX+2*EAX to 3*EAX */
1997 bt
= -1, bx
= 0, s
++;
1998 if (bt
== -1 && s
== 1 && !(hb
== it
&& ht
== EAH_NOTBASE
)) {
1999 /* make single reg base, unless hint */
2000 bt
= it
, bx
= ix
, it
= -1, ix
= 0;
2002 if (((s
== 2 && it
!= REG_NUM_ESP
2003 && !(input
->eaflags
& EAF_TIMESTWO
)) || s
== 3
2004 || s
== 5 || s
== 9) && bt
== -1)
2005 bt
= it
, bx
= ix
, s
--; /* convert 3*EAX to EAX+2*EAX */
2006 if (it
== -1 && (bt
& 7) != REG_NUM_ESP
2007 && (input
->eaflags
& EAF_TIMESTWO
))
2008 it
= bt
, ix
= bx
, bt
= -1, bx
= 0, s
= 1;
2009 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2010 if (s
== 1 && it
== REG_NUM_ESP
) {
2011 /* swap ESP into base if scale is 1 */
2012 t
= it
, it
= bt
, bt
= t
;
2013 t
= ix
, ix
= bx
, bx
= t
;
2015 if (it
== REG_NUM_ESP
2016 || (s
!= 1 && s
!= 2 && s
!= 4 && s
!= 8 && it
!= -1))
2017 return NULL
; /* wrong, for various reasons */
2019 output
->rex
|= rexflags(it
, ix
, REX_X
);
2020 output
->rex
|= rexflags(bt
, bx
, REX_B
);
2022 if (it
== -1 && (bt
& 7) != REG_NUM_ESP
) {
2031 if (rm
!= REG_NUM_EBP
&& o
== 0 &&
2032 seg
== NO_SEG
&& !forw_ref
&&
2034 (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2036 else if (input
->eaflags
& EAF_BYTEOFFS
||
2037 (o
>= -128 && o
<= 127 && seg
== NO_SEG
2039 && !(input
->eaflags
& EAF_WORDOFFS
)))
2045 output
->sib_present
= false;
2046 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2047 output
->modrm
= (mod
<< 6) | ((rfield
& 7) << 3) | rm
;
2050 int mod
, scale
, index
, base
;
2070 default: /* then what the smeg is it? */
2071 return NULL
; /* panic */
2079 if (base
!= REG_NUM_EBP
&& o
== 0 &&
2080 seg
== NO_SEG
&& !forw_ref
&&
2082 (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2084 else if (input
->eaflags
& EAF_BYTEOFFS
||
2085 (o
>= -128 && o
<= 127 && seg
== NO_SEG
2087 && !(input
->eaflags
& EAF_WORDOFFS
)))
2093 output
->sib_present
= true;
2094 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2095 output
->modrm
= (mod
<< 6) | ((rfield
& 7) << 3) | 4;
2096 output
->sib
= (scale
<< 6) | (index
<< 3) | base
;
2098 } else { /* it's 16-bit */
2101 /* check for 64-bit long mode */
2105 /* check all registers are BX, BP, SI or DI */
2106 if ((b
!= -1 && b
!= R_BP
&& b
!= R_BX
&& b
!= R_SI
2107 && b
!= R_DI
) || (i
!= -1 && i
!= R_BP
&& i
!= R_BX
2108 && i
!= R_SI
&& i
!= R_DI
))
2111 /* ensure the user didn't specify DWORD/QWORD */
2112 if (input
->disp_size
== 32 || input
->disp_size
== 64)
2115 if (s
!= 1 && i
!= -1)
2116 return NULL
; /* no can do, in 16-bit EA */
2117 if (b
== -1 && i
!= -1) {
2122 if ((b
== R_SI
|| b
== R_DI
) && i
!= -1) {
2127 /* have BX/BP as base, SI/DI index */
2129 return NULL
; /* shouldn't ever happen, in theory */
2130 if (i
!= -1 && b
!= -1 &&
2131 (i
== R_BP
|| i
== R_BX
|| b
== R_SI
|| b
== R_DI
))
2132 return NULL
; /* invalid combinations */
2133 if (b
== -1) /* pure offset: handled above */
2134 return NULL
; /* so if it gets to here, panic! */
2138 switch (i
* 256 + b
) {
2139 case R_SI
* 256 + R_BX
:
2142 case R_DI
* 256 + R_BX
:
2145 case R_SI
* 256 + R_BP
:
2148 case R_DI
* 256 + R_BP
:
2166 if (rm
== -1) /* can't happen, in theory */
2167 return NULL
; /* so panic if it does */
2169 if (o
== 0 && seg
== NO_SEG
&& !forw_ref
&& rm
!= 6 &&
2170 !(input
->eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2172 else if (input
->eaflags
& EAF_BYTEOFFS
||
2173 (o
>= -128 && o
<= 127 && seg
== NO_SEG
2175 && !(input
->eaflags
& EAF_WORDOFFS
)))
2180 output
->sib_present
= false; /* no SIB - it's 16-bit */
2181 output
->bytes
= mod
; /* bytes of offset needed */
2182 output
->modrm
= (mod
<< 6) | ((rfield
& 7) << 3) | rm
;
2187 output
->size
= 1 + output
->sib_present
+ output
->bytes
;
2191 static void add_asp(insn
*ins
, int addrbits
)
2196 valid
= (addrbits
== 64) ? 64|32 : 32|16;
2198 switch (ins
->prefixes
[PPS_ASIZE
]) {
2209 valid
&= (addrbits
== 32) ? 16 : 32;
2215 for (j
= 0; j
< ins
->operands
; j
++) {
2216 if (!(MEMORY
& ~ins
->oprs
[j
].type
)) {
2219 /* Verify as Register */
2220 if (ins
->oprs
[j
].indexreg
< EXPR_REG_START
2221 || ins
->oprs
[j
].indexreg
>= REG_ENUM_LIMIT
)
2224 i
= reg_flags
[ins
->oprs
[j
].indexreg
];
2226 /* Verify as Register */
2227 if (ins
->oprs
[j
].basereg
< EXPR_REG_START
2228 || ins
->oprs
[j
].basereg
>= REG_ENUM_LIMIT
)
2231 b
= reg_flags
[ins
->oprs
[j
].basereg
];
2233 if (ins
->oprs
[j
].scale
== 0)
2237 int ds
= ins
->oprs
[j
].disp_size
;
2238 if ((addrbits
!= 64 && ds
> 8) ||
2239 (addrbits
== 64 && ds
== 16))
2259 if (valid
& addrbits
) {
2260 ins
->addr_size
= addrbits
;
2261 } else if (valid
& ((addrbits
== 32) ? 16 : 32)) {
2262 /* Add an address size prefix */
2263 enum prefixes pref
= (addrbits
== 32) ? P_A16
: P_A32
;
2264 ins
->prefixes
[PPS_ASIZE
] = pref
;
2265 ins
->addr_size
= (addrbits
== 32) ? 16 : 32;
2268 errfunc(ERR_NONFATAL
, "impossible combination of address sizes");
2269 ins
->addr_size
= addrbits
; /* Error recovery */
2272 defdisp
= ins
->addr_size
== 16 ? 16 : 32;
2274 for (j
= 0; j
< ins
->operands
; j
++) {
2275 if (!(MEM_OFFS
& ~ins
->oprs
[j
].type
) &&
2276 (ins
->oprs
[j
].disp_size
? ins
->oprs
[j
].disp_size
: defdisp
)
2277 != ins
->addr_size
) {
2278 /* mem_offs sizes must match the address size; if not,
2279 strip the MEM_OFFS bit and match only EA instructions */
2280 ins
->oprs
[j
].type
&= ~(MEM_OFFS
& ~MEMORY
);