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NASM 2.02rc2
[nasm.git] / assemble.c
blob681af699ac31edc8046848e1cfb67884993620bd
1 /* assemble.c code generation for the Netwide Assembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
7 *
8 * the actual codes (C syntax, i.e. octal):
9 * \0 - terminates the code. (Unless it's a literal of course.)
10 * \1, \2, \3 - that many literal bytes follow in the code stream
11 * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
12 * (POP is never used for CS) depending on operand 0
13 * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
14 * on operand 0
15 * \10..\13 - a literal byte follows in the code stream, to be added
16 * to the register value of operand 0..3
17 * \14..\17 - a signed byte immediate operand, from operand 0..3
18 * \20..\23 - a byte immediate operand, from operand 0..3
19 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
20 * \30..\33 - a word immediate operand, from operand 0..3
21 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
22 * assembly mode or the operand-size override on the operand
23 * \40..\43 - a long immediate operand, from operand 0..3
24 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
25 * depending on the address size of the instruction.
26 * \50..\53 - a byte relative operand, from operand 0..3
27 * \54..\57 - a qword immediate operand, from operand 0..3
28 * \60..\63 - a word relative operand, from operand 0..3
29 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
30 * assembly mode or the operand-size override on the operand
31 * \70..\73 - a long relative operand, from operand 0..3
32 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
33 * \1ab - a ModRM, calculated on EA in operand a, with the spare
34 * field the register value of operand b.
35 * \140..\143 - an immediate word or signed byte for operand 0..3
36 * \144..\147 - or 2 (s-field) into opcode byte if operand 0..3
37 * is a signed byte rather than a word. Opcode byte follows.
38 * \150..\153 - an immediate dword or signed byte for operand 0..3
39 * \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
40 * is a signed byte rather than a word. Opcode byte follows.
41 * \160..\163 - this instruction uses DREX rather than REX, with the
42 * OC0 field set to 0, and the dest field taken from
43 * operand 0..3.
44 * \164..\167 - this instruction uses DREX rather than REX, with the
45 * OC0 field set to 1, and the dest field taken from
46 * operand 0..3.
47 * \170 - encodes the literal byte 0. (Some compilers don't take
48 * kindly to a zero byte in the _middle_ of a compile time
49 * string constant, so I had to put this hack in.)
50 * \171 - placement of DREX suffix in the absence of an EA
51 * \2ab - a ModRM, calculated on EA in operand a, with the spare
52 * field equal to digit b.
53 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
54 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
55 * \312 - (disassembler only) marker on LOOP, LOOPxx instructions.
56 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
57 * \314 - (disassembler only) invalid with REX.B
58 * \315 - (disassembler only) invalid with REX.X
59 * \316 - (disassembler only) invalid with REX.R
60 * \317 - (disassembler only) invalid with REX.W
61 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
62 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
63 * \322 - indicates that this instruction is only valid when the
64 * operand size is the default (instruction to disassembler,
65 * generates no code in the assembler)
66 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
67 * \324 - indicates 64-bit operand size requiring REX prefix.
68 * \330 - a literal byte follows in the code stream, to be added
69 * to the condition code value of the instruction.
70 * \331 - instruction not valid with REP prefix. Hint for
71 * disassembler only; for SSE instructions.
72 * \332 - REP prefix (0xF2 byte) used as opcode extension.
73 * \333 - REP prefix (0xF3 byte) used as opcode extension.
74 * \334 - LOCK prefix used instead of REX.R
75 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
76 * \340 - reserve <operand 0> bytes of uninitialized storage.
77 * Operand 0 had better be a segmentless constant.
78 * \364 - operand-size prefix (0x66) not permitted
79 * \365 - address-size prefix (0x67) not permitted
80 * \366 - operand-size prefix (0x66) used as opcode extension
81 * \367 - address-size prefix (0x67) used as opcode extension
82 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
83 * 370 is used for Jcc, 371 is used for JMP.
84 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
85 * used for conditional jump over longer jump
86 */
87
88 #include "compiler.h"
89
90 #include <stdio.h>
91 #include <string.h>
92 #include <inttypes.h>
93
94 #include "nasm.h"
95 #include "nasmlib.h"
96 #include "assemble.h"
97 #include "insns.h"
98 #include "preproc.h"
99 #include "regflags.c"
100 #include "regvals.c"
101
102 typedef struct {
103 int sib_present; /* is a SIB byte necessary? */
104 int bytes; /* # of bytes of offset needed */
105 int size; /* lazy - this is sib+bytes+1 */
106 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
107 } ea;
108
109 static uint32_t cpu; /* cpu level received from nasm.c */
110 static efunc errfunc;
111 static struct ofmt *outfmt;
112 static ListGen *list;
113
114 static int64_t calcsize(int32_t, int64_t, int, insn *, const char *);
115 static void gencode(int32_t, int64_t, int, insn *, const char *, int64_t);
116 static int matches(const struct itemplate *, insn *, int bits);
117 static int32_t regflag(const operand *);
118 static int32_t regval(const operand *);
119 static int rexflags(int, int32_t, int);
120 static int op_rexflags(const operand *, int);
121 static ea *process_ea(operand *, ea *, int, int, int, int32_t, int);
122 static void add_asp(insn *, int);
123
124 static int has_prefix(insn * ins, enum prefix_pos pos, enum prefixes prefix)
125 {
126 return ins->prefixes[pos] == prefix;
127 }
128
129 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
130 {
131 if (ins->prefixes[pos])
132 errfunc(ERR_NONFATAL, "invalid %s prefix",
133 prefix_name(ins->prefixes[pos]));
134 }
135
136 static const char *size_name(int size)
137 {
138 switch (size) {
139 case 1:
140 return "byte";
141 case 2:
142 return "word";
143 case 4:
144 return "dword";
145 case 8:
146 return "qword";
147 case 10:
148 return "tword";
149 case 16:
150 return "oword";
151 default:
152 return "???";
153 }
154 }
155
156 static void warn_overflow(int size, int64_t data)
157 {
158 if (size < 8) {
159 int64_t lim = ((int64_t)1 << (size*8))-1;
160
161 if (data < ~lim || data > lim)
162 errfunc(ERR_WARNING | ERR_WARN_NOV, "%s data exceeds bounds", size_name(size));
163 }
164 }
165 /*
166 * This routine wrappers the real output format's output routine,
167 * in order to pass a copy of the data off to the listing file
168 * generator at the same time.
169 */
170 static void out(int64_t offset, int32_t segto, const void *data,
171 enum out_type type, uint64_t size,
172 int32_t segment, int32_t wrt)
173 {
174 static int32_t lineno = 0; /* static!!! */
175 static char *lnfname = NULL;
176 uint8_t p[8];
177
178 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
179 /*
180 * This is a non-relocated address, and we're going to
181 * convert it into RAWDATA format.
182 */
183 uint8_t *q = p;
184
185 if (size > 8) {
186 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
187 return;
188 }
189
190 WRITEADDR(q, *(int64_t *)data, size);
191 data = p;
192 type = OUT_RAWDATA;
193 }
194
195 list->output(offset, data, type, size);
196
197 /*
198 * this call to src_get determines when we call the
199 * debug-format-specific "linenum" function
200 * it updates lineno and lnfname to the current values
201 * returning 0 if "same as last time", -2 if lnfname
202 * changed, and the amount by which lineno changed,
203 * if it did. thus, these variables must be static
204 */
205
206 if (src_get(&lineno, &lnfname)) {
207 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
208 }
209
210 outfmt->output(segto, data, type, size, segment, wrt);
211 }
212
213 static int jmp_match(int32_t segment, int64_t offset, int bits,
214 insn * ins, const char *code)
215 {
216 int64_t isize;
217 uint8_t c = code[0];
218
219 if (c != 0370 && c != 0371)
220 return 0;
221 if (ins->oprs[0].opflags & OPFLAG_FORWARD) {
222 if ((optimizing < 0 || (ins->oprs[0].type & STRICT))
223 && c == 0370)
224 return 1;
225 else
226 return (pass0 == 0); /* match a forward reference */
227 }
228 isize = calcsize(segment, offset, bits, ins, code);
229 if (ins->oprs[0].segment != segment)
230 return 0;
231 isize = ins->oprs[0].offset - offset - isize; /* isize is now the delta */
232 if (isize >= -128L && isize <= 127L)
233 return 1; /* it is byte size */
234
235 return 0;
236 }
237
238 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
239 insn * instruction, struct ofmt *output, efunc error,
240 ListGen * listgen)
241 {
242 const struct itemplate *temp;
243 int j;
244 int size_prob;
245 int64_t insn_end;
246 int32_t itimes;
247 int64_t start = offset;
248 int64_t wsize = 0; /* size for DB etc. */
249
250 errfunc = error; /* to pass to other functions */
251 cpu = cp;
252 outfmt = output; /* likewise */
253 list = listgen; /* and again */
254
255 switch (instruction->opcode) {
256 case -1:
257 return 0;
258 case I_DB:
259 wsize = 1;
260 break;
261 case I_DW:
262 wsize = 2;
263 break;
264 case I_DD:
265 wsize = 4;
266 break;
267 case I_DQ:
268 wsize = 8;
269 break;
270 case I_DT:
271 wsize = 10;
272 break;
273 case I_DO:
274 wsize = 16;
275 break;
276 default:
277 break;
278 }
279
280 if (wsize) {
281 extop *e;
282 int32_t t = instruction->times;
283 if (t < 0)
284 errfunc(ERR_PANIC,
285 "instruction->times < 0 (%ld) in assemble()", t);
286
287 while (t--) { /* repeat TIMES times */
288 for (e = instruction->eops; e; e = e->next) {
289 if (e->type == EOT_DB_NUMBER) {
290 if (wsize == 1) {
291 if (e->segment != NO_SEG)
292 errfunc(ERR_NONFATAL,
293 "one-byte relocation attempted");
294 else {
295 uint8_t out_byte = e->offset;
296 out(offset, segment, &out_byte,
297 OUT_RAWDATA, 1, NO_SEG, NO_SEG);
298 }
299 } else if (wsize > 8) {
300 errfunc(ERR_NONFATAL, "integer supplied to a DT or DO"
301 " instruction");
302 } else
303 out(offset, segment, &e->offset,
304 OUT_ADDRESS, wsize, e->segment, e->wrt);
305 offset += wsize;
306 } else if (e->type == EOT_DB_STRING) {
307 int align;
308
309 out(offset, segment, e->stringval,
310 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
311 align = e->stringlen % wsize;
312
313 if (align) {
314 align = wsize - align;
315 out(offset, segment,
316 "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0",
317 OUT_RAWDATA, align, NO_SEG, NO_SEG);
318 }
319 offset += e->stringlen + align;
320 }
321 }
322 if (t > 0 && t == instruction->times - 1) {
323 /*
324 * Dummy call to list->output to give the offset to the
325 * listing module.
326 */
327 list->output(offset, NULL, OUT_RAWDATA, 0);
328 list->uplevel(LIST_TIMES);
329 }
330 }
331 if (instruction->times > 1)
332 list->downlevel(LIST_TIMES);
333 return offset - start;
334 }
335
336 if (instruction->opcode == I_INCBIN) {
337 static char fname[FILENAME_MAX];
338 FILE *fp;
339 int32_t len;
340 char *prefix = "", *combine;
341 char **pPrevPath = NULL;
342
343 len = FILENAME_MAX - 1;
344 if (len > instruction->eops->stringlen)
345 len = instruction->eops->stringlen;
346 strncpy(fname, instruction->eops->stringval, len);
347 fname[len] = '\0';
348
349 while (1) { /* added by alexfru: 'incbin' uses include paths */
350 combine = nasm_malloc(strlen(prefix) + len + 1);
351 strcpy(combine, prefix);
352 strcat(combine, fname);
353
354 if ((fp = fopen(combine, "rb")) != NULL) {
355 nasm_free(combine);
356 break;
357 }
358
359 nasm_free(combine);
360 pPrevPath = pp_get_include_path_ptr(pPrevPath);
361 if (pPrevPath == NULL)
362 break;
363 prefix = *pPrevPath;
364 }
365
366 if (fp == NULL)
367 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
368 fname);
369 else if (fseek(fp, 0L, SEEK_END) < 0)
370 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
371 fname);
372 else {
373 static char buf[2048];
374 int32_t t = instruction->times;
375 int32_t base = 0;
376
377 len = ftell(fp);
378 if (instruction->eops->next) {
379 base = instruction->eops->next->offset;
380 len -= base;
381 if (instruction->eops->next->next &&
382 len > instruction->eops->next->next->offset)
383 len = instruction->eops->next->next->offset;
384 }
385 /*
386 * Dummy call to list->output to give the offset to the
387 * listing module.
388 */
389 list->output(offset, NULL, OUT_RAWDATA, 0);
390 list->uplevel(LIST_INCBIN);
391 while (t--) {
392 int32_t l;
393
394 fseek(fp, base, SEEK_SET);
395 l = len;
396 while (l > 0) {
397 int32_t m =
398 fread(buf, 1, (l > (int32_t) sizeof(buf) ? (int32_t) sizeof(buf) : l),
399 fp);
400 if (!m) {
401 /*
402 * This shouldn't happen unless the file
403 * actually changes while we are reading
404 * it.
405 */
406 error(ERR_NONFATAL,
407 "`incbin': unexpected EOF while"
408 " reading file `%s'", fname);
409 t = 0; /* Try to exit cleanly */
410 break;
411 }
412 out(offset, segment, buf, OUT_RAWDATA, m,
413 NO_SEG, NO_SEG);
414 l -= m;
415 }
416 }
417 list->downlevel(LIST_INCBIN);
418 if (instruction->times > 1) {
419 /*
420 * Dummy call to list->output to give the offset to the
421 * listing module.
422 */
423 list->output(offset, NULL, OUT_RAWDATA, 0);
424 list->uplevel(LIST_TIMES);
425 list->downlevel(LIST_TIMES);
426 }
427 fclose(fp);
428 return instruction->times * len;
429 }
430 return 0; /* if we're here, there's an error */
431 }
432
433 /* Check to see if we need an address-size prefix */
434 add_asp(instruction, bits);
435
436 size_prob = false;
437
438 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++){
439 int m = matches(temp, instruction, bits);
440
441 if (m == 99)
442 m += jmp_match(segment, offset, bits, instruction, temp->code);
443
444 if (m == 100) { /* matches! */
445 const char *codes = temp->code;
446 int64_t insn_size = calcsize(segment, offset, bits,
447 instruction, codes);
448 itimes = instruction->times;
449 if (insn_size < 0) /* shouldn't be, on pass two */
450 error(ERR_PANIC, "errors made it through from pass one");
451 else
452 while (itimes--) {
453 for (j = 0; j < MAXPREFIX; j++) {
454 uint8_t c = 0;
455 switch (instruction->prefixes[j]) {
456 case P_LOCK:
457 c = 0xF0;
458 break;
459 case P_REPNE:
460 case P_REPNZ:
461 c = 0xF2;
462 break;
463 case P_REPE:
464 case P_REPZ:
465 case P_REP:
466 c = 0xF3;
467 break;
468 case R_CS:
469 if (bits == 64) {
470 error(ERR_WARNING,
471 "cs segment base generated, but will be ignored in 64-bit mode");
472 }
473 c = 0x2E;
474 break;
475 case R_DS:
476 if (bits == 64) {
477 error(ERR_WARNING,
478 "ds segment base generated, but will be ignored in 64-bit mode");
479 }
480 c = 0x3E;
481 break;
482 case R_ES:
483 if (bits == 64) {
484 error(ERR_WARNING,
485 "es segment base generated, but will be ignored in 64-bit mode");
486 }
487 c = 0x26;
488 break;
489 case R_FS:
490 c = 0x64;
491 break;
492 case R_GS:
493 c = 0x65;
494 break;
495 case R_SS:
496 if (bits == 64) {
497 error(ERR_WARNING,
498 "ss segment base generated, but will be ignored in 64-bit mode");
499 }
500 c = 0x36;
501 break;
502 case R_SEGR6:
503 case R_SEGR7:
504 error(ERR_NONFATAL,
505 "segr6 and segr7 cannot be used as prefixes");
506 break;
507 case P_A16:
508 if (bits == 64) {
509 error(ERR_NONFATAL,
510 "16-bit addressing is not supported "
511 "in 64-bit mode");
512 } else if (bits != 16)
513 c = 0x67;
514 break;
515 case P_A32:
516 if (bits != 32)
517 c = 0x67;
518 break;
519 case P_A64:
520 if (bits != 64) {
521 error(ERR_NONFATAL,
522 "64-bit addressing is only supported "
523 "in 64-bit mode");
524 }
525 break;
526 case P_ASP:
527 c = 0x67;
528 break;
529 case P_O16:
530 if (bits != 16)
531 c = 0x66;
532 break;
533 case P_O32:
534 if (bits == 16)
535 c = 0x66;
536 break;
537 case P_O64:
538 /* REX.W */
539 break;
540 case P_OSP:
541 c = 0x66;
542 break;
543 case P_none:
544 break;
545 default:
546 error(ERR_PANIC, "invalid instruction prefix");
547 }
548 if (c != 0) {
549 out(offset, segment, &c, OUT_RAWDATA, 1,
550 NO_SEG, NO_SEG);
551 offset++;
552 }
553 }
554 insn_end = offset + insn_size;
555 gencode(segment, offset, bits, instruction, codes,
556 insn_end);
557 offset += insn_size;
558 if (itimes > 0 && itimes == instruction->times - 1) {
559 /*
560 * Dummy call to list->output to give the offset to the
561 * listing module.
562 */
563 list->output(offset, NULL, OUT_RAWDATA, 0);
564 list->uplevel(LIST_TIMES);
565 }
566 }
567 if (instruction->times > 1)
568 list->downlevel(LIST_TIMES);
569 return offset - start;
570 } else if (m > 0 && m > size_prob) {
571 size_prob = m;
572 }
573 // temp++;
574 }
575
576 if (temp->opcode == -1) { /* didn't match any instruction */
577 switch (size_prob) {
578 case 1:
579 error(ERR_NONFATAL, "operation size not specified");
580 break;
581 case 2:
582 error(ERR_NONFATAL, "mismatch in operand sizes");
583 break;
584 case 3:
585 error(ERR_NONFATAL, "no instruction for this cpu level");
586 break;
587 case 4:
588 error(ERR_NONFATAL, "instruction not supported in 64-bit mode");
589 break;
590 default:
591 error(ERR_NONFATAL,
592 "invalid combination of opcode and operands");
593 break;
594 }
595 }
596 return 0;
597 }
598
599 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
600 insn * instruction, efunc error)
601 {
602 const struct itemplate *temp;
603
604 errfunc = error; /* to pass to other functions */
605 cpu = cp;
606
607 if (instruction->opcode == -1)
608 return 0;
609
610 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
611 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
612 instruction->opcode == I_DT || instruction->opcode == I_DO) {
613 extop *e;
614 int32_t isize, osize, wsize = 0; /* placate gcc */
615
616 isize = 0;
617 switch (instruction->opcode) {
618 case I_DB:
619 wsize = 1;
620 break;
621 case I_DW:
622 wsize = 2;
623 break;
624 case I_DD:
625 wsize = 4;
626 break;
627 case I_DQ:
628 wsize = 8;
629 break;
630 case I_DT:
631 wsize = 10;
632 break;
633 case I_DO:
634 wsize = 16;
635 break;
636 default:
637 break;
638 }
639
640 for (e = instruction->eops; e; e = e->next) {
641 int32_t align;
642
643 osize = 0;
644 if (e->type == EOT_DB_NUMBER)
645 osize = 1;
646 else if (e->type == EOT_DB_STRING)
647 osize = e->stringlen;
648
649 align = (-osize) % wsize;
650 if (align < 0)
651 align += wsize;
652 isize += osize + align;
653 }
654 return isize * instruction->times;
655 }
656
657 if (instruction->opcode == I_INCBIN) {
658 char fname[FILENAME_MAX];
659 FILE *fp;
660 int32_t len;
661 char *prefix = "", *combine;
662 char **pPrevPath = NULL;
663
664 len = FILENAME_MAX - 1;
665 if (len > instruction->eops->stringlen)
666 len = instruction->eops->stringlen;
667 strncpy(fname, instruction->eops->stringval, len);
668 fname[len] = '\0';
669
670 /* added by alexfru: 'incbin' uses include paths */
671 while (1) {
672 combine = nasm_malloc(strlen(prefix) + len + 1);
673 strcpy(combine, prefix);
674 strcat(combine, fname);
675
676 if ((fp = fopen(combine, "rb")) != NULL) {
677 nasm_free(combine);
678 break;
679 }
680
681 nasm_free(combine);
682 pPrevPath = pp_get_include_path_ptr(pPrevPath);
683 if (pPrevPath == NULL)
684 break;
685 prefix = *pPrevPath;
686 }
687
688 if (fp == NULL)
689 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
690 fname);
691 else if (fseek(fp, 0L, SEEK_END) < 0)
692 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
693 fname);
694 else {
695 len = ftell(fp);
696 fclose(fp);
697 if (instruction->eops->next) {
698 len -= instruction->eops->next->offset;
699 if (instruction->eops->next->next &&
700 len > instruction->eops->next->next->offset) {
701 len = instruction->eops->next->next->offset;
702 }
703 }
704 return instruction->times * len;
705 }
706 return 0; /* if we're here, there's an error */
707 }
708
709 /* Check to see if we need an address-size prefix */
710 add_asp(instruction, bits);
711
712 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++) {
713 int m = matches(temp, instruction, bits);
714 if (m == 99)
715 m += jmp_match(segment, offset, bits, instruction, temp->code);
716
717 if (m == 100) {
718 /* we've matched an instruction. */
719 int64_t isize;
720 const char *codes = temp->code;
721 int j;
722
723 isize = calcsize(segment, offset, bits, instruction, codes);
724 if (isize < 0)
725 return -1;
726 for (j = 0; j < MAXPREFIX; j++) {
727 switch (instruction->prefixes[j]) {
728 case P_A16:
729 if (bits != 16)
730 isize++;
731 break;
732 case P_A32:
733 if (bits != 32)
734 isize++;
735 break;
736 case P_O16:
737 if (bits != 16)
738 isize++;
739 break;
740 case P_O32:
741 if (bits == 16)
742 isize++;
743 break;
744 case P_A64:
745 case P_O64:
746 case P_none:
747 break;
748 default:
749 isize++;
750 break;
751 }
752 }
753 return isize * instruction->times;
754 }
755 }
756 return -1; /* didn't match any instruction */
757 }
758
759 /* check that opn[op] is a signed byte of size 16 or 32,
760 and return the signed value*/
761 static int is_sbyte(insn * ins, int op, int size)
762 {
763 int32_t v;
764 int ret;
765
766 ret = !(ins->forw_ref && ins->oprs[op].opflags) && /* dead in the water on forward reference or External */
767 optimizing >= 0 &&
768 !(ins->oprs[op].type & STRICT) &&
769 ins->oprs[op].wrt == NO_SEG && ins->oprs[op].segment == NO_SEG;
770
771 v = ins->oprs[op].offset;
772 if (size == 16)
773 v = (int16_t)v; /* sign extend if 16 bits */
774
775 return ret && v >= -128L && v <= 127L;
776 }
777
778 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
779 insn * ins, const char *codes)
780 {
781 int64_t length = 0;
782 uint8_t c;
783 int rex_mask = ~0;
784 struct operand *opx;
785
786 ins->rex = 0; /* Ensure REX is reset */
787
788 if (ins->prefixes[PPS_OSIZE] == P_O64)
789 ins->rex |= REX_W;
790
791 (void)segment; /* Don't warn that this parameter is unused */
792 (void)offset; /* Don't warn that this parameter is unused */
793
794 while (*codes) {
795 c = *codes++;
796 opx = &ins->oprs[c & 3];
797 switch (c) {
798 case 01:
799 case 02:
800 case 03:
801 codes += c, length += c;
802 break;
803 case 04:
804 case 05:
805 case 06:
806 case 07:
807 length++;
808 break;
809 case 010:
810 case 011:
811 case 012:
812 case 013:
813 ins->rex |=
814 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
815 codes++, length++;
816 break;
817 case 014:
818 case 015:
819 case 016:
820 case 017:
821 length++;
822 break;
823 case 020:
824 case 021:
825 case 022:
826 case 023:
827 length++;
828 break;
829 case 024:
830 case 025:
831 case 026:
832 case 027:
833 length++;
834 break;
835 case 030:
836 case 031:
837 case 032:
838 case 033:
839 length += 2;
840 break;
841 case 034:
842 case 035:
843 case 036:
844 case 037:
845 if (opx->type & (BITS16 | BITS32 | BITS64))
846 length += (opx->type & BITS16) ? 2 : 4;
847 else
848 length += (bits == 16) ? 2 : 4;
849 break;
850 case 040:
851 case 041:
852 case 042:
853 case 043:
854 length += 4;
855 break;
856 case 044:
857 case 045:
858 case 046:
859 case 047:
860 length += ins->addr_size >> 3;
861 break;
862 case 050:
863 case 051:
864 case 052:
865 case 053:
866 length++;
867 break;
868 case 054:
869 case 055:
870 case 056:
871 case 057:
872 length += 8; /* MOV reg64/imm */
873 break;
874 case 060:
875 case 061:
876 case 062:
877 case 063:
878 length += 2;
879 break;
880 case 064:
881 case 065:
882 case 066:
883 case 067:
884 if (opx->type & (BITS16 | BITS32 | BITS64))
885 length += (opx->type & BITS16) ? 2 : 4;
886 else
887 length += (bits == 16) ? 2 : 4;
888 break;
889 case 070:
890 case 071:
891 case 072:
892 case 073:
893 length += 4;
894 break;
895 case 074:
896 case 075:
897 case 076:
898 case 077:
899 length += 2;
900 break;
901 case 0140:
902 case 0141:
903 case 0142:
904 case 0143:
905 length += is_sbyte(ins, c & 3, 16) ? 1 : 2;
906 break;
907 case 0144:
908 case 0145:
909 case 0146:
910 case 0147:
911 codes++;
912 length++;
913 break;
914 case 0150:
915 case 0151:
916 case 0152:
917 case 0153:
918 length += is_sbyte(ins, c & 3, 32) ? 1 : 4;
919 break;
920 case 0154:
921 case 0155:
922 case 0156:
923 case 0157:
924 codes++;
925 length++;
926 break;
927 case 0160:
928 case 0161:
929 case 0162:
930 case 0163:
931 length++;
932 ins->rex |= REX_D;
933 ins->drexdst = regval(&ins->oprs[c & 3]);
934 break;
935 case 0164:
936 case 0165:
937 case 0166:
938 case 0167:
939 length++;
940 ins->rex |= REX_D|REX_OC;
941 ins->drexdst = regval(&ins->oprs[c & 3]);
942 break;
943 case 0170:
944 length++;
945 break;
946 case 0171:
947 break;
948 case 0300:
949 case 0301:
950 case 0302:
951 case 0303:
952 break;
953 case 0310:
954 if (bits == 64)
955 return -1;
956 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
957 break;
958 case 0311:
959 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
960 break;
961 case 0312:
962 break;
963 case 0313:
964 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
965 has_prefix(ins, PPS_ASIZE, P_A32))
966 return -1;
967 break;
968 case 0314:
969 case 0315:
970 case 0316:
971 case 0317:
972 break;
973 case 0320:
974 length += (bits != 16);
975 break;
976 case 0321:
977 length += (bits == 16);
978 break;
979 case 0322:
980 break;
981 case 0323:
982 rex_mask &= ~REX_W;
983 break;
984 case 0324:
985 ins->rex |= REX_W;
986 break;
987 case 0330:
988 codes++, length++;
989 break;
990 case 0331:
991 break;
992 case 0332:
993 case 0333:
994 length++;
995 break;
996 case 0334:
997 ins->rex |= REX_L;
998 break;
999 case 0335:
1000 break;
1001 case 0340:
1002 if (ins->oprs[0].segment != NO_SEG)
1003 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1004 " quantity of BSS space");
1005 else
1006 length += ins->oprs[0].offset;
1007 break;
1008 case 0364:
1009 case 0365:
1010 break;
1011 case 0366:
1012 case 0367:
1013 length++;
1014 break;
1015 case 0370:
1016 case 0371:
1017 case 0372:
1018 break;
1019 case 0373:
1020 length++;
1021 break;
1022 default: /* can't do it by 'case' statements */
1023 if (c >= 0100 && c <= 0277) { /* it's an EA */
1024 ea ea_data;
1025 int rfield;
1026 int32_t rflags;
1027 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1028
1029 if (c <= 0177) {
1030 /* pick rfield from operand b */
1031 rflags = regflag(&ins->oprs[c & 7]);
1032 rfield = regvals[ins->oprs[c & 7].basereg];
1033 } else {
1034 rflags = 0;
1035 rfield = c & 7;
1036 }
1037
1038 if (!process_ea
1039 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1040 ins->addr_size, rfield, rflags, ins->forw_ref)) {
1041 errfunc(ERR_NONFATAL, "invalid effective address");
1042 return -1;
1043 } else {
1044 ins->rex |= ea_data.rex;
1045 length += ea_data.size;
1046 }
1047 } else {
1048 errfunc(ERR_PANIC, "internal instruction table corrupt"
1049 ": instruction code 0x%02X given", c);
1050 }
1051 }
1052 }
1053
1054 ins->rex &= rex_mask;
1055
1056 if (ins->rex & REX_D) {
1057 if (ins->rex & REX_H) {
1058 errfunc(ERR_NONFATAL, "cannot use high register in drex instruction");
1059 return -1;
1060 }
1061 if (bits != 64 && ((ins->rex & (REX_W|REX_X|REX_B)) ||
1062 ins->drexdst > 7)) {
1063 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1064 return -1;
1065 }
1066 length++;
1067 } else if (ins->rex & REX_REAL) {
1068 if (ins->rex & REX_H) {
1069 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1070 return -1;
1071 } else if (bits == 64) {
1072 length++;
1073 } else if ((ins->rex & REX_L) &&
1074 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1075 cpu >= IF_X86_64) {
1076 /* LOCK-as-REX.R */
1077 assert_no_prefix(ins, PPS_LREP);
1078 length++;
1079 } else {
1080 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1081 return -1;
1082 }
1083 }
1084
1085 return length;
1086 }
1087
1088 #define EMIT_REX() \
1089 if (!(ins->rex & REX_D) && (ins->rex & REX_REAL) && (bits == 64)) { \
1090 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1091 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1092 ins->rex = 0; \
1093 offset += 1; \
1094 }
1095
1096 static void gencode(int32_t segment, int64_t offset, int bits,
1097 insn * ins, const char *codes, int64_t insn_end)
1098 {
1099 static char condval[] = { /* conditional opcodes */
1100 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1101 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1102 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1103 };
1104 uint8_t c;
1105 uint8_t bytes[4];
1106 int64_t size;
1107 int64_t data;
1108 struct operand *opx;
1109
1110 while (*codes) {
1111 c = *codes++;
1112 opx = &ins->oprs[c & 3];
1113 switch (c) {
1114 case 01:
1115 case 02:
1116 case 03:
1117 EMIT_REX();
1118 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1119 codes += c;
1120 offset += c;
1121 break;
1122
1123 case 04:
1124 case 06:
1125 switch (ins->oprs[0].basereg) {
1126 case R_CS:
1127 bytes[0] = 0x0E + (c == 0x04 ? 1 : 0);
1128 break;
1129 case R_DS:
1130 bytes[0] = 0x1E + (c == 0x04 ? 1 : 0);
1131 break;
1132 case R_ES:
1133 bytes[0] = 0x06 + (c == 0x04 ? 1 : 0);
1134 break;
1135 case R_SS:
1136 bytes[0] = 0x16 + (c == 0x04 ? 1 : 0);
1137 break;
1138 default:
1139 errfunc(ERR_PANIC,
1140 "bizarre 8086 segment register received");
1141 }
1142 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1143 offset++;
1144 break;
1145
1146 case 05:
1147 case 07:
1148 switch (ins->oprs[0].basereg) {
1149 case R_FS:
1150 bytes[0] = 0xA0 + (c == 0x05 ? 1 : 0);
1151 break;
1152 case R_GS:
1153 bytes[0] = 0xA8 + (c == 0x05 ? 1 : 0);
1154 break;
1155 default:
1156 errfunc(ERR_PANIC,
1157 "bizarre 386 segment register received");
1158 }
1159 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1160 offset++;
1161 break;
1162
1163 case 010:
1164 case 011:
1165 case 012:
1166 case 013:
1167 EMIT_REX();
1168 bytes[0] = *codes++ + ((regval(opx)) & 7);
1169 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1170 offset += 1;
1171 break;
1172
1173 case 014:
1174 case 015:
1175 case 016:
1176 case 017:
1177 if (opx->offset < -128 || opx->offset > 127) {
1178 errfunc(ERR_WARNING | ERR_WARN_NOV,
1179 "signed byte value exceeds bounds");
1180 }
1181
1182 if (opx->segment != NO_SEG) {
1183 data = opx->offset;
1184 out(offset, segment, &data, OUT_ADDRESS, 1,
1185 opx->segment, opx->wrt);
1186 } else {
1187 bytes[0] = opx->offset;
1188 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1189 NO_SEG);
1190 }
1191 offset += 1;
1192 break;
1193
1194 case 020:
1195 case 021:
1196 case 022:
1197 case 023:
1198 if (opx->offset < -256 || opx->offset > 255) {
1199 errfunc(ERR_WARNING | ERR_WARN_NOV,
1200 "byte value exceeds bounds");
1201 }
1202 if (opx->segment != NO_SEG) {
1203 data = opx->offset;
1204 out(offset, segment, &data, OUT_ADDRESS, 1,
1205 opx->segment, opx->wrt);
1206 } else {
1207 bytes[0] = opx->offset;
1208 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1209 NO_SEG);
1210 }
1211 offset += 1;
1212 break;
1213
1214 case 024:
1215 case 025:
1216 case 026:
1217 case 027:
1218 if (opx->offset < 0 || opx->offset > 255)
1219 errfunc(ERR_WARNING | ERR_WARN_NOV,
1220 "unsigned byte value exceeds bounds");
1221 if (opx->segment != NO_SEG) {
1222 data = opx->offset;
1223 out(offset, segment, &data, OUT_ADDRESS, 1,
1224 opx->segment, opx->wrt);
1225 } else {
1226 bytes[0] = opx->offset;
1227 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1228 NO_SEG);
1229 }
1230 offset += 1;
1231 break;
1232
1233 case 030:
1234 case 031:
1235 case 032:
1236 case 033:
1237 data = opx->offset;
1238 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1239 warn_overflow(2, data);
1240 out(offset, segment, &data, OUT_ADDRESS, 2,
1241 opx->segment, opx->wrt);
1242 offset += 2;
1243 break;
1244
1245 case 034:
1246 case 035:
1247 case 036:
1248 case 037:
1249 if (opx->type & (BITS16 | BITS32))
1250 size = (opx->type & BITS16) ? 2 : 4;
1251 else
1252 size = (bits == 16) ? 2 : 4;
1253 data = opx->offset;
1254 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1255 warn_overflow(size, data);
1256 out(offset, segment, &data, OUT_ADDRESS, size,
1257 opx->segment, opx->wrt);
1258 offset += size;
1259 break;
1260
1261 case 040:
1262 case 041:
1263 case 042:
1264 case 043:
1265 data = opx->offset;
1266 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1267 warn_overflow(4, data);
1268 out(offset, segment, &data, OUT_ADDRESS, 4,
1269 opx->segment, opx->wrt);
1270 offset += 4;
1271 break;
1272
1273 case 044:
1274 case 045:
1275 case 046:
1276 case 047:
1277 data = opx->offset;
1278 size = ins->addr_size >> 3;
1279 if (opx->segment == NO_SEG &&
1280 opx->wrt == NO_SEG)
1281 warn_overflow(size, data);
1282 out(offset, segment, &data, OUT_ADDRESS, size,
1283 opx->segment, opx->wrt);
1284 offset += size;
1285 break;
1286
1287 case 050:
1288 case 051:
1289 case 052:
1290 case 053:
1291 if (opx->segment != segment)
1292 errfunc(ERR_NONFATAL,
1293 "short relative jump outside segment");
1294 data = opx->offset - insn_end;
1295 if (data > 127 || data < -128)
1296 errfunc(ERR_NONFATAL, "short jump is out of range");
1297 bytes[0] = data;
1298 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1299 offset += 1;
1300 break;
1301
1302 case 054:
1303 case 055:
1304 case 056:
1305 case 057:
1306 data = (int64_t)opx->offset;
1307 out(offset, segment, &data, OUT_ADDRESS, 8,
1308 opx->segment, opx->wrt);
1309 offset += 8;
1310 break;
1311
1312 case 060:
1313 case 061:
1314 case 062:
1315 case 063:
1316 if (opx->segment != segment) {
1317 data = opx->offset;
1318 out(offset, segment, &data,
1319 OUT_REL2ADR, insn_end - offset,
1320 opx->segment, opx->wrt);
1321 } else {
1322 data = opx->offset - insn_end;
1323 out(offset, segment, &data,
1324 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1325 }
1326 offset += 2;
1327 break;
1328
1329 case 064:
1330 case 065:
1331 case 066:
1332 case 067:
1333 if (opx->type & (BITS16 | BITS32 | BITS64))
1334 size = (opx->type & BITS16) ? 2 : 4;
1335 else
1336 size = (bits == 16) ? 2 : 4;
1337 if (opx->segment != segment) {
1338 data = opx->offset;
1339 out(offset, segment, &data,
1340 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1341 insn_end - offset, opx->segment, opx->wrt);
1342 } else {
1343 data = opx->offset - insn_end;
1344 out(offset, segment, &data,
1345 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1346 }
1347 offset += size;
1348 break;
1349
1350 case 070:
1351 case 071:
1352 case 072:
1353 case 073:
1354 if (opx->segment != segment) {
1355 data = opx->offset;
1356 out(offset, segment, &data,
1357 OUT_REL4ADR, insn_end - offset,
1358 opx->segment, opx->wrt);
1359 } else {
1360 data = opx->offset - insn_end;
1361 out(offset, segment, &data,
1362 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1363 }
1364 offset += 4;
1365 break;
1366
1367 case 074:
1368 case 075:
1369 case 076:
1370 case 077:
1371 if (opx->segment == NO_SEG)
1372 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1373 " relocatable");
1374 data = 0L;
1375 out(offset, segment, &data, OUT_ADDRESS, 2,
1376 outfmt->segbase(1 + opx->segment),
1377 opx->wrt);
1378 offset += 2;
1379 break;
1380
1381 case 0140:
1382 case 0141:
1383 case 0142:
1384 case 0143:
1385 data = opx->offset;
1386 if (is_sbyte(ins, c & 3, 16)) {
1387 bytes[0] = data;
1388 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1389 NO_SEG);
1390 offset++;
1391 } else {
1392 if (opx->segment == NO_SEG &&
1393 opx->wrt == NO_SEG)
1394 warn_overflow(2, data);
1395 out(offset, segment, &data, OUT_ADDRESS, 2,
1396 opx->segment, opx->wrt);
1397 offset += 2;
1398 }
1399 break;
1400
1401 case 0144:
1402 case 0145:
1403 case 0146:
1404 case 0147:
1405 EMIT_REX();
1406 bytes[0] = *codes++;
1407 if (is_sbyte(ins, c & 3, 16))
1408 bytes[0] |= 2; /* s-bit */
1409 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1410 offset++;
1411 break;
1412
1413 case 0150:
1414 case 0151:
1415 case 0152:
1416 case 0153:
1417 data = opx->offset;
1418 if (is_sbyte(ins, c & 3, 32)) {
1419 bytes[0] = data;
1420 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1421 NO_SEG);
1422 offset++;
1423 } else {
1424 out(offset, segment, &data, OUT_ADDRESS, 4,
1425 opx->segment, opx->wrt);
1426 offset += 4;
1427 }
1428 break;
1429
1430 case 0154:
1431 case 0155:
1432 case 0156:
1433 case 0157:
1434 EMIT_REX();
1435 bytes[0] = *codes++;
1436 if (is_sbyte(ins, c & 3, 32))
1437 bytes[0] |= 2; /* s-bit */
1438 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1439 offset++;
1440 break;
1441
1442 case 0160:
1443 case 0161:
1444 case 0162:
1445 case 0163:
1446 case 0164:
1447 case 0165:
1448 case 0166:
1449 case 0167:
1450 break;
1451
1452 case 0170:
1453 EMIT_REX();
1454 bytes[0] = 0;
1455 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1456 offset += 1;
1457 break;
1458
1459 case 0171:
1460 bytes[0] =
1461 (ins->drexdst << 4) |
1462 (ins->rex & REX_OC ? 0x08 : 0) |
1463 (ins->rex & (REX_R|REX_X|REX_B));
1464 ins->rex = 0;
1465 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1466 offset++;
1467 break;
1468
1469 case 0300:
1470 case 0301:
1471 case 0302:
1472 case 0303:
1473 break;
1474
1475 case 0310:
1476 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1477 *bytes = 0x67;
1478 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1479 offset += 1;
1480 } else
1481 offset += 0;
1482 break;
1483
1484 case 0311:
1485 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1486 *bytes = 0x67;
1487 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1488 offset += 1;
1489 } else
1490 offset += 0;
1491 break;
1492
1493 case 0312:
1494 break;
1495
1496 case 0313:
1497 ins->rex = 0;
1498 break;
1499
1500 case 0314:
1501 case 0315:
1502 case 0316:
1503 case 0317:
1504 break;
1505
1506 case 0320:
1507 if (bits != 16) {
1508 *bytes = 0x66;
1509 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1510 offset += 1;
1511 } else
1512 offset += 0;
1513 break;
1514
1515 case 0321:
1516 if (bits == 16) {
1517 *bytes = 0x66;
1518 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1519 offset += 1;
1520 } else
1521 offset += 0;
1522 break;
1523
1524 case 0322:
1525 case 0323:
1526 break;
1527
1528 case 0324:
1529 ins->rex |= REX_W;
1530 break;
1531
1532 case 0330:
1533 *bytes = *codes++ ^ condval[ins->condition];
1534 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1535 offset += 1;
1536 break;
1537
1538 case 0331:
1539 break;
1540
1541 case 0332:
1542 case 0333:
1543 *bytes = c - 0332 + 0xF2;
1544 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1545 offset += 1;
1546 break;
1547
1548 case 0334:
1549 if (ins->rex & REX_R) {
1550 *bytes = 0xF0;
1551 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1552 offset += 1;
1553 }
1554 ins->rex &= ~(REX_L|REX_R);
1555 break;
1556
1557 case 0335:
1558 break;
1559
1560 case 0340:
1561 if (ins->oprs[0].segment != NO_SEG)
1562 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1563 else {
1564 int64_t size = ins->oprs[0].offset;
1565 if (size > 0)
1566 out(offset, segment, NULL,
1567 OUT_RESERVE, size, NO_SEG, NO_SEG);
1568 offset += size;
1569 }
1570 break;
1571
1572 case 0364:
1573 case 0365:
1574 break;
1575
1576 case 0366:
1577 case 0367:
1578 *bytes = c - 0366 + 0x66;
1579 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1580 offset += 1;
1581 break;
1582
1583 case 0370:
1584 case 0371:
1585 case 0372:
1586 break;
1587
1588 case 0373:
1589 *bytes = bits == 16 ? 3 : 5;
1590 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1591 offset += 1;
1592 break;
1593
1594 default: /* can't do it by 'case' statements */
1595 if (c >= 0100 && c <= 0277) { /* it's an EA */
1596 ea ea_data;
1597 int rfield;
1598 int32_t rflags;
1599 uint8_t *p;
1600 int32_t s;
1601
1602 if (c <= 0177) {
1603 /* pick rfield from operand b */
1604 rflags = regflag(&ins->oprs[c & 7]);
1605 rfield = regvals[ins->oprs[c & 7].basereg];
1606 } else {
1607 /* rfield is constant */
1608 rflags = 0;
1609 rfield = c & 7;
1610 }
1611
1612 if (!process_ea
1613 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1614 ins->addr_size, rfield, rflags, ins->forw_ref)) {
1615 errfunc(ERR_NONFATAL, "invalid effective address");
1616 }
1617
1618
1619 p = bytes;
1620 *p++ = ea_data.modrm;
1621 if (ea_data.sib_present)
1622 *p++ = ea_data.sib;
1623
1624 /* DREX suffixes come between the SIB and the displacement */
1625 if (ins->rex & REX_D) {
1626 *p++ =
1627 (ins->drexdst << 4) |
1628 (ins->rex & REX_OC ? 0x08 : 0) |
1629 (ins->rex & (REX_R|REX_X|REX_B));
1630 ins->rex = 0;
1631 }
1632
1633 s = p - bytes;
1634 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1635
1636 switch (ea_data.bytes) {
1637 case 0:
1638 break;
1639 case 1:
1640 if (ins->oprs[(c >> 3) & 7].segment != NO_SEG) {
1641 data = ins->oprs[(c >> 3) & 7].offset;
1642 out(offset, segment, &data, OUT_ADDRESS, 1,
1643 ins->oprs[(c >> 3) & 7].segment,
1644 ins->oprs[(c >> 3) & 7].wrt);
1645 } else {
1646 *bytes = ins->oprs[(c >> 3) & 7].offset;
1647 out(offset, segment, bytes, OUT_RAWDATA, 1,
1648 NO_SEG, NO_SEG);
1649 }
1650 s++;
1651 break;
1652 case 8:
1653 case 2:
1654 case 4:
1655 data = ins->oprs[(c >> 3) & 7].offset;
1656 warn_overflow(ea_data.bytes, data);
1657 out(offset, segment, &data,
1658 ea_data.rip ? OUT_REL4ADR : OUT_ADDRESS,
1659 ea_data.bytes,
1660 ins->oprs[(c >> 3) & 7].segment,
1661 ins->oprs[(c >> 3) & 7].wrt);
1662 s += ea_data.bytes;
1663 break;
1664 }
1665 offset += s;
1666 } else {
1667 errfunc(ERR_PANIC, "internal instruction table corrupt"
1668 ": instruction code 0x%02X given", c);
1669 }
1670 }
1671 }
1672 }
1673
1674 static int32_t regflag(const operand * o)
1675 {
1676 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1677 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1678 }
1679 return reg_flags[o->basereg];
1680 }
1681
1682 static int32_t regval(const operand * o)
1683 {
1684 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1685 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1686 }
1687 return regvals[o->basereg];
1688 }
1689
1690 static int op_rexflags(const operand * o, int mask)
1691 {
1692 int32_t flags;
1693 int val;
1694
1695 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1696 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1697 }
1698
1699 flags = reg_flags[o->basereg];
1700 val = regvals[o->basereg];
1701
1702 return rexflags(val, flags, mask);
1703 }
1704
1705 static int rexflags(int val, int32_t flags, int mask)
1706 {
1707 int rex = 0;
1708
1709 if (val >= 8)
1710 rex |= REX_B|REX_X|REX_R;
1711 if (flags & BITS64)
1712 rex |= REX_W;
1713 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1714 rex |= REX_H;
1715 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1716 rex |= REX_P;
1717
1718 return rex & mask;
1719 }
1720
1721 static int matches(const struct itemplate *itemp, insn * instruction, int bits)
1722 {
1723 int i, size[MAX_OPERANDS], asize, oprs, ret;
1724
1725 ret = 100;
1726
1727 /*
1728 * Check the opcode
1729 */
1730 if (itemp->opcode != instruction->opcode)
1731 return 0;
1732
1733 /*
1734 * Count the operands
1735 */
1736 if (itemp->operands != instruction->operands)
1737 return 0;
1738
1739 /*
1740 * Check that no spurious colons or TOs are present
1741 */
1742 for (i = 0; i < itemp->operands; i++)
1743 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1744 return 0;
1745
1746 /*
1747 * Check that the operand flags all match up
1748 */
1749 for (i = 0; i < itemp->operands; i++) {
1750 if (itemp->opd[i] & SAME_AS) {
1751 int j = itemp->opd[i] & ~SAME_AS;
1752 if (instruction->oprs[i].type != instruction->oprs[j].type ||
1753 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
1754 return 0;
1755 } else if (itemp->opd[i] & ~instruction->oprs[i].type ||
1756 ((itemp->opd[i] & SIZE_MASK) &&
1757 ((itemp->opd[i] ^ instruction->oprs[i].type) & SIZE_MASK))) {
1758 if ((itemp->opd[i] & ~instruction->oprs[i].type & ~SIZE_MASK) ||
1759 (instruction->oprs[i].type & SIZE_MASK))
1760 return 0;
1761 else
1762 return 1;
1763 }
1764 }
1765
1766 /*
1767 * Check operand sizes
1768 */
1769 if (itemp->flags & IF_ARMASK) {
1770 memset(size, 0, sizeof size);
1771
1772 switch (itemp->flags & IF_ARMASK) {
1773 case IF_AR0:
1774 i = 0;
1775 break;
1776 case IF_AR1:
1777 i = 1;
1778 break;
1779 case IF_AR2:
1780 i = 2;
1781 break;
1782 case IF_AR3:
1783 i = 3;
1784 break;
1785 default:
1786 break; /* Shouldn't happen */
1787 }
1788 switch (itemp->flags & IF_SMASK) {
1789 case IF_SB:
1790 size[i] = BITS8;
1791 break;
1792 case IF_SW:
1793 size[i] = BITS16;
1794 break;
1795 case IF_SD:
1796 size[i] = BITS32;
1797 break;
1798 case IF_SQ:
1799 size[i] = BITS64;
1800 break;
1801 case IF_SO:
1802 size[i] = BITS128;
1803 break;
1804 default:
1805 break;
1806 }
1807 } else {
1808 asize = 0;
1809 switch (itemp->flags & IF_SMASK) {
1810 case IF_SB:
1811 asize = BITS8;
1812 oprs = itemp->operands;
1813 break;
1814 case IF_SW:
1815 asize = BITS16;
1816 oprs = itemp->operands;
1817 break;
1818 case IF_SD:
1819 asize = BITS32;
1820 oprs = itemp->operands;
1821 break;
1822 case IF_SQ:
1823 asize = BITS64;
1824 oprs = itemp->operands;
1825 break;
1826 case IF_SO:
1827 asize = BITS128;
1828 oprs = itemp->operands;
1829 break;
1830 default:
1831 break;
1832 }
1833 for (i = 0; i < MAX_OPERANDS; i++)
1834 size[i] = asize;
1835 }
1836
1837 if (itemp->flags & (IF_SM | IF_SM2)) {
1838 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
1839 asize = 0;
1840 for (i = 0; i < oprs; i++) {
1841 if ((asize = itemp->opd[i] & SIZE_MASK) != 0) {
1842 int j;
1843 for (j = 0; j < oprs; j++)
1844 size[j] = asize;
1845 break;
1846 }
1847 }
1848 } else {
1849 oprs = itemp->operands;
1850 }
1851
1852 for (i = 0; i < itemp->operands; i++) {
1853 if (!(itemp->opd[i] & SIZE_MASK) &&
1854 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
1855 return 2;
1856 }
1857
1858 /*
1859 * Check template is okay at the set cpu level
1860 */
1861 if (((itemp->flags & IF_PLEVEL) > cpu))
1862 return 3;
1863
1864 /*
1865 * Check if instruction is available in long mode
1866 */
1867 if ((itemp->flags & IF_NOLONG) && (bits == 64))
1868 return 4;
1869
1870 /*
1871 * Check if special handling needed for Jumps
1872 */
1873 if ((uint8_t)(itemp->code[0]) >= 0370)
1874 return 99;
1875
1876 return ret;
1877 }
1878
1879 static ea *process_ea(operand * input, ea * output, int bits,
1880 int addrbits, int rfield, int32_t rflags, int forw_ref)
1881 {
1882 output->rip = false;
1883
1884 /* REX flags for the rfield operand */
1885 output->rex |= rexflags(rfield, rflags, REX_R|REX_P|REX_W|REX_H);
1886
1887 if (!(REGISTER & ~input->type)) { /* register direct */
1888 int i;
1889 int32_t f;
1890
1891 if (input->basereg < EXPR_REG_START /* Verify as Register */
1892 || input->basereg >= REG_ENUM_LIMIT)
1893 return NULL;
1894 f = regflag(input);
1895 i = regvals[input->basereg];
1896
1897 if (REG_EA & ~f)
1898 return NULL; /* Invalid EA register */
1899
1900 output->rex |= op_rexflags(input, REX_B|REX_P|REX_W|REX_H);
1901
1902 output->sib_present = false; /* no SIB necessary */
1903 output->bytes = 0; /* no offset necessary either */
1904 output->modrm = 0xC0 | ((rfield & 7) << 3) | (i & 7);
1905 } else { /* it's a memory reference */
1906 if (input->basereg == -1
1907 && (input->indexreg == -1 || input->scale == 0)) {
1908 /* it's a pure offset */
1909 if (bits == 64 && (~input->type & IP_REL)) {
1910 int scale, index, base;
1911 output->sib_present = true;
1912 scale = 0;
1913 index = 4;
1914 base = 5;
1915 output->sib = (scale << 6) | (index << 3) | base;
1916 output->bytes = 4;
1917 output->modrm = 4 | ((rfield & 7) << 3);
1918 output->rip = false;
1919 } else {
1920 output->sib_present = false;
1921 output->bytes = (addrbits != 16 ? 4 : 2);
1922 output->modrm = (addrbits != 16 ? 5 : 6) | ((rfield & 7) << 3);
1923 output->rip = bits == 64;
1924 }
1925 } else { /* it's an indirection */
1926 int i = input->indexreg, b = input->basereg, s = input->scale;
1927 int32_t o = input->offset, seg = input->segment;
1928 int hb = input->hintbase, ht = input->hinttype;
1929 int t;
1930 int it, bt;
1931 int32_t ix, bx; /* register flags */
1932
1933 if (s == 0)
1934 i = -1; /* make this easy, at least */
1935
1936 if (i >= EXPR_REG_START && i < REG_ENUM_LIMIT) {
1937 it = regvals[i];
1938 ix = reg_flags[i];
1939 } else {
1940 it = -1;
1941 ix = 0;
1942 }
1943
1944 if (b >= EXPR_REG_START && b < REG_ENUM_LIMIT) {
1945 bt = regvals[b];
1946 bx = reg_flags[b];
1947 } else {
1948 bt = -1;
1949 bx = 0;
1950 }
1951
1952 /* check for a 32/64-bit memory reference... */
1953 if ((ix|bx) & (BITS32|BITS64)) {
1954 /* it must be a 32/64-bit memory reference. Firstly we have
1955 * to check that all registers involved are type E/Rxx. */
1956 int32_t sok = BITS32|BITS64;
1957
1958 if (it != -1) {
1959 if (!(REG64 & ~ix) || !(REG32 & ~ix))
1960 sok &= ix;
1961 else
1962 return NULL;
1963 }
1964
1965 if (bt != -1) {
1966 if (REG_GPR & ~bx)
1967 return NULL; /* Invalid register */
1968 if (~sok & bx & SIZE_MASK)
1969 return NULL; /* Invalid size */
1970 sok &= bx;
1971 }
1972
1973 /* While we're here, ensure the user didn't specify
1974 WORD or QWORD. */
1975 if (input->disp_size == 16 || input->disp_size == 64)
1976 return NULL;
1977
1978 if (addrbits == 16 ||
1979 (addrbits == 32 && !(sok & BITS32)) ||
1980 (addrbits == 64 && !(sok & BITS64)))
1981 return NULL;
1982
1983 /* now reorganize base/index */
1984 if (s == 1 && bt != it && bt != -1 && it != -1 &&
1985 ((hb == b && ht == EAH_NOTBASE)
1986 || (hb == i && ht == EAH_MAKEBASE))) {
1987 /* swap if hints say so */
1988 t = bt, bt = it, it = t;
1989 t = bx, bx = ix, ix = t;
1990 }
1991 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
1992 bt = -1, bx = 0, s++;
1993 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
1994 /* make single reg base, unless hint */
1995 bt = it, bx = ix, it = -1, ix = 0;
1996 }
1997 if (((s == 2 && it != REG_NUM_ESP
1998 && !(input->eaflags & EAF_TIMESTWO)) || s == 3
1999 || s == 5 || s == 9) && bt == -1)
2000 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2001 if (it == -1 && (bt & 7) != REG_NUM_ESP
2002 && (input->eaflags & EAF_TIMESTWO))
2003 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2004 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2005 if (s == 1 && it == REG_NUM_ESP) {
2006 /* swap ESP into base if scale is 1 */
2007 t = it, it = bt, bt = t;
2008 t = ix, ix = bx, bx = t;
2009 }
2010 if (it == REG_NUM_ESP
2011 || (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2012 return NULL; /* wrong, for various reasons */
2013
2014 output->rex |= rexflags(it, ix, REX_X);
2015 output->rex |= rexflags(bt, bx, REX_B);
2016
2017 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2018 /* no SIB needed */
2019 int mod, rm;
2020
2021 if (bt == -1) {
2022 rm = 5;
2023 mod = 0;
2024 } else {
2025 rm = (bt & 7);
2026 if (rm != REG_NUM_EBP && o == 0 &&
2027 seg == NO_SEG && !forw_ref &&
2028 !(input->eaflags &
2029 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2030 mod = 0;
2031 else if (input->eaflags & EAF_BYTEOFFS ||
2032 (o >= -128 && o <= 127 && seg == NO_SEG
2033 && !forw_ref
2034 && !(input->eaflags & EAF_WORDOFFS)))
2035 mod = 1;
2036 else
2037 mod = 2;
2038 }
2039
2040 output->sib_present = false;
2041 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2042 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2043 } else {
2044 /* we need a SIB */
2045 int mod, scale, index, base;
2046
2047 if (it == -1)
2048 index = 4, s = 1;
2049 else
2050 index = (it & 7);
2051
2052 switch (s) {
2053 case 1:
2054 scale = 0;
2055 break;
2056 case 2:
2057 scale = 1;
2058 break;
2059 case 4:
2060 scale = 2;
2061 break;
2062 case 8:
2063 scale = 3;
2064 break;
2065 default: /* then what the smeg is it? */
2066 return NULL; /* panic */
2067 }
2068
2069 if (bt == -1) {
2070 base = 5;
2071 mod = 0;
2072 } else {
2073 base = (bt & 7);
2074 if (base != REG_NUM_EBP && o == 0 &&
2075 seg == NO_SEG && !forw_ref &&
2076 !(input->eaflags &
2077 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2078 mod = 0;
2079 else if (input->eaflags & EAF_BYTEOFFS ||
2080 (o >= -128 && o <= 127 && seg == NO_SEG
2081 && !forw_ref
2082 && !(input->eaflags & EAF_WORDOFFS)))
2083 mod = 1;
2084 else
2085 mod = 2;
2086 }
2087
2088 output->sib_present = true;
2089 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2090 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2091 output->sib = (scale << 6) | (index << 3) | base;
2092 }
2093 } else { /* it's 16-bit */
2094 int mod, rm;
2095
2096 /* check for 64-bit long mode */
2097 if (addrbits == 64)
2098 return NULL;
2099
2100 /* check all registers are BX, BP, SI or DI */
2101 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI
2102 && b != R_DI) || (i != -1 && i != R_BP && i != R_BX
2103 && i != R_SI && i != R_DI))
2104 return NULL;
2105
2106 /* ensure the user didn't specify DWORD/QWORD */
2107 if (input->disp_size == 32 || input->disp_size == 64)
2108 return NULL;
2109
2110 if (s != 1 && i != -1)
2111 return NULL; /* no can do, in 16-bit EA */
2112 if (b == -1 && i != -1) {
2113 int tmp = b;
2114 b = i;
2115 i = tmp;
2116 } /* swap */
2117 if ((b == R_SI || b == R_DI) && i != -1) {
2118 int tmp = b;
2119 b = i;
2120 i = tmp;
2121 }
2122 /* have BX/BP as base, SI/DI index */
2123 if (b == i)
2124 return NULL; /* shouldn't ever happen, in theory */
2125 if (i != -1 && b != -1 &&
2126 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2127 return NULL; /* invalid combinations */
2128 if (b == -1) /* pure offset: handled above */
2129 return NULL; /* so if it gets to here, panic! */
2130
2131 rm = -1;
2132 if (i != -1)
2133 switch (i * 256 + b) {
2134 case R_SI * 256 + R_BX:
2135 rm = 0;
2136 break;
2137 case R_DI * 256 + R_BX:
2138 rm = 1;
2139 break;
2140 case R_SI * 256 + R_BP:
2141 rm = 2;
2142 break;
2143 case R_DI * 256 + R_BP:
2144 rm = 3;
2145 break;
2146 } else
2147 switch (b) {
2148 case R_SI:
2149 rm = 4;
2150 break;
2151 case R_DI:
2152 rm = 5;
2153 break;
2154 case R_BP:
2155 rm = 6;
2156 break;
2157 case R_BX:
2158 rm = 7;
2159 break;
2160 }
2161 if (rm == -1) /* can't happen, in theory */
2162 return NULL; /* so panic if it does */
2163
2164 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2165 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2166 mod = 0;
2167 else if (input->eaflags & EAF_BYTEOFFS ||
2168 (o >= -128 && o <= 127 && seg == NO_SEG
2169 && !forw_ref
2170 && !(input->eaflags & EAF_WORDOFFS)))
2171 mod = 1;
2172 else
2173 mod = 2;
2174
2175 output->sib_present = false; /* no SIB - it's 16-bit */
2176 output->bytes = mod; /* bytes of offset needed */
2177 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2178 }
2179 }
2180 }
2181
2182 output->size = 1 + output->sib_present + output->bytes;
2183 return output;
2184 }
2185
2186 static void add_asp(insn *ins, int addrbits)
2187 {
2188 int j, valid;
2189 int defdisp;
2190
2191 valid = (addrbits == 64) ? 64|32 : 32|16;
2192
2193 switch (ins->prefixes[PPS_ASIZE]) {
2194 case P_A16:
2195 valid &= 16;
2196 break;
2197 case P_A32:
2198 valid &= 32;
2199 break;
2200 case P_A64:
2201 valid &= 64;
2202 break;
2203 case P_ASP:
2204 valid &= (addrbits == 32) ? 16 : 32;
2205 break;
2206 default:
2207 break;
2208 }
2209
2210 for (j = 0; j < ins->operands; j++) {
2211 if (!(MEMORY & ~ins->oprs[j].type)) {
2212 int32_t i, b;
2213
2214 /* Verify as Register */
2215 if (ins->oprs[j].indexreg < EXPR_REG_START
2216 || ins->oprs[j].indexreg >= REG_ENUM_LIMIT)
2217 i = 0;
2218 else
2219 i = reg_flags[ins->oprs[j].indexreg];
2220
2221 /* Verify as Register */
2222 if (ins->oprs[j].basereg < EXPR_REG_START
2223 || ins->oprs[j].basereg >= REG_ENUM_LIMIT)
2224 b = 0;
2225 else
2226 b = reg_flags[ins->oprs[j].basereg];
2227
2228 if (ins->oprs[j].scale == 0)
2229 i = 0;
2230
2231 if (!i && !b) {
2232 int ds = ins->oprs[j].disp_size;
2233 if ((addrbits != 64 && ds > 8) ||
2234 (addrbits == 64 && ds == 16))
2235 valid &= ds;
2236 } else {
2237 if (!(REG16 & ~b))
2238 valid &= 16;
2239 if (!(REG32 & ~b))
2240 valid &= 32;
2241 if (!(REG64 & ~b))
2242 valid &= 64;
2243
2244 if (!(REG16 & ~i))
2245 valid &= 16;
2246 if (!(REG32 & ~i))
2247 valid &= 32;
2248 if (!(REG64 & ~i))
2249 valid &= 64;
2250 }
2251 }
2252 }
2253
2254 if (valid & addrbits) {
2255 ins->addr_size = addrbits;
2256 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2257 /* Add an address size prefix */
2258 enum prefixes pref = (addrbits == 32) ? P_A16 : P_A32;
2259 ins->prefixes[PPS_ASIZE] = pref;
2260 ins->addr_size = (addrbits == 32) ? 16 : 32;
2261 } else {
2262 /* Impossible... */
2263 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2264 ins->addr_size = addrbits; /* Error recovery */
2265 }
2266
2267 defdisp = ins->addr_size == 16 ? 16 : 32;
2268
2269 for (j = 0; j < ins->operands; j++) {
2270 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2271 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp)
2272 != ins->addr_size) {
2273 /* mem_offs sizes must match the address size; if not,
2274 strip the MEM_OFFS bit and match only EA instructions */
2275 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2276 }
2277 }
2278 }
The Netwide Assembler