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insns.dat: Enable contracted forms for additional instructions
[nasm.git] / disasm.c
blobcd5c6effa93d122586fc92a48b20ef4ca91c3142
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2012 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * disasm.c where all the _work_ gets done in the Netwide Disassembler
36 */
37
38 #include "compiler.h"
39
40 #include <stdio.h>
41 #include <string.h>
42 #include <limits.h>
43 #include <inttypes.h>
44
45 #include "nasm.h"
46 #include "disasm.h"
47 #include "sync.h"
48 #include "insns.h"
49 #include "tables.h"
50 #include "regdis.h"
51 #include "disp8.h"
52
53 /*
54 * Flags that go into the `segment' field of `insn' structures
55 * during disassembly.
56 */
57 #define SEG_RELATIVE 1
58 #define SEG_32BIT 2
59 #define SEG_RMREG 4
60 #define SEG_DISP8 8
61 #define SEG_DISP16 16
62 #define SEG_DISP32 32
63 #define SEG_NODISP 64
64 #define SEG_SIGNED 128
65 #define SEG_64BIT 256
66
67 /*
68 * Prefix information
69 */
70 struct prefix_info {
71 uint8_t osize; /* Operand size */
72 uint8_t asize; /* Address size */
73 uint8_t osp; /* Operand size prefix present */
74 uint8_t asp; /* Address size prefix present */
75 uint8_t rep; /* Rep prefix present */
76 uint8_t seg; /* Segment override prefix present */
77 uint8_t wait; /* WAIT "prefix" present */
78 uint8_t lock; /* Lock prefix present */
79 uint8_t vex[3]; /* VEX prefix present */
80 uint8_t vex_c; /* VEX "class" (VEX, XOP, ...) */
81 uint8_t vex_m; /* VEX.M field */
82 uint8_t vex_v;
83 uint8_t vex_lp; /* VEX.LP fields */
84 uint32_t rex; /* REX prefix present */
85 uint8_t evex[3]; /* EVEX prefix present */
86 };
87
88 #define getu8(x) (*(uint8_t *)(x))
89 #if X86_MEMORY
90 /* Littleendian CPU which can handle unaligned references */
91 #define getu16(x) (*(uint16_t *)(x))
92 #define getu32(x) (*(uint32_t *)(x))
93 #define getu64(x) (*(uint64_t *)(x))
94 #else
95 static uint16_t getu16(uint8_t *data)
96 {
97 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
98 }
99 static uint32_t getu32(uint8_t *data)
100 {
101 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
102 }
103 static uint64_t getu64(uint8_t *data)
104 {
105 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
106 }
107 #endif
108
109 #define gets8(x) ((int8_t)getu8(x))
110 #define gets16(x) ((int16_t)getu16(x))
111 #define gets32(x) ((int32_t)getu32(x))
112 #define gets64(x) ((int64_t)getu64(x))
113
114 /* Important: regval must already have been adjusted for rex extensions */
115 static enum reg_enum whichreg(opflags_t regflags, int regval, int rex)
116 {
117 size_t i;
118
119 static const struct {
120 opflags_t flags;
121 enum reg_enum reg;
122 } specific_registers[] = {
123 {REG_AL, R_AL},
124 {REG_AX, R_AX},
125 {REG_EAX, R_EAX},
126 {REG_RAX, R_RAX},
127 {REG_DL, R_DL},
128 {REG_DX, R_DX},
129 {REG_EDX, R_EDX},
130 {REG_RDX, R_RDX},
131 {REG_CL, R_CL},
132 {REG_CX, R_CX},
133 {REG_ECX, R_ECX},
134 {REG_RCX, R_RCX},
135 {FPU0, R_ST0},
136 {XMM0, R_XMM0},
137 {YMM0, R_YMM0},
138 {ZMM0, R_ZMM0},
139 {REG_ES, R_ES},
140 {REG_CS, R_CS},
141 {REG_SS, R_SS},
142 {REG_DS, R_DS},
143 {REG_FS, R_FS},
144 {REG_GS, R_GS},
145 {OPMASK0, R_K0},
146 };
147
148 if (!(regflags & (REGISTER|REGMEM)))
149 return 0; /* Registers not permissible?! */
150
151 regflags |= REGISTER;
152
153 for (i = 0; i < ARRAY_SIZE(specific_registers); i++)
154 if (!(specific_registers[i].flags & ~regflags))
155 return specific_registers[i].reg;
156
157 /* All the entries below look up regval in an 16-entry array */
158 if (regval < 0 || regval > (rex & REX_EV ? 31 : 15))
159 return 0;
160
161 #define GET_REGISTER(__array, __index) \
162 ((size_t)(__index) < (size_t)ARRAY_SIZE(__array) ? __array[(__index)] : 0)
163
164 if (!(REG8 & ~regflags)) {
165 if (rex & (REX_P|REX_NH))
166 return GET_REGISTER(nasm_rd_reg8_rex, regval);
167 else
168 return GET_REGISTER(nasm_rd_reg8, regval);
169 }
170 if (!(REG16 & ~regflags))
171 return GET_REGISTER(nasm_rd_reg16, regval);
172 if (!(REG32 & ~regflags))
173 return GET_REGISTER(nasm_rd_reg32, regval);
174 if (!(REG64 & ~regflags))
175 return GET_REGISTER(nasm_rd_reg64, regval);
176 if (!(REG_SREG & ~regflags))
177 return GET_REGISTER(nasm_rd_sreg, regval & 7); /* Ignore REX */
178 if (!(REG_CREG & ~regflags))
179 return GET_REGISTER(nasm_rd_creg, regval);
180 if (!(REG_DREG & ~regflags))
181 return GET_REGISTER(nasm_rd_dreg, regval);
182 if (!(REG_TREG & ~regflags)) {
183 if (regval > 7)
184 return 0; /* TR registers are ill-defined with rex */
185 return GET_REGISTER(nasm_rd_treg, regval);
186 }
187 if (!(FPUREG & ~regflags))
188 return GET_REGISTER(nasm_rd_fpureg, regval & 7); /* Ignore REX */
189 if (!(MMXREG & ~regflags))
190 return GET_REGISTER(nasm_rd_mmxreg, regval & 7); /* Ignore REX */
191 if (!(XMMREG & ~regflags))
192 return GET_REGISTER(nasm_rd_xmmreg, regval);
193 if (!(YMMREG & ~regflags))
194 return GET_REGISTER(nasm_rd_ymmreg, regval);
195 if (!(ZMMREG & ~regflags))
196 return GET_REGISTER(nasm_rd_zmmreg, regval);
197 if (!(OPMASKREG & ~regflags))
198 return GET_REGISTER(nasm_rd_opmaskreg, regval);
199 if (!(BNDREG & ~regflags))
200 return GET_REGISTER(nasm_rd_bndreg, regval);
201
202 #undef GET_REGISTER
203 return 0;
204 }
205
206 static uint32_t append_evex_reg_deco(char *buf, uint32_t num,
207 decoflags_t deco, uint8_t *evex)
208 {
209 const char * const er_names[] = {"rn-sae", "rd-sae", "ru-sae", "rz-sae"};
210 uint32_t num_chars = 0;
211
212 if ((deco & MASK) && (evex[2] & EVEX_P2AAA)) {
213 enum reg_enum opmasknum = nasm_rd_opmaskreg[evex[2] & EVEX_P2AAA];
214 const char * regname = nasm_reg_names[opmasknum - EXPR_REG_START];
215
216 num_chars += snprintf(buf + num_chars, num - num_chars,
217 "{%s}", regname);
218
219 if ((deco & Z) && (evex[2] & EVEX_P2Z)) {
220 num_chars += snprintf(buf + num_chars, num - num_chars,
221 "{z}");
222 }
223 }
224
225 if (evex[2] & EVEX_P2B) {
226 if (deco & ER) {
227 uint8_t er_type = (evex[2] & EVEX_P2LL) >> 5;
228 num_chars += snprintf(buf + num_chars, num - num_chars,
229 ",{%s}", er_names[er_type]);
230 } else if (deco & SAE) {
231 num_chars += snprintf(buf + num_chars, num - num_chars,
232 ",{sae}");
233 }
234 }
235
236 return num_chars;
237 }
238
239 static uint32_t append_evex_mem_deco(char *buf, uint32_t num, opflags_t type,
240 decoflags_t deco, uint8_t *evex)
241 {
242 uint32_t num_chars = 0;
243
244 if ((evex[2] & EVEX_P2B) && (deco & BRDCAST_MASK)) {
245 decoflags_t deco_brsize = deco & BRSIZE_MASK;
246 opflags_t template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
247 uint8_t br_num = (type & SIZE_MASK) / BITS128 *
248 BITS64 / template_opsize * 2;
249
250 num_chars += snprintf(buf + num_chars, num - num_chars,
251 "{1to%d}", br_num);
252 }
253
254 if ((deco & MASK) && (evex[2] & EVEX_P2AAA)) {
255 enum reg_enum opmasknum = nasm_rd_opmaskreg[evex[2] & EVEX_P2AAA];
256 const char * regname = nasm_reg_names[opmasknum - EXPR_REG_START];
257
258 num_chars += snprintf(buf + num_chars, num - num_chars,
259 "{%s}", regname);
260
261 if ((deco & Z) && (evex[2] & EVEX_P2Z)) {
262 num_chars += snprintf(buf + num_chars, num - num_chars,
263 "{z}");
264 }
265 }
266
267
268 return num_chars;
269 }
270
271 /*
272 * Process an effective address (ModRM) specification.
273 */
274 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
275 int segsize, enum ea_type type,
276 operand *op, insn *ins)
277 {
278 int mod, rm, scale, index, base;
279 int rex;
280 uint8_t *evex;
281 uint8_t sib = 0;
282 bool is_evex = !!(ins->rex & REX_EV);
283
284 mod = (modrm >> 6) & 03;
285 rm = modrm & 07;
286
287 if (mod != 3 && asize != 16 && rm == 4)
288 sib = *data++;
289
290 rex = ins->rex;
291 evex = ins->evex_p;
292
293 if (mod == 3) { /* pure register version */
294 op->basereg = rm+(rex & REX_B ? 8 : 0);
295 op->segment |= SEG_RMREG;
296 if (is_evex && segsize == 64) {
297 op->basereg += (evex[0] & EVEX_P0X ? 0 : 16);
298 }
299 return data;
300 }
301
302 op->disp_size = 0;
303 op->eaflags = 0;
304
305 if (asize == 16) {
306 /*
307 * <mod> specifies the displacement size (none, byte or
308 * word), and <rm> specifies the register combination.
309 * Exception: mod=0,rm=6 does not specify [BP] as one might
310 * expect, but instead specifies [disp16].
311 */
312
313 if (type != EA_SCALAR)
314 return NULL;
315
316 op->indexreg = op->basereg = -1;
317 op->scale = 1; /* always, in 16 bits */
318 switch (rm) {
319 case 0:
320 op->basereg = R_BX;
321 op->indexreg = R_SI;
322 break;
323 case 1:
324 op->basereg = R_BX;
325 op->indexreg = R_DI;
326 break;
327 case 2:
328 op->basereg = R_BP;
329 op->indexreg = R_SI;
330 break;
331 case 3:
332 op->basereg = R_BP;
333 op->indexreg = R_DI;
334 break;
335 case 4:
336 op->basereg = R_SI;
337 break;
338 case 5:
339 op->basereg = R_DI;
340 break;
341 case 6:
342 op->basereg = R_BP;
343 break;
344 case 7:
345 op->basereg = R_BX;
346 break;
347 }
348 if (rm == 6 && mod == 0) { /* special case */
349 op->basereg = -1;
350 if (segsize != 16)
351 op->disp_size = 16;
352 mod = 2; /* fake disp16 */
353 }
354 switch (mod) {
355 case 0:
356 op->segment |= SEG_NODISP;
357 break;
358 case 1:
359 op->segment |= SEG_DISP8;
360 if (ins->evex_tuple != 0) {
361 op->offset = gets8(data) * get_disp8N(ins);
362 } else {
363 op->offset = gets8(data);
364 }
365 data++;
366 break;
367 case 2:
368 op->segment |= SEG_DISP16;
369 op->offset = *data++;
370 op->offset |= ((unsigned)*data++) << 8;
371 break;
372 }
373 return data;
374 } else {
375 /*
376 * Once again, <mod> specifies displacement size (this time
377 * none, byte or *dword*), while <rm> specifies the base
378 * register. Again, [EBP] is missing, replaced by a pure
379 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
380 * and RIP-relative addressing in 64-bit mode.
381 *
382 * However, rm=4
383 * indicates not a single base register, but instead the
384 * presence of a SIB byte...
385 */
386 int a64 = asize == 64;
387
388 op->indexreg = -1;
389
390 if (a64)
391 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
392 else
393 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
394
395 if (rm == 5 && mod == 0) {
396 if (segsize == 64) {
397 op->eaflags |= EAF_REL;
398 op->segment |= SEG_RELATIVE;
399 mod = 2; /* fake disp32 */
400 }
401
402 if (asize != 64)
403 op->disp_size = asize;
404
405 op->basereg = -1;
406 mod = 2; /* fake disp32 */
407 }
408
409
410 if (rm == 4) { /* process SIB */
411 uint8_t vsib_hi = 0;
412 scale = (sib >> 6) & 03;
413 index = (sib >> 3) & 07;
414 base = sib & 07;
415
416 op->scale = 1 << scale;
417
418 if (segsize == 64) {
419 vsib_hi = (rex & REX_X ? 8 : 0) |
420 (evex[2] & EVEX_P2VP ? 0 : 16);
421 }
422
423 if (type == EA_XMMVSIB)
424 op->indexreg = nasm_rd_xmmreg[index | vsib_hi];
425 else if (type == EA_YMMVSIB)
426 op->indexreg = nasm_rd_ymmreg[index | vsib_hi];
427 else if (type == EA_ZMMVSIB)
428 op->indexreg = nasm_rd_zmmreg[index | vsib_hi];
429 else if (index == 4 && !(rex & REX_X))
430 op->indexreg = -1; /* ESP/RSP cannot be an index */
431 else if (a64)
432 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
433 else
434 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
435
436 if (base == 5 && mod == 0) {
437 op->basereg = -1;
438 mod = 2; /* Fake disp32 */
439 } else if (a64)
440 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
441 else
442 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
443
444 if (segsize == 16)
445 op->disp_size = 32;
446 } else if (type != EA_SCALAR) {
447 /* Can't have VSIB without SIB */
448 return NULL;
449 }
450
451 switch (mod) {
452 case 0:
453 op->segment |= SEG_NODISP;
454 break;
455 case 1:
456 op->segment |= SEG_DISP8;
457 if (ins->evex_tuple != 0) {
458 op->offset = gets8(data) * get_disp8N(ins);
459 } else {
460 op->offset = gets8(data);
461 }
462 data++;
463 break;
464 case 2:
465 op->segment |= SEG_DISP32;
466 op->offset = gets32(data);
467 data += 4;
468 break;
469 }
470 return data;
471 }
472 }
473
474 /*
475 * Determine whether the instruction template in t corresponds to the data
476 * stream in data. Return the number of bytes matched if so.
477 */
478 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
479
480 static int matches(const struct itemplate *t, uint8_t *data,
481 const struct prefix_info *prefix, int segsize, insn *ins)
482 {
483 uint8_t *r = (uint8_t *)(t->code);
484 uint8_t *origdata = data;
485 bool a_used = false, o_used = false;
486 enum prefixes drep = 0;
487 enum prefixes dwait = 0;
488 uint8_t lock = prefix->lock;
489 int osize = prefix->osize;
490 int asize = prefix->asize;
491 int i, c;
492 int op1, op2;
493 struct operand *opx, *opy;
494 uint8_t opex = 0;
495 bool vex_ok = false;
496 int regmask = (segsize == 64) ? 15 : 7;
497 enum ea_type eat = EA_SCALAR;
498
499 for (i = 0; i < MAX_OPERANDS; i++) {
500 ins->oprs[i].segment = ins->oprs[i].disp_size =
501 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
502 }
503 ins->condition = -1;
504 ins->evex_tuple = 0;
505 ins->rex = prefix->rex;
506 memset(ins->prefixes, 0, sizeof ins->prefixes);
507
508 if (itemp_has(t, (segsize == 64 ? IF_NOLONG : IF_LONG)))
509 return 0;
510
511 if (prefix->rep == 0xF2)
512 drep = (itemp_has(t, IF_BND) ? P_BND : P_REPNE);
513 else if (prefix->rep == 0xF3)
514 drep = P_REP;
515
516 dwait = prefix->wait ? P_WAIT : 0;
517
518 while ((c = *r++) != 0) {
519 op1 = (c & 3) + ((opex & 1) << 2);
520 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
521 opx = &ins->oprs[op1];
522 opy = &ins->oprs[op2];
523 opex = 0;
524
525 switch (c) {
526 case 01:
527 case 02:
528 case 03:
529 case 04:
530 while (c--)
531 if (*r++ != *data++)
532 return 0;
533 break;
534
535 case 05:
536 case 06:
537 case 07:
538 opex = c;
539 break;
540
541 case4(010):
542 {
543 int t = *r++, d = *data++;
544 if (d < t || d > t + 7)
545 return 0;
546 else {
547 opx->basereg = (d-t)+
548 (ins->rex & REX_B ? 8 : 0);
549 opx->segment |= SEG_RMREG;
550 }
551 break;
552 }
553
554 case4(014):
555 /* this is an separate index reg position of MIB operand (ICC) */
556 /* Disassembler uses NASM's split EA form only */
557 break;
558
559 case4(0274):
560 opx->offset = (int8_t)*data++;
561 opx->segment |= SEG_SIGNED;
562 break;
563
564 case4(020):
565 opx->offset = *data++;
566 break;
567
568 case4(024):
569 opx->offset = *data++;
570 break;
571
572 case4(030):
573 opx->offset = getu16(data);
574 data += 2;
575 break;
576
577 case4(034):
578 if (osize == 32) {
579 opx->offset = getu32(data);
580 data += 4;
581 } else {
582 opx->offset = getu16(data);
583 data += 2;
584 }
585 if (segsize != asize)
586 opx->disp_size = asize;
587 break;
588
589 case4(040):
590 opx->offset = getu32(data);
591 data += 4;
592 break;
593
594 case4(0254):
595 opx->offset = gets32(data);
596 data += 4;
597 break;
598
599 case4(044):
600 switch (asize) {
601 case 16:
602 opx->offset = getu16(data);
603 data += 2;
604 if (segsize != 16)
605 opx->disp_size = 16;
606 break;
607 case 32:
608 opx->offset = getu32(data);
609 data += 4;
610 if (segsize == 16)
611 opx->disp_size = 32;
612 break;
613 case 64:
614 opx->offset = getu64(data);
615 opx->disp_size = 64;
616 data += 8;
617 break;
618 }
619 break;
620
621 case4(050):
622 opx->offset = gets8(data++);
623 opx->segment |= SEG_RELATIVE;
624 break;
625
626 case4(054):
627 opx->offset = getu64(data);
628 data += 8;
629 break;
630
631 case4(060):
632 opx->offset = gets16(data);
633 data += 2;
634 opx->segment |= SEG_RELATIVE;
635 opx->segment &= ~SEG_32BIT;
636 break;
637
638 case4(064): /* rel */
639 opx->segment |= SEG_RELATIVE;
640 /* In long mode rel is always 32 bits, sign extended. */
641 if (segsize == 64 || osize == 32) {
642 opx->offset = gets32(data);
643 data += 4;
644 if (segsize != 64)
645 opx->segment |= SEG_32BIT;
646 opx->type = (opx->type & ~SIZE_MASK)
647 | (segsize == 64 ? BITS64 : BITS32);
648 } else {
649 opx->offset = gets16(data);
650 data += 2;
651 opx->segment &= ~SEG_32BIT;
652 opx->type = (opx->type & ~SIZE_MASK) | BITS16;
653 }
654 break;
655
656 case4(070):
657 opx->offset = gets32(data);
658 data += 4;
659 opx->segment |= SEG_32BIT | SEG_RELATIVE;
660 break;
661
662 case4(0100):
663 case4(0110):
664 case4(0120):
665 case4(0130):
666 {
667 int modrm = *data++;
668 opx->segment |= SEG_RMREG;
669 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
670 if (!data)
671 return 0;
672 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
673 if ((ins->rex & REX_EV) && (segsize == 64))
674 opx->basereg += (ins->evex_p[0] & EVEX_P0RP ? 0 : 16);
675 break;
676 }
677
678 case 0172:
679 {
680 uint8_t ximm = *data++;
681 c = *r++;
682 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
683 ins->oprs[c >> 3].segment |= SEG_RMREG;
684 ins->oprs[c & 7].offset = ximm & 15;
685 }
686 break;
687
688 case 0173:
689 {
690 uint8_t ximm = *data++;
691 c = *r++;
692
693 if ((c ^ ximm) & 15)
694 return 0;
695
696 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
697 ins->oprs[c >> 4].segment |= SEG_RMREG;
698 }
699 break;
700
701 case4(0174):
702 {
703 uint8_t ximm = *data++;
704
705 opx->basereg = (ximm >> 4) & regmask;
706 opx->segment |= SEG_RMREG;
707 }
708 break;
709
710 case4(0200):
711 case4(0204):
712 case4(0210):
713 case4(0214):
714 case4(0220):
715 case4(0224):
716 case4(0230):
717 case4(0234):
718 {
719 int modrm = *data++;
720 if (((modrm >> 3) & 07) != (c & 07))
721 return 0; /* spare field doesn't match up */
722 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
723 if (!data)
724 return 0;
725 break;
726 }
727
728 case4(0240):
729 case 0250:
730 {
731 uint8_t evexm = *r++;
732 uint8_t evexwlp = *r++;
733 uint8_t modrm, valid_mask;
734 ins->evex_tuple = *r++ - 0300;
735 modrm = *(origdata + 1);
736
737 ins->rex |= REX_EV;
738 if ((prefix->rex & (REX_EV|REX_V|REX_P)) != REX_EV)
739 return 0;
740
741 if ((evexm & 0x1f) != prefix->vex_m)
742 return 0;
743
744 switch (evexwlp & 060) {
745 case 000:
746 if (prefix->rex & REX_W)
747 return 0;
748 break;
749 case 020:
750 if (!(prefix->rex & REX_W))
751 return 0;
752 ins->rex |= REX_W;
753 break;
754 case 040: /* VEX.W is a don't care */
755 ins->rex &= ~REX_W;
756 break;
757 case 060:
758 break;
759 }
760
761 /* If EVEX.b is set with reg-reg op,
762 * EVEX.L'L contains embedded rounding control info
763 */
764 if ((prefix->evex[2] & EVEX_P2B) && ((modrm >> 6) == 3)) {
765 valid_mask = 0x3; /* prefix only */
766 } else {
767 valid_mask = 0xf; /* vector length and prefix */
768 }
769 if ((evexwlp ^ prefix->vex_lp) & valid_mask)
770 return 0;
771
772 if (c == 0250) {
773 if ((prefix->vex_v != 0) ||
774 (!(prefix->evex[2] & EVEX_P2VP) &&
775 ((eat < EA_XMMVSIB) || (eat > EA_ZMMVSIB))))
776 return 0;
777 } else {
778 opx->segment |= SEG_RMREG;
779 opx->basereg = ((~prefix->evex[2] & EVEX_P2VP) << (4 - 3) ) |
780 prefix->vex_v;
781 }
782 vex_ok = true;
783 memcpy(ins->evex_p, prefix->evex, 3);
784 break;
785 }
786
787 case4(0260):
788 case 0270:
789 {
790 int vexm = *r++;
791 int vexwlp = *r++;
792
793 ins->rex |= REX_V;
794 if ((prefix->rex & (REX_V|REX_P)) != REX_V)
795 return 0;
796
797 if ((vexm & 0x1f) != prefix->vex_m)
798 return 0;
799
800 switch (vexwlp & 060) {
801 case 000:
802 if (prefix->rex & REX_W)
803 return 0;
804 break;
805 case 020:
806 if (!(prefix->rex & REX_W))
807 return 0;
808 ins->rex &= ~REX_W;
809 break;
810 case 040: /* VEX.W is a don't care */
811 ins->rex &= ~REX_W;
812 break;
813 case 060:
814 break;
815 }
816
817 /* The 010 bit of vexwlp is set if VEX.L is ignored */
818 if ((vexwlp ^ prefix->vex_lp) & ((vexwlp & 010) ? 03 : 07))
819 return 0;
820
821 if (c == 0270) {
822 if (prefix->vex_v != 0)
823 return 0;
824 } else {
825 opx->segment |= SEG_RMREG;
826 opx->basereg = prefix->vex_v;
827 }
828 vex_ok = true;
829 break;
830 }
831
832 case 0271:
833 if (prefix->rep == 0xF3)
834 drep = P_XRELEASE;
835 break;
836
837 case 0272:
838 if (prefix->rep == 0xF2)
839 drep = P_XACQUIRE;
840 else if (prefix->rep == 0xF3)
841 drep = P_XRELEASE;
842 break;
843
844 case 0273:
845 if (prefix->lock == 0xF0) {
846 if (prefix->rep == 0xF2)
847 drep = P_XACQUIRE;
848 else if (prefix->rep == 0xF3)
849 drep = P_XRELEASE;
850 }
851 break;
852
853 case 0310:
854 if (asize != 16)
855 return 0;
856 else
857 a_used = true;
858 break;
859
860 case 0311:
861 if (asize != 32)
862 return 0;
863 else
864 a_used = true;
865 break;
866
867 case 0312:
868 if (asize != segsize)
869 return 0;
870 else
871 a_used = true;
872 break;
873
874 case 0313:
875 if (asize != 64)
876 return 0;
877 else
878 a_used = true;
879 break;
880
881 case 0314:
882 if (prefix->rex & REX_B)
883 return 0;
884 break;
885
886 case 0315:
887 if (prefix->rex & REX_X)
888 return 0;
889 break;
890
891 case 0316:
892 if (prefix->rex & REX_R)
893 return 0;
894 break;
895
896 case 0317:
897 if (prefix->rex & REX_W)
898 return 0;
899 break;
900
901 case 0320:
902 if (osize != 16)
903 return 0;
904 else
905 o_used = true;
906 break;
907
908 case 0321:
909 if (osize != 32)
910 return 0;
911 else
912 o_used = true;
913 break;
914
915 case 0322:
916 if (osize != (segsize == 16) ? 16 : 32)
917 return 0;
918 else
919 o_used = true;
920 break;
921
922 case 0323:
923 ins->rex |= REX_W; /* 64-bit only instruction */
924 osize = 64;
925 o_used = true;
926 break;
927
928 case 0324:
929 if (osize != 64)
930 return 0;
931 o_used = true;
932 break;
933
934 case 0325:
935 ins->rex |= REX_NH;
936 break;
937
938 case 0330:
939 {
940 int t = *r++, d = *data++;
941 if (d < t || d > t + 15)
942 return 0;
943 else
944 ins->condition = d - t;
945 break;
946 }
947
948 case 0326:
949 if (prefix->rep == 0xF3)
950 return 0;
951 break;
952
953 case 0331:
954 if (prefix->rep)
955 return 0;
956 break;
957
958 case 0332:
959 if (prefix->rep != 0xF2)
960 return 0;
961 drep = 0;
962 break;
963
964 case 0333:
965 if (prefix->rep != 0xF3)
966 return 0;
967 drep = 0;
968 break;
969
970 case 0334:
971 if (lock) {
972 ins->rex |= REX_R;
973 lock = 0;
974 }
975 break;
976
977 case 0335:
978 if (drep == P_REP)
979 drep = P_REPE;
980 break;
981
982 case 0336:
983 case 0337:
984 break;
985
986 case 0340:
987 return 0;
988
989 case 0341:
990 if (prefix->wait != 0x9B)
991 return 0;
992 dwait = 0;
993 break;
994
995 case 0360:
996 if (prefix->osp || prefix->rep)
997 return 0;
998 break;
999
1000 case 0361:
1001 if (!prefix->osp || prefix->rep)
1002 return 0;
1003 o_used = true;
1004 break;
1005
1006 case 0364:
1007 if (prefix->osp)
1008 return 0;
1009 break;
1010
1011 case 0365:
1012 if (prefix->asp)
1013 return 0;
1014 break;
1015
1016 case 0366:
1017 if (!prefix->osp)
1018 return 0;
1019 o_used = true;
1020 break;
1021
1022 case 0367:
1023 if (!prefix->asp)
1024 return 0;
1025 a_used = true;
1026 break;
1027
1028 case 0370:
1029 case 0371:
1030 break;
1031
1032 case 0374:
1033 eat = EA_XMMVSIB;
1034 break;
1035
1036 case 0375:
1037 eat = EA_YMMVSIB;
1038 break;
1039
1040 case 0376:
1041 eat = EA_ZMMVSIB;
1042 break;
1043
1044 default:
1045 return 0; /* Unknown code */
1046 }
1047 }
1048
1049 if (!vex_ok && (ins->rex & (REX_V | REX_EV)))
1050 return 0;
1051
1052 /* REX cannot be combined with VEX */
1053 if ((ins->rex & REX_V) && (prefix->rex & REX_P))
1054 return 0;
1055
1056 /*
1057 * Check for unused rep or a/o prefixes.
1058 */
1059 for (i = 0; i < t->operands; i++) {
1060 if (ins->oprs[i].segment != SEG_RMREG)
1061 a_used = true;
1062 }
1063
1064 if (lock) {
1065 if (ins->prefixes[PPS_LOCK])
1066 return 0;
1067 ins->prefixes[PPS_LOCK] = P_LOCK;
1068 }
1069 if (drep) {
1070 if (ins->prefixes[PPS_REP])
1071 return 0;
1072 ins->prefixes[PPS_REP] = drep;
1073 }
1074 ins->prefixes[PPS_WAIT] = dwait;
1075 if (!o_used) {
1076 if (osize != ((segsize == 16) ? 16 : 32)) {
1077 enum prefixes pfx = 0;
1078
1079 switch (osize) {
1080 case 16:
1081 pfx = P_O16;
1082 break;
1083 case 32:
1084 pfx = P_O32;
1085 break;
1086 case 64:
1087 pfx = P_O64;
1088 break;
1089 }
1090
1091 if (ins->prefixes[PPS_OSIZE])
1092 return 0;
1093 ins->prefixes[PPS_OSIZE] = pfx;
1094 }
1095 }
1096 if (!a_used && asize != segsize) {
1097 if (ins->prefixes[PPS_ASIZE])
1098 return 0;
1099 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
1100 }
1101
1102 /* Fix: check for redundant REX prefixes */
1103
1104 return data - origdata;
1105 }
1106
1107 /* Condition names for disassembly, sorted by x86 code */
1108 static const char * const condition_name[16] = {
1109 "o", "no", "c", "nc", "z", "nz", "na", "a",
1110 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
1111 };
1112
1113 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
1114 int32_t offset, int autosync, iflag_t *prefer)
1115 {
1116 const struct itemplate * const *p, * const *best_p;
1117 const struct disasm_index *ix;
1118 uint8_t *dp;
1119 int length, best_length = 0;
1120 char *segover;
1121 int i, slen, colon, n;
1122 uint8_t *origdata;
1123 int works;
1124 insn tmp_ins, ins;
1125 iflag_t goodness, best;
1126 int best_pref;
1127 struct prefix_info prefix;
1128 bool end_prefix;
1129 bool is_evex;
1130
1131 memset(&ins, 0, sizeof ins);
1132
1133 /*
1134 * Scan for prefixes.
1135 */
1136 memset(&prefix, 0, sizeof prefix);
1137 prefix.asize = segsize;
1138 prefix.osize = (segsize == 64) ? 32 : segsize;
1139 segover = NULL;
1140 origdata = data;
1141
1142 ix = itable;
1143
1144 end_prefix = false;
1145 while (!end_prefix) {
1146 switch (*data) {
1147 case 0xF2:
1148 case 0xF3:
1149 prefix.rep = *data++;
1150 break;
1151
1152 case 0x9B:
1153 prefix.wait = *data++;
1154 break;
1155
1156 case 0xF0:
1157 prefix.lock = *data++;
1158 break;
1159
1160 case 0x2E:
1161 segover = "cs", prefix.seg = *data++;
1162 break;
1163 case 0x36:
1164 segover = "ss", prefix.seg = *data++;
1165 break;
1166 case 0x3E:
1167 segover = "ds", prefix.seg = *data++;
1168 break;
1169 case 0x26:
1170 segover = "es", prefix.seg = *data++;
1171 break;
1172 case 0x64:
1173 segover = "fs", prefix.seg = *data++;
1174 break;
1175 case 0x65:
1176 segover = "gs", prefix.seg = *data++;
1177 break;
1178
1179 case 0x66:
1180 prefix.osize = (segsize == 16) ? 32 : 16;
1181 prefix.osp = *data++;
1182 break;
1183 case 0x67:
1184 prefix.asize = (segsize == 32) ? 16 : 32;
1185 prefix.asp = *data++;
1186 break;
1187
1188 case 0xC4:
1189 case 0xC5:
1190 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1191 prefix.vex[0] = *data++;
1192 prefix.vex[1] = *data++;
1193
1194 prefix.rex = REX_V;
1195 prefix.vex_c = RV_VEX;
1196
1197 if (prefix.vex[0] == 0xc4) {
1198 prefix.vex[2] = *data++;
1199 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1200 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1201 prefix.vex_m = prefix.vex[1] & 0x1f;
1202 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1203 prefix.vex_lp = prefix.vex[2] & 7;
1204 } else {
1205 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1206 prefix.vex_m = 1;
1207 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1208 prefix.vex_lp = prefix.vex[1] & 7;
1209 }
1210
1211 ix = itable_vex[RV_VEX][prefix.vex_m][prefix.vex_lp & 3];
1212 }
1213 end_prefix = true;
1214 break;
1215
1216 case 0x62:
1217 {
1218 if (segsize == 64 || ((data[1] & 0xc0) == 0xc0)) {
1219 data++; /* 62h EVEX prefix */
1220 prefix.evex[0] = *data++;
1221 prefix.evex[1] = *data++;
1222 prefix.evex[2] = *data++;
1223
1224 prefix.rex = REX_EV;
1225 prefix.vex_c = RV_EVEX;
1226 prefix.rex |= (~prefix.evex[0] >> 5) & 7; /* REX_RXB */
1227 prefix.rex |= (prefix.evex[1] >> (7-3)) & REX_W;
1228 prefix.vex_m = prefix.evex[0] & EVEX_P0MM;
1229 prefix.vex_v = (~prefix.evex[1] & EVEX_P1VVVV) >> 3;
1230 prefix.vex_lp = ((prefix.evex[2] & EVEX_P2LL) >> (5-2)) |
1231 (prefix.evex[1] & EVEX_P1PP);
1232
1233 ix = itable_vex[prefix.vex_c][prefix.vex_m][prefix.vex_lp & 3];
1234 }
1235 end_prefix = true;
1236 break;
1237 }
1238
1239 case 0x8F:
1240 if ((data[1] & 030) != 0 &&
1241 (segsize == 64 || (data[1] & 0xc0) == 0xc0)) {
1242 prefix.vex[0] = *data++;
1243 prefix.vex[1] = *data++;
1244 prefix.vex[2] = *data++;
1245
1246 prefix.rex = REX_V;
1247 prefix.vex_c = RV_XOP;
1248
1249 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1250 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1251 prefix.vex_m = prefix.vex[1] & 0x1f;
1252 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1253 prefix.vex_lp = prefix.vex[2] & 7;
1254
1255 ix = itable_vex[RV_XOP][prefix.vex_m][prefix.vex_lp & 3];
1256 }
1257 end_prefix = true;
1258 break;
1259
1260 case REX_P + 0x0:
1261 case REX_P + 0x1:
1262 case REX_P + 0x2:
1263 case REX_P + 0x3:
1264 case REX_P + 0x4:
1265 case REX_P + 0x5:
1266 case REX_P + 0x6:
1267 case REX_P + 0x7:
1268 case REX_P + 0x8:
1269 case REX_P + 0x9:
1270 case REX_P + 0xA:
1271 case REX_P + 0xB:
1272 case REX_P + 0xC:
1273 case REX_P + 0xD:
1274 case REX_P + 0xE:
1275 case REX_P + 0xF:
1276 if (segsize == 64) {
1277 prefix.rex = *data++;
1278 if (prefix.rex & REX_W)
1279 prefix.osize = 64;
1280 }
1281 end_prefix = true;
1282 break;
1283
1284 default:
1285 end_prefix = true;
1286 break;
1287 }
1288 }
1289
1290 iflag_set_all(&best); /* Worst possible */
1291 best_p = NULL;
1292 best_pref = INT_MAX;
1293
1294 if (!ix)
1295 return 0; /* No instruction table at all... */
1296
1297 dp = data;
1298 ix += *dp++;
1299 while (ix->n == -1) {
1300 ix = (const struct disasm_index *)ix->p + *dp++;
1301 }
1302
1303 p = (const struct itemplate * const *)ix->p;
1304 for (n = ix->n; n; n--, p++) {
1305 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1306 works = true;
1307 /*
1308 * Final check to make sure the types of r/m match up.
1309 * XXX: Need to make sure this is actually correct.
1310 */
1311 for (i = 0; i < (*p)->operands; i++) {
1312 if (
1313 /* If it's a mem-only EA but we have a
1314 register, die. */
1315 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1316 is_class(MEMORY, (*p)->opd[i])) ||
1317 /* If it's a reg-only EA but we have a memory
1318 ref, die. */
1319 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1320 !(REG_EA & ~(*p)->opd[i]) &&
1321 !((*p)->opd[i] & REG_SMASK)) ||
1322 /* Register type mismatch (eg FS vs REG_DESS):
1323 die. */
1324 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1325 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1326 !whichreg((*p)->opd[i],
1327 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1328 ) {
1329 works = false;
1330 break;
1331 }
1332 }
1333
1334 /*
1335 * Note: we always prefer instructions which incorporate
1336 * prefixes in the instructions themselves. This is to allow
1337 * e.g. PAUSE to be preferred to REP NOP, and deal with
1338 * MMX/SSE instructions where prefixes are used to select
1339 * between MMX and SSE register sets or outright opcode
1340 * selection.
1341 */
1342 if (works) {
1343 int i, nprefix;
1344 goodness = iflag_pfmask(*p);
1345 goodness = iflag_xor(&goodness, prefer);
1346 nprefix = 0;
1347 for (i = 0; i < MAXPREFIX; i++)
1348 if (tmp_ins.prefixes[i])
1349 nprefix++;
1350 if (nprefix < best_pref ||
1351 (nprefix == best_pref &&
1352 iflag_cmp(&goodness, &best) < 0)) {
1353 /* This is the best one found so far */
1354 best = goodness;
1355 best_p = p;
1356 best_pref = nprefix;
1357 best_length = length;
1358 ins = tmp_ins;
1359 }
1360 }
1361 }
1362 }
1363
1364 if (!best_p)
1365 return 0; /* no instruction was matched */
1366
1367 /* Pick the best match */
1368 p = best_p;
1369 length = best_length;
1370
1371 slen = 0;
1372
1373 /* TODO: snprintf returns the value that the string would have if
1374 * the buffer were long enough, and not the actual length of
1375 * the returned string, so each instance of using the return
1376 * value of snprintf should actually be checked to assure that
1377 * the return value is "sane." Maybe a macro wrapper could
1378 * be used for that purpose.
1379 */
1380 for (i = 0; i < MAXPREFIX; i++) {
1381 const char *prefix = prefix_name(ins.prefixes[i]);
1382 if (prefix)
1383 slen += snprintf(output+slen, outbufsize-slen, "%s ", prefix);
1384 }
1385
1386 i = (*p)->opcode;
1387 if (i >= FIRST_COND_OPCODE)
1388 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1389 nasm_insn_names[i], condition_name[ins.condition]);
1390 else
1391 slen += snprintf(output + slen, outbufsize - slen, "%s",
1392 nasm_insn_names[i]);
1393
1394 colon = false;
1395 is_evex = !!(ins.rex & REX_EV);
1396 length += data - origdata; /* fix up for prefixes */
1397 for (i = 0; i < (*p)->operands; i++) {
1398 opflags_t t = (*p)->opd[i];
1399 decoflags_t deco = (*p)->deco[i];
1400 const operand *o = &ins.oprs[i];
1401 int64_t offs;
1402
1403 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1404
1405 offs = o->offset;
1406 if (o->segment & SEG_RELATIVE) {
1407 offs += offset + length;
1408 /*
1409 * sort out wraparound
1410 */
1411 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1412 offs &= 0xffff;
1413 else if (segsize != 64)
1414 offs &= 0xffffffff;
1415
1416 /*
1417 * add sync marker, if autosync is on
1418 */
1419 if (autosync)
1420 add_sync(offs, 0L);
1421 }
1422
1423 if (t & COLON)
1424 colon = true;
1425 else
1426 colon = false;
1427
1428 if ((t & (REGISTER | FPUREG)) ||
1429 (o->segment & SEG_RMREG)) {
1430 enum reg_enum reg;
1431 reg = whichreg(t, o->basereg, ins.rex);
1432 if (t & TO)
1433 slen += snprintf(output + slen, outbufsize - slen, "to ");
1434 slen += snprintf(output + slen, outbufsize - slen, "%s",
1435 nasm_reg_names[reg-EXPR_REG_START]);
1436 if (is_evex && deco)
1437 slen += append_evex_reg_deco(output + slen, outbufsize - slen,
1438 deco, ins.evex_p);
1439 } else if (!(UNITY & ~t)) {
1440 output[slen++] = '1';
1441 } else if (t & IMMEDIATE) {
1442 if (t & BITS8) {
1443 slen +=
1444 snprintf(output + slen, outbufsize - slen, "byte ");
1445 if (o->segment & SEG_SIGNED) {
1446 if (offs < 0) {
1447 offs *= -1;
1448 output[slen++] = '-';
1449 } else
1450 output[slen++] = '+';
1451 }
1452 } else if (t & BITS16) {
1453 slen +=
1454 snprintf(output + slen, outbufsize - slen, "word ");
1455 } else if (t & BITS32) {
1456 slen +=
1457 snprintf(output + slen, outbufsize - slen, "dword ");
1458 } else if (t & BITS64) {
1459 slen +=
1460 snprintf(output + slen, outbufsize - slen, "qword ");
1461 } else if (t & NEAR) {
1462 slen +=
1463 snprintf(output + slen, outbufsize - slen, "near ");
1464 } else if (t & SHORT) {
1465 slen +=
1466 snprintf(output + slen, outbufsize - slen, "short ");
1467 }
1468 slen +=
1469 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1470 offs);
1471 } else if (!(MEM_OFFS & ~t)) {
1472 slen +=
1473 snprintf(output + slen, outbufsize - slen,
1474 "[%s%s%s0x%"PRIx64"]",
1475 (segover ? segover : ""),
1476 (segover ? ":" : ""),
1477 (o->disp_size == 64 ? "qword " :
1478 o->disp_size == 32 ? "dword " :
1479 o->disp_size == 16 ? "word " : ""), offs);
1480 segover = NULL;
1481 } else if (is_class(REGMEM, t)) {
1482 int started = false;
1483 if (t & BITS8)
1484 slen +=
1485 snprintf(output + slen, outbufsize - slen, "byte ");
1486 if (t & BITS16)
1487 slen +=
1488 snprintf(output + slen, outbufsize - slen, "word ");
1489 if (t & BITS32)
1490 slen +=
1491 snprintf(output + slen, outbufsize - slen, "dword ");
1492 if (t & BITS64)
1493 slen +=
1494 snprintf(output + slen, outbufsize - slen, "qword ");
1495 if (t & BITS80)
1496 slen +=
1497 snprintf(output + slen, outbufsize - slen, "tword ");
1498 if ((ins.evex_p[2] & EVEX_P2B) && (deco & BRDCAST_MASK)) {
1499 /* when broadcasting, each element size should be used */
1500 if (deco & BR_BITS32)
1501 slen +=
1502 snprintf(output + slen, outbufsize - slen, "dword ");
1503 else if (deco & BR_BITS64)
1504 slen +=
1505 snprintf(output + slen, outbufsize - slen, "qword ");
1506 } else {
1507 if (t & BITS128)
1508 slen +=
1509 snprintf(output + slen, outbufsize - slen, "oword ");
1510 if (t & BITS256)
1511 slen +=
1512 snprintf(output + slen, outbufsize - slen, "yword ");
1513 if (t & BITS512)
1514 slen +=
1515 snprintf(output + slen, outbufsize - slen, "zword ");
1516 }
1517 if (t & FAR)
1518 slen += snprintf(output + slen, outbufsize - slen, "far ");
1519 if (t & NEAR)
1520 slen +=
1521 snprintf(output + slen, outbufsize - slen, "near ");
1522 output[slen++] = '[';
1523 if (o->disp_size)
1524 slen += snprintf(output + slen, outbufsize - slen, "%s",
1525 (o->disp_size == 64 ? "qword " :
1526 o->disp_size == 32 ? "dword " :
1527 o->disp_size == 16 ? "word " :
1528 ""));
1529 if (o->eaflags & EAF_REL)
1530 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1531 if (segover) {
1532 slen +=
1533 snprintf(output + slen, outbufsize - slen, "%s:",
1534 segover);
1535 segover = NULL;
1536 }
1537 if (o->basereg != -1) {
1538 slen += snprintf(output + slen, outbufsize - slen, "%s",
1539 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1540 started = true;
1541 }
1542 if (o->indexreg != -1 && !itemp_has(*best_p, IF_MIB)) {
1543 if (started)
1544 output[slen++] = '+';
1545 slen += snprintf(output + slen, outbufsize - slen, "%s",
1546 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1547 if (o->scale > 1)
1548 slen +=
1549 snprintf(output + slen, outbufsize - slen, "*%d",
1550 o->scale);
1551 started = true;
1552 }
1553
1554
1555 if (o->segment & SEG_DISP8) {
1556 if (is_evex) {
1557 const char *prefix;
1558 uint32_t offset = offs;
1559 if ((int32_t)offset < 0) {
1560 prefix = "-";
1561 offset = -offset;
1562 } else {
1563 prefix = "+";
1564 }
1565 slen +=
1566 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx32"",
1567 prefix, offset);
1568 } else {
1569 const char *prefix;
1570 uint8_t offset = offs;
1571 if ((int8_t)offset < 0) {
1572 prefix = "-";
1573 offset = -offset;
1574 } else {
1575 prefix = "+";
1576 }
1577 slen +=
1578 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1579 prefix, offset);
1580 }
1581 } else if (o->segment & SEG_DISP16) {
1582 const char *prefix;
1583 uint16_t offset = offs;
1584 if ((int16_t)offset < 0 && started) {
1585 offset = -offset;
1586 prefix = "-";
1587 } else {
1588 prefix = started ? "+" : "";
1589 }
1590 slen +=
1591 snprintf(output + slen, outbufsize - slen,
1592 "%s0x%"PRIx16"", prefix, offset);
1593 } else if (o->segment & SEG_DISP32) {
1594 if (prefix.asize == 64) {
1595 const char *prefix;
1596 uint64_t offset = (int64_t)(int32_t)offs;
1597 if ((int32_t)offs < 0 && started) {
1598 offset = -offset;
1599 prefix = "-";
1600 } else {
1601 prefix = started ? "+" : "";
1602 }
1603 slen +=
1604 snprintf(output + slen, outbufsize - slen,
1605 "%s0x%"PRIx64"", prefix, offset);
1606 } else {
1607 const char *prefix;
1608 uint32_t offset = offs;
1609 if ((int32_t) offset < 0 && started) {
1610 offset = -offset;
1611 prefix = "-";
1612 } else {
1613 prefix = started ? "+" : "";
1614 }
1615 slen +=
1616 snprintf(output + slen, outbufsize - slen,
1617 "%s0x%"PRIx32"", prefix, offset);
1618 }
1619 }
1620
1621 if (o->indexreg != -1 && itemp_has(*best_p, IF_MIB)) {
1622 output[slen++] = ',';
1623 slen += snprintf(output + slen, outbufsize - slen, "%s",
1624 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1625 if (o->scale > 1)
1626 slen +=
1627 snprintf(output + slen, outbufsize - slen, "*%d",
1628 o->scale);
1629 started = true;
1630 }
1631
1632 output[slen++] = ']';
1633
1634 if (is_evex && deco)
1635 slen += append_evex_mem_deco(output + slen, outbufsize - slen,
1636 t, deco, ins.evex_p);
1637 } else {
1638 slen +=
1639 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1640 i);
1641 }
1642 }
1643 output[slen] = '\0';
1644 if (segover) { /* unused segment override */
1645 char *p = output;
1646 int count = slen + 1;
1647 while (count--)
1648 p[count + 3] = p[count];
1649 strncpy(output, segover, 2);
1650 output[2] = ' ';
1651 }
1652 return length;
1653 }
1654
1655 /*
1656 * This is called when we don't have a complete instruction. If it
1657 * is a standalone *single-byte* prefix show it as such, otherwise
1658 * print it as a literal.
1659 */
1660 int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize)
1661 {
1662 uint8_t byte = *data;
1663 const char *str = NULL;
1664
1665 switch (byte) {
1666 case 0xF2:
1667 str = "repne";
1668 break;
1669 case 0xF3:
1670 str = "rep";
1671 break;
1672 case 0x9B:
1673 str = "wait";
1674 break;
1675 case 0xF0:
1676 str = "lock";
1677 break;
1678 case 0x2E:
1679 str = "cs";
1680 break;
1681 case 0x36:
1682 str = "ss";
1683 break;
1684 case 0x3E:
1685 str = "ds";
1686 break;
1687 case 0x26:
1688 str = "es";
1689 break;
1690 case 0x64:
1691 str = "fs";
1692 break;
1693 case 0x65:
1694 str = "gs";
1695 break;
1696 case 0x66:
1697 str = (segsize == 16) ? "o32" : "o16";
1698 break;
1699 case 0x67:
1700 str = (segsize == 32) ? "a16" : "a32";
1701 break;
1702 case REX_P + 0x0:
1703 case REX_P + 0x1:
1704 case REX_P + 0x2:
1705 case REX_P + 0x3:
1706 case REX_P + 0x4:
1707 case REX_P + 0x5:
1708 case REX_P + 0x6:
1709 case REX_P + 0x7:
1710 case REX_P + 0x8:
1711 case REX_P + 0x9:
1712 case REX_P + 0xA:
1713 case REX_P + 0xB:
1714 case REX_P + 0xC:
1715 case REX_P + 0xD:
1716 case REX_P + 0xE:
1717 case REX_P + 0xF:
1718 if (segsize == 64) {
1719 snprintf(output, outbufsize, "rex%s%s%s%s%s",
1720 (byte == REX_P) ? "" : ".",
1721 (byte & REX_W) ? "w" : "",
1722 (byte & REX_R) ? "r" : "",
1723 (byte & REX_X) ? "x" : "",
1724 (byte & REX_B) ? "b" : "");
1725 break;
1726 }
1727 /* else fall through */
1728 default:
1729 snprintf(output, outbufsize, "db 0x%02x", byte);
1730 break;
1731 }
1732
1733 if (str)
1734 snprintf(output, outbufsize, "%s", str);
1735
1736 return 1;
1737 }
The Netwide Assembler