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test: add test for cv8 structure bug (BR 3392342 and 3392343)
[nasm.git] / assemble.c
blobf051b26d81cca37aaabffd80bc7838b85801c158
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2016 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * Bytecode specification
38 * ----------------------
39 *
40 *
41 * Codes Mnemonic Explanation
42 *
43 * \0 terminates the code. (Unless it's a literal of course.)
44 * \1..\4 that many literal bytes follow in the code stream
45 * \5 add 4 to the primary operand number (b, low octdigit)
46 * \6 add 4 to the secondary operand number (a, middle octdigit)
47 * \7 add 4 to both the primary and the secondary operand number
48 * \10..\13 a literal byte follows in the code stream, to be added
49 * to the register value of operand 0..3
50 * \14..\17 the position of index register operand in MIB (BND insns)
51 * \20..\23 ib a byte immediate operand, from operand 0..3
52 * \24..\27 ib,u a zero-extended byte immediate operand, from operand 0..3
53 * \30..\33 iw a word immediate operand, from operand 0..3
54 * \34..\37 iwd select between \3[0-3] and \4[0-3] depending on 16/32 bit
55 * assembly mode or the operand-size override on the operand
56 * \40..\43 id a long immediate operand, from operand 0..3
57 * \44..\47 iwdq select between \3[0-3], \4[0-3] and \5[4-7]
58 * depending on the address size of the instruction.
59 * \50..\53 rel8 a byte relative operand, from operand 0..3
60 * \54..\57 iq a qword immediate operand, from operand 0..3
61 * \60..\63 rel16 a word relative operand, from operand 0..3
62 * \64..\67 rel select between \6[0-3] and \7[0-3] depending on 16/32 bit
63 * assembly mode or the operand-size override on the operand
64 * \70..\73 rel32 a long relative operand, from operand 0..3
65 * \74..\77 seg a word constant, from the _segment_ part of operand 0..3
66 * \1ab a ModRM, calculated on EA in operand a, with the spare
67 * field the register value of operand b.
68 * \172\ab the register number from operand a in bits 7..4, with
69 * the 4-bit immediate from operand b in bits 3..0.
70 * \173\xab the register number from operand a in bits 7..4, with
71 * the value b in bits 3..0.
72 * \174..\177 the register number from operand 0..3 in bits 7..4, and
73 * an arbitrary value in bits 3..0 (assembled as zero.)
74 * \2ab a ModRM, calculated on EA in operand a, with the spare
75 * field equal to digit b.
76 *
77 * \240..\243 this instruction uses EVEX rather than REX or VEX/XOP, with the
78 * V field taken from operand 0..3.
79 * \250 this instruction uses EVEX rather than REX or VEX/XOP, with the
80 * V field set to 1111b.
81 *
82 * EVEX prefixes are followed by the sequence:
83 * \cm\wlp\tup where cm is:
84 * cc 000 0mm
85 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
86 * and wlp is:
87 * 00 wwl lpp
88 * [l0] ll = 0 (.128, .lz)
89 * [l1] ll = 1 (.256)
90 * [l2] ll = 2 (.512)
91 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
92 *
93 * [w0] ww = 0 for W = 0
94 * [w1] ww = 1 for W = 1
95 * [wig] ww = 2 for W don't care (always assembled as 0)
96 * [ww] ww = 3 for W used as REX.W
97 *
98 * [p0] pp = 0 for no prefix
99 * [60] pp = 1 for legacy prefix 60
100 * [f3] pp = 2
101 * [f2] pp = 3
102 *
103 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
104 * (compressed displacement encoding)
105 *
106 * \254..\257 id,s a signed 32-bit operand to be extended to 64 bits.
107 * \260..\263 this instruction uses VEX/XOP rather than REX, with the
108 * V field taken from operand 0..3.
109 * \270 this instruction uses VEX/XOP rather than REX, with the
110 * V field set to 1111b.
111 *
112 * VEX/XOP prefixes are followed by the sequence:
113 * \tmm\wlp where mm is the M field; and wlp is:
114 * 00 wwl lpp
115 * [l0] ll = 0 for L = 0 (.128, .lz)
116 * [l1] ll = 1 for L = 1 (.256)
117 * [lig] ll = 2 for L don't care (always assembled as 0)
118 *
119 * [w0] ww = 0 for W = 0
120 * [w1 ] ww = 1 for W = 1
121 * [wig] ww = 2 for W don't care (always assembled as 0)
122 * [ww] ww = 3 for W used as REX.W
123 *
124 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
125 *
126 * \271 hlexr instruction takes XRELEASE (F3) with or without lock
127 * \272 hlenl instruction takes XACQUIRE/XRELEASE with or without lock
128 * \273 hle instruction takes XACQUIRE/XRELEASE with lock only
129 * \274..\277 ib,s a byte immediate operand, from operand 0..3, sign-extended
130 * to the operand size (if o16/o32/o64 present) or the bit size
131 * \310 a16 indicates fixed 16-bit address size, i.e. optional 0x67.
132 * \311 a32 indicates fixed 32-bit address size, i.e. optional 0x67.
133 * \312 adf (disassembler only) invalid with non-default address size.
134 * \313 a64 indicates fixed 64-bit address size, 0x67 invalid.
135 * \314 norexb (disassembler only) invalid with REX.B
136 * \315 norexx (disassembler only) invalid with REX.X
137 * \316 norexr (disassembler only) invalid with REX.R
138 * \317 norexw (disassembler only) invalid with REX.W
139 * \320 o16 indicates fixed 16-bit operand size, i.e. optional 0x66.
140 * \321 o32 indicates fixed 32-bit operand size, i.e. optional 0x66.
141 * \322 odf indicates that this instruction is only valid when the
142 * operand size is the default (instruction to disassembler,
143 * generates no code in the assembler)
144 * \323 o64nw indicates fixed 64-bit operand size, REX on extensions only.
145 * \324 o64 indicates 64-bit operand size requiring REX prefix.
146 * \325 nohi instruction which always uses spl/bpl/sil/dil
147 * \326 nof3 instruction not valid with 0xF3 REP prefix. Hint for
148 disassembler only; for SSE instructions.
149 * \330 a literal byte follows in the code stream, to be added
150 * to the condition code value of the instruction.
151 * \331 norep instruction not valid with REP prefix. Hint for
152 * disassembler only; for SSE instructions.
153 * \332 f2i REP prefix (0xF2 byte) used as opcode extension.
154 * \333 f3i REP prefix (0xF3 byte) used as opcode extension.
155 * \334 rex.l LOCK prefix used as REX.R (used in non-64-bit mode)
156 * \335 repe disassemble a rep (0xF3 byte) prefix as repe not rep.
157 * \336 mustrep force a REP(E) prefix (0xF3) even if not specified.
158 * \337 mustrepne force a REPNE prefix (0xF2) even if not specified.
159 * \336-\337 are still listed as prefixes in the disassembler.
160 * \340 resb reserve <operand 0> bytes of uninitialized storage.
161 * Operand 0 had better be a segmentless constant.
162 * \341 wait this instruction needs a WAIT "prefix"
163 * \360 np no SSE prefix (== \364\331)
164 * \361 66 SSE prefix (== \366\331)
165 * \364 !osp operand-size prefix (0x66) not permitted
166 * \365 !asp address-size prefix (0x67) not permitted
167 * \366 operand-size prefix (0x66) used as opcode extension
168 * \367 address-size prefix (0x67) used as opcode extension
169 * \370,\371 jcc8 match only if operand 0 meets byte jump criteria.
170 * jmp8 370 is used for Jcc, 371 is used for JMP.
171 * \373 jlen assemble 0x03 if bits==16, 0x05 if bits==32;
172 * used for conditional jump over longer jump
173 * \374 vsibx|vm32x|vm64x this instruction takes an XMM VSIB memory EA
174 * \375 vsiby|vm32y|vm64y this instruction takes an YMM VSIB memory EA
175 * \376 vsibz|vm32z|vm64z this instruction takes an ZMM VSIB memory EA
176 */
177
178 #include "compiler.h"
179
180 #include <stdio.h>
181 #include <string.h>
182 #include <stdlib.h>
183 #include <inttypes.h>
184
185 #include "nasm.h"
186 #include "nasmlib.h"
187 #include "assemble.h"
188 #include "insns.h"
189 #include "tables.h"
190 #include "disp8.h"
191
192 enum match_result {
193 /*
194 * Matching errors. These should be sorted so that more specific
195 * errors come later in the sequence.
196 */
197 MERR_INVALOP,
198 MERR_OPSIZEMISSING,
199 MERR_OPSIZEMISMATCH,
200 MERR_BRNUMMISMATCH,
201 MERR_BADCPU,
202 MERR_BADMODE,
203 MERR_BADHLE,
204 MERR_ENCMISMATCH,
205 MERR_BADBND,
206 MERR_BADREPNE,
207 /*
208 * Matching success; the conditional ones first
209 */
210 MOK_JUMP, /* Matching OK but needs jmp_match() */
211 MOK_GOOD /* Matching unconditionally OK */
212 };
213
214 typedef struct {
215 enum ea_type type; /* what kind of EA is this? */
216 int sib_present; /* is a SIB byte necessary? */
217 int bytes; /* # of bytes of offset needed */
218 int size; /* lazy - this is sib+bytes+1 */
219 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
220 int8_t disp8; /* compressed displacement for EVEX */
221 } ea;
222
223 #define GEN_SIB(scale, index, base) \
224 (((scale) << 6) | ((index) << 3) | ((base)))
225
226 #define GEN_MODRM(mod, reg, rm) \
227 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
228
229 static iflag_t cpu; /* cpu level received from nasm.c */
230
231 static int64_t calcsize(int32_t, int64_t, int, insn *,
232 const struct itemplate *);
233 static void gencode(int32_t segment, int64_t offset, int bits,
234 insn * ins, const struct itemplate *temp,
235 int64_t insn_end);
236 static enum match_result find_match(const struct itemplate **tempp,
237 insn *instruction,
238 int32_t segment, int64_t offset, int bits);
239 static enum match_result matches(const struct itemplate *, insn *, int bits);
240 static opflags_t regflag(const operand *);
241 static int32_t regval(const operand *);
242 static int rexflags(int, opflags_t, int);
243 static int op_rexflags(const operand *, int);
244 static int op_evexflags(const operand *, int, uint8_t);
245 static void add_asp(insn *, int);
246
247 static enum ea_type process_ea(operand *, ea *, int, int, opflags_t, insn *);
248
249 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
250 {
251 return ins->prefixes[pos] == prefix;
252 }
253
254 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
255 {
256 if (ins->prefixes[pos])
257 nasm_error(ERR_NONFATAL, "invalid %s prefix",
258 prefix_name(ins->prefixes[pos]));
259 }
260
261 static const char *size_name(int size)
262 {
263 switch (size) {
264 case 1:
265 return "byte";
266 case 2:
267 return "word";
268 case 4:
269 return "dword";
270 case 8:
271 return "qword";
272 case 10:
273 return "tword";
274 case 16:
275 return "oword";
276 case 32:
277 return "yword";
278 case 64:
279 return "zword";
280 default:
281 return "???";
282 }
283 }
284
285 static void warn_overflow(int pass, int size)
286 {
287 nasm_error(ERR_WARNING | pass | ERR_WARN_NOV,
288 "%s data exceeds bounds", size_name(size));
289 }
290
291 static void warn_overflow_const(int64_t data, int size)
292 {
293 if (overflow_general(data, size))
294 warn_overflow(ERR_PASS1, size);
295 }
296
297 static void warn_overflow_opd(const struct operand *o, int size)
298 {
299 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
300 if (overflow_general(o->offset, size))
301 warn_overflow(ERR_PASS2, size);
302 }
303 }
304
305 /*
306 * Size of an address relocation, or zero if not an address
307 */
308 static int addrsize(enum out_type type, uint64_t size)
309 {
310 switch (type) {
311 case OUT_ADDRESS:
312 return abs((int)size);
313 case OUT_REL1ADR:
314 return 1;
315 case OUT_REL2ADR:
316 return 2;
317 case OUT_REL4ADR:
318 return 4;
319 case OUT_REL8ADR:
320 return 8;
321 default:
322 return 0;
323 }
324 }
325
326 /*
327 * This routine wrappers the real output format's output routine,
328 * in order to pass a copy of the data off to the listing file
329 * generator at the same time, flatten unnecessary relocations,
330 * and verify backend compatibility.
331 */
332 static void out(int64_t offset, int32_t segto, const void *data,
333 enum out_type type, uint64_t size,
334 int32_t segment, int32_t wrt)
335 {
336 static int32_t lineno = 0; /* static!!! */
337 static char *lnfname = NULL;
338 uint8_t p[8];
339 int asize = addrsize(type, size); /* Address size in bytes */
340 const int amax = ofmt->maxbits >> 3; /* Maximum address size in bytes */
341
342 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
343 /*
344 * This is a non-relocated address, and we're going to
345 * convert it into RAWDATA format.
346 */
347 uint8_t *q = p;
348
349 if (asize > 8) {
350 nasm_panic(0, "OUT_ADDRESS with size > 8");
351 return;
352 }
353
354 WRITEADDR(q, *(int64_t *)data, asize);
355 data = p;
356 type = OUT_RAWDATA;
357 size = asize;
358 asize = 0; /* No longer an address */
359 }
360
361 nasmlist->output(offset, data, type, size);
362
363 /*
364 * this call to src_get determines when we call the
365 * debug-format-specific "linenum" function
366 * it updates lineno and lnfname to the current values
367 * returning 0 if "same as last time", -2 if lnfname
368 * changed, and the amount by which lineno changed,
369 * if it did. thus, these variables must be static
370 */
371
372 if (src_get(&lineno, &lnfname))
373 ofmt->current_dfmt->linenum(lnfname, lineno, segto);
374
375 if (asize && asize > amax) {
376 if (type != OUT_ADDRESS || (int)size < 0) {
377 nasm_error(ERR_NONFATAL,
378 "%d-bit signed relocation unsupported by output format %s\n",
379 asize << 3, ofmt->shortname);
380 size = asize;
381 } else {
382 nasm_error(ERR_WARNING | ERR_WARN_ZEXTRELOC,
383 "%d-bit unsigned relocation zero-extended from %d bits\n",
384 asize << 3, ofmt->maxbits);
385 ofmt->output(segto, data, type, amax, segment, wrt);
386 size = asize - amax;
387 }
388 data = zero_buffer;
389 type = OUT_RAWDATA;
390 segment = wrt = NO_SEG;
391 }
392
393 ofmt->output(segto, data, type, size, segment, wrt);
394 }
395
396 static void out_imm8(int64_t offset, int32_t segment,
397 struct operand *opx, int asize)
398 {
399 if (opx->segment != NO_SEG) {
400 uint64_t data = opx->offset;
401 out(offset, segment, &data, OUT_ADDRESS, asize, opx->segment, opx->wrt);
402 } else {
403 uint8_t byte = opx->offset;
404 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
405 }
406 }
407
408 static bool jmp_match(int32_t segment, int64_t offset, int bits,
409 insn * ins, const struct itemplate *temp)
410 {
411 int64_t isize;
412 const uint8_t *code = temp->code;
413 uint8_t c = code[0];
414 bool is_byte;
415
416 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
417 return false;
418 if (!optimizing)
419 return false;
420 if (optimizing < 0 && c == 0371)
421 return false;
422
423 isize = calcsize(segment, offset, bits, ins, temp);
424
425 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
426 /* Be optimistic in pass 1 */
427 return true;
428
429 if (ins->oprs[0].segment != segment)
430 return false;
431
432 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
433 is_byte = (isize >= -128 && isize <= 127); /* is it byte size? */
434
435 if (is_byte && c == 0371 && ins->prefixes[PPS_REP] == P_BND) {
436 /* jmp short (opcode eb) cannot be used with bnd prefix. */
437 ins->prefixes[PPS_REP] = P_none;
438 nasm_error(ERR_WARNING | ERR_WARN_BND | ERR_PASS2 ,
439 "jmp short does not init bnd regs - bnd prefix dropped.");
440 }
441
442 return is_byte;
443 }
444
445 int64_t assemble(int32_t segment, int64_t offset, int bits, iflag_t cp,
446 insn * instruction)
447 {
448 const struct itemplate *temp;
449 int j;
450 enum match_result m;
451 int64_t insn_end;
452 int32_t itimes;
453 int64_t start = offset;
454 int64_t wsize; /* size for DB etc. */
455
456 cpu = cp;
457
458 wsize = idata_bytes(instruction->opcode);
459 if (wsize == -1)
460 return 0;
461
462 if (wsize) {
463 extop *e;
464 int32_t t = instruction->times;
465 if (t < 0)
466 nasm_panic(0, "instruction->times < 0 (%"PRId32") in assemble()", t);
467
468 while (t--) { /* repeat TIMES times */
469 list_for_each(e, instruction->eops) {
470 if (e->type == EOT_DB_NUMBER) {
471 if (wsize > 8) {
472 nasm_error(ERR_NONFATAL,
473 "integer supplied to a DT, DO or DY"
474 " instruction");
475 } else {
476 out(offset, segment, &e->offset,
477 OUT_ADDRESS, wsize, e->segment, e->wrt);
478 offset += wsize;
479 }
480 } else if (e->type == EOT_DB_STRING ||
481 e->type == EOT_DB_STRING_FREE) {
482 int align;
483
484 out(offset, segment, e->stringval,
485 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
486 align = e->stringlen % wsize;
487
488 if (align) {
489 align = wsize - align;
490 out(offset, segment, zero_buffer,
491 OUT_RAWDATA, align, NO_SEG, NO_SEG);
492 }
493 offset += e->stringlen + align;
494 }
495 }
496 if (t > 0 && t == instruction->times - 1) {
497 /*
498 * Dummy call to nasmlist->output to give the offset to the
499 * listing module.
500 */
501 nasmlist->output(offset, NULL, OUT_RAWDATA, 0);
502 nasmlist->uplevel(LIST_TIMES);
503 }
504 }
505 if (instruction->times > 1)
506 nasmlist->downlevel(LIST_TIMES);
507 return offset - start;
508 }
509
510 if (instruction->opcode == I_INCBIN) {
511 const char *fname = instruction->eops->stringval;
512 FILE *fp;
513
514 fp = fopen(fname, "rb");
515 if (!fp) {
516 nasm_error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
517 fname);
518 } else if (fseek(fp, 0L, SEEK_END) < 0) {
519 nasm_error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
520 fname);
521 fclose(fp);
522 } else {
523 static char buf[4096];
524 size_t t = instruction->times;
525 size_t base = 0;
526 size_t len;
527
528 len = ftell(fp);
529 if (instruction->eops->next) {
530 base = instruction->eops->next->offset;
531 len -= base;
532 if (instruction->eops->next->next &&
533 len > (size_t)instruction->eops->next->next->offset)
534 len = (size_t)instruction->eops->next->next->offset;
535 }
536 /*
537 * Dummy call to nasmlist->output to give the offset to the
538 * listing module.
539 */
540 nasmlist->output(offset, NULL, OUT_RAWDATA, 0);
541 nasmlist->uplevel(LIST_INCBIN);
542 while (t--) {
543 size_t l;
544
545 fseek(fp, base, SEEK_SET);
546 l = len;
547 while (l > 0) {
548 int32_t m;
549 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
550 if (!m) {
551 /*
552 * This shouldn't happen unless the file
553 * actually changes while we are reading
554 * it.
555 */
556 nasm_error(ERR_NONFATAL,
557 "`incbin': unexpected EOF while"
558 " reading file `%s'", fname);
559 t = 0; /* Try to exit cleanly */
560 break;
561 }
562 out(offset, segment, buf, OUT_RAWDATA, m,
563 NO_SEG, NO_SEG);
564 l -= m;
565 }
566 }
567 nasmlist->downlevel(LIST_INCBIN);
568 if (instruction->times > 1) {
569 /*
570 * Dummy call to nasmlist->output to give the offset to the
571 * listing module.
572 */
573 nasmlist->output(offset, NULL, OUT_RAWDATA, 0);
574 nasmlist->uplevel(LIST_TIMES);
575 nasmlist->downlevel(LIST_TIMES);
576 }
577 fclose(fp);
578 return instruction->times * len;
579 }
580 return 0; /* if we're here, there's an error */
581 }
582
583 /* Check to see if we need an address-size prefix */
584 add_asp(instruction, bits);
585
586 m = find_match(&temp, instruction, segment, offset, bits);
587
588 if (m == MOK_GOOD) {
589 /* Matches! */
590 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
591 itimes = instruction->times;
592 if (insn_size < 0) /* shouldn't be, on pass two */
593 nasm_panic(0, "errors made it through from pass one");
594 else
595 while (itimes--) {
596 for (j = 0; j < MAXPREFIX; j++) {
597 uint8_t c = 0;
598 switch (instruction->prefixes[j]) {
599 case P_WAIT:
600 c = 0x9B;
601 break;
602 case P_LOCK:
603 c = 0xF0;
604 break;
605 case P_REPNE:
606 case P_REPNZ:
607 case P_XACQUIRE:
608 case P_BND:
609 c = 0xF2;
610 break;
611 case P_REPE:
612 case P_REPZ:
613 case P_REP:
614 case P_XRELEASE:
615 c = 0xF3;
616 break;
617 case R_CS:
618 if (bits == 64) {
619 nasm_error(ERR_WARNING | ERR_PASS2,
620 "cs segment base generated, but will be ignored in 64-bit mode");
621 }
622 c = 0x2E;
623 break;
624 case R_DS:
625 if (bits == 64) {
626 nasm_error(ERR_WARNING | ERR_PASS2,
627 "ds segment base generated, but will be ignored in 64-bit mode");
628 }
629 c = 0x3E;
630 break;
631 case R_ES:
632 if (bits == 64) {
633 nasm_error(ERR_WARNING | ERR_PASS2,
634 "es segment base generated, but will be ignored in 64-bit mode");
635 }
636 c = 0x26;
637 break;
638 case R_FS:
639 c = 0x64;
640 break;
641 case R_GS:
642 c = 0x65;
643 break;
644 case R_SS:
645 if (bits == 64) {
646 nasm_error(ERR_WARNING | ERR_PASS2,
647 "ss segment base generated, but will be ignored in 64-bit mode");
648 }
649 c = 0x36;
650 break;
651 case R_SEGR6:
652 case R_SEGR7:
653 nasm_error(ERR_NONFATAL,
654 "segr6 and segr7 cannot be used as prefixes");
655 break;
656 case P_A16:
657 if (bits == 64) {
658 nasm_error(ERR_NONFATAL,
659 "16-bit addressing is not supported "
660 "in 64-bit mode");
661 } else if (bits != 16)
662 c = 0x67;
663 break;
664 case P_A32:
665 if (bits != 32)
666 c = 0x67;
667 break;
668 case P_A64:
669 if (bits != 64) {
670 nasm_error(ERR_NONFATAL,
671 "64-bit addressing is only supported "
672 "in 64-bit mode");
673 }
674 break;
675 case P_ASP:
676 c = 0x67;
677 break;
678 case P_O16:
679 if (bits != 16)
680 c = 0x66;
681 break;
682 case P_O32:
683 if (bits == 16)
684 c = 0x66;
685 break;
686 case P_O64:
687 /* REX.W */
688 break;
689 case P_OSP:
690 c = 0x66;
691 break;
692 case P_EVEX:
693 case P_VEX3:
694 case P_VEX2:
695 case P_NOBND:
696 case P_none:
697 break;
698 default:
699 nasm_panic(0, "invalid instruction prefix");
700 }
701 if (c != 0) {
702 out(offset, segment, &c, OUT_RAWDATA, 1,
703 NO_SEG, NO_SEG);
704 offset++;
705 }
706 }
707 insn_end = offset + insn_size;
708 gencode(segment, offset, bits, instruction,
709 temp, insn_end);
710 offset += insn_size;
711 if (itimes > 0 && itimes == instruction->times - 1) {
712 /*
713 * Dummy call to nasmlist->output to give the offset to the
714 * listing module.
715 */
716 nasmlist->output(offset, NULL, OUT_RAWDATA, 0);
717 nasmlist->uplevel(LIST_TIMES);
718 }
719 }
720 if (instruction->times > 1)
721 nasmlist->downlevel(LIST_TIMES);
722 return offset - start;
723 } else {
724 /* No match */
725 switch (m) {
726 case MERR_OPSIZEMISSING:
727 nasm_error(ERR_NONFATAL, "operation size not specified");
728 break;
729 case MERR_OPSIZEMISMATCH:
730 nasm_error(ERR_NONFATAL, "mismatch in operand sizes");
731 break;
732 case MERR_BRNUMMISMATCH:
733 nasm_error(ERR_NONFATAL,
734 "mismatch in the number of broadcasting elements");
735 break;
736 case MERR_BADCPU:
737 nasm_error(ERR_NONFATAL, "no instruction for this cpu level");
738 break;
739 case MERR_BADMODE:
740 nasm_error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
741 bits);
742 break;
743 case MERR_ENCMISMATCH:
744 nasm_error(ERR_NONFATAL, "specific encoding scheme not available");
745 break;
746 case MERR_BADBND:
747 nasm_error(ERR_NONFATAL, "bnd prefix is not allowed");
748 break;
749 case MERR_BADREPNE:
750 nasm_error(ERR_NONFATAL, "%s prefix is not allowed",
751 (has_prefix(instruction, PPS_REP, P_REPNE) ?
752 "repne" : "repnz"));
753 break;
754 default:
755 nasm_error(ERR_NONFATAL,
756 "invalid combination of opcode and operands");
757 break;
758 }
759 }
760 return 0;
761 }
762
763 int64_t insn_size(int32_t segment, int64_t offset, int bits, iflag_t cp,
764 insn * instruction)
765 {
766 const struct itemplate *temp;
767 enum match_result m;
768
769 cpu = cp;
770
771 if (instruction->opcode == I_none)
772 return 0;
773
774 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
775 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
776 instruction->opcode == I_DT || instruction->opcode == I_DO ||
777 instruction->opcode == I_DY) {
778 extop *e;
779 int32_t isize, osize, wsize;
780
781 isize = 0;
782 wsize = idata_bytes(instruction->opcode);
783
784 list_for_each(e, instruction->eops) {
785 int32_t align;
786
787 osize = 0;
788 if (e->type == EOT_DB_NUMBER) {
789 osize = 1;
790 warn_overflow_const(e->offset, wsize);
791 } else if (e->type == EOT_DB_STRING ||
792 e->type == EOT_DB_STRING_FREE)
793 osize = e->stringlen;
794
795 align = (-osize) % wsize;
796 if (align < 0)
797 align += wsize;
798 isize += osize + align;
799 }
800 return isize * instruction->times;
801 }
802
803 if (instruction->opcode == I_INCBIN) {
804 const char *fname = instruction->eops->stringval;
805 FILE *fp;
806 int64_t val = 0;
807 size_t len;
808
809 fp = fopen(fname, "rb");
810 if (!fp)
811 nasm_error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
812 fname);
813 else if (fseek(fp, 0L, SEEK_END) < 0)
814 nasm_error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
815 fname);
816 else {
817 len = ftell(fp);
818 if (instruction->eops->next) {
819 len -= instruction->eops->next->offset;
820 if (instruction->eops->next->next &&
821 len > (size_t)instruction->eops->next->next->offset) {
822 len = (size_t)instruction->eops->next->next->offset;
823 }
824 }
825 val = instruction->times * len;
826 }
827 if (fp)
828 fclose(fp);
829 return val;
830 }
831
832 /* Check to see if we need an address-size prefix */
833 add_asp(instruction, bits);
834
835 m = find_match(&temp, instruction, segment, offset, bits);
836 if (m == MOK_GOOD) {
837 /* we've matched an instruction. */
838 int64_t isize;
839 int j;
840
841 isize = calcsize(segment, offset, bits, instruction, temp);
842 if (isize < 0)
843 return -1;
844 for (j = 0; j < MAXPREFIX; j++) {
845 switch (instruction->prefixes[j]) {
846 case P_A16:
847 if (bits != 16)
848 isize++;
849 break;
850 case P_A32:
851 if (bits != 32)
852 isize++;
853 break;
854 case P_O16:
855 if (bits != 16)
856 isize++;
857 break;
858 case P_O32:
859 if (bits == 16)
860 isize++;
861 break;
862 case P_A64:
863 case P_O64:
864 case P_EVEX:
865 case P_VEX3:
866 case P_VEX2:
867 case P_NOBND:
868 case P_none:
869 break;
870 default:
871 isize++;
872 break;
873 }
874 }
875 return isize * instruction->times;
876 } else {
877 return -1; /* didn't match any instruction */
878 }
879 }
880
881 static void bad_hle_warn(const insn * ins, uint8_t hleok)
882 {
883 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
884 enum whatwarn { w_none, w_lock, w_inval } ww;
885 static const enum whatwarn warn[2][4] =
886 {
887 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
888 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
889 };
890 unsigned int n;
891
892 n = (unsigned int)rep_pfx - P_XACQUIRE;
893 if (n > 1)
894 return; /* Not XACQUIRE/XRELEASE */
895
896 ww = warn[n][hleok];
897 if (!is_class(MEMORY, ins->oprs[0].type))
898 ww = w_inval; /* HLE requires operand 0 to be memory */
899
900 switch (ww) {
901 case w_none:
902 break;
903
904 case w_lock:
905 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
906 nasm_error(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
907 "%s with this instruction requires lock",
908 prefix_name(rep_pfx));
909 }
910 break;
911
912 case w_inval:
913 nasm_error(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
914 "%s invalid with this instruction",
915 prefix_name(rep_pfx));
916 break;
917 }
918 }
919
920 /* Common construct */
921 #define case3(x) case (x): case (x)+1: case (x)+2
922 #define case4(x) case3(x): case (x)+3
923
924 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
925 insn * ins, const struct itemplate *temp)
926 {
927 const uint8_t *codes = temp->code;
928 int64_t length = 0;
929 uint8_t c;
930 int rex_mask = ~0;
931 int op1, op2;
932 struct operand *opx;
933 uint8_t opex = 0;
934 enum ea_type eat;
935 uint8_t hleok = 0;
936 bool lockcheck = true;
937 enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
938
939 ins->rex = 0; /* Ensure REX is reset */
940 eat = EA_SCALAR; /* Expect a scalar EA */
941 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
942
943 if (ins->prefixes[PPS_OSIZE] == P_O64)
944 ins->rex |= REX_W;
945
946 (void)segment; /* Don't warn that this parameter is unused */
947 (void)offset; /* Don't warn that this parameter is unused */
948
949 while (*codes) {
950 c = *codes++;
951 op1 = (c & 3) + ((opex & 1) << 2);
952 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
953 opx = &ins->oprs[op1];
954 opex = 0; /* For the next iteration */
955
956 switch (c) {
957 case4(01):
958 codes += c, length += c;
959 break;
960
961 case3(05):
962 opex = c;
963 break;
964
965 case4(010):
966 ins->rex |=
967 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
968 codes++, length++;
969 break;
970
971 case4(014):
972 /* this is an index reg of MIB operand */
973 mib_index = opx->basereg;
974 break;
975
976 case4(020):
977 case4(024):
978 length++;
979 break;
980
981 case4(030):
982 length += 2;
983 break;
984
985 case4(034):
986 if (opx->type & (BITS16 | BITS32 | BITS64))
987 length += (opx->type & BITS16) ? 2 : 4;
988 else
989 length += (bits == 16) ? 2 : 4;
990 break;
991
992 case4(040):
993 length += 4;
994 break;
995
996 case4(044):
997 length += ins->addr_size >> 3;
998 break;
999
1000 case4(050):
1001 length++;
1002 break;
1003
1004 case4(054):
1005 length += 8; /* MOV reg64/imm */
1006 break;
1007
1008 case4(060):
1009 length += 2;
1010 break;
1011
1012 case4(064):
1013 if (opx->type & (BITS16 | BITS32 | BITS64))
1014 length += (opx->type & BITS16) ? 2 : 4;
1015 else
1016 length += (bits == 16) ? 2 : 4;
1017 break;
1018
1019 case4(070):
1020 length += 4;
1021 break;
1022
1023 case4(074):
1024 length += 2;
1025 break;
1026
1027 case 0172:
1028 case 0173:
1029 codes++;
1030 length++;
1031 break;
1032
1033 case4(0174):
1034 length++;
1035 break;
1036
1037 case4(0240):
1038 ins->rex |= REX_EV;
1039 ins->vexreg = regval(opx);
1040 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
1041 ins->vex_cm = *codes++;
1042 ins->vex_wlp = *codes++;
1043 ins->evex_tuple = (*codes++ - 0300);
1044 break;
1045
1046 case 0250:
1047 ins->rex |= REX_EV;
1048 ins->vexreg = 0;
1049 ins->vex_cm = *codes++;
1050 ins->vex_wlp = *codes++;
1051 ins->evex_tuple = (*codes++ - 0300);
1052 break;
1053
1054 case4(0254):
1055 length += 4;
1056 break;
1057
1058 case4(0260):
1059 ins->rex |= REX_V;
1060 ins->vexreg = regval(opx);
1061 ins->vex_cm = *codes++;
1062 ins->vex_wlp = *codes++;
1063 break;
1064
1065 case 0270:
1066 ins->rex |= REX_V;
1067 ins->vexreg = 0;
1068 ins->vex_cm = *codes++;
1069 ins->vex_wlp = *codes++;
1070 break;
1071
1072 case3(0271):
1073 hleok = c & 3;
1074 break;
1075
1076 case4(0274):
1077 length++;
1078 break;
1079
1080 case4(0300):
1081 break;
1082
1083 case 0310:
1084 if (bits == 64)
1085 return -1;
1086 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1087 break;
1088
1089 case 0311:
1090 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1091 break;
1092
1093 case 0312:
1094 break;
1095
1096 case 0313:
1097 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1098 has_prefix(ins, PPS_ASIZE, P_A32))
1099 return -1;
1100 break;
1101
1102 case4(0314):
1103 break;
1104
1105 case 0320:
1106 {
1107 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1108 if (pfx == P_O16)
1109 break;
1110 if (pfx != P_none)
1111 nasm_error(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1112 else
1113 ins->prefixes[PPS_OSIZE] = P_O16;
1114 break;
1115 }
1116
1117 case 0321:
1118 {
1119 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1120 if (pfx == P_O32)
1121 break;
1122 if (pfx != P_none)
1123 nasm_error(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1124 else
1125 ins->prefixes[PPS_OSIZE] = P_O32;
1126 break;
1127 }
1128
1129 case 0322:
1130 break;
1131
1132 case 0323:
1133 rex_mask &= ~REX_W;
1134 break;
1135
1136 case 0324:
1137 ins->rex |= REX_W;
1138 break;
1139
1140 case 0325:
1141 ins->rex |= REX_NH;
1142 break;
1143
1144 case 0326:
1145 break;
1146
1147 case 0330:
1148 codes++, length++;
1149 break;
1150
1151 case 0331:
1152 break;
1153
1154 case 0332:
1155 case 0333:
1156 length++;
1157 break;
1158
1159 case 0334:
1160 ins->rex |= REX_L;
1161 break;
1162
1163 case 0335:
1164 break;
1165
1166 case 0336:
1167 if (!ins->prefixes[PPS_REP])
1168 ins->prefixes[PPS_REP] = P_REP;
1169 break;
1170
1171 case 0337:
1172 if (!ins->prefixes[PPS_REP])
1173 ins->prefixes[PPS_REP] = P_REPNE;
1174 break;
1175
1176 case 0340:
1177 if (ins->oprs[0].segment != NO_SEG)
1178 nasm_error(ERR_NONFATAL, "attempt to reserve non-constant"
1179 " quantity of BSS space");
1180 else
1181 length += ins->oprs[0].offset;
1182 break;
1183
1184 case 0341:
1185 if (!ins->prefixes[PPS_WAIT])
1186 ins->prefixes[PPS_WAIT] = P_WAIT;
1187 break;
1188
1189 case 0360:
1190 break;
1191
1192 case 0361:
1193 length++;
1194 break;
1195
1196 case 0364:
1197 case 0365:
1198 break;
1199
1200 case 0366:
1201 case 0367:
1202 length++;
1203 break;
1204
1205 case 0370:
1206 case 0371:
1207 break;
1208
1209 case 0373:
1210 length++;
1211 break;
1212
1213 case 0374:
1214 eat = EA_XMMVSIB;
1215 break;
1216
1217 case 0375:
1218 eat = EA_YMMVSIB;
1219 break;
1220
1221 case 0376:
1222 eat = EA_ZMMVSIB;
1223 break;
1224
1225 case4(0100):
1226 case4(0110):
1227 case4(0120):
1228 case4(0130):
1229 case4(0200):
1230 case4(0204):
1231 case4(0210):
1232 case4(0214):
1233 case4(0220):
1234 case4(0224):
1235 case4(0230):
1236 case4(0234):
1237 {
1238 ea ea_data;
1239 int rfield;
1240 opflags_t rflags;
1241 struct operand *opy = &ins->oprs[op2];
1242 struct operand *op_er_sae;
1243
1244 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1245
1246 if (c <= 0177) {
1247 /* pick rfield from operand b (opx) */
1248 rflags = regflag(opx);
1249 rfield = nasm_regvals[opx->basereg];
1250 } else {
1251 rflags = 0;
1252 rfield = c & 7;
1253 }
1254
1255 /* EVEX.b1 : evex_brerop contains the operand position */
1256 op_er_sae = (ins->evex_brerop >= 0 ?
1257 &ins->oprs[ins->evex_brerop] : NULL);
1258
1259 if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
1260 /* set EVEX.b */
1261 ins->evex_p[2] |= EVEX_P2B;
1262 if (op_er_sae->decoflags & ER) {
1263 /* set EVEX.RC (rounding control) */
1264 ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
1265 & EVEX_P2RC;
1266 }
1267 } else {
1268 /* set EVEX.L'L (vector length) */
1269 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1270 ins->evex_p[1] |= ((ins->vex_wlp << (7 - 4)) & EVEX_P1W);
1271 if (opy->decoflags & BRDCAST_MASK) {
1272 /* set EVEX.b */
1273 ins->evex_p[2] |= EVEX_P2B;
1274 }
1275 }
1276
1277 if (itemp_has(temp, IF_MIB)) {
1278 opy->eaflags |= EAF_MIB;
1279 /*
1280 * if a separate form of MIB (ICC style) is used,
1281 * the index reg info is merged into mem operand
1282 */
1283 if (mib_index != R_none) {
1284 opy->indexreg = mib_index;
1285 opy->scale = 1;
1286 opy->hintbase = mib_index;
1287 opy->hinttype = EAH_NOTBASE;
1288 }
1289 }
1290
1291 if (process_ea(opy, &ea_data, bits,
1292 rfield, rflags, ins) != eat) {
1293 nasm_error(ERR_NONFATAL, "invalid effective address");
1294 return -1;
1295 } else {
1296 ins->rex |= ea_data.rex;
1297 length += ea_data.size;
1298 }
1299 }
1300 break;
1301
1302 default:
1303 nasm_panic(0, "internal instruction table corrupt"
1304 ": instruction code \\%o (0x%02X) given", c, c);
1305 break;
1306 }
1307 }
1308
1309 ins->rex &= rex_mask;
1310
1311 if (ins->rex & REX_NH) {
1312 if (ins->rex & REX_H) {
1313 nasm_error(ERR_NONFATAL, "instruction cannot use high registers");
1314 return -1;
1315 }
1316 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1317 }
1318
1319 switch (ins->prefixes[PPS_VEX]) {
1320 case P_EVEX:
1321 if (!(ins->rex & REX_EV))
1322 return -1;
1323 break;
1324 case P_VEX3:
1325 case P_VEX2:
1326 if (!(ins->rex & REX_V))
1327 return -1;
1328 break;
1329 default:
1330 break;
1331 }
1332
1333 if (ins->rex & (REX_V | REX_EV)) {
1334 int bad32 = REX_R|REX_W|REX_X|REX_B;
1335
1336 if (ins->rex & REX_H) {
1337 nasm_error(ERR_NONFATAL, "cannot use high register in AVX instruction");
1338 return -1;
1339 }
1340 switch (ins->vex_wlp & 060) {
1341 case 000:
1342 case 040:
1343 ins->rex &= ~REX_W;
1344 break;
1345 case 020:
1346 ins->rex |= REX_W;
1347 bad32 &= ~REX_W;
1348 break;
1349 case 060:
1350 /* Follow REX_W */
1351 break;
1352 }
1353
1354 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1355 nasm_error(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1356 return -1;
1357 } else if (!(ins->rex & REX_EV) &&
1358 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1359 nasm_error(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1360 return -1;
1361 }
1362 if (ins->rex & REX_EV)
1363 length += 4;
1364 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1365 ins->prefixes[PPS_VEX] == P_VEX3)
1366 length += 3;
1367 else
1368 length += 2;
1369 } else if (ins->rex & REX_MASK) {
1370 if (ins->rex & REX_H) {
1371 nasm_error(ERR_NONFATAL, "cannot use high register in rex instruction");
1372 return -1;
1373 } else if (bits == 64) {
1374 length++;
1375 } else if ((ins->rex & REX_L) &&
1376 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1377 iflag_ffs(&cpu) >= IF_X86_64) {
1378 /* LOCK-as-REX.R */
1379 assert_no_prefix(ins, PPS_LOCK);
1380 lockcheck = false; /* Already errored, no need for warning */
1381 length++;
1382 } else {
1383 nasm_error(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1384 return -1;
1385 }
1386 }
1387
1388 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1389 (!itemp_has(temp,IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1390 nasm_error(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1391 "instruction is not lockable");
1392 }
1393
1394 bad_hle_warn(ins, hleok);
1395
1396 /*
1397 * when BND prefix is set by DEFAULT directive,
1398 * BND prefix is added to every appropriate instruction line
1399 * unless it is overridden by NOBND prefix.
1400 */
1401 if (globalbnd &&
1402 (itemp_has(temp, IF_BND) && !has_prefix(ins, PPS_REP, P_NOBND)))
1403 ins->prefixes[PPS_REP] = P_BND;
1404
1405 return length;
1406 }
1407
1408 static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
1409 {
1410 if (bits == 64) {
1411 if ((ins->rex & REX_MASK) &&
1412 !(ins->rex & (REX_V | REX_EV)) &&
1413 !ins->rex_done) {
1414 int rex = (ins->rex & REX_MASK) | REX_P;
1415 out(offset, segment, &rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1416 ins->rex_done = true;
1417 return 1;
1418 }
1419 }
1420
1421 return 0;
1422 }
1423
1424 static void gencode(int32_t segment, int64_t offset, int bits,
1425 insn * ins, const struct itemplate *temp,
1426 int64_t insn_end)
1427 {
1428 uint8_t c;
1429 uint8_t bytes[4];
1430 int64_t size;
1431 int64_t data;
1432 int op1, op2;
1433 struct operand *opx;
1434 const uint8_t *codes = temp->code;
1435 uint8_t opex = 0;
1436 enum ea_type eat = EA_SCALAR;
1437
1438 ins->rex_done = false;
1439
1440 while (*codes) {
1441 c = *codes++;
1442 op1 = (c & 3) + ((opex & 1) << 2);
1443 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1444 opx = &ins->oprs[op1];
1445 opex = 0; /* For the next iteration */
1446
1447 switch (c) {
1448 case 01:
1449 case 02:
1450 case 03:
1451 case 04:
1452 offset += emit_rex(ins, segment, offset, bits);
1453 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1454 codes += c;
1455 offset += c;
1456 break;
1457
1458 case 05:
1459 case 06:
1460 case 07:
1461 opex = c;
1462 break;
1463
1464 case4(010):
1465 offset += emit_rex(ins, segment, offset, bits);
1466 bytes[0] = *codes++ + (regval(opx) & 7);
1467 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1468 offset += 1;
1469 break;
1470
1471 case4(014):
1472 break;
1473
1474 case4(020):
1475 if (opx->offset < -256 || opx->offset > 255) {
1476 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1477 "byte value exceeds bounds");
1478 }
1479 out_imm8(offset, segment, opx, -1);
1480 offset += 1;
1481 break;
1482
1483 case4(024):
1484 if (opx->offset < 0 || opx->offset > 255)
1485 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1486 "unsigned byte value exceeds bounds");
1487 out_imm8(offset, segment, opx, 1);
1488 offset += 1;
1489 break;
1490
1491 case4(030):
1492 warn_overflow_opd(opx, 2);
1493 data = opx->offset;
1494 out(offset, segment, &data, OUT_ADDRESS, 2,
1495 opx->segment, opx->wrt);
1496 offset += 2;
1497 break;
1498
1499 case4(034):
1500 if (opx->type & (BITS16 | BITS32))
1501 size = (opx->type & BITS16) ? 2 : 4;
1502 else
1503 size = (bits == 16) ? 2 : 4;
1504 warn_overflow_opd(opx, size);
1505 data = opx->offset;
1506 out(offset, segment, &data, OUT_ADDRESS, size,
1507 opx->segment, opx->wrt);
1508 offset += size;
1509 break;
1510
1511 case4(040):
1512 warn_overflow_opd(opx, 4);
1513 data = opx->offset;
1514 out(offset, segment, &data, OUT_ADDRESS, 4,
1515 opx->segment, opx->wrt);
1516 offset += 4;
1517 break;
1518
1519 case4(044):
1520 data = opx->offset;
1521 size = ins->addr_size >> 3;
1522 warn_overflow_opd(opx, size);
1523 out(offset, segment, &data, OUT_ADDRESS, size,
1524 opx->segment, opx->wrt);
1525 offset += size;
1526 break;
1527
1528 case4(050):
1529 if (opx->segment != segment) {
1530 data = opx->offset;
1531 out(offset, segment, &data,
1532 OUT_REL1ADR, insn_end - offset,
1533 opx->segment, opx->wrt);
1534 } else {
1535 data = opx->offset - insn_end;
1536 if (data > 127 || data < -128)
1537 nasm_error(ERR_NONFATAL, "short jump is out of range");
1538 out(offset, segment, &data,
1539 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1540 }
1541 offset += 1;
1542 break;
1543
1544 case4(054):
1545 data = (int64_t)opx->offset;
1546 out(offset, segment, &data, OUT_ADDRESS, 8,
1547 opx->segment, opx->wrt);
1548 offset += 8;
1549 break;
1550
1551 case4(060):
1552 if (opx->segment != segment) {
1553 data = opx->offset;
1554 out(offset, segment, &data,
1555 OUT_REL2ADR, insn_end - offset,
1556 opx->segment, opx->wrt);
1557 } else {
1558 data = opx->offset - insn_end;
1559 out(offset, segment, &data,
1560 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1561 }
1562 offset += 2;
1563 break;
1564
1565 case4(064):
1566 if (opx->type & (BITS16 | BITS32 | BITS64))
1567 size = (opx->type & BITS16) ? 2 : 4;
1568 else
1569 size = (bits == 16) ? 2 : 4;
1570 if (opx->segment != segment) {
1571 data = opx->offset;
1572 out(offset, segment, &data,
1573 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1574 insn_end - offset, opx->segment, opx->wrt);
1575 } else {
1576 data = opx->offset - insn_end;
1577 out(offset, segment, &data,
1578 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1579 }
1580 offset += size;
1581 break;
1582
1583 case4(070):
1584 if (opx->segment != segment) {
1585 data = opx->offset;
1586 out(offset, segment, &data,
1587 OUT_REL4ADR, insn_end - offset,
1588 opx->segment, opx->wrt);
1589 } else {
1590 data = opx->offset - insn_end;
1591 out(offset, segment, &data,
1592 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1593 }
1594 offset += 4;
1595 break;
1596
1597 case4(074):
1598 if (opx->segment == NO_SEG)
1599 nasm_error(ERR_NONFATAL, "value referenced by FAR is not"
1600 " relocatable");
1601 data = 0;
1602 out(offset, segment, &data, OUT_ADDRESS, 2,
1603 ofmt->segbase(1 + opx->segment),
1604 opx->wrt);
1605 offset += 2;
1606 break;
1607
1608 case 0172:
1609 c = *codes++;
1610 opx = &ins->oprs[c >> 3];
1611 bytes[0] = nasm_regvals[opx->basereg] << 4;
1612 opx = &ins->oprs[c & 7];
1613 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1614 nasm_error(ERR_NONFATAL,
1615 "non-absolute expression not permitted as argument %d",
1616 c & 7);
1617 } else {
1618 if (opx->offset & ~15) {
1619 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1620 "four-bit argument exceeds bounds");
1621 }
1622 bytes[0] |= opx->offset & 15;
1623 }
1624 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1625 offset++;
1626 break;
1627
1628 case 0173:
1629 c = *codes++;
1630 opx = &ins->oprs[c >> 4];
1631 bytes[0] = nasm_regvals[opx->basereg] << 4;
1632 bytes[0] |= c & 15;
1633 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1634 offset++;
1635 break;
1636
1637 case4(0174):
1638 bytes[0] = nasm_regvals[opx->basereg] << 4;
1639 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1640 offset++;
1641 break;
1642
1643 case4(0254):
1644 data = opx->offset;
1645 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1646 (int32_t)data != (int64_t)data) {
1647 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1648 "signed dword immediate exceeds bounds");
1649 }
1650 out(offset, segment, &data, OUT_ADDRESS, -4,
1651 opx->segment, opx->wrt);
1652 offset += 4;
1653 break;
1654
1655 case4(0240):
1656 case 0250:
1657 codes += 3;
1658 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1659 EVEX_P2Z | EVEX_P2AAA, 2);
1660 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1661 bytes[0] = 0x62;
1662 /* EVEX.X can be set by either REX or EVEX for different reasons */
1663 bytes[1] = ((((ins->rex & 7) << 5) |
1664 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) ^ 0xf0) |
1665 (ins->vex_cm & 3);
1666 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1667 ((~ins->vexreg & 15) << 3) |
1668 (1 << 2) | (ins->vex_wlp & 3);
1669 bytes[3] = ins->evex_p[2];
1670 out(offset, segment, &bytes, OUT_RAWDATA, 4, NO_SEG, NO_SEG);
1671 offset += 4;
1672 break;
1673
1674 case4(0260):
1675 case 0270:
1676 codes += 2;
1677 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1678 ins->prefixes[PPS_VEX] == P_VEX3) {
1679 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1680 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1681 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1682 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1683 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1684 offset += 3;
1685 } else {
1686 bytes[0] = 0xc5;
1687 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1688 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1689 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1690 offset += 2;
1691 }
1692 break;
1693
1694 case 0271:
1695 case 0272:
1696 case 0273:
1697 break;
1698
1699 case4(0274):
1700 {
1701 uint64_t uv, um;
1702 int s;
1703
1704 if (ins->rex & REX_W)
1705 s = 64;
1706 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1707 s = 16;
1708 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1709 s = 32;
1710 else
1711 s = bits;
1712
1713 um = (uint64_t)2 << (s-1);
1714 uv = opx->offset;
1715
1716 if (uv > 127 && uv < (uint64_t)-128 &&
1717 (uv < um-128 || uv > um-1)) {
1718 /* If this wasn't explicitly byte-sized, warn as though we
1719 * had fallen through to the imm16/32/64 case.
1720 */
1721 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1722 "%s value exceeds bounds",
1723 (opx->type & BITS8) ? "signed byte" :
1724 s == 16 ? "word" :
1725 s == 32 ? "dword" :
1726 "signed dword");
1727 }
1728 if (opx->segment != NO_SEG) {
1729 data = uv;
1730 out(offset, segment, &data, OUT_ADDRESS, 1,
1731 opx->segment, opx->wrt);
1732 } else {
1733 bytes[0] = uv;
1734 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1735 NO_SEG);
1736 }
1737 offset += 1;
1738 break;
1739 }
1740
1741 case4(0300):
1742 break;
1743
1744 case 0310:
1745 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1746 *bytes = 0x67;
1747 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1748 offset += 1;
1749 } else
1750 offset += 0;
1751 break;
1752
1753 case 0311:
1754 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1755 *bytes = 0x67;
1756 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1757 offset += 1;
1758 } else
1759 offset += 0;
1760 break;
1761
1762 case 0312:
1763 break;
1764
1765 case 0313:
1766 ins->rex = 0;
1767 break;
1768
1769 case4(0314):
1770 break;
1771
1772 case 0320:
1773 case 0321:
1774 break;
1775
1776 case 0322:
1777 case 0323:
1778 break;
1779
1780 case 0324:
1781 ins->rex |= REX_W;
1782 break;
1783
1784 case 0325:
1785 break;
1786
1787 case 0326:
1788 break;
1789
1790 case 0330:
1791 *bytes = *codes++ ^ get_cond_opcode(ins->condition);
1792 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1793 offset += 1;
1794 break;
1795
1796 case 0331:
1797 break;
1798
1799 case 0332:
1800 case 0333:
1801 *bytes = c - 0332 + 0xF2;
1802 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1803 offset += 1;
1804 break;
1805
1806 case 0334:
1807 if (ins->rex & REX_R) {
1808 *bytes = 0xF0;
1809 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1810 offset += 1;
1811 }
1812 ins->rex &= ~(REX_L|REX_R);
1813 break;
1814
1815 case 0335:
1816 break;
1817
1818 case 0336:
1819 case 0337:
1820 break;
1821
1822 case 0340:
1823 if (ins->oprs[0].segment != NO_SEG)
1824 nasm_panic(0, "non-constant BSS size in pass two");
1825 else {
1826 int64_t size = ins->oprs[0].offset;
1827 if (size > 0)
1828 out(offset, segment, NULL,
1829 OUT_RESERVE, size, NO_SEG, NO_SEG);
1830 offset += size;
1831 }
1832 break;
1833
1834 case 0341:
1835 break;
1836
1837 case 0360:
1838 break;
1839
1840 case 0361:
1841 bytes[0] = 0x66;
1842 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1843 offset += 1;
1844 break;
1845
1846 case 0364:
1847 case 0365:
1848 break;
1849
1850 case 0366:
1851 case 0367:
1852 *bytes = c - 0366 + 0x66;
1853 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1854 offset += 1;
1855 break;
1856
1857 case3(0370):
1858 break;
1859
1860 case 0373:
1861 *bytes = bits == 16 ? 3 : 5;
1862 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1863 offset += 1;
1864 break;
1865
1866 case 0374:
1867 eat = EA_XMMVSIB;
1868 break;
1869
1870 case 0375:
1871 eat = EA_YMMVSIB;
1872 break;
1873
1874 case 0376:
1875 eat = EA_ZMMVSIB;
1876 break;
1877
1878 case4(0100):
1879 case4(0110):
1880 case4(0120):
1881 case4(0130):
1882 case4(0200):
1883 case4(0204):
1884 case4(0210):
1885 case4(0214):
1886 case4(0220):
1887 case4(0224):
1888 case4(0230):
1889 case4(0234):
1890 {
1891 ea ea_data;
1892 int rfield;
1893 opflags_t rflags;
1894 uint8_t *p;
1895 int32_t s;
1896 struct operand *opy = &ins->oprs[op2];
1897
1898 if (c <= 0177) {
1899 /* pick rfield from operand b (opx) */
1900 rflags = regflag(opx);
1901 rfield = nasm_regvals[opx->basereg];
1902 } else {
1903 /* rfield is constant */
1904 rflags = 0;
1905 rfield = c & 7;
1906 }
1907
1908 if (process_ea(opy, &ea_data, bits,
1909 rfield, rflags, ins) != eat)
1910 nasm_error(ERR_NONFATAL, "invalid effective address");
1911
1912 p = bytes;
1913 *p++ = ea_data.modrm;
1914 if (ea_data.sib_present)
1915 *p++ = ea_data.sib;
1916
1917 s = p - bytes;
1918 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1919
1920 /*
1921 * Make sure the address gets the right offset in case
1922 * the line breaks in the .lst file (BR 1197827)
1923 */
1924 offset += s;
1925 s = 0;
1926
1927 if (ea_data.bytes) {
1928 /* use compressed displacement, if available */
1929 data = ea_data.disp8 ? ea_data.disp8 : opy->offset;
1930 s += ea_data.bytes;
1931 if (ea_data.rip) {
1932 if (opy->segment == segment) {
1933 data -= insn_end;
1934 if (overflow_signed(data, ea_data.bytes))
1935 warn_overflow(ERR_PASS2, ea_data.bytes);
1936 out(offset, segment, &data, OUT_ADDRESS,
1937 ea_data.bytes, NO_SEG, NO_SEG);
1938 } else {
1939 /* overflow check in output/linker? */
1940 out(offset, segment, &data, OUT_REL4ADR,
1941 insn_end - offset, opy->segment, opy->wrt);
1942 }
1943 } else {
1944 int asize = ins->addr_size >> 3;
1945 int atype = ea_data.bytes;
1946
1947 if (overflow_general(data, asize) ||
1948 signed_bits(data, ins->addr_size) !=
1949 signed_bits(data, ea_data.bytes << 3))
1950 warn_overflow(ERR_PASS2, ea_data.bytes);
1951
1952 if (asize > ea_data.bytes) {
1953 /*
1954 * If the address isn't the full width of
1955 * the address size, treat is as signed...
1956 */
1957 atype = -atype;
1958 }
1959
1960 out(offset, segment, &data, OUT_ADDRESS,
1961 atype, opy->segment, opy->wrt);
1962 }
1963 }
1964 offset += s;
1965 }
1966 break;
1967
1968 default:
1969 nasm_panic(0, "internal instruction table corrupt"
1970 ": instruction code \\%o (0x%02X) given", c, c);
1971 break;
1972 }
1973 }
1974 }
1975
1976 static opflags_t regflag(const operand * o)
1977 {
1978 if (!is_register(o->basereg))
1979 nasm_panic(0, "invalid operand passed to regflag()");
1980 return nasm_reg_flags[o->basereg];
1981 }
1982
1983 static int32_t regval(const operand * o)
1984 {
1985 if (!is_register(o->basereg))
1986 nasm_panic(0, "invalid operand passed to regval()");
1987 return nasm_regvals[o->basereg];
1988 }
1989
1990 static int op_rexflags(const operand * o, int mask)
1991 {
1992 opflags_t flags;
1993 int val;
1994
1995 if (!is_register(o->basereg))
1996 nasm_panic(0, "invalid operand passed to op_rexflags()");
1997
1998 flags = nasm_reg_flags[o->basereg];
1999 val = nasm_regvals[o->basereg];
2000
2001 return rexflags(val, flags, mask);
2002 }
2003
2004 static int rexflags(int val, opflags_t flags, int mask)
2005 {
2006 int rex = 0;
2007
2008 if (val >= 0 && (val & 8))
2009 rex |= REX_B|REX_X|REX_R;
2010 if (flags & BITS64)
2011 rex |= REX_W;
2012 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
2013 rex |= REX_H;
2014 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
2015 rex |= REX_P;
2016
2017 return rex & mask;
2018 }
2019
2020 static int evexflags(int val, decoflags_t deco,
2021 int mask, uint8_t byte)
2022 {
2023 int evex = 0;
2024
2025 switch (byte) {
2026 case 0:
2027 if (val >= 0 && (val & 16))
2028 evex |= (EVEX_P0RP | EVEX_P0X);
2029 break;
2030 case 2:
2031 if (val >= 0 && (val & 16))
2032 evex |= EVEX_P2VP;
2033 if (deco & Z)
2034 evex |= EVEX_P2Z;
2035 if (deco & OPMASK_MASK)
2036 evex |= deco & EVEX_P2AAA;
2037 break;
2038 }
2039 return evex & mask;
2040 }
2041
2042 static int op_evexflags(const operand * o, int mask, uint8_t byte)
2043 {
2044 int val;
2045
2046 val = nasm_regvals[o->basereg];
2047
2048 return evexflags(val, o->decoflags, mask, byte);
2049 }
2050
2051 static enum match_result find_match(const struct itemplate **tempp,
2052 insn *instruction,
2053 int32_t segment, int64_t offset, int bits)
2054 {
2055 const struct itemplate *temp;
2056 enum match_result m, merr;
2057 opflags_t xsizeflags[MAX_OPERANDS];
2058 bool opsizemissing = false;
2059 int8_t broadcast = instruction->evex_brerop;
2060 int i;
2061
2062 /* broadcasting uses a different data element size */
2063 for (i = 0; i < instruction->operands; i++)
2064 if (i == broadcast)
2065 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
2066 else
2067 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
2068
2069 merr = MERR_INVALOP;
2070
2071 for (temp = nasm_instructions[instruction->opcode];
2072 temp->opcode != I_none; temp++) {
2073 m = matches(temp, instruction, bits);
2074 if (m == MOK_JUMP) {
2075 if (jmp_match(segment, offset, bits, instruction, temp))
2076 m = MOK_GOOD;
2077 else
2078 m = MERR_INVALOP;
2079 } else if (m == MERR_OPSIZEMISSING && !itemp_has(temp, IF_SX)) {
2080 /*
2081 * Missing operand size and a candidate for fuzzy matching...
2082 */
2083 for (i = 0; i < temp->operands; i++)
2084 if (i == broadcast)
2085 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
2086 else
2087 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
2088 opsizemissing = true;
2089 }
2090 if (m > merr)
2091 merr = m;
2092 if (merr == MOK_GOOD)
2093 goto done;
2094 }
2095
2096 /* No match, but see if we can get a fuzzy operand size match... */
2097 if (!opsizemissing)
2098 goto done;
2099
2100 for (i = 0; i < instruction->operands; i++) {
2101 /*
2102 * We ignore extrinsic operand sizes on registers, so we should
2103 * never try to fuzzy-match on them. This also resolves the case
2104 * when we have e.g. "xmmrm128" in two different positions.
2105 */
2106 if (is_class(REGISTER, instruction->oprs[i].type))
2107 continue;
2108
2109 /* This tests if xsizeflags[i] has more than one bit set */
2110 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2111 goto done; /* No luck */
2112
2113 if (i == broadcast) {
2114 instruction->oprs[i].decoflags |= xsizeflags[i];
2115 instruction->oprs[i].type |= (xsizeflags[i] == BR_BITS32 ?
2116 BITS32 : BITS64);
2117 } else {
2118 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2119 }
2120 }
2121
2122 /* Try matching again... */
2123 for (temp = nasm_instructions[instruction->opcode];
2124 temp->opcode != I_none; temp++) {
2125 m = matches(temp, instruction, bits);
2126 if (m == MOK_JUMP) {
2127 if (jmp_match(segment, offset, bits, instruction, temp))
2128 m = MOK_GOOD;
2129 else
2130 m = MERR_INVALOP;
2131 }
2132 if (m > merr)
2133 merr = m;
2134 if (merr == MOK_GOOD)
2135 goto done;
2136 }
2137
2138 done:
2139 *tempp = temp;
2140 return merr;
2141 }
2142
2143 static uint8_t get_broadcast_num(opflags_t opflags, opflags_t brsize)
2144 {
2145 opflags_t opsize = opflags & SIZE_MASK;
2146 uint8_t brcast_num;
2147
2148 /*
2149 * Due to discontinuity between BITS64 and BITS128 (BITS80),
2150 * this cannot be a simple arithmetic calculation.
2151 */
2152 if (brsize > BITS64)
2153 nasm_error(ERR_FATAL,
2154 "size of broadcasting element is greater than 64 bits");
2155
2156 switch (opsize) {
2157 case BITS64:
2158 brcast_num = BITS64 / brsize;
2159 break;
2160 default:
2161 brcast_num = (opsize / BITS128) * (BITS64 / brsize) * 2;
2162 break;
2163 }
2164
2165 return brcast_num;
2166 }
2167
2168 static enum match_result matches(const struct itemplate *itemp,
2169 insn *instruction, int bits)
2170 {
2171 opflags_t size[MAX_OPERANDS], asize;
2172 bool opsizemissing = false;
2173 int i, oprs;
2174
2175 /*
2176 * Check the opcode
2177 */
2178 if (itemp->opcode != instruction->opcode)
2179 return MERR_INVALOP;
2180
2181 /*
2182 * Count the operands
2183 */
2184 if (itemp->operands != instruction->operands)
2185 return MERR_INVALOP;
2186
2187 /*
2188 * Is it legal?
2189 */
2190 if (!(optimizing > 0) && itemp_has(itemp, IF_OPT))
2191 return MERR_INVALOP;
2192
2193 /*
2194 * {evex} available?
2195 */
2196 switch (instruction->prefixes[PPS_VEX]) {
2197 case P_EVEX:
2198 if (!itemp_has(itemp, IF_EVEX))
2199 return MERR_ENCMISMATCH;
2200 break;
2201 case P_VEX3:
2202 case P_VEX2:
2203 if (!itemp_has(itemp, IF_VEX))
2204 return MERR_ENCMISMATCH;
2205 break;
2206 default:
2207 break;
2208 }
2209
2210 /*
2211 * Check that no spurious colons or TOs are present
2212 */
2213 for (i = 0; i < itemp->operands; i++)
2214 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2215 return MERR_INVALOP;
2216
2217 /*
2218 * Process size flags
2219 */
2220 switch (itemp_smask(itemp)) {
2221 case IF_GENBIT(IF_SB):
2222 asize = BITS8;
2223 break;
2224 case IF_GENBIT(IF_SW):
2225 asize = BITS16;
2226 break;
2227 case IF_GENBIT(IF_SD):
2228 asize = BITS32;
2229 break;
2230 case IF_GENBIT(IF_SQ):
2231 asize = BITS64;
2232 break;
2233 case IF_GENBIT(IF_SO):
2234 asize = BITS128;
2235 break;
2236 case IF_GENBIT(IF_SY):
2237 asize = BITS256;
2238 break;
2239 case IF_GENBIT(IF_SZ):
2240 asize = BITS512;
2241 break;
2242 case IF_GENBIT(IF_SIZE):
2243 switch (bits) {
2244 case 16:
2245 asize = BITS16;
2246 break;
2247 case 32:
2248 asize = BITS32;
2249 break;
2250 case 64:
2251 asize = BITS64;
2252 break;
2253 default:
2254 asize = 0;
2255 break;
2256 }
2257 break;
2258 default:
2259 asize = 0;
2260 break;
2261 }
2262
2263 if (itemp_armask(itemp)) {
2264 /* S- flags only apply to a specific operand */
2265 i = itemp_arg(itemp);
2266 memset(size, 0, sizeof size);
2267 size[i] = asize;
2268 } else {
2269 /* S- flags apply to all operands */
2270 for (i = 0; i < MAX_OPERANDS; i++)
2271 size[i] = asize;
2272 }
2273
2274 /*
2275 * Check that the operand flags all match up,
2276 * it's a bit tricky so lets be verbose:
2277 *
2278 * 1) Find out the size of operand. If instruction
2279 * doesn't have one specified -- we're trying to
2280 * guess it either from template (IF_S* flag) or
2281 * from code bits.
2282 *
2283 * 2) If template operand do not match the instruction OR
2284 * template has an operand size specified AND this size differ
2285 * from which instruction has (perhaps we got it from code bits)
2286 * we are:
2287 * a) Check that only size of instruction and operand is differ
2288 * other characteristics do match
2289 * b) Perhaps it's a register specified in instruction so
2290 * for such a case we just mark that operand as "size
2291 * missing" and this will turn on fuzzy operand size
2292 * logic facility (handled by a caller)
2293 */
2294 for (i = 0; i < itemp->operands; i++) {
2295 opflags_t type = instruction->oprs[i].type;
2296 decoflags_t deco = instruction->oprs[i].decoflags;
2297 bool is_broadcast = deco & BRDCAST_MASK;
2298 uint8_t brcast_num = 0;
2299 opflags_t template_opsize, insn_opsize;
2300
2301 if (!(type & SIZE_MASK))
2302 type |= size[i];
2303
2304 insn_opsize = type & SIZE_MASK;
2305 if (!is_broadcast) {
2306 template_opsize = itemp->opd[i] & SIZE_MASK;
2307 } else {
2308 decoflags_t deco_brsize = itemp->deco[i] & BRSIZE_MASK;
2309 /*
2310 * when broadcasting, the element size depends on
2311 * the instruction type. decorator flag should match.
2312 */
2313
2314 if (deco_brsize) {
2315 template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
2316 /* calculate the proper number : {1to<brcast_num>} */
2317 brcast_num = get_broadcast_num(itemp->opd[i], template_opsize);
2318 } else {
2319 template_opsize = 0;
2320 }
2321 }
2322
2323 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2324 (deco & ~itemp->deco[i] & ~BRNUM_MASK)) {
2325 return MERR_INVALOP;
2326 } else if (template_opsize) {
2327 if (template_opsize != insn_opsize) {
2328 if (insn_opsize) {
2329 return MERR_INVALOP;
2330 } else if (!is_class(REGISTER, type)) {
2331 /*
2332 * Note: we don't honor extrinsic operand sizes for registers,
2333 * so "missing operand size" for a register should be
2334 * considered a wildcard match rather than an error.
2335 */
2336 opsizemissing = true;
2337 }
2338 } else if (is_broadcast &&
2339 (brcast_num !=
2340 (2U << ((deco & BRNUM_MASK) >> BRNUM_SHIFT)))) {
2341 /*
2342 * broadcasting opsize matches but the number of repeated memory
2343 * element does not match.
2344 * if 64b double precision float is broadcasted to ymm (256b),
2345 * broadcasting decorator must be {1to4}.
2346 */
2347 return MERR_BRNUMMISMATCH;
2348 }
2349 }
2350 }
2351
2352 if (opsizemissing)
2353 return MERR_OPSIZEMISSING;
2354
2355 /*
2356 * Check operand sizes
2357 */
2358 if (itemp_has(itemp, IF_SM) || itemp_has(itemp, IF_SM2)) {
2359 oprs = (itemp_has(itemp, IF_SM2) ? 2 : itemp->operands);
2360 for (i = 0; i < oprs; i++) {
2361 asize = itemp->opd[i] & SIZE_MASK;
2362 if (asize) {
2363 for (i = 0; i < oprs; i++)
2364 size[i] = asize;
2365 break;
2366 }
2367 }
2368 } else {
2369 oprs = itemp->operands;
2370 }
2371
2372 for (i = 0; i < itemp->operands; i++) {
2373 if (!(itemp->opd[i] & SIZE_MASK) &&
2374 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2375 return MERR_OPSIZEMISMATCH;
2376 }
2377
2378 /*
2379 * Check template is okay at the set cpu level
2380 */
2381 if (iflag_cmp_cpu_level(&insns_flags[itemp->iflag_idx], &cpu) > 0)
2382 return MERR_BADCPU;
2383
2384 /*
2385 * Verify the appropriate long mode flag.
2386 */
2387 if (itemp_has(itemp, (bits == 64 ? IF_NOLONG : IF_LONG)))
2388 return MERR_BADMODE;
2389
2390 /*
2391 * If we have a HLE prefix, look for the NOHLE flag
2392 */
2393 if (itemp_has(itemp, IF_NOHLE) &&
2394 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2395 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2396 return MERR_BADHLE;
2397
2398 /*
2399 * Check if special handling needed for Jumps
2400 */
2401 if ((itemp->code[0] & ~1) == 0370)
2402 return MOK_JUMP;
2403
2404 /*
2405 * Check if BND prefix is allowed.
2406 * Other 0xF2 (REPNE/REPNZ) prefix is prohibited.
2407 */
2408 if (!itemp_has(itemp, IF_BND) &&
2409 (has_prefix(instruction, PPS_REP, P_BND) ||
2410 has_prefix(instruction, PPS_REP, P_NOBND)))
2411 return MERR_BADBND;
2412 else if (itemp_has(itemp, IF_BND) &&
2413 (has_prefix(instruction, PPS_REP, P_REPNE) ||
2414 has_prefix(instruction, PPS_REP, P_REPNZ)))
2415 return MERR_BADREPNE;
2416
2417 return MOK_GOOD;
2418 }
2419
2420 /*
2421 * Check if ModR/M.mod should/can be 01.
2422 * - EAF_BYTEOFFS is set
2423 * - offset can fit in a byte when EVEX is not used
2424 * - offset can be compressed when EVEX is used
2425 */
2426 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2427 (o >= -128 && o <= 127 && \
2428 seg == NO_SEG && !forw_ref && \
2429 !(input->eaflags & EAF_WORDOFFS) && \
2430 !(ins->rex & REX_EV)) || \
2431 (ins->rex & REX_EV && \
2432 is_disp8n(input, ins, &output->disp8)))
2433
2434 static enum ea_type process_ea(operand *input, ea *output, int bits,
2435 int rfield, opflags_t rflags, insn *ins)
2436 {
2437 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2438 int addrbits = ins->addr_size;
2439 int eaflags = input->eaflags;
2440
2441 output->type = EA_SCALAR;
2442 output->rip = false;
2443 output->disp8 = 0;
2444
2445 /* REX flags for the rfield operand */
2446 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2447 /* EVEX.R' flag for the REG operand */
2448 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2449
2450 if (is_class(REGISTER, input->type)) {
2451 /*
2452 * It's a direct register.
2453 */
2454 if (!is_register(input->basereg))
2455 goto err;
2456
2457 if (!is_reg_class(REG_EA, input->basereg))
2458 goto err;
2459
2460 /* broadcasting is not available with a direct register operand. */
2461 if (input->decoflags & BRDCAST_MASK) {
2462 nasm_error(ERR_NONFATAL, "Broadcasting not allowed from a register");
2463 goto err;
2464 }
2465
2466 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2467 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2468 output->sib_present = false; /* no SIB necessary */
2469 output->bytes = 0; /* no offset necessary either */
2470 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2471 } else {
2472 /*
2473 * It's a memory reference.
2474 */
2475
2476 /* Embedded rounding or SAE is not available with a mem ref operand. */
2477 if (input->decoflags & (ER | SAE)) {
2478 nasm_error(ERR_NONFATAL,
2479 "Embedded rounding is available only with reg-reg op.");
2480 return -1;
2481 }
2482
2483 if (input->basereg == -1 &&
2484 (input->indexreg == -1 || input->scale == 0)) {
2485 /*
2486 * It's a pure offset.
2487 */
2488 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2489 input->segment == NO_SEG) {
2490 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2491 input->type &= ~IP_REL;
2492 input->type |= MEMORY;
2493 }
2494
2495 if (bits == 64 &&
2496 !(IP_REL & ~input->type) && (eaflags & EAF_MIB)) {
2497 nasm_error(ERR_NONFATAL, "RIP-relative addressing is prohibited for mib.");
2498 return -1;
2499 }
2500
2501 if (eaflags & EAF_BYTEOFFS ||
2502 (eaflags & EAF_WORDOFFS &&
2503 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2504 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2505 }
2506
2507 if (bits == 64 && (~input->type & IP_REL)) {
2508 output->sib_present = true;
2509 output->sib = GEN_SIB(0, 4, 5);
2510 output->bytes = 4;
2511 output->modrm = GEN_MODRM(0, rfield, 4);
2512 output->rip = false;
2513 } else {
2514 output->sib_present = false;
2515 output->bytes = (addrbits != 16 ? 4 : 2);
2516 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2517 output->rip = bits == 64;
2518 }
2519 } else {
2520 /*
2521 * It's an indirection.
2522 */
2523 int i = input->indexreg, b = input->basereg, s = input->scale;
2524 int32_t seg = input->segment;
2525 int hb = input->hintbase, ht = input->hinttype;
2526 int t, it, bt; /* register numbers */
2527 opflags_t x, ix, bx; /* register flags */
2528
2529 if (s == 0)
2530 i = -1; /* make this easy, at least */
2531
2532 if (is_register(i)) {
2533 it = nasm_regvals[i];
2534 ix = nasm_reg_flags[i];
2535 } else {
2536 it = -1;
2537 ix = 0;
2538 }
2539
2540 if (is_register(b)) {
2541 bt = nasm_regvals[b];
2542 bx = nasm_reg_flags[b];
2543 } else {
2544 bt = -1;
2545 bx = 0;
2546 }
2547
2548 /* if either one are a vector register... */
2549 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2550 opflags_t sok = BITS32 | BITS64;
2551 int32_t o = input->offset;
2552 int mod, scale, index, base;
2553
2554 /*
2555 * For a vector SIB, one has to be a vector and the other,
2556 * if present, a GPR. The vector must be the index operand.
2557 */
2558 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2559 if (s == 0)
2560 s = 1;
2561 else if (s != 1)
2562 goto err;
2563
2564 t = bt, bt = it, it = t;
2565 x = bx, bx = ix, ix = x;
2566 }
2567
2568 if (bt != -1) {
2569 if (REG_GPR & ~bx)
2570 goto err;
2571 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2572 sok &= bx;
2573 else
2574 goto err;
2575 }
2576
2577 /*
2578 * While we're here, ensure the user didn't specify
2579 * WORD or QWORD
2580 */
2581 if (input->disp_size == 16 || input->disp_size == 64)
2582 goto err;
2583
2584 if (addrbits == 16 ||
2585 (addrbits == 32 && !(sok & BITS32)) ||
2586 (addrbits == 64 && !(sok & BITS64)))
2587 goto err;
2588
2589 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2590 : ((ix & YMMREG & ~REG_EA)
2591 ? EA_YMMVSIB : EA_XMMVSIB));
2592
2593 output->rex |= rexflags(it, ix, REX_X);
2594 output->rex |= rexflags(bt, bx, REX_B);
2595 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2596
2597 index = it & 7; /* it is known to be != -1 */
2598
2599 switch (s) {
2600 case 1:
2601 scale = 0;
2602 break;
2603 case 2:
2604 scale = 1;
2605 break;
2606 case 4:
2607 scale = 2;
2608 break;
2609 case 8:
2610 scale = 3;
2611 break;
2612 default: /* then what the smeg is it? */
2613 goto err; /* panic */
2614 }
2615
2616 if (bt == -1) {
2617 base = 5;
2618 mod = 0;
2619 } else {
2620 base = (bt & 7);
2621 if (base != REG_NUM_EBP && o == 0 &&
2622 seg == NO_SEG && !forw_ref &&
2623 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2624 mod = 0;
2625 else if (IS_MOD_01())
2626 mod = 1;
2627 else
2628 mod = 2;
2629 }
2630
2631 output->sib_present = true;
2632 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2633 output->modrm = GEN_MODRM(mod, rfield, 4);
2634 output->sib = GEN_SIB(scale, index, base);
2635 } else if ((ix|bx) & (BITS32|BITS64)) {
2636 /*
2637 * it must be a 32/64-bit memory reference. Firstly we have
2638 * to check that all registers involved are type E/Rxx.
2639 */
2640 opflags_t sok = BITS32 | BITS64;
2641 int32_t o = input->offset;
2642
2643 if (it != -1) {
2644 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2645 sok &= ix;
2646 else
2647 goto err;
2648 }
2649
2650 if (bt != -1) {
2651 if (REG_GPR & ~bx)
2652 goto err; /* Invalid register */
2653 if (~sok & bx & SIZE_MASK)
2654 goto err; /* Invalid size */
2655 sok &= bx;
2656 }
2657
2658 /*
2659 * While we're here, ensure the user didn't specify
2660 * WORD or QWORD
2661 */
2662 if (input->disp_size == 16 || input->disp_size == 64)
2663 goto err;
2664
2665 if (addrbits == 16 ||
2666 (addrbits == 32 && !(sok & BITS32)) ||
2667 (addrbits == 64 && !(sok & BITS64)))
2668 goto err;
2669
2670 /* now reorganize base/index */
2671 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2672 ((hb == b && ht == EAH_NOTBASE) ||
2673 (hb == i && ht == EAH_MAKEBASE))) {
2674 /* swap if hints say so */
2675 t = bt, bt = it, it = t;
2676 x = bx, bx = ix, ix = x;
2677 }
2678
2679 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
2680 /* make single reg base, unless hint */
2681 bt = it, bx = ix, it = -1, ix = 0;
2682 }
2683 if (eaflags & EAF_MIB) {
2684 /* only for mib operands */
2685 if (it == -1 && (hb == b && ht == EAH_NOTBASE)) {
2686 /*
2687 * make a single reg index [reg*1].
2688 * gas uses this form for an explicit index register.
2689 */
2690 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2691 }
2692 if ((ht == EAH_SUMMED) && bt == -1) {
2693 /* separate once summed index into [base, index] */
2694 bt = it, bx = ix, s--;
2695 }
2696 } else {
2697 if (((s == 2 && it != REG_NUM_ESP &&
2698 (!(eaflags & EAF_TIMESTWO) || (ht == EAH_SUMMED))) ||
2699 s == 3 || s == 5 || s == 9) && bt == -1) {
2700 /* convert 3*EAX to EAX+2*EAX */
2701 bt = it, bx = ix, s--;
2702 }
2703 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2704 (eaflags & EAF_TIMESTWO) &&
2705 (hb == b && ht == EAH_NOTBASE)) {
2706 /*
2707 * convert [NOSPLIT EAX*1]
2708 * to sib format with 0x0 displacement - [EAX*1+0].
2709 */
2710 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2711 }
2712 }
2713 if (s == 1 && it == REG_NUM_ESP) {
2714 /* swap ESP into base if scale is 1 */
2715 t = it, it = bt, bt = t;
2716 x = ix, ix = bx, bx = x;
2717 }
2718 if (it == REG_NUM_ESP ||
2719 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2720 goto err; /* wrong, for various reasons */
2721
2722 output->rex |= rexflags(it, ix, REX_X);
2723 output->rex |= rexflags(bt, bx, REX_B);
2724
2725 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2726 /* no SIB needed */
2727 int mod, rm;
2728
2729 if (bt == -1) {
2730 rm = 5;
2731 mod = 0;
2732 } else {
2733 rm = (bt & 7);
2734 if (rm != REG_NUM_EBP && o == 0 &&
2735 seg == NO_SEG && !forw_ref &&
2736 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2737 mod = 0;
2738 else if (IS_MOD_01())
2739 mod = 1;
2740 else
2741 mod = 2;
2742 }
2743
2744 output->sib_present = false;
2745 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2746 output->modrm = GEN_MODRM(mod, rfield, rm);
2747 } else {
2748 /* we need a SIB */
2749 int mod, scale, index, base;
2750
2751 if (it == -1)
2752 index = 4, s = 1;
2753 else
2754 index = (it & 7);
2755
2756 switch (s) {
2757 case 1:
2758 scale = 0;
2759 break;
2760 case 2:
2761 scale = 1;
2762 break;
2763 case 4:
2764 scale = 2;
2765 break;
2766 case 8:
2767 scale = 3;
2768 break;
2769 default: /* then what the smeg is it? */
2770 goto err; /* panic */
2771 }
2772
2773 if (bt == -1) {
2774 base = 5;
2775 mod = 0;
2776 } else {
2777 base = (bt & 7);
2778 if (base != REG_NUM_EBP && o == 0 &&
2779 seg == NO_SEG && !forw_ref &&
2780 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2781 mod = 0;
2782 else if (IS_MOD_01())
2783 mod = 1;
2784 else
2785 mod = 2;
2786 }
2787
2788 output->sib_present = true;
2789 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2790 output->modrm = GEN_MODRM(mod, rfield, 4);
2791 output->sib = GEN_SIB(scale, index, base);
2792 }
2793 } else { /* it's 16-bit */
2794 int mod, rm;
2795 int16_t o = input->offset;
2796
2797 /* check for 64-bit long mode */
2798 if (addrbits == 64)
2799 goto err;
2800
2801 /* check all registers are BX, BP, SI or DI */
2802 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2803 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2804 goto err;
2805
2806 /* ensure the user didn't specify DWORD/QWORD */
2807 if (input->disp_size == 32 || input->disp_size == 64)
2808 goto err;
2809
2810 if (s != 1 && i != -1)
2811 goto err; /* no can do, in 16-bit EA */
2812 if (b == -1 && i != -1) {
2813 int tmp = b;
2814 b = i;
2815 i = tmp;
2816 } /* swap */
2817 if ((b == R_SI || b == R_DI) && i != -1) {
2818 int tmp = b;
2819 b = i;
2820 i = tmp;
2821 }
2822 /* have BX/BP as base, SI/DI index */
2823 if (b == i)
2824 goto err; /* shouldn't ever happen, in theory */
2825 if (i != -1 && b != -1 &&
2826 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2827 goto err; /* invalid combinations */
2828 if (b == -1) /* pure offset: handled above */
2829 goto err; /* so if it gets to here, panic! */
2830
2831 rm = -1;
2832 if (i != -1)
2833 switch (i * 256 + b) {
2834 case R_SI * 256 + R_BX:
2835 rm = 0;
2836 break;
2837 case R_DI * 256 + R_BX:
2838 rm = 1;
2839 break;
2840 case R_SI * 256 + R_BP:
2841 rm = 2;
2842 break;
2843 case R_DI * 256 + R_BP:
2844 rm = 3;
2845 break;
2846 } else
2847 switch (b) {
2848 case R_SI:
2849 rm = 4;
2850 break;
2851 case R_DI:
2852 rm = 5;
2853 break;
2854 case R_BP:
2855 rm = 6;
2856 break;
2857 case R_BX:
2858 rm = 7;
2859 break;
2860 }
2861 if (rm == -1) /* can't happen, in theory */
2862 goto err; /* so panic if it does */
2863
2864 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2865 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2866 mod = 0;
2867 else if (IS_MOD_01())
2868 mod = 1;
2869 else
2870 mod = 2;
2871
2872 output->sib_present = false; /* no SIB - it's 16-bit */
2873 output->bytes = mod; /* bytes of offset needed */
2874 output->modrm = GEN_MODRM(mod, rfield, rm);
2875 }
2876 }
2877 }
2878
2879 output->size = 1 + output->sib_present + output->bytes;
2880 return output->type;
2881
2882 err:
2883 return output->type = EA_INVALID;
2884 }
2885
2886 static void add_asp(insn *ins, int addrbits)
2887 {
2888 int j, valid;
2889 int defdisp;
2890
2891 valid = (addrbits == 64) ? 64|32 : 32|16;
2892
2893 switch (ins->prefixes[PPS_ASIZE]) {
2894 case P_A16:
2895 valid &= 16;
2896 break;
2897 case P_A32:
2898 valid &= 32;
2899 break;
2900 case P_A64:
2901 valid &= 64;
2902 break;
2903 case P_ASP:
2904 valid &= (addrbits == 32) ? 16 : 32;
2905 break;
2906 default:
2907 break;
2908 }
2909
2910 for (j = 0; j < ins->operands; j++) {
2911 if (is_class(MEMORY, ins->oprs[j].type)) {
2912 opflags_t i, b;
2913
2914 /* Verify as Register */
2915 if (!is_register(ins->oprs[j].indexreg))
2916 i = 0;
2917 else
2918 i = nasm_reg_flags[ins->oprs[j].indexreg];
2919
2920 /* Verify as Register */
2921 if (!is_register(ins->oprs[j].basereg))
2922 b = 0;
2923 else
2924 b = nasm_reg_flags[ins->oprs[j].basereg];
2925
2926 if (ins->oprs[j].scale == 0)
2927 i = 0;
2928
2929 if (!i && !b) {
2930 int ds = ins->oprs[j].disp_size;
2931 if ((addrbits != 64 && ds > 8) ||
2932 (addrbits == 64 && ds == 16))
2933 valid &= ds;
2934 } else {
2935 if (!(REG16 & ~b))
2936 valid &= 16;
2937 if (!(REG32 & ~b))
2938 valid &= 32;
2939 if (!(REG64 & ~b))
2940 valid &= 64;
2941
2942 if (!(REG16 & ~i))
2943 valid &= 16;
2944 if (!(REG32 & ~i))
2945 valid &= 32;
2946 if (!(REG64 & ~i))
2947 valid &= 64;
2948 }
2949 }
2950 }
2951
2952 if (valid & addrbits) {
2953 ins->addr_size = addrbits;
2954 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2955 /* Add an address size prefix */
2956 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2957 ins->addr_size = (addrbits == 32) ? 16 : 32;
2958 } else {
2959 /* Impossible... */
2960 nasm_error(ERR_NONFATAL, "impossible combination of address sizes");
2961 ins->addr_size = addrbits; /* Error recovery */
2962 }
2963
2964 defdisp = ins->addr_size == 16 ? 16 : 32;
2965
2966 for (j = 0; j < ins->operands; j++) {
2967 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2968 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2969 /*
2970 * mem_offs sizes must match the address size; if not,
2971 * strip the MEM_OFFS bit and match only EA instructions
2972 */
2973 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2974 }
2975 }
2976 }
The Netwide Assembler