1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2012 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * disasm.c where all the _work_ gets done in the Netwide Disassembler
54 * Flags that go into the `segment' field of `insn' structures
57 #define SEG_RELATIVE 1
64 #define SEG_SIGNED 128
71 uint8_t osize
; /* Operand size */
72 uint8_t asize
; /* Address size */
73 uint8_t osp
; /* Operand size prefix present */
74 uint8_t asp
; /* Address size prefix present */
75 uint8_t rep
; /* Rep prefix present */
76 uint8_t seg
; /* Segment override prefix present */
77 uint8_t wait
; /* WAIT "prefix" present */
78 uint8_t lock
; /* Lock prefix present */
79 uint8_t vex
[3]; /* VEX prefix present */
80 uint8_t vex_c
; /* VEX "class" (VEX, XOP, ...) */
81 uint8_t vex_m
; /* VEX.M field */
83 uint8_t vex_lp
; /* VEX.LP fields */
84 uint32_t rex
; /* REX prefix present */
85 uint8_t evex
[3]; /* EVEX prefix present */
88 #define getu8(x) (*(uint8_t *)(x))
90 /* Littleendian CPU which can handle unaligned references */
91 #define getu16(x) (*(uint16_t *)(x))
92 #define getu32(x) (*(uint32_t *)(x))
93 #define getu64(x) (*(uint64_t *)(x))
95 static uint16_t getu16(uint8_t *data
)
97 return (uint16_t)data
[0] + ((uint16_t)data
[1] << 8);
99 static uint32_t getu32(uint8_t *data
)
101 return (uint32_t)getu16(data
) + ((uint32_t)getu16(data
+2) << 16);
103 static uint64_t getu64(uint8_t *data
)
105 return (uint64_t)getu32(data
) + ((uint64_t)getu32(data
+4) << 32);
109 #define gets8(x) ((int8_t)getu8(x))
110 #define gets16(x) ((int16_t)getu16(x))
111 #define gets32(x) ((int32_t)getu32(x))
112 #define gets64(x) ((int64_t)getu64(x))
114 /* Important: regval must already have been adjusted for rex extensions */
115 static enum reg_enum
whichreg(opflags_t regflags
, int regval
, int rex
)
119 static const struct {
122 } specific_registers
[] = {
148 if (!(regflags
& (REGISTER
|REGMEM
)))
149 return 0; /* Registers not permissible?! */
151 regflags
|= REGISTER
;
153 for (i
= 0; i
< ARRAY_SIZE(specific_registers
); i
++)
154 if (!(specific_registers
[i
].flags
& ~regflags
))
155 return specific_registers
[i
].reg
;
157 /* All the entries below look up regval in an 16-entry array */
158 if (regval
< 0 || regval
> (rex
& REX_EV
? 31 : 15))
161 if (!(REG8
& ~regflags
)) {
162 if (rex
& (REX_P
|REX_NH
))
163 return nasm_rd_reg8_rex
[regval
];
165 return nasm_rd_reg8
[regval
];
167 if (!(REG16
& ~regflags
))
168 return nasm_rd_reg16
[regval
];
169 if (!(REG32
& ~regflags
))
170 return nasm_rd_reg32
[regval
];
171 if (!(REG64
& ~regflags
))
172 return nasm_rd_reg64
[regval
];
173 if (!(REG_SREG
& ~regflags
))
174 return nasm_rd_sreg
[regval
& 7]; /* Ignore REX */
175 if (!(REG_CREG
& ~regflags
))
176 return nasm_rd_creg
[regval
];
177 if (!(REG_DREG
& ~regflags
))
178 return nasm_rd_dreg
[regval
];
179 if (!(REG_TREG
& ~regflags
)) {
181 return 0; /* TR registers are ill-defined with rex */
182 return nasm_rd_treg
[regval
];
184 if (!(FPUREG
& ~regflags
))
185 return nasm_rd_fpureg
[regval
& 7]; /* Ignore REX */
186 if (!(MMXREG
& ~regflags
))
187 return nasm_rd_mmxreg
[regval
& 7]; /* Ignore REX */
188 if (!(XMMREG
& ~regflags
))
189 return nasm_rd_xmmreg
[regval
];
190 if (!(YMMREG
& ~regflags
))
191 return nasm_rd_ymmreg
[regval
];
192 if (!(ZMMREG
& ~regflags
))
193 return nasm_rd_zmmreg
[regval
];
194 if (!(OPMASKREG
& ~regflags
))
195 return nasm_rd_opmaskreg
[regval
];
196 if (!(BNDREG
& ~regflags
))
197 return nasm_rd_bndreg
[regval
];
202 static uint32_t append_evex_reg_deco(char *buf
, uint32_t num
,
203 decoflags_t deco
, uint8_t *evex
)
205 const char * const er_names
[] = {"rn-sae", "rd-sae", "ru-sae", "rz-sae"};
206 uint32_t num_chars
= 0;
208 if ((deco
& MASK
) && (evex
[2] & EVEX_P2AAA
)) {
209 enum reg_enum opmasknum
= nasm_rd_opmaskreg
[evex
[2] & EVEX_P2AAA
];
210 const char * regname
= nasm_reg_names
[opmasknum
- EXPR_REG_START
];
212 num_chars
+= snprintf(buf
+ num_chars
, num
- num_chars
,
215 if ((deco
& Z
) && (evex
[2] & EVEX_P2Z
)) {
216 num_chars
+= snprintf(buf
+ num_chars
, num
- num_chars
,
221 if (evex
[2] & EVEX_P2B
) {
223 uint8_t er_type
= (evex
[2] & EVEX_P2LL
) >> 5;
224 num_chars
+= snprintf(buf
+ num_chars
, num
- num_chars
,
225 ",{%s}", er_names
[er_type
]);
226 } else if (deco
& SAE
) {
227 num_chars
+= snprintf(buf
+ num_chars
, num
- num_chars
,
235 static uint32_t append_evex_mem_deco(char *buf
, uint32_t num
, opflags_t type
,
236 decoflags_t deco
, uint8_t *evex
)
238 uint32_t num_chars
= 0;
240 if ((evex
[2] & EVEX_P2B
) && (deco
& BRDCAST_MASK
)) {
241 decoflags_t deco_brsize
= deco
& BRSIZE_MASK
;
242 opflags_t template_opsize
= (deco_brsize
== BR_BITS32
? BITS32
: BITS64
);
243 uint8_t br_num
= (type
& SIZE_MASK
) / BITS128
*
244 BITS64
/ template_opsize
* 2;
246 num_chars
+= snprintf(buf
+ num_chars
, num
- num_chars
,
250 if ((deco
& MASK
) && (evex
[2] & EVEX_P2AAA
)) {
251 enum reg_enum opmasknum
= nasm_rd_opmaskreg
[evex
[2] & EVEX_P2AAA
];
252 const char * regname
= nasm_reg_names
[opmasknum
- EXPR_REG_START
];
254 num_chars
+= snprintf(buf
+ num_chars
, num
- num_chars
,
257 if ((deco
& Z
) && (evex
[2] & EVEX_P2Z
)) {
258 num_chars
+= snprintf(buf
+ num_chars
, num
- num_chars
,
268 * Process an effective address (ModRM) specification.
270 static uint8_t *do_ea(uint8_t *data
, int modrm
, int asize
,
271 int segsize
, enum ea_type type
,
272 operand
*op
, insn
*ins
)
274 int mod
, rm
, scale
, index
, base
;
278 bool is_evex
= !!(ins
->rex
& REX_EV
);
280 mod
= (modrm
>> 6) & 03;
283 if (mod
!= 3 && asize
!= 16 && rm
== 4)
289 if (mod
== 3) { /* pure register version */
290 op
->basereg
= rm
+(rex
& REX_B
? 8 : 0);
291 op
->segment
|= SEG_RMREG
;
292 if (is_evex
&& segsize
== 64) {
293 op
->basereg
+= (evex
[0] & EVEX_P0X
? 0 : 16);
303 * <mod> specifies the displacement size (none, byte or
304 * word), and <rm> specifies the register combination.
305 * Exception: mod=0,rm=6 does not specify [BP] as one might
306 * expect, but instead specifies [disp16].
309 if (type
!= EA_SCALAR
)
312 op
->indexreg
= op
->basereg
= -1;
313 op
->scale
= 1; /* always, in 16 bits */
344 if (rm
== 6 && mod
== 0) { /* special case */
348 mod
= 2; /* fake disp16 */
352 op
->segment
|= SEG_NODISP
;
355 op
->segment
|= SEG_DISP8
;
356 if (ins
->evex_tuple
!= 0) {
357 op
->offset
= gets8(data
) * get_disp8N(ins
);
359 op
->offset
= gets8(data
);
364 op
->segment
|= SEG_DISP16
;
365 op
->offset
= *data
++;
366 op
->offset
|= ((unsigned)*data
++) << 8;
372 * Once again, <mod> specifies displacement size (this time
373 * none, byte or *dword*), while <rm> specifies the base
374 * register. Again, [EBP] is missing, replaced by a pure
375 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
376 * and RIP-relative addressing in 64-bit mode.
379 * indicates not a single base register, but instead the
380 * presence of a SIB byte...
382 int a64
= asize
== 64;
387 op
->basereg
= nasm_rd_reg64
[rm
| ((rex
& REX_B
) ? 8 : 0)];
389 op
->basereg
= nasm_rd_reg32
[rm
| ((rex
& REX_B
) ? 8 : 0)];
391 if (rm
== 5 && mod
== 0) {
393 op
->eaflags
|= EAF_REL
;
394 op
->segment
|= SEG_RELATIVE
;
395 mod
= 2; /* fake disp32 */
399 op
->disp_size
= asize
;
402 mod
= 2; /* fake disp32 */
406 if (rm
== 4) { /* process SIB */
408 scale
= (sib
>> 6) & 03;
409 index
= (sib
>> 3) & 07;
412 op
->scale
= 1 << scale
;
415 vsib_hi
= (rex
& REX_X
? 8 : 0) |
416 (evex
[2] & EVEX_P2VP
? 0 : 16);
419 if (type
== EA_XMMVSIB
)
420 op
->indexreg
= nasm_rd_xmmreg
[index
| vsib_hi
];
421 else if (type
== EA_YMMVSIB
)
422 op
->indexreg
= nasm_rd_ymmreg
[index
| vsib_hi
];
423 else if (type
== EA_ZMMVSIB
)
424 op
->indexreg
= nasm_rd_zmmreg
[index
| vsib_hi
];
425 else if (index
== 4 && !(rex
& REX_X
))
426 op
->indexreg
= -1; /* ESP/RSP cannot be an index */
428 op
->indexreg
= nasm_rd_reg64
[index
| ((rex
& REX_X
) ? 8 : 0)];
430 op
->indexreg
= nasm_rd_reg32
[index
| ((rex
& REX_X
) ? 8 : 0)];
432 if (base
== 5 && mod
== 0) {
434 mod
= 2; /* Fake disp32 */
436 op
->basereg
= nasm_rd_reg64
[base
| ((rex
& REX_B
) ? 8 : 0)];
438 op
->basereg
= nasm_rd_reg32
[base
| ((rex
& REX_B
) ? 8 : 0)];
442 } else if (type
!= EA_SCALAR
) {
443 /* Can't have VSIB without SIB */
449 op
->segment
|= SEG_NODISP
;
452 op
->segment
|= SEG_DISP8
;
453 if (ins
->evex_tuple
!= 0) {
454 op
->offset
= gets8(data
) * get_disp8N(ins
);
456 op
->offset
= gets8(data
);
461 op
->segment
|= SEG_DISP32
;
462 op
->offset
= gets32(data
);
471 * Determine whether the instruction template in t corresponds to the data
472 * stream in data. Return the number of bytes matched if so.
474 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
476 static int matches(const struct itemplate
*t
, uint8_t *data
,
477 const struct prefix_info
*prefix
, int segsize
, insn
*ins
)
479 uint8_t *r
= (uint8_t *)(t
->code
);
480 uint8_t *origdata
= data
;
481 bool a_used
= false, o_used
= false;
482 enum prefixes drep
= 0;
483 enum prefixes dwait
= 0;
484 uint8_t lock
= prefix
->lock
;
485 int osize
= prefix
->osize
;
486 int asize
= prefix
->asize
;
489 struct operand
*opx
, *opy
;
492 int regmask
= (segsize
== 64) ? 15 : 7;
493 enum ea_type eat
= EA_SCALAR
;
495 for (i
= 0; i
< MAX_OPERANDS
; i
++) {
496 ins
->oprs
[i
].segment
= ins
->oprs
[i
].disp_size
=
497 (segsize
== 64 ? SEG_64BIT
: segsize
== 32 ? SEG_32BIT
: 0);
501 ins
->rex
= prefix
->rex
;
502 memset(ins
->prefixes
, 0, sizeof ins
->prefixes
);
504 if (itemp_has(t
, (segsize
== 64 ? IF_NOLONG
: IF_LONG
)))
507 if (prefix
->rep
== 0xF2)
508 drep
= (itemp_has(t
, IF_BND
) ? P_BND
: P_REPNE
);
509 else if (prefix
->rep
== 0xF3)
512 dwait
= prefix
->wait
? P_WAIT
: 0;
514 while ((c
= *r
++) != 0) {
515 op1
= (c
& 3) + ((opex
& 1) << 2);
516 op2
= ((c
>> 3) & 3) + ((opex
& 2) << 1);
517 opx
= &ins
->oprs
[op1
];
518 opy
= &ins
->oprs
[op2
];
539 int t
= *r
++, d
= *data
++;
540 if (d
< t
|| d
> t
+ 7)
543 opx
->basereg
= (d
-t
)+
544 (ins
->rex
& REX_B
? 8 : 0);
545 opx
->segment
|= SEG_RMREG
;
551 /* this is an separate index reg position of MIB operand (ICC) */
552 /* Disassembler uses NASM's split EA form only */
556 opx
->offset
= (int8_t)*data
++;
557 opx
->segment
|= SEG_SIGNED
;
561 opx
->offset
= *data
++;
565 opx
->offset
= *data
++;
569 opx
->offset
= getu16(data
);
575 opx
->offset
= getu32(data
);
578 opx
->offset
= getu16(data
);
581 if (segsize
!= asize
)
582 opx
->disp_size
= asize
;
586 opx
->offset
= getu32(data
);
591 opx
->offset
= gets32(data
);
598 opx
->offset
= getu16(data
);
604 opx
->offset
= getu32(data
);
610 opx
->offset
= getu64(data
);
618 opx
->offset
= gets8(data
++);
619 opx
->segment
|= SEG_RELATIVE
;
623 opx
->offset
= getu64(data
);
628 opx
->offset
= gets16(data
);
630 opx
->segment
|= SEG_RELATIVE
;
631 opx
->segment
&= ~SEG_32BIT
;
634 case4(064): /* rel */
635 opx
->segment
|= SEG_RELATIVE
;
636 /* In long mode rel is always 32 bits, sign extended. */
637 if (segsize
== 64 || osize
== 32) {
638 opx
->offset
= gets32(data
);
641 opx
->segment
|= SEG_32BIT
;
642 opx
->type
= (opx
->type
& ~SIZE_MASK
)
643 | (segsize
== 64 ? BITS64
: BITS32
);
645 opx
->offset
= gets16(data
);
647 opx
->segment
&= ~SEG_32BIT
;
648 opx
->type
= (opx
->type
& ~SIZE_MASK
) | BITS16
;
653 opx
->offset
= gets32(data
);
655 opx
->segment
|= SEG_32BIT
| SEG_RELATIVE
;
664 opx
->segment
|= SEG_RMREG
;
665 data
= do_ea(data
, modrm
, asize
, segsize
, eat
, opy
, ins
);
668 opx
->basereg
= ((modrm
>> 3) & 7) + (ins
->rex
& REX_R
? 8 : 0);
669 if ((ins
->rex
& REX_EV
) && (segsize
== 64))
670 opx
->basereg
+= (ins
->evex_p
[0] & EVEX_P0RP
? 0 : 16);
676 uint8_t ximm
= *data
++;
678 ins
->oprs
[c
>> 3].basereg
= (ximm
>> 4) & regmask
;
679 ins
->oprs
[c
>> 3].segment
|= SEG_RMREG
;
680 ins
->oprs
[c
& 7].offset
= ximm
& 15;
686 uint8_t ximm
= *data
++;
692 ins
->oprs
[c
>> 4].basereg
= (ximm
>> 4) & regmask
;
693 ins
->oprs
[c
>> 4].segment
|= SEG_RMREG
;
699 uint8_t ximm
= *data
++;
701 opx
->basereg
= (ximm
>> 4) & regmask
;
702 opx
->segment
|= SEG_RMREG
;
716 if (((modrm
>> 3) & 07) != (c
& 07))
717 return false; /* spare field doesn't match up */
718 data
= do_ea(data
, modrm
, asize
, segsize
, eat
, opy
, ins
);
727 uint8_t evexm
= *r
++;
728 uint8_t evexwlp
= *r
++;
729 uint8_t modrm
, valid_mask
;
730 ins
->evex_tuple
= *r
++ - 0300;
731 modrm
= *(origdata
+ 1);
734 if ((prefix
->rex
& (REX_EV
|REX_V
|REX_P
)) != REX_EV
)
737 if ((evexm
& 0x1f) != prefix
->vex_m
)
740 switch (evexwlp
& 060) {
742 if (prefix
->rex
& REX_W
)
746 if (!(prefix
->rex
& REX_W
))
750 case 040: /* VEX.W is a don't care */
757 /* If EVEX.b is set with reg-reg op,
758 * EVEX.L'L contains embedded rounding control info
760 if ((prefix
->evex
[2] & EVEX_P2B
) && ((modrm
>> 6) == 3)) {
761 valid_mask
= 0x3; /* prefix only */
763 valid_mask
= 0xf; /* vector length and prefix */
765 if ((evexwlp
^ prefix
->vex_lp
) & valid_mask
)
769 if ((prefix
->vex_v
!= 0) ||
770 (!(prefix
->evex
[2] & EVEX_P2VP
) &&
771 ((eat
< EA_XMMVSIB
) || (eat
> EA_ZMMVSIB
))))
774 opx
->segment
|= SEG_RMREG
;
775 opx
->basereg
= ((~prefix
->evex
[2] & EVEX_P2VP
) << (4 - 3) ) |
779 memcpy(ins
->evex_p
, prefix
->evex
, 3);
790 if ((prefix
->rex
& (REX_V
|REX_P
)) != REX_V
)
793 if ((vexm
& 0x1f) != prefix
->vex_m
)
796 switch (vexwlp
& 060) {
798 if (prefix
->rex
& REX_W
)
802 if (!(prefix
->rex
& REX_W
))
806 case 040: /* VEX.W is a don't care */
813 /* The 010 bit of vexwlp is set if VEX.L is ignored */
814 if ((vexwlp
^ prefix
->vex_lp
) & ((vexwlp
& 010) ? 03 : 07))
818 if (prefix
->vex_v
!= 0)
821 opx
->segment
|= SEG_RMREG
;
822 opx
->basereg
= prefix
->vex_v
;
829 if (prefix
->rep
== 0xF3)
834 if (prefix
->rep
== 0xF2)
836 else if (prefix
->rep
== 0xF3)
841 if (prefix
->lock
== 0xF0) {
842 if (prefix
->rep
== 0xF2)
844 else if (prefix
->rep
== 0xF3)
864 if (asize
!= segsize
)
878 if (prefix
->rex
& REX_B
)
883 if (prefix
->rex
& REX_X
)
888 if (prefix
->rex
& REX_R
)
893 if (prefix
->rex
& REX_W
)
912 if (osize
!= (segsize
== 16) ? 16 : 32)
919 ins
->rex
|= REX_W
; /* 64-bit only instruction */
936 int t
= *r
++, d
= *data
++;
937 if (d
< t
|| d
> t
+ 15)
940 ins
->condition
= d
- t
;
945 if (prefix
->rep
== 0xF3)
955 if (prefix
->rep
!= 0xF2)
961 if (prefix
->rep
!= 0xF3)
986 if (prefix
->wait
!= 0x9B)
992 if (prefix
->osp
|| prefix
->rep
)
997 if (!prefix
->osp
|| prefix
->rep
)
1041 return false; /* Unknown code */
1045 if (!vex_ok
&& (ins
->rex
& (REX_V
| REX_EV
)))
1048 /* REX cannot be combined with VEX */
1049 if ((ins
->rex
& REX_V
) && (prefix
->rex
& REX_P
))
1053 * Check for unused rep or a/o prefixes.
1055 for (i
= 0; i
< t
->operands
; i
++) {
1056 if (ins
->oprs
[i
].segment
!= SEG_RMREG
)
1061 if (ins
->prefixes
[PPS_LOCK
])
1063 ins
->prefixes
[PPS_LOCK
] = P_LOCK
;
1066 if (ins
->prefixes
[PPS_REP
])
1068 ins
->prefixes
[PPS_REP
] = drep
;
1070 ins
->prefixes
[PPS_WAIT
] = dwait
;
1072 if (osize
!= ((segsize
== 16) ? 16 : 32)) {
1073 enum prefixes pfx
= 0;
1087 if (ins
->prefixes
[PPS_OSIZE
])
1089 ins
->prefixes
[PPS_OSIZE
] = pfx
;
1092 if (!a_used
&& asize
!= segsize
) {
1093 if (ins
->prefixes
[PPS_ASIZE
])
1095 ins
->prefixes
[PPS_ASIZE
] = asize
== 16 ? P_A16
: P_A32
;
1098 /* Fix: check for redundant REX prefixes */
1100 return data
- origdata
;
1103 /* Condition names for disassembly, sorted by x86 code */
1104 static const char * const condition_name
[16] = {
1105 "o", "no", "c", "nc", "z", "nz", "na", "a",
1106 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
1109 int32_t disasm(uint8_t *data
, char *output
, int outbufsize
, int segsize
,
1110 int32_t offset
, int autosync
, iflag_t
*prefer
)
1112 const struct itemplate
* const *p
, * const *best_p
;
1113 const struct disasm_index
*ix
;
1115 int length
, best_length
= 0;
1117 int i
, slen
, colon
, n
;
1121 iflag_t goodness
, best
;
1123 struct prefix_info prefix
;
1127 memset(&ins
, 0, sizeof ins
);
1130 * Scan for prefixes.
1132 memset(&prefix
, 0, sizeof prefix
);
1133 prefix
.asize
= segsize
;
1134 prefix
.osize
= (segsize
== 64) ? 32 : segsize
;
1141 while (!end_prefix
) {
1145 prefix
.rep
= *data
++;
1149 prefix
.wait
= *data
++;
1153 prefix
.lock
= *data
++;
1157 segover
= "cs", prefix
.seg
= *data
++;
1160 segover
= "ss", prefix
.seg
= *data
++;
1163 segover
= "ds", prefix
.seg
= *data
++;
1166 segover
= "es", prefix
.seg
= *data
++;
1169 segover
= "fs", prefix
.seg
= *data
++;
1172 segover
= "gs", prefix
.seg
= *data
++;
1176 prefix
.osize
= (segsize
== 16) ? 32 : 16;
1177 prefix
.osp
= *data
++;
1180 prefix
.asize
= (segsize
== 32) ? 16 : 32;
1181 prefix
.asp
= *data
++;
1186 if (segsize
== 64 || (data
[1] & 0xc0) == 0xc0) {
1187 prefix
.vex
[0] = *data
++;
1188 prefix
.vex
[1] = *data
++;
1191 prefix
.vex_c
= RV_VEX
;
1193 if (prefix
.vex
[0] == 0xc4) {
1194 prefix
.vex
[2] = *data
++;
1195 prefix
.rex
|= (~prefix
.vex
[1] >> 5) & 7; /* REX_RXB */
1196 prefix
.rex
|= (prefix
.vex
[2] >> (7-3)) & REX_W
;
1197 prefix
.vex_m
= prefix
.vex
[1] & 0x1f;
1198 prefix
.vex_v
= (~prefix
.vex
[2] >> 3) & 15;
1199 prefix
.vex_lp
= prefix
.vex
[2] & 7;
1201 prefix
.rex
|= (~prefix
.vex
[1] >> (7-2)) & REX_R
;
1203 prefix
.vex_v
= (~prefix
.vex
[1] >> 3) & 15;
1204 prefix
.vex_lp
= prefix
.vex
[1] & 7;
1207 ix
= itable_vex
[RV_VEX
][prefix
.vex_m
][prefix
.vex_lp
& 3];
1214 uint8_t evex_p0
= data
[1] & 0x0f;
1215 if (segsize
== 64 ||
1216 ((evex_p0
>= 0x01) && (evex_p0
<= 0x03))) {
1217 data
++; /* 62h EVEX prefix */
1218 prefix
.evex
[0] = *data
++;
1219 prefix
.evex
[1] = *data
++;
1220 prefix
.evex
[2] = *data
++;
1222 prefix
.rex
= REX_EV
;
1223 prefix
.vex_c
= RV_EVEX
;
1224 prefix
.rex
|= (~prefix
.evex
[0] >> 5) & 7; /* REX_RXB */
1225 prefix
.rex
|= (prefix
.evex
[1] >> (7-3)) & REX_W
;
1226 prefix
.vex_m
= prefix
.evex
[0] & EVEX_P0MM
;
1227 prefix
.vex_v
= (~prefix
.evex
[1] & EVEX_P1VVVV
) >> 3;
1228 prefix
.vex_lp
= ((prefix
.evex
[2] & EVEX_P2LL
) >> (5-2)) |
1229 (prefix
.evex
[1] & EVEX_P1PP
);
1231 ix
= itable_vex
[prefix
.vex_c
][prefix
.vex_m
][prefix
.vex_lp
& 3];
1238 if ((data
[1] & 030) != 0 &&
1239 (segsize
== 64 || (data
[1] & 0xc0) == 0xc0)) {
1240 prefix
.vex
[0] = *data
++;
1241 prefix
.vex
[1] = *data
++;
1242 prefix
.vex
[2] = *data
++;
1245 prefix
.vex_c
= RV_XOP
;
1247 prefix
.rex
|= (~prefix
.vex
[1] >> 5) & 7; /* REX_RXB */
1248 prefix
.rex
|= (prefix
.vex
[2] >> (7-3)) & REX_W
;
1249 prefix
.vex_m
= prefix
.vex
[1] & 0x1f;
1250 prefix
.vex_v
= (~prefix
.vex
[2] >> 3) & 15;
1251 prefix
.vex_lp
= prefix
.vex
[2] & 7;
1253 ix
= itable_vex
[RV_XOP
][prefix
.vex_m
][prefix
.vex_lp
& 3];
1274 if (segsize
== 64) {
1275 prefix
.rex
= *data
++;
1276 if (prefix
.rex
& REX_W
)
1288 iflag_set_all(&best
); /* Worst possible */
1290 best_pref
= INT_MAX
;
1293 return 0; /* No instruction table at all... */
1297 while (ix
->n
== -1) {
1298 ix
= (const struct disasm_index
*)ix
->p
+ *dp
++;
1301 p
= (const struct itemplate
* const *)ix
->p
;
1302 for (n
= ix
->n
; n
; n
--, p
++) {
1303 if ((length
= matches(*p
, data
, &prefix
, segsize
, &tmp_ins
))) {
1306 * Final check to make sure the types of r/m match up.
1307 * XXX: Need to make sure this is actually correct.
1309 for (i
= 0; i
< (*p
)->operands
; i
++) {
1311 /* If it's a mem-only EA but we have a
1313 ((tmp_ins
.oprs
[i
].segment
& SEG_RMREG
) &&
1314 is_class(MEMORY
, (*p
)->opd
[i
])) ||
1315 /* If it's a reg-only EA but we have a memory
1317 (!(tmp_ins
.oprs
[i
].segment
& SEG_RMREG
) &&
1318 !(REG_EA
& ~(*p
)->opd
[i
]) &&
1319 !((*p
)->opd
[i
] & REG_SMASK
)) ||
1320 /* Register type mismatch (eg FS vs REG_DESS):
1322 ((((*p
)->opd
[i
] & (REGISTER
| FPUREG
)) ||
1323 (tmp_ins
.oprs
[i
].segment
& SEG_RMREG
)) &&
1324 !whichreg((*p
)->opd
[i
],
1325 tmp_ins
.oprs
[i
].basereg
, tmp_ins
.rex
))
1333 * Note: we always prefer instructions which incorporate
1334 * prefixes in the instructions themselves. This is to allow
1335 * e.g. PAUSE to be preferred to REP NOP, and deal with
1336 * MMX/SSE instructions where prefixes are used to select
1337 * between MMX and SSE register sets or outright opcode
1342 goodness
= iflag_pfmask(*p
);
1343 goodness
= iflag_xor(&goodness
, prefer
);
1345 for (i
= 0; i
< MAXPREFIX
; i
++)
1346 if (tmp_ins
.prefixes
[i
])
1348 if (nprefix
< best_pref
||
1349 (nprefix
== best_pref
&&
1350 iflag_cmp(&goodness
, &best
) < 0)) {
1351 /* This is the best one found so far */
1354 best_pref
= nprefix
;
1355 best_length
= length
;
1363 return 0; /* no instruction was matched */
1365 /* Pick the best match */
1367 length
= best_length
;
1371 /* TODO: snprintf returns the value that the string would have if
1372 * the buffer were long enough, and not the actual length of
1373 * the returned string, so each instance of using the return
1374 * value of snprintf should actually be checked to assure that
1375 * the return value is "sane." Maybe a macro wrapper could
1376 * be used for that purpose.
1378 for (i
= 0; i
< MAXPREFIX
; i
++) {
1379 const char *prefix
= prefix_name(ins
.prefixes
[i
]);
1381 slen
+= snprintf(output
+slen
, outbufsize
-slen
, "%s ", prefix
);
1385 if (i
>= FIRST_COND_OPCODE
)
1386 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "%s%s",
1387 nasm_insn_names
[i
], condition_name
[ins
.condition
]);
1389 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "%s",
1390 nasm_insn_names
[i
]);
1393 is_evex
= !!(ins
.rex
& REX_EV
);
1394 length
+= data
- origdata
; /* fix up for prefixes */
1395 for (i
= 0; i
< (*p
)->operands
; i
++) {
1396 opflags_t t
= (*p
)->opd
[i
];
1397 decoflags_t deco
= (*p
)->deco
[i
];
1398 const operand
*o
= &ins
.oprs
[i
];
1401 output
[slen
++] = (colon
? ':' : i
== 0 ? ' ' : ',');
1404 if (o
->segment
& SEG_RELATIVE
) {
1405 offs
+= offset
+ length
;
1407 * sort out wraparound
1409 if (!(o
->segment
& (SEG_32BIT
|SEG_64BIT
)))
1411 else if (segsize
!= 64)
1415 * add sync marker, if autosync is on
1426 if ((t
& (REGISTER
| FPUREG
)) ||
1427 (o
->segment
& SEG_RMREG
)) {
1429 reg
= whichreg(t
, o
->basereg
, ins
.rex
);
1431 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "to ");
1432 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "%s",
1433 nasm_reg_names
[reg
-EXPR_REG_START
]);
1434 if (is_evex
&& deco
)
1435 slen
+= append_evex_reg_deco(output
+ slen
, outbufsize
- slen
,
1437 } else if (!(UNITY
& ~t
)) {
1438 output
[slen
++] = '1';
1439 } else if (t
& IMMEDIATE
) {
1442 snprintf(output
+ slen
, outbufsize
- slen
, "byte ");
1443 if (o
->segment
& SEG_SIGNED
) {
1446 output
[slen
++] = '-';
1448 output
[slen
++] = '+';
1450 } else if (t
& BITS16
) {
1452 snprintf(output
+ slen
, outbufsize
- slen
, "word ");
1453 } else if (t
& BITS32
) {
1455 snprintf(output
+ slen
, outbufsize
- slen
, "dword ");
1456 } else if (t
& BITS64
) {
1458 snprintf(output
+ slen
, outbufsize
- slen
, "qword ");
1459 } else if (t
& NEAR
) {
1461 snprintf(output
+ slen
, outbufsize
- slen
, "near ");
1462 } else if (t
& SHORT
) {
1464 snprintf(output
+ slen
, outbufsize
- slen
, "short ");
1467 snprintf(output
+ slen
, outbufsize
- slen
, "0x%"PRIx64
"",
1469 } else if (!(MEM_OFFS
& ~t
)) {
1471 snprintf(output
+ slen
, outbufsize
- slen
,
1472 "[%s%s%s0x%"PRIx64
"]",
1473 (segover
? segover
: ""),
1474 (segover
? ":" : ""),
1475 (o
->disp_size
== 64 ? "qword " :
1476 o
->disp_size
== 32 ? "dword " :
1477 o
->disp_size
== 16 ? "word " : ""), offs
);
1479 } else if (is_class(REGMEM
, t
)) {
1480 int started
= false;
1483 snprintf(output
+ slen
, outbufsize
- slen
, "byte ");
1486 snprintf(output
+ slen
, outbufsize
- slen
, "word ");
1489 snprintf(output
+ slen
, outbufsize
- slen
, "dword ");
1492 snprintf(output
+ slen
, outbufsize
- slen
, "qword ");
1495 snprintf(output
+ slen
, outbufsize
- slen
, "tword ");
1496 if ((ins
.evex_p
[2] & EVEX_P2B
) && (deco
& BRDCAST_MASK
)) {
1497 /* when broadcasting, each element size should be used */
1498 if (deco
& BR_BITS32
)
1500 snprintf(output
+ slen
, outbufsize
- slen
, "dword ");
1501 else if (deco
& BR_BITS64
)
1503 snprintf(output
+ slen
, outbufsize
- slen
, "qword ");
1507 snprintf(output
+ slen
, outbufsize
- slen
, "oword ");
1510 snprintf(output
+ slen
, outbufsize
- slen
, "yword ");
1513 snprintf(output
+ slen
, outbufsize
- slen
, "zword ");
1516 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "far ");
1519 snprintf(output
+ slen
, outbufsize
- slen
, "near ");
1520 output
[slen
++] = '[';
1522 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "%s",
1523 (o
->disp_size
== 64 ? "qword " :
1524 o
->disp_size
== 32 ? "dword " :
1525 o
->disp_size
== 16 ? "word " :
1527 if (o
->eaflags
& EAF_REL
)
1528 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "rel ");
1531 snprintf(output
+ slen
, outbufsize
- slen
, "%s:",
1535 if (o
->basereg
!= -1) {
1536 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "%s",
1537 nasm_reg_names
[(o
->basereg
-EXPR_REG_START
)]);
1540 if (o
->indexreg
!= -1 && !itemp_has(*best_p
, IF_MIB
)) {
1542 output
[slen
++] = '+';
1543 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "%s",
1544 nasm_reg_names
[(o
->indexreg
-EXPR_REG_START
)]);
1547 snprintf(output
+ slen
, outbufsize
- slen
, "*%d",
1553 if (o
->segment
& SEG_DISP8
) {
1556 uint32_t offset
= offs
;
1557 if ((int32_t)offset
< 0) {
1564 snprintf(output
+ slen
, outbufsize
- slen
, "%s0x%"PRIx32
"",
1568 uint8_t offset
= offs
;
1569 if ((int8_t)offset
< 0) {
1576 snprintf(output
+ slen
, outbufsize
- slen
, "%s0x%"PRIx8
"",
1579 } else if (o
->segment
& SEG_DISP16
) {
1581 uint16_t offset
= offs
;
1582 if ((int16_t)offset
< 0 && started
) {
1586 prefix
= started
? "+" : "";
1589 snprintf(output
+ slen
, outbufsize
- slen
,
1590 "%s0x%"PRIx16
"", prefix
, offset
);
1591 } else if (o
->segment
& SEG_DISP32
) {
1592 if (prefix
.asize
== 64) {
1594 uint64_t offset
= (int64_t)(int32_t)offs
;
1595 if ((int32_t)offs
< 0 && started
) {
1599 prefix
= started
? "+" : "";
1602 snprintf(output
+ slen
, outbufsize
- slen
,
1603 "%s0x%"PRIx64
"", prefix
, offset
);
1606 uint32_t offset
= offs
;
1607 if ((int32_t) offset
< 0 && started
) {
1611 prefix
= started
? "+" : "";
1614 snprintf(output
+ slen
, outbufsize
- slen
,
1615 "%s0x%"PRIx32
"", prefix
, offset
);
1619 if (o
->indexreg
!= -1 && itemp_has(*best_p
, IF_MIB
)) {
1620 output
[slen
++] = ',';
1621 slen
+= snprintf(output
+ slen
, outbufsize
- slen
, "%s",
1622 nasm_reg_names
[(o
->indexreg
-EXPR_REG_START
)]);
1625 snprintf(output
+ slen
, outbufsize
- slen
, "*%d",
1630 output
[slen
++] = ']';
1632 if (is_evex
&& deco
)
1633 slen
+= append_evex_mem_deco(output
+ slen
, outbufsize
- slen
,
1634 t
, deco
, ins
.evex_p
);
1637 snprintf(output
+ slen
, outbufsize
- slen
, "<operand%d>",
1641 output
[slen
] = '\0';
1642 if (segover
) { /* unused segment override */
1644 int count
= slen
+ 1;
1646 p
[count
+ 3] = p
[count
];
1647 strncpy(output
, segover
, 2);
1654 * This is called when we don't have a complete instruction. If it
1655 * is a standalone *single-byte* prefix show it as such, otherwise
1656 * print it as a literal.
1658 int32_t eatbyte(uint8_t *data
, char *output
, int outbufsize
, int segsize
)
1660 uint8_t byte
= *data
;
1661 const char *str
= NULL
;
1695 str
= (segsize
== 16) ? "o32" : "o16";
1698 str
= (segsize
== 32) ? "a16" : "a32";
1716 if (segsize
== 64) {
1717 snprintf(output
, outbufsize
, "rex%s%s%s%s%s",
1718 (byte
== REX_P
) ? "" : ".",
1719 (byte
& REX_W
) ? "w" : "",
1720 (byte
& REX_R
) ? "r" : "",
1721 (byte
& REX_X
) ? "x" : "",
1722 (byte
& REX_B
) ? "b" : "");
1725 /* else fall through */
1727 snprintf(output
, outbufsize
, "db 0x%02x", byte
);
1732 snprintf(output
, outbufsize
, "%s", str
);