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doc: Add Unicode Strings to Unicode index
[nasm.git] / assemble.c
blob7ab53ad31dfefdbd822a20f7358e54ce840d09ab
1 /* assemble.c code generation for the Netwide Assembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
7 *
8 * the actual codes (C syntax, i.e. octal):
9 * \0 - terminates the code. (Unless it's a literal of course.)
10 * \1, \2, \3 - that many literal bytes follow in the code stream
11 * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
12 * (POP is never used for CS) depending on operand 0
13 * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
14 * on operand 0
15 * \10..\13 - a literal byte follows in the code stream, to be added
16 * to the register value of operand 0..3
17 * \14..\17 - a signed byte immediate operand, from operand 0..3
18 * \20..\23 - a byte immediate operand, from operand 0..3
19 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
20 * \30..\33 - a word immediate operand, from operand 0..3
21 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
22 * assembly mode or the operand-size override on the operand
23 * \40..\43 - a long immediate operand, from operand 0..3
24 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
25 * depending on the address size of the instruction.
26 * \50..\53 - a byte relative operand, from operand 0..3
27 * \54..\57 - a qword immediate operand, from operand 0..3
28 * \60..\63 - a word relative operand, from operand 0..3
29 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
30 * assembly mode or the operand-size override on the operand
31 * \70..\73 - a long relative operand, from operand 0..3
32 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
33 * \1ab - a ModRM, calculated on EA in operand a, with the spare
34 * field the register value of operand b.
35 * \140..\143 - an immediate word or signed byte for operand 0..3
36 * \144..\147 - or 2 (s-field) into opcode byte if operand 0..3
37 * is a signed byte rather than a word. Opcode byte follows.
38 * \150..\153 - an immediate dword or signed byte for operand 0..3
39 * \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
40 * is a signed byte rather than a dword. Opcode byte follows.
41 * \160..\163 - this instruction uses DREX rather than REX, with the
42 * OC0 field set to 0, and the dest field taken from
43 * operand 0..3.
44 * \164..\167 - this instruction uses DREX rather than REX, with the
45 * OC0 field set to 1, and the dest field taken from
46 * operand 0..3.
47 * \171 - placement of DREX suffix in the absence of an EA
48 * \172\ab - the register number from operand a in bits 7..4, with
49 * the 4-bit immediate from operand b in bits 3..0.
50 * \173\xab - the register number from operand a in bits 7..4, with
51 * the value b in bits 3..0.
52 * \174\a - the register number from operand a in bits 7..4, and
53 * an arbitrary value in bits 3..0 (assembled as zero.)
54 * \2ab - a ModRM, calculated on EA in operand a, with the spare
55 * field equal to digit b.
56 * \250..\253 - same as \150..\153, except warn if the 64-bit operand
57 * is not equal to the truncated and sign-extended 32-bit
58 * operand; used for 32-bit immediates in 64-bit mode.
59 * \260..\263 - this instruction uses VEX rather than REX, with the
60 * V field taken from operand 0..3.
61 * \270 - this instruction uses VEX rather than REX, with the
62 * V field set to 1111b.
63 *
64 * VEX prefixes are followed by the sequence:
65 * \mm\wlp where mm is the M field; and wlp is:
66 * 00 0ww lpp
67 * [w0] ww = 0 for W = 0
68 * [w1] ww = 1 for W = 1
69 * [wx] ww = 2 for W don't care (always assembled as 0)
70 * [ww] ww = 3 for W used as REX.W
71 *
72 *
73 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
74 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
75 * \312 - (disassembler only) marker on LOOP, LOOPxx instructions.
76 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
77 * \314 - (disassembler only) invalid with REX.B
78 * \315 - (disassembler only) invalid with REX.X
79 * \316 - (disassembler only) invalid with REX.R
80 * \317 - (disassembler only) invalid with REX.W
81 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
82 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
83 * \322 - indicates that this instruction is only valid when the
84 * operand size is the default (instruction to disassembler,
85 * generates no code in the assembler)
86 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
87 * \324 - indicates 64-bit operand size requiring REX prefix.
88 * \330 - a literal byte follows in the code stream, to be added
89 * to the condition code value of the instruction.
90 * \331 - instruction not valid with REP prefix. Hint for
91 * disassembler only; for SSE instructions.
92 * \332 - REP prefix (0xF2 byte) used as opcode extension.
93 * \333 - REP prefix (0xF3 byte) used as opcode extension.
94 * \334 - LOCK prefix used instead of REX.R
95 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
96 * \340 - reserve <operand 0> bytes of uninitialized storage.
97 * Operand 0 had better be a segmentless constant.
98 * \360 - no SSE prefix (== \364\331)
99 * \361 - 66 SSE prefix (== \366\331)
100 * \362 - F2 SSE prefix (== \364\332)
101 * \363 - F3 SSE prefix (== \364\333)
102 * \364 - operand-size prefix (0x66) not permitted
103 * \365 - address-size prefix (0x67) not permitted
104 * \366 - operand-size prefix (0x66) used as opcode extension
105 * \367 - address-size prefix (0x67) used as opcode extension
106 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
107 * 370 is used for Jcc, 371 is used for JMP.
108 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
109 * used for conditional jump over longer jump
110 */
111
112 #include "compiler.h"
113
114 #include <stdio.h>
115 #include <string.h>
116 #include <inttypes.h>
117
118 #include "nasm.h"
119 #include "nasmlib.h"
120 #include "assemble.h"
121 #include "insns.h"
122 #include "tables.h"
123
124 /* Initialized to zero by the C standard */
125 static const uint8_t const_zero_buf[256];
126
127 typedef struct {
128 int sib_present; /* is a SIB byte necessary? */
129 int bytes; /* # of bytes of offset needed */
130 int size; /* lazy - this is sib+bytes+1 */
131 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
132 } ea;
133
134 static uint32_t cpu; /* cpu level received from nasm.c */
135 static efunc errfunc;
136 static struct ofmt *outfmt;
137 static ListGen *list;
138
139 static int64_t calcsize(int32_t, int64_t, int, insn *, const uint8_t *);
140 static void gencode(int32_t, int64_t, int, insn *, const uint8_t *, int64_t);
141 static int matches(const struct itemplate *, insn *, int bits);
142 static int32_t regflag(const operand *);
143 static int32_t regval(const operand *);
144 static int rexflags(int, int32_t, int);
145 static int op_rexflags(const operand *, int);
146 static ea *process_ea(operand *, ea *, int, int, int, int32_t, int);
147 static void add_asp(insn *, int);
148
149 static int has_prefix(insn * ins, enum prefix_pos pos, enum prefixes prefix)
150 {
151 return ins->prefixes[pos] == prefix;
152 }
153
154 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
155 {
156 if (ins->prefixes[pos])
157 errfunc(ERR_NONFATAL, "invalid %s prefix",
158 prefix_name(ins->prefixes[pos]));
159 }
160
161 static const char *size_name(int size)
162 {
163 switch (size) {
164 case 1:
165 return "byte";
166 case 2:
167 return "word";
168 case 4:
169 return "dword";
170 case 8:
171 return "qword";
172 case 10:
173 return "tword";
174 case 16:
175 return "oword";
176 case 32:
177 return "yword";
178 default:
179 return "???";
180 }
181 }
182
183 static void warn_overflow(int size, int64_t data)
184 {
185 if (size < 8) {
186 int64_t lim = ((int64_t)1 << (size*8))-1;
187
188 if (data < ~lim || data > lim)
189 errfunc(ERR_WARNING | ERR_WARN_NOV,
190 "%s data exceeds bounds", size_name(size));
191 }
192 }
193 /*
194 * This routine wrappers the real output format's output routine,
195 * in order to pass a copy of the data off to the listing file
196 * generator at the same time.
197 */
198 static void out(int64_t offset, int32_t segto, const void *data,
199 enum out_type type, uint64_t size,
200 int32_t segment, int32_t wrt)
201 {
202 static int32_t lineno = 0; /* static!!! */
203 static char *lnfname = NULL;
204 uint8_t p[8];
205
206 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
207 /*
208 * This is a non-relocated address, and we're going to
209 * convert it into RAWDATA format.
210 */
211 uint8_t *q = p;
212
213 if (size > 8) {
214 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
215 return;
216 }
217
218 WRITEADDR(q, *(int64_t *)data, size);
219 data = p;
220 type = OUT_RAWDATA;
221 }
222
223 list->output(offset, data, type, size);
224
225 /*
226 * this call to src_get determines when we call the
227 * debug-format-specific "linenum" function
228 * it updates lineno and lnfname to the current values
229 * returning 0 if "same as last time", -2 if lnfname
230 * changed, and the amount by which lineno changed,
231 * if it did. thus, these variables must be static
232 */
233
234 if (src_get(&lineno, &lnfname)) {
235 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
236 }
237
238 outfmt->output(segto, data, type, size, segment, wrt);
239 }
240
241 static int jmp_match(int32_t segment, int64_t offset, int bits,
242 insn * ins, const uint8_t *code)
243 {
244 int64_t isize;
245 uint8_t c = code[0];
246
247 if (c != 0370 && c != 0371)
248 return 0;
249 if (ins->oprs[0].opflags & OPFLAG_FORWARD) {
250 if ((optimizing < 0 || (ins->oprs[0].type & STRICT))
251 && c == 0370)
252 return 1;
253 else
254 return (pass0 == 0); /* match a forward reference */
255 }
256 isize = calcsize(segment, offset, bits, ins, code);
257 if (ins->oprs[0].segment != segment)
258 return 0;
259 isize = ins->oprs[0].offset - offset - isize; /* isize is now the delta */
260 if (isize >= -128L && isize <= 127L)
261 return 1; /* it is byte size */
262
263 return 0;
264 }
265
266 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
267 insn * instruction, struct ofmt *output, efunc error,
268 ListGen * listgen)
269 {
270 const struct itemplate *temp;
271 int j;
272 int size_prob;
273 int64_t insn_end;
274 int32_t itimes;
275 int64_t start = offset;
276 int64_t wsize = 0; /* size for DB etc. */
277
278 errfunc = error; /* to pass to other functions */
279 cpu = cp;
280 outfmt = output; /* likewise */
281 list = listgen; /* and again */
282
283 switch (instruction->opcode) {
284 case -1:
285 return 0;
286 case I_DB:
287 wsize = 1;
288 break;
289 case I_DW:
290 wsize = 2;
291 break;
292 case I_DD:
293 wsize = 4;
294 break;
295 case I_DQ:
296 wsize = 8;
297 break;
298 case I_DT:
299 wsize = 10;
300 break;
301 case I_DO:
302 wsize = 16;
303 break;
304 case I_DY:
305 wsize = 32;
306 break;
307 default:
308 break;
309 }
310
311 if (wsize) {
312 extop *e;
313 int32_t t = instruction->times;
314 if (t < 0)
315 errfunc(ERR_PANIC,
316 "instruction->times < 0 (%ld) in assemble()", t);
317
318 while (t--) { /* repeat TIMES times */
319 for (e = instruction->eops; e; e = e->next) {
320 if (e->type == EOT_DB_NUMBER) {
321 if (wsize == 1) {
322 if (e->segment != NO_SEG)
323 errfunc(ERR_NONFATAL,
324 "one-byte relocation attempted");
325 else {
326 uint8_t out_byte = e->offset;
327 out(offset, segment, &out_byte,
328 OUT_RAWDATA, 1, NO_SEG, NO_SEG);
329 }
330 } else if (wsize > 8) {
331 errfunc(ERR_NONFATAL,
332 "integer supplied to a DT, DO or DY"
333 " instruction");
334 } else
335 out(offset, segment, &e->offset,
336 OUT_ADDRESS, wsize, e->segment, e->wrt);
337 offset += wsize;
338 } else if (e->type == EOT_DB_STRING ||
339 e->type == EOT_DB_STRING_FREE) {
340 int align;
341
342 out(offset, segment, e->stringval,
343 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
344 align = e->stringlen % wsize;
345
346 if (align) {
347 align = wsize - align;
348 out(offset, segment, const_zero_buf,
349 OUT_RAWDATA, align, NO_SEG, NO_SEG);
350 }
351 offset += e->stringlen + align;
352 if (e->type == EOT_DB_STRING_FREE)
353 nasm_free(e->stringval);
354 }
355 }
356 if (t > 0 && t == instruction->times - 1) {
357 /*
358 * Dummy call to list->output to give the offset to the
359 * listing module.
360 */
361 list->output(offset, NULL, OUT_RAWDATA, 0);
362 list->uplevel(LIST_TIMES);
363 }
364 }
365 if (instruction->times > 1)
366 list->downlevel(LIST_TIMES);
367 return offset - start;
368 }
369
370 if (instruction->opcode == I_INCBIN) {
371 const char *fname = instruction->eops->stringval;
372 FILE *fp;
373
374 fp = fopen(fname, "rb");
375 if (!fp) {
376 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
377 fname);
378 } else if (fseek(fp, 0L, SEEK_END) < 0) {
379 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
380 fname);
381 } else {
382 static char buf[4096];
383 size_t t = instruction->times;
384 size_t base = 0;
385 size_t len;
386
387 len = ftell(fp);
388 if (instruction->eops->next) {
389 base = instruction->eops->next->offset;
390 len -= base;
391 if (instruction->eops->next->next &&
392 len > (size_t)instruction->eops->next->next->offset)
393 len = (size_t)instruction->eops->next->next->offset;
394 }
395 /*
396 * Dummy call to list->output to give the offset to the
397 * listing module.
398 */
399 list->output(offset, NULL, OUT_RAWDATA, 0);
400 list->uplevel(LIST_INCBIN);
401 while (t--) {
402 size_t l;
403
404 fseek(fp, base, SEEK_SET);
405 l = len;
406 while (l > 0) {
407 int32_t m =
408 fread(buf, 1, (l > (int32_t) sizeof(buf) ? (int32_t) sizeof(buf) : l),
409 fp);
410 if (!m) {
411 /*
412 * This shouldn't happen unless the file
413 * actually changes while we are reading
414 * it.
415 */
416 error(ERR_NONFATAL,
417 "`incbin': unexpected EOF while"
418 " reading file `%s'", fname);
419 t = 0; /* Try to exit cleanly */
420 break;
421 }
422 out(offset, segment, buf, OUT_RAWDATA, m,
423 NO_SEG, NO_SEG);
424 l -= m;
425 }
426 }
427 list->downlevel(LIST_INCBIN);
428 if (instruction->times > 1) {
429 /*
430 * Dummy call to list->output to give the offset to the
431 * listing module.
432 */
433 list->output(offset, NULL, OUT_RAWDATA, 0);
434 list->uplevel(LIST_TIMES);
435 list->downlevel(LIST_TIMES);
436 }
437 fclose(fp);
438 return instruction->times * len;
439 }
440 return 0; /* if we're here, there's an error */
441 }
442
443 /* Check to see if we need an address-size prefix */
444 add_asp(instruction, bits);
445
446 size_prob = false;
447
448 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++){
449 int m = matches(temp, instruction, bits);
450
451 if (m == 99)
452 m += jmp_match(segment, offset, bits, instruction, temp->code);
453
454 if (m == 100) { /* matches! */
455 const uint8_t *codes = temp->code;
456 int64_t insn_size = calcsize(segment, offset, bits,
457 instruction, codes);
458 itimes = instruction->times;
459 if (insn_size < 0) /* shouldn't be, on pass two */
460 error(ERR_PANIC, "errors made it through from pass one");
461 else
462 while (itimes--) {
463 for (j = 0; j < MAXPREFIX; j++) {
464 uint8_t c = 0;
465 switch (instruction->prefixes[j]) {
466 case P_LOCK:
467 c = 0xF0;
468 break;
469 case P_REPNE:
470 case P_REPNZ:
471 c = 0xF2;
472 break;
473 case P_REPE:
474 case P_REPZ:
475 case P_REP:
476 c = 0xF3;
477 break;
478 case R_CS:
479 if (bits == 64) {
480 error(ERR_WARNING,
481 "cs segment base generated, but will be ignored in 64-bit mode");
482 }
483 c = 0x2E;
484 break;
485 case R_DS:
486 if (bits == 64) {
487 error(ERR_WARNING,
488 "ds segment base generated, but will be ignored in 64-bit mode");
489 }
490 c = 0x3E;
491 break;
492 case R_ES:
493 if (bits == 64) {
494 error(ERR_WARNING,
495 "es segment base generated, but will be ignored in 64-bit mode");
496 }
497 c = 0x26;
498 break;
499 case R_FS:
500 c = 0x64;
501 break;
502 case R_GS:
503 c = 0x65;
504 break;
505 case R_SS:
506 if (bits == 64) {
507 error(ERR_WARNING,
508 "ss segment base generated, but will be ignored in 64-bit mode");
509 }
510 c = 0x36;
511 break;
512 case R_SEGR6:
513 case R_SEGR7:
514 error(ERR_NONFATAL,
515 "segr6 and segr7 cannot be used as prefixes");
516 break;
517 case P_A16:
518 if (bits == 64) {
519 error(ERR_NONFATAL,
520 "16-bit addressing is not supported "
521 "in 64-bit mode");
522 } else if (bits != 16)
523 c = 0x67;
524 break;
525 case P_A32:
526 if (bits != 32)
527 c = 0x67;
528 break;
529 case P_A64:
530 if (bits != 64) {
531 error(ERR_NONFATAL,
532 "64-bit addressing is only supported "
533 "in 64-bit mode");
534 }
535 break;
536 case P_ASP:
537 c = 0x67;
538 break;
539 case P_O16:
540 if (bits != 16)
541 c = 0x66;
542 break;
543 case P_O32:
544 if (bits == 16)
545 c = 0x66;
546 break;
547 case P_O64:
548 /* REX.W */
549 break;
550 case P_OSP:
551 c = 0x66;
552 break;
553 case P_none:
554 break;
555 default:
556 error(ERR_PANIC, "invalid instruction prefix");
557 }
558 if (c != 0) {
559 out(offset, segment, &c, OUT_RAWDATA, 1,
560 NO_SEG, NO_SEG);
561 offset++;
562 }
563 }
564 insn_end = offset + insn_size;
565 gencode(segment, offset, bits, instruction, codes,
566 insn_end);
567 offset += insn_size;
568 if (itimes > 0 && itimes == instruction->times - 1) {
569 /*
570 * Dummy call to list->output to give the offset to the
571 * listing module.
572 */
573 list->output(offset, NULL, OUT_RAWDATA, 0);
574 list->uplevel(LIST_TIMES);
575 }
576 }
577 if (instruction->times > 1)
578 list->downlevel(LIST_TIMES);
579 return offset - start;
580 } else if (m > 0 && m > size_prob) {
581 size_prob = m;
582 }
583 // temp++;
584 }
585
586 if (temp->opcode == -1) { /* didn't match any instruction */
587 switch (size_prob) {
588 case 1:
589 error(ERR_NONFATAL, "operation size not specified");
590 break;
591 case 2:
592 error(ERR_NONFATAL, "mismatch in operand sizes");
593 break;
594 case 3:
595 error(ERR_NONFATAL, "no instruction for this cpu level");
596 break;
597 case 4:
598 error(ERR_NONFATAL, "instruction not supported in 64-bit mode");
599 break;
600 default:
601 error(ERR_NONFATAL,
602 "invalid combination of opcode and operands");
603 break;
604 }
605 }
606 return 0;
607 }
608
609 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
610 insn * instruction, efunc error)
611 {
612 const struct itemplate *temp;
613
614 errfunc = error; /* to pass to other functions */
615 cpu = cp;
616
617 if (instruction->opcode == -1)
618 return 0;
619
620 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
621 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
622 instruction->opcode == I_DT || instruction->opcode == I_DO ||
623 instruction->opcode == I_DY) {
624 extop *e;
625 int32_t isize, osize, wsize = 0; /* placate gcc */
626
627 isize = 0;
628 switch (instruction->opcode) {
629 case I_DB:
630 wsize = 1;
631 break;
632 case I_DW:
633 wsize = 2;
634 break;
635 case I_DD:
636 wsize = 4;
637 break;
638 case I_DQ:
639 wsize = 8;
640 break;
641 case I_DT:
642 wsize = 10;
643 break;
644 case I_DO:
645 wsize = 16;
646 break;
647 case I_DY:
648 wsize = 32;
649 break;
650 default:
651 break;
652 }
653
654 for (e = instruction->eops; e; e = e->next) {
655 int32_t align;
656
657 osize = 0;
658 if (e->type == EOT_DB_NUMBER)
659 osize = 1;
660 else if (e->type == EOT_DB_STRING ||
661 e->type == EOT_DB_STRING_FREE)
662 osize = e->stringlen;
663
664 align = (-osize) % wsize;
665 if (align < 0)
666 align += wsize;
667 isize += osize + align;
668 }
669 return isize * instruction->times;
670 }
671
672 if (instruction->opcode == I_INCBIN) {
673 const char *fname = instruction->eops->stringval;
674 FILE *fp;
675 size_t len;
676
677 fp = fopen(fname, "rb");
678 if (!fp)
679 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
680 fname);
681 else if (fseek(fp, 0L, SEEK_END) < 0)
682 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
683 fname);
684 else {
685 len = ftell(fp);
686 fclose(fp);
687 if (instruction->eops->next) {
688 len -= instruction->eops->next->offset;
689 if (instruction->eops->next->next &&
690 len > (size_t)instruction->eops->next->next->offset) {
691 len = (size_t)instruction->eops->next->next->offset;
692 }
693 }
694 return instruction->times * len;
695 }
696 return 0; /* if we're here, there's an error */
697 }
698
699 /* Check to see if we need an address-size prefix */
700 add_asp(instruction, bits);
701
702 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++) {
703 int m = matches(temp, instruction, bits);
704 if (m == 99)
705 m += jmp_match(segment, offset, bits, instruction, temp->code);
706
707 if (m == 100) {
708 /* we've matched an instruction. */
709 int64_t isize;
710 const uint8_t *codes = temp->code;
711 int j;
712
713 isize = calcsize(segment, offset, bits, instruction, codes);
714 if (isize < 0)
715 return -1;
716 for (j = 0; j < MAXPREFIX; j++) {
717 switch (instruction->prefixes[j]) {
718 case P_A16:
719 if (bits != 16)
720 isize++;
721 break;
722 case P_A32:
723 if (bits != 32)
724 isize++;
725 break;
726 case P_O16:
727 if (bits != 16)
728 isize++;
729 break;
730 case P_O32:
731 if (bits == 16)
732 isize++;
733 break;
734 case P_A64:
735 case P_O64:
736 case P_none:
737 break;
738 default:
739 isize++;
740 break;
741 }
742 }
743 return isize * instruction->times;
744 }
745 }
746 return -1; /* didn't match any instruction */
747 }
748
749 static bool possible_sbyte(insn * ins, int op)
750 {
751 return !(ins->forw_ref && ins->oprs[op].opflags) &&
752 optimizing >= 0 &&
753 !(ins->oprs[op].type & STRICT) &&
754 ins->oprs[op].wrt == NO_SEG && ins->oprs[op].segment == NO_SEG;
755 }
756
757 /* check that opn[op] is a signed byte of size 16 or 32 */
758 static bool is_sbyte16(insn * ins, int op)
759 {
760 int16_t v;
761
762 if (!possible_sbyte(ins, op))
763 return false;
764
765 v = ins->oprs[op].offset;
766 return v >= -128 && v <= 127;
767 }
768
769 static bool is_sbyte32(insn * ins, int op)
770 {
771 int32_t v;
772
773 if (!possible_sbyte(ins, op))
774 return false;
775
776 v = ins->oprs[op].offset;
777 return v >= -128 && v <= 127;
778 }
779
780 /* check that opn[op] is a signed byte of size 32; warn if this is not
781 the original value when extended to 64 bits */
782 static bool is_sbyte64(insn * ins, int op)
783 {
784 int64_t v64;
785 int32_t v32;
786
787 /* dead in the water on forward reference or External */
788 if (!possible_sbyte(ins, op))
789 return false;
790
791 v64 = ins->oprs[op].offset;
792 v32 = (int32_t)v64;
793
794 warn_overflow(32, v64);
795
796 return v32 >= -128 && v32 <= 127;
797 }
798 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
799 insn * ins, const uint8_t *codes)
800 {
801 int64_t length = 0;
802 uint8_t c;
803 int rex_mask = ~0;
804 struct operand *opx;
805
806 ins->rex = 0; /* Ensure REX is reset */
807
808 if (ins->prefixes[PPS_OSIZE] == P_O64)
809 ins->rex |= REX_W;
810
811 (void)segment; /* Don't warn that this parameter is unused */
812 (void)offset; /* Don't warn that this parameter is unused */
813
814 while (*codes) {
815 c = *codes++;
816 opx = &ins->oprs[c & 3];
817 switch (c) {
818 case 01:
819 case 02:
820 case 03:
821 codes += c, length += c;
822 break;
823 case 04:
824 case 05:
825 case 06:
826 case 07:
827 length++;
828 break;
829 case 010:
830 case 011:
831 case 012:
832 case 013:
833 ins->rex |=
834 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
835 codes++, length++;
836 break;
837 case 014:
838 case 015:
839 case 016:
840 case 017:
841 length++;
842 break;
843 case 020:
844 case 021:
845 case 022:
846 case 023:
847 length++;
848 break;
849 case 024:
850 case 025:
851 case 026:
852 case 027:
853 length++;
854 break;
855 case 030:
856 case 031:
857 case 032:
858 case 033:
859 length += 2;
860 break;
861 case 034:
862 case 035:
863 case 036:
864 case 037:
865 if (opx->type & (BITS16 | BITS32 | BITS64))
866 length += (opx->type & BITS16) ? 2 : 4;
867 else
868 length += (bits == 16) ? 2 : 4;
869 break;
870 case 040:
871 case 041:
872 case 042:
873 case 043:
874 length += 4;
875 break;
876 case 044:
877 case 045:
878 case 046:
879 case 047:
880 length += ins->addr_size >> 3;
881 break;
882 case 050:
883 case 051:
884 case 052:
885 case 053:
886 length++;
887 break;
888 case 054:
889 case 055:
890 case 056:
891 case 057:
892 length += 8; /* MOV reg64/imm */
893 break;
894 case 060:
895 case 061:
896 case 062:
897 case 063:
898 length += 2;
899 break;
900 case 064:
901 case 065:
902 case 066:
903 case 067:
904 if (opx->type & (BITS16 | BITS32 | BITS64))
905 length += (opx->type & BITS16) ? 2 : 4;
906 else
907 length += (bits == 16) ? 2 : 4;
908 break;
909 case 070:
910 case 071:
911 case 072:
912 case 073:
913 length += 4;
914 break;
915 case 074:
916 case 075:
917 case 076:
918 case 077:
919 length += 2;
920 break;
921 case 0140:
922 case 0141:
923 case 0142:
924 case 0143:
925 length += is_sbyte16(ins, c & 3) ? 1 : 2;
926 break;
927 case 0144:
928 case 0145:
929 case 0146:
930 case 0147:
931 codes++;
932 length++;
933 break;
934 case 0150:
935 case 0151:
936 case 0152:
937 case 0153:
938 length += is_sbyte32(ins, c & 3) ? 1 : 4;
939 break;
940 case 0154:
941 case 0155:
942 case 0156:
943 case 0157:
944 codes++;
945 length++;
946 break;
947 case 0160:
948 case 0161:
949 case 0162:
950 case 0163:
951 length++;
952 ins->rex |= REX_D;
953 ins->drexdst = regval(opx);
954 break;
955 case 0164:
956 case 0165:
957 case 0166:
958 case 0167:
959 length++;
960 ins->rex |= REX_D|REX_OC;
961 ins->drexdst = regval(opx);
962 break;
963 case 0171:
964 break;
965 case 0172:
966 case 0173:
967 case 0174:
968 codes++;
969 length++;
970 break;
971 case 0250:
972 case 0251:
973 case 0252:
974 case 0253:
975 length += is_sbyte64(ins, c & 3) ? 1 : 4;
976 break;
977 case 0260:
978 case 0261:
979 case 0262:
980 case 0263:
981 length += 2;
982 ins->rex |= REX_V;
983 ins->drexdst = regval(opx);
984 ins->vex_m = *codes++;
985 ins->vex_wlp = *codes++;
986 break;
987 case 0270:
988 length += 2;
989 ins->rex |= REX_V;
990 ins->drexdst = 0;
991 ins->vex_m = *codes++;
992 ins->vex_wlp = *codes++;
993 break;
994 case 0300:
995 case 0301:
996 case 0302:
997 case 0303:
998 break;
999 case 0310:
1000 if (bits == 64)
1001 return -1;
1002 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1003 break;
1004 case 0311:
1005 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1006 break;
1007 case 0312:
1008 break;
1009 case 0313:
1010 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1011 has_prefix(ins, PPS_ASIZE, P_A32))
1012 return -1;
1013 break;
1014 case 0314:
1015 case 0315:
1016 case 0316:
1017 case 0317:
1018 break;
1019 case 0320:
1020 length += (bits != 16);
1021 break;
1022 case 0321:
1023 length += (bits == 16);
1024 break;
1025 case 0322:
1026 break;
1027 case 0323:
1028 rex_mask &= ~REX_W;
1029 break;
1030 case 0324:
1031 ins->rex |= REX_W;
1032 break;
1033 case 0330:
1034 codes++, length++;
1035 break;
1036 case 0331:
1037 break;
1038 case 0332:
1039 case 0333:
1040 length++;
1041 break;
1042 case 0334:
1043 ins->rex |= REX_L;
1044 break;
1045 case 0335:
1046 break;
1047 case 0340:
1048 if (ins->oprs[0].segment != NO_SEG)
1049 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1050 " quantity of BSS space");
1051 else
1052 length += ins->oprs[0].offset;
1053 break;
1054 case 0360:
1055 break;
1056 case 0361:
1057 case 0362:
1058 case 0363:
1059 length++;
1060 break;
1061 case 0364:
1062 case 0365:
1063 break;
1064 case 0366:
1065 case 0367:
1066 length++;
1067 break;
1068 case 0370:
1069 case 0371:
1070 case 0372:
1071 break;
1072 case 0373:
1073 length++;
1074 break;
1075 default: /* can't do it by 'case' statements */
1076 if (c >= 0100 && c <= 0277) { /* it's an EA */
1077 ea ea_data;
1078 int rfield;
1079 int32_t rflags;
1080 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1081
1082 if (c <= 0177) {
1083 /* pick rfield from operand b */
1084 rflags = regflag(&ins->oprs[c & 7]);
1085 rfield = nasm_regvals[ins->oprs[c & 7].basereg];
1086 } else {
1087 rflags = 0;
1088 rfield = c & 7;
1089 }
1090
1091 if (!process_ea
1092 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1093 ins->addr_size, rfield, rflags, ins->forw_ref)) {
1094 errfunc(ERR_NONFATAL, "invalid effective address");
1095 return -1;
1096 } else {
1097 ins->rex |= ea_data.rex;
1098 length += ea_data.size;
1099 }
1100 } else {
1101 errfunc(ERR_PANIC, "internal instruction table corrupt"
1102 ": instruction code 0x%02X given", c);
1103 }
1104 }
1105 }
1106
1107 ins->rex &= rex_mask;
1108
1109 if (ins->rex & REX_V) {
1110 int bad32 = REX_R|REX_W|REX_X|REX_B;
1111
1112 if (ins->rex & REX_H) {
1113 errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
1114 return -1;
1115 }
1116 switch (ins->vex_wlp & 030) {
1117 case 000:
1118 case 020:
1119 ins->rex &= ~REX_W;
1120 break;
1121 case 010:
1122 ins->rex |= REX_W;
1123 bad32 &= ~REX_W;
1124 break;
1125 case 030:
1126 /* Follow REX_W */
1127 break;
1128 }
1129
1130 if (bits != 64 && ((ins->rex & bad32) || ins->drexdst > 7)) {
1131 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1132 return -1;
1133 }
1134 if (ins->vex_m != 1 || (ins->rex & (REX_W|REX_R|REX_B)))
1135 length += 3;
1136 else
1137 length += 2;
1138 } else if (ins->rex & REX_D) {
1139 if (ins->rex & REX_H) {
1140 errfunc(ERR_NONFATAL, "cannot use high register in drex instruction");
1141 return -1;
1142 }
1143 if (bits != 64 && ((ins->rex & (REX_R|REX_W|REX_X|REX_B)) ||
1144 ins->drexdst > 7)) {
1145 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1146 return -1;
1147 }
1148 length++;
1149 } else if (ins->rex & REX_REAL) {
1150 if (ins->rex & REX_H) {
1151 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1152 return -1;
1153 } else if (bits == 64) {
1154 length++;
1155 } else if ((ins->rex & REX_L) &&
1156 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1157 cpu >= IF_X86_64) {
1158 /* LOCK-as-REX.R */
1159 assert_no_prefix(ins, PPS_LREP);
1160 length++;
1161 } else {
1162 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1163 return -1;
1164 }
1165 }
1166
1167 return length;
1168 }
1169
1170 #define EMIT_REX() \
1171 if (!(ins->rex & (REX_D|REX_V)) && (ins->rex & REX_REAL) && (bits == 64)) { \
1172 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1173 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1174 ins->rex = 0; \
1175 offset += 1; \
1176 }
1177
1178 static void gencode(int32_t segment, int64_t offset, int bits,
1179 insn * ins, const uint8_t *codes, int64_t insn_end)
1180 {
1181 static char condval[] = { /* conditional opcodes */
1182 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1183 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1184 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1185 };
1186 uint8_t c;
1187 uint8_t bytes[4];
1188 int64_t size;
1189 int64_t data;
1190 struct operand *opx;
1191
1192 while (*codes) {
1193 c = *codes++;
1194 opx = &ins->oprs[c & 3];
1195 switch (c) {
1196 case 01:
1197 case 02:
1198 case 03:
1199 EMIT_REX();
1200 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1201 codes += c;
1202 offset += c;
1203 break;
1204
1205 case 04:
1206 case 06:
1207 switch (ins->oprs[0].basereg) {
1208 case R_CS:
1209 bytes[0] = 0x0E + (c == 0x04 ? 1 : 0);
1210 break;
1211 case R_DS:
1212 bytes[0] = 0x1E + (c == 0x04 ? 1 : 0);
1213 break;
1214 case R_ES:
1215 bytes[0] = 0x06 + (c == 0x04 ? 1 : 0);
1216 break;
1217 case R_SS:
1218 bytes[0] = 0x16 + (c == 0x04 ? 1 : 0);
1219 break;
1220 default:
1221 errfunc(ERR_PANIC,
1222 "bizarre 8086 segment register received");
1223 }
1224 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1225 offset++;
1226 break;
1227
1228 case 05:
1229 case 07:
1230 switch (ins->oprs[0].basereg) {
1231 case R_FS:
1232 bytes[0] = 0xA0 + (c == 0x05 ? 1 : 0);
1233 break;
1234 case R_GS:
1235 bytes[0] = 0xA8 + (c == 0x05 ? 1 : 0);
1236 break;
1237 default:
1238 errfunc(ERR_PANIC,
1239 "bizarre 386 segment register received");
1240 }
1241 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1242 offset++;
1243 break;
1244
1245 case 010:
1246 case 011:
1247 case 012:
1248 case 013:
1249 EMIT_REX();
1250 bytes[0] = *codes++ + ((regval(opx)) & 7);
1251 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1252 offset += 1;
1253 break;
1254
1255 case 014:
1256 case 015:
1257 case 016:
1258 case 017:
1259 /* XXX: warns for legitimate optimizer actions */
1260 if (opx->offset < -128 || opx->offset > 127) {
1261 errfunc(ERR_WARNING | ERR_WARN_NOV,
1262 "signed byte value exceeds bounds");
1263 }
1264
1265 if (opx->segment != NO_SEG) {
1266 data = opx->offset;
1267 out(offset, segment, &data, OUT_ADDRESS, 1,
1268 opx->segment, opx->wrt);
1269 } else {
1270 bytes[0] = opx->offset;
1271 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1272 NO_SEG);
1273 }
1274 offset += 1;
1275 break;
1276
1277 case 020:
1278 case 021:
1279 case 022:
1280 case 023:
1281 if (opx->offset < -256 || opx->offset > 255) {
1282 errfunc(ERR_WARNING | ERR_WARN_NOV,
1283 "byte value exceeds bounds");
1284 }
1285 if (opx->segment != NO_SEG) {
1286 data = opx->offset;
1287 out(offset, segment, &data, OUT_ADDRESS, 1,
1288 opx->segment, opx->wrt);
1289 } else {
1290 bytes[0] = opx->offset;
1291 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1292 NO_SEG);
1293 }
1294 offset += 1;
1295 break;
1296
1297 case 024:
1298 case 025:
1299 case 026:
1300 case 027:
1301 if (opx->offset < 0 || opx->offset > 255)
1302 errfunc(ERR_WARNING | ERR_WARN_NOV,
1303 "unsigned byte value exceeds bounds");
1304 if (opx->segment != NO_SEG) {
1305 data = opx->offset;
1306 out(offset, segment, &data, OUT_ADDRESS, 1,
1307 opx->segment, opx->wrt);
1308 } else {
1309 bytes[0] = opx->offset;
1310 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1311 NO_SEG);
1312 }
1313 offset += 1;
1314 break;
1315
1316 case 030:
1317 case 031:
1318 case 032:
1319 case 033:
1320 data = opx->offset;
1321 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1322 warn_overflow(2, data);
1323 out(offset, segment, &data, OUT_ADDRESS, 2,
1324 opx->segment, opx->wrt);
1325 offset += 2;
1326 break;
1327
1328 case 034:
1329 case 035:
1330 case 036:
1331 case 037:
1332 if (opx->type & (BITS16 | BITS32))
1333 size = (opx->type & BITS16) ? 2 : 4;
1334 else
1335 size = (bits == 16) ? 2 : 4;
1336 data = opx->offset;
1337 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1338 warn_overflow(size, data);
1339 out(offset, segment, &data, OUT_ADDRESS, size,
1340 opx->segment, opx->wrt);
1341 offset += size;
1342 break;
1343
1344 case 040:
1345 case 041:
1346 case 042:
1347 case 043:
1348 data = opx->offset;
1349 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1350 warn_overflow(4, data);
1351 out(offset, segment, &data, OUT_ADDRESS, 4,
1352 opx->segment, opx->wrt);
1353 offset += 4;
1354 break;
1355
1356 case 044:
1357 case 045:
1358 case 046:
1359 case 047:
1360 data = opx->offset;
1361 size = ins->addr_size >> 3;
1362 if (opx->segment == NO_SEG &&
1363 opx->wrt == NO_SEG)
1364 warn_overflow(size, data);
1365 out(offset, segment, &data, OUT_ADDRESS, size,
1366 opx->segment, opx->wrt);
1367 offset += size;
1368 break;
1369
1370 case 050:
1371 case 051:
1372 case 052:
1373 case 053:
1374 if (opx->segment != segment)
1375 errfunc(ERR_NONFATAL,
1376 "short relative jump outside segment");
1377 data = opx->offset - insn_end;
1378 if (data > 127 || data < -128)
1379 errfunc(ERR_NONFATAL, "short jump is out of range");
1380 bytes[0] = data;
1381 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1382 offset += 1;
1383 break;
1384
1385 case 054:
1386 case 055:
1387 case 056:
1388 case 057:
1389 data = (int64_t)opx->offset;
1390 out(offset, segment, &data, OUT_ADDRESS, 8,
1391 opx->segment, opx->wrt);
1392 offset += 8;
1393 break;
1394
1395 case 060:
1396 case 061:
1397 case 062:
1398 case 063:
1399 if (opx->segment != segment) {
1400 data = opx->offset;
1401 out(offset, segment, &data,
1402 OUT_REL2ADR, insn_end - offset,
1403 opx->segment, opx->wrt);
1404 } else {
1405 data = opx->offset - insn_end;
1406 out(offset, segment, &data,
1407 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1408 }
1409 offset += 2;
1410 break;
1411
1412 case 064:
1413 case 065:
1414 case 066:
1415 case 067:
1416 if (opx->type & (BITS16 | BITS32 | BITS64))
1417 size = (opx->type & BITS16) ? 2 : 4;
1418 else
1419 size = (bits == 16) ? 2 : 4;
1420 if (opx->segment != segment) {
1421 data = opx->offset;
1422 out(offset, segment, &data,
1423 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1424 insn_end - offset, opx->segment, opx->wrt);
1425 } else {
1426 data = opx->offset - insn_end;
1427 out(offset, segment, &data,
1428 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1429 }
1430 offset += size;
1431 break;
1432
1433 case 070:
1434 case 071:
1435 case 072:
1436 case 073:
1437 if (opx->segment != segment) {
1438 data = opx->offset;
1439 out(offset, segment, &data,
1440 OUT_REL4ADR, insn_end - offset,
1441 opx->segment, opx->wrt);
1442 } else {
1443 data = opx->offset - insn_end;
1444 out(offset, segment, &data,
1445 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1446 }
1447 offset += 4;
1448 break;
1449
1450 case 074:
1451 case 075:
1452 case 076:
1453 case 077:
1454 if (opx->segment == NO_SEG)
1455 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1456 " relocatable");
1457 data = 0;
1458 out(offset, segment, &data, OUT_ADDRESS, 2,
1459 outfmt->segbase(1 + opx->segment),
1460 opx->wrt);
1461 offset += 2;
1462 break;
1463
1464 case 0140:
1465 case 0141:
1466 case 0142:
1467 case 0143:
1468 data = opx->offset;
1469 if (is_sbyte16(ins, c & 3)) {
1470 bytes[0] = data;
1471 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1472 NO_SEG);
1473 offset++;
1474 } else {
1475 if (opx->segment == NO_SEG &&
1476 opx->wrt == NO_SEG)
1477 warn_overflow(2, data);
1478 out(offset, segment, &data, OUT_ADDRESS, 2,
1479 opx->segment, opx->wrt);
1480 offset += 2;
1481 }
1482 break;
1483
1484 case 0144:
1485 case 0145:
1486 case 0146:
1487 case 0147:
1488 EMIT_REX();
1489 bytes[0] = *codes++;
1490 if (is_sbyte16(ins, c & 3))
1491 bytes[0] |= 2; /* s-bit */
1492 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1493 offset++;
1494 break;
1495
1496 case 0150:
1497 case 0151:
1498 case 0152:
1499 case 0153:
1500 data = opx->offset;
1501 if (is_sbyte32(ins, c & 3)) {
1502 bytes[0] = data;
1503 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1504 NO_SEG);
1505 offset++;
1506 } else {
1507 out(offset, segment, &data, OUT_ADDRESS, 4,
1508 opx->segment, opx->wrt);
1509 offset += 4;
1510 }
1511 break;
1512
1513 case 0154:
1514 case 0155:
1515 case 0156:
1516 case 0157:
1517 EMIT_REX();
1518 bytes[0] = *codes++;
1519 if (is_sbyte32(ins, c & 3))
1520 bytes[0] |= 2; /* s-bit */
1521 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1522 offset++;
1523 break;
1524
1525 case 0160:
1526 case 0161:
1527 case 0162:
1528 case 0163:
1529 case 0164:
1530 case 0165:
1531 case 0166:
1532 case 0167:
1533 break;
1534
1535 case 0171:
1536 bytes[0] =
1537 (ins->drexdst << 4) |
1538 (ins->rex & REX_OC ? 0x08 : 0) |
1539 (ins->rex & (REX_R|REX_X|REX_B));
1540 ins->rex = 0;
1541 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1542 offset++;
1543 break;
1544
1545 case 0172:
1546 c = *codes++;
1547 opx = &ins->oprs[c >> 3];
1548 bytes[0] = nasm_regvals[opx->basereg] << 4;
1549 opx = &ins->oprs[c & 7];
1550 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1551 errfunc(ERR_NONFATAL,
1552 "non-absolute expression not permitted as argument %d",
1553 c & 7);
1554 } else {
1555 if (opx->offset & ~15) {
1556 errfunc(ERR_WARNING | ERR_WARN_NOV,
1557 "four-bit argument exceeds bounds");
1558 }
1559 bytes[0] |= opx->offset & 15;
1560 }
1561 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1562 offset++;
1563 break;
1564
1565 case 0173:
1566 c = *codes++;
1567 opx = &ins->oprs[c >> 4];
1568 bytes[0] = nasm_regvals[opx->basereg] << 4;
1569 bytes[0] |= c & 15;
1570 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1571 offset++;
1572 break;
1573
1574 case 0174:
1575 c = *codes++;
1576 opx = &ins->oprs[c];
1577 bytes[0] = nasm_regvals[opx->basereg] << 4;
1578 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1579 offset++;
1580 break;
1581
1582 case 0250:
1583 case 0251:
1584 case 0252:
1585 case 0253:
1586 data = opx->offset;
1587 /* is_sbyte32() is right here, we have already warned */
1588 if (is_sbyte32(ins, c & 3)) {
1589 bytes[0] = data;
1590 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1591 NO_SEG);
1592 offset++;
1593 } else {
1594 out(offset, segment, &data, OUT_ADDRESS, 4,
1595 opx->segment, opx->wrt);
1596 offset += 4;
1597 }
1598 break;
1599
1600 case 0260:
1601 case 0261:
1602 case 0262:
1603 case 0263:
1604 case 0270:
1605 codes += 2;
1606 if (ins->vex_m != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1607 bytes[0] = 0xc4;
1608 bytes[1] = ins->vex_m | ((~ins->rex & 7) << 5);
1609 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1610 ((~ins->drexdst & 15)<< 3) | (ins->vex_wlp & 07);
1611 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1612 offset += 3;
1613 } else {
1614 bytes[0] = 0xc5;
1615 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1616 ((~ins->drexdst & 15) << 3) | (ins->vex_wlp & 07);
1617 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1618 offset += 2;
1619 }
1620 break;
1621
1622 case 0300:
1623 case 0301:
1624 case 0302:
1625 case 0303:
1626 break;
1627
1628 case 0310:
1629 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1630 *bytes = 0x67;
1631 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1632 offset += 1;
1633 } else
1634 offset += 0;
1635 break;
1636
1637 case 0311:
1638 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1639 *bytes = 0x67;
1640 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1641 offset += 1;
1642 } else
1643 offset += 0;
1644 break;
1645
1646 case 0312:
1647 break;
1648
1649 case 0313:
1650 ins->rex = 0;
1651 break;
1652
1653 case 0314:
1654 case 0315:
1655 case 0316:
1656 case 0317:
1657 break;
1658
1659 case 0320:
1660 if (bits != 16) {
1661 *bytes = 0x66;
1662 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1663 offset += 1;
1664 } else
1665 offset += 0;
1666 break;
1667
1668 case 0321:
1669 if (bits == 16) {
1670 *bytes = 0x66;
1671 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1672 offset += 1;
1673 } else
1674 offset += 0;
1675 break;
1676
1677 case 0322:
1678 case 0323:
1679 break;
1680
1681 case 0324:
1682 ins->rex |= REX_W;
1683 break;
1684
1685 case 0330:
1686 *bytes = *codes++ ^ condval[ins->condition];
1687 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1688 offset += 1;
1689 break;
1690
1691 case 0331:
1692 break;
1693
1694 case 0332:
1695 case 0333:
1696 *bytes = c - 0332 + 0xF2;
1697 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1698 offset += 1;
1699 break;
1700
1701 case 0334:
1702 if (ins->rex & REX_R) {
1703 *bytes = 0xF0;
1704 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1705 offset += 1;
1706 }
1707 ins->rex &= ~(REX_L|REX_R);
1708 break;
1709
1710 case 0335:
1711 break;
1712
1713 case 0340:
1714 if (ins->oprs[0].segment != NO_SEG)
1715 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1716 else {
1717 int64_t size = ins->oprs[0].offset;
1718 if (size > 0)
1719 out(offset, segment, NULL,
1720 OUT_RESERVE, size, NO_SEG, NO_SEG);
1721 offset += size;
1722 }
1723 break;
1724
1725 case 0360:
1726 break;
1727
1728 case 0361:
1729 bytes[0] = 0x66;
1730 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1731 offset += 1;
1732 break;
1733
1734 case 0362:
1735 case 0363:
1736 bytes[0] = c - 0362 + 0xf2;
1737 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1738 offset += 1;
1739 break;
1740
1741 case 0364:
1742 case 0365:
1743 break;
1744
1745 case 0366:
1746 case 0367:
1747 *bytes = c - 0366 + 0x66;
1748 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1749 offset += 1;
1750 break;
1751
1752 case 0370:
1753 case 0371:
1754 case 0372:
1755 break;
1756
1757 case 0373:
1758 *bytes = bits == 16 ? 3 : 5;
1759 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1760 offset += 1;
1761 break;
1762
1763 default: /* can't do it by 'case' statements */
1764 if (c >= 0100 && c <= 0277) { /* it's an EA */
1765 ea ea_data;
1766 int rfield;
1767 int32_t rflags;
1768 uint8_t *p;
1769 int32_t s;
1770
1771 if (c <= 0177) {
1772 /* pick rfield from operand b */
1773 rflags = regflag(&ins->oprs[c & 7]);
1774 rfield = nasm_regvals[ins->oprs[c & 7].basereg];
1775 } else {
1776 /* rfield is constant */
1777 rflags = 0;
1778 rfield = c & 7;
1779 }
1780
1781 if (!process_ea
1782 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1783 ins->addr_size, rfield, rflags, ins->forw_ref)) {
1784 errfunc(ERR_NONFATAL, "invalid effective address");
1785 }
1786
1787
1788 p = bytes;
1789 *p++ = ea_data.modrm;
1790 if (ea_data.sib_present)
1791 *p++ = ea_data.sib;
1792
1793 /* DREX suffixes come between the SIB and the displacement */
1794 if (ins->rex & REX_D) {
1795 *p++ =
1796 (ins->drexdst << 4) |
1797 (ins->rex & REX_OC ? 0x08 : 0) |
1798 (ins->rex & (REX_R|REX_X|REX_B));
1799 ins->rex = 0;
1800 }
1801
1802 s = p - bytes;
1803 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1804
1805 switch (ea_data.bytes) {
1806 case 0:
1807 break;
1808 case 1:
1809 if (ins->oprs[(c >> 3) & 7].segment != NO_SEG) {
1810 data = ins->oprs[(c >> 3) & 7].offset;
1811 out(offset, segment, &data, OUT_ADDRESS, 1,
1812 ins->oprs[(c >> 3) & 7].segment,
1813 ins->oprs[(c >> 3) & 7].wrt);
1814 } else {
1815 *bytes = ins->oprs[(c >> 3) & 7].offset;
1816 out(offset, segment, bytes, OUT_RAWDATA, 1,
1817 NO_SEG, NO_SEG);
1818 }
1819 s++;
1820 break;
1821 case 8:
1822 case 2:
1823 case 4:
1824 data = ins->oprs[(c >> 3) & 7].offset;
1825 warn_overflow(ea_data.bytes, data);
1826 out(offset, segment, &data,
1827 ea_data.rip ? OUT_REL4ADR : OUT_ADDRESS,
1828 ea_data.bytes,
1829 ins->oprs[(c >> 3) & 7].segment,
1830 ins->oprs[(c >> 3) & 7].wrt);
1831 s += ea_data.bytes;
1832 break;
1833 }
1834 offset += s;
1835 } else {
1836 errfunc(ERR_PANIC, "internal instruction table corrupt"
1837 ": instruction code 0x%02X given", c);
1838 }
1839 }
1840 }
1841 }
1842
1843 static int32_t regflag(const operand * o)
1844 {
1845 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1846 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1847 }
1848 return nasm_reg_flags[o->basereg];
1849 }
1850
1851 static int32_t regval(const operand * o)
1852 {
1853 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1854 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1855 }
1856 return nasm_regvals[o->basereg];
1857 }
1858
1859 static int op_rexflags(const operand * o, int mask)
1860 {
1861 int32_t flags;
1862 int val;
1863
1864 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1865 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1866 }
1867
1868 flags = nasm_reg_flags[o->basereg];
1869 val = nasm_regvals[o->basereg];
1870
1871 return rexflags(val, flags, mask);
1872 }
1873
1874 static int rexflags(int val, int32_t flags, int mask)
1875 {
1876 int rex = 0;
1877
1878 if (val >= 8)
1879 rex |= REX_B|REX_X|REX_R;
1880 if (flags & BITS64)
1881 rex |= REX_W;
1882 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1883 rex |= REX_H;
1884 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1885 rex |= REX_P;
1886
1887 return rex & mask;
1888 }
1889
1890 static int matches(const struct itemplate *itemp, insn * instruction, int bits)
1891 {
1892 int i, size[MAX_OPERANDS], asize, oprs, ret;
1893
1894 ret = 100;
1895
1896 /*
1897 * Check the opcode
1898 */
1899 if (itemp->opcode != instruction->opcode)
1900 return 0;
1901
1902 /*
1903 * Count the operands
1904 */
1905 if (itemp->operands != instruction->operands)
1906 return 0;
1907
1908 /*
1909 * Check that no spurious colons or TOs are present
1910 */
1911 for (i = 0; i < itemp->operands; i++)
1912 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1913 return 0;
1914
1915 /*
1916 * Process size flags
1917 */
1918 if (itemp->flags & IF_ARMASK) {
1919 memset(size, 0, sizeof size);
1920
1921 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
1922
1923 switch (itemp->flags & IF_SMASK) {
1924 case IF_SB:
1925 size[i] = BITS8;
1926 break;
1927 case IF_SW:
1928 size[i] = BITS16;
1929 break;
1930 case IF_SD:
1931 size[i] = BITS32;
1932 break;
1933 case IF_SQ:
1934 size[i] = BITS64;
1935 break;
1936 case IF_SO:
1937 size[i] = BITS128;
1938 break;
1939 case IF_SY:
1940 size[i] = BITS256;
1941 break;
1942 case IF_SZ:
1943 switch (bits) {
1944 case 16:
1945 size[i] = BITS16;
1946 break;
1947 case 32:
1948 size[i] = BITS32;
1949 break;
1950 case 64:
1951 size[i] = BITS64;
1952 break;
1953 }
1954 break;
1955 default:
1956 break;
1957 }
1958 } else {
1959 asize = 0;
1960 switch (itemp->flags & IF_SMASK) {
1961 case IF_SB:
1962 asize = BITS8;
1963 break;
1964 case IF_SW:
1965 asize = BITS16;
1966 break;
1967 case IF_SD:
1968 asize = BITS32;
1969 break;
1970 case IF_SQ:
1971 asize = BITS64;
1972 break;
1973 case IF_SO:
1974 asize = BITS128;
1975 break;
1976 case IF_SY:
1977 asize = BITS256;
1978 break;
1979 case IF_SZ:
1980 switch (bits) {
1981 case 16:
1982 asize = BITS16;
1983 break;
1984 case 32:
1985 asize = BITS32;
1986 break;
1987 case 64:
1988 asize = BITS64;
1989 break;
1990 }
1991 break;
1992 default:
1993 break;
1994 }
1995 for (i = 0; i < MAX_OPERANDS; i++)
1996 size[i] = asize;
1997 }
1998
1999 /*
2000 * Check that the operand flags all match up
2001 */
2002 for (i = 0; i < itemp->operands; i++) {
2003 int32_t type = instruction->oprs[i].type;
2004 if (!(type & SIZE_MASK))
2005 type |= size[i];
2006
2007 if (itemp->opd[i] & SAME_AS) {
2008 int j = itemp->opd[i] & ~SAME_AS;
2009 if (type != instruction->oprs[j].type ||
2010 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
2011 return 0;
2012 } else if (itemp->opd[i] & ~type ||
2013 ((itemp->opd[i] & SIZE_MASK) &&
2014 ((itemp->opd[i] ^ type) & SIZE_MASK))) {
2015 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2016 (type & SIZE_MASK))
2017 return 0;
2018 else
2019 return 1;
2020 }
2021 }
2022
2023 /*
2024 * Check operand sizes
2025 */
2026 if (itemp->flags & (IF_SM | IF_SM2)) {
2027 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2028 asize = 0;
2029 for (i = 0; i < oprs; i++) {
2030 if ((asize = itemp->opd[i] & SIZE_MASK) != 0) {
2031 int j;
2032 for (j = 0; j < oprs; j++)
2033 size[j] = asize;
2034 break;
2035 }
2036 }
2037 } else {
2038 oprs = itemp->operands;
2039 }
2040
2041 for (i = 0; i < itemp->operands; i++) {
2042 if (!(itemp->opd[i] & SIZE_MASK) &&
2043 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2044 return 2;
2045 }
2046
2047 /*
2048 * Check template is okay at the set cpu level
2049 */
2050 if (((itemp->flags & IF_PLEVEL) > cpu))
2051 return 3;
2052
2053 /*
2054 * Check if instruction is available in long mode
2055 */
2056 if ((itemp->flags & IF_NOLONG) && (bits == 64))
2057 return 4;
2058
2059 /*
2060 * Check if special handling needed for Jumps
2061 */
2062 if ((uint8_t)(itemp->code[0]) >= 0370)
2063 return 99;
2064
2065 return ret;
2066 }
2067
2068 static ea *process_ea(operand * input, ea * output, int bits,
2069 int addrbits, int rfield, int32_t rflags, int forw_ref)
2070 {
2071 output->rip = false;
2072
2073 /* REX flags for the rfield operand */
2074 output->rex |= rexflags(rfield, rflags, REX_R|REX_P|REX_W|REX_H);
2075
2076 if (!(REGISTER & ~input->type)) { /* register direct */
2077 int i;
2078 int32_t f;
2079
2080 if (input->basereg < EXPR_REG_START /* Verify as Register */
2081 || input->basereg >= REG_ENUM_LIMIT)
2082 return NULL;
2083 f = regflag(input);
2084 i = nasm_regvals[input->basereg];
2085
2086 if (REG_EA & ~f)
2087 return NULL; /* Invalid EA register */
2088
2089 output->rex |= op_rexflags(input, REX_B|REX_P|REX_W|REX_H);
2090
2091 output->sib_present = false; /* no SIB necessary */
2092 output->bytes = 0; /* no offset necessary either */
2093 output->modrm = 0xC0 | ((rfield & 7) << 3) | (i & 7);
2094 } else { /* it's a memory reference */
2095 if (input->basereg == -1
2096 && (input->indexreg == -1 || input->scale == 0)) {
2097 /* it's a pure offset */
2098 if (bits == 64 && (~input->type & IP_REL)) {
2099 int scale, index, base;
2100 output->sib_present = true;
2101 scale = 0;
2102 index = 4;
2103 base = 5;
2104 output->sib = (scale << 6) | (index << 3) | base;
2105 output->bytes = 4;
2106 output->modrm = 4 | ((rfield & 7) << 3);
2107 output->rip = false;
2108 } else {
2109 output->sib_present = false;
2110 output->bytes = (addrbits != 16 ? 4 : 2);
2111 output->modrm = (addrbits != 16 ? 5 : 6) | ((rfield & 7) << 3);
2112 output->rip = bits == 64;
2113 }
2114 } else { /* it's an indirection */
2115 int i = input->indexreg, b = input->basereg, s = input->scale;
2116 int32_t o = input->offset, seg = input->segment;
2117 int hb = input->hintbase, ht = input->hinttype;
2118 int t;
2119 int it, bt;
2120 int32_t ix, bx; /* register flags */
2121
2122 if (s == 0)
2123 i = -1; /* make this easy, at least */
2124
2125 if (i >= EXPR_REG_START && i < REG_ENUM_LIMIT) {
2126 it = nasm_regvals[i];
2127 ix = nasm_reg_flags[i];
2128 } else {
2129 it = -1;
2130 ix = 0;
2131 }
2132
2133 if (b >= EXPR_REG_START && b < REG_ENUM_LIMIT) {
2134 bt = nasm_regvals[b];
2135 bx = nasm_reg_flags[b];
2136 } else {
2137 bt = -1;
2138 bx = 0;
2139 }
2140
2141 /* check for a 32/64-bit memory reference... */
2142 if ((ix|bx) & (BITS32|BITS64)) {
2143 /* it must be a 32/64-bit memory reference. Firstly we have
2144 * to check that all registers involved are type E/Rxx. */
2145 int32_t sok = BITS32|BITS64;
2146
2147 if (it != -1) {
2148 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2149 sok &= ix;
2150 else
2151 return NULL;
2152 }
2153
2154 if (bt != -1) {
2155 if (REG_GPR & ~bx)
2156 return NULL; /* Invalid register */
2157 if (~sok & bx & SIZE_MASK)
2158 return NULL; /* Invalid size */
2159 sok &= bx;
2160 }
2161
2162 /* While we're here, ensure the user didn't specify
2163 WORD or QWORD. */
2164 if (input->disp_size == 16 || input->disp_size == 64)
2165 return NULL;
2166
2167 if (addrbits == 16 ||
2168 (addrbits == 32 && !(sok & BITS32)) ||
2169 (addrbits == 64 && !(sok & BITS64)))
2170 return NULL;
2171
2172 /* now reorganize base/index */
2173 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2174 ((hb == b && ht == EAH_NOTBASE)
2175 || (hb == i && ht == EAH_MAKEBASE))) {
2176 /* swap if hints say so */
2177 t = bt, bt = it, it = t;
2178 t = bx, bx = ix, ix = t;
2179 }
2180 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2181 bt = -1, bx = 0, s++;
2182 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2183 /* make single reg base, unless hint */
2184 bt = it, bx = ix, it = -1, ix = 0;
2185 }
2186 if (((s == 2 && it != REG_NUM_ESP
2187 && !(input->eaflags & EAF_TIMESTWO)) || s == 3
2188 || s == 5 || s == 9) && bt == -1)
2189 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2190 if (it == -1 && (bt & 7) != REG_NUM_ESP
2191 && (input->eaflags & EAF_TIMESTWO))
2192 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2193 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2194 if (s == 1 && it == REG_NUM_ESP) {
2195 /* swap ESP into base if scale is 1 */
2196 t = it, it = bt, bt = t;
2197 t = ix, ix = bx, bx = t;
2198 }
2199 if (it == REG_NUM_ESP
2200 || (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2201 return NULL; /* wrong, for various reasons */
2202
2203 output->rex |= rexflags(it, ix, REX_X);
2204 output->rex |= rexflags(bt, bx, REX_B);
2205
2206 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2207 /* no SIB needed */
2208 int mod, rm;
2209
2210 if (bt == -1) {
2211 rm = 5;
2212 mod = 0;
2213 } else {
2214 rm = (bt & 7);
2215 if (rm != REG_NUM_EBP && o == 0 &&
2216 seg == NO_SEG && !forw_ref &&
2217 !(input->eaflags &
2218 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2219 mod = 0;
2220 else if (input->eaflags & EAF_BYTEOFFS ||
2221 (o >= -128 && o <= 127 && seg == NO_SEG
2222 && !forw_ref
2223 && !(input->eaflags & EAF_WORDOFFS)))
2224 mod = 1;
2225 else
2226 mod = 2;
2227 }
2228
2229 output->sib_present = false;
2230 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2231 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2232 } else {
2233 /* we need a SIB */
2234 int mod, scale, index, base;
2235
2236 if (it == -1)
2237 index = 4, s = 1;
2238 else
2239 index = (it & 7);
2240
2241 switch (s) {
2242 case 1:
2243 scale = 0;
2244 break;
2245 case 2:
2246 scale = 1;
2247 break;
2248 case 4:
2249 scale = 2;
2250 break;
2251 case 8:
2252 scale = 3;
2253 break;
2254 default: /* then what the smeg is it? */
2255 return NULL; /* panic */
2256 }
2257
2258 if (bt == -1) {
2259 base = 5;
2260 mod = 0;
2261 } else {
2262 base = (bt & 7);
2263 if (base != REG_NUM_EBP && o == 0 &&
2264 seg == NO_SEG && !forw_ref &&
2265 !(input->eaflags &
2266 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2267 mod = 0;
2268 else if (input->eaflags & EAF_BYTEOFFS ||
2269 (o >= -128 && o <= 127 && seg == NO_SEG
2270 && !forw_ref
2271 && !(input->eaflags & EAF_WORDOFFS)))
2272 mod = 1;
2273 else
2274 mod = 2;
2275 }
2276
2277 output->sib_present = true;
2278 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2279 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2280 output->sib = (scale << 6) | (index << 3) | base;
2281 }
2282 } else { /* it's 16-bit */
2283 int mod, rm;
2284
2285 /* check for 64-bit long mode */
2286 if (addrbits == 64)
2287 return NULL;
2288
2289 /* check all registers are BX, BP, SI or DI */
2290 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI
2291 && b != R_DI) || (i != -1 && i != R_BP && i != R_BX
2292 && i != R_SI && i != R_DI))
2293 return NULL;
2294
2295 /* ensure the user didn't specify DWORD/QWORD */
2296 if (input->disp_size == 32 || input->disp_size == 64)
2297 return NULL;
2298
2299 if (s != 1 && i != -1)
2300 return NULL; /* no can do, in 16-bit EA */
2301 if (b == -1 && i != -1) {
2302 int tmp = b;
2303 b = i;
2304 i = tmp;
2305 } /* swap */
2306 if ((b == R_SI || b == R_DI) && i != -1) {
2307 int tmp = b;
2308 b = i;
2309 i = tmp;
2310 }
2311 /* have BX/BP as base, SI/DI index */
2312 if (b == i)
2313 return NULL; /* shouldn't ever happen, in theory */
2314 if (i != -1 && b != -1 &&
2315 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2316 return NULL; /* invalid combinations */
2317 if (b == -1) /* pure offset: handled above */
2318 return NULL; /* so if it gets to here, panic! */
2319
2320 rm = -1;
2321 if (i != -1)
2322 switch (i * 256 + b) {
2323 case R_SI * 256 + R_BX:
2324 rm = 0;
2325 break;
2326 case R_DI * 256 + R_BX:
2327 rm = 1;
2328 break;
2329 case R_SI * 256 + R_BP:
2330 rm = 2;
2331 break;
2332 case R_DI * 256 + R_BP:
2333 rm = 3;
2334 break;
2335 } else
2336 switch (b) {
2337 case R_SI:
2338 rm = 4;
2339 break;
2340 case R_DI:
2341 rm = 5;
2342 break;
2343 case R_BP:
2344 rm = 6;
2345 break;
2346 case R_BX:
2347 rm = 7;
2348 break;
2349 }
2350 if (rm == -1) /* can't happen, in theory */
2351 return NULL; /* so panic if it does */
2352
2353 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2354 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2355 mod = 0;
2356 else if (input->eaflags & EAF_BYTEOFFS ||
2357 (o >= -128 && o <= 127 && seg == NO_SEG
2358 && !forw_ref
2359 && !(input->eaflags & EAF_WORDOFFS)))
2360 mod = 1;
2361 else
2362 mod = 2;
2363
2364 output->sib_present = false; /* no SIB - it's 16-bit */
2365 output->bytes = mod; /* bytes of offset needed */
2366 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2367 }
2368 }
2369 }
2370
2371 output->size = 1 + output->sib_present + output->bytes;
2372 return output;
2373 }
2374
2375 static void add_asp(insn *ins, int addrbits)
2376 {
2377 int j, valid;
2378 int defdisp;
2379
2380 valid = (addrbits == 64) ? 64|32 : 32|16;
2381
2382 switch (ins->prefixes[PPS_ASIZE]) {
2383 case P_A16:
2384 valid &= 16;
2385 break;
2386 case P_A32:
2387 valid &= 32;
2388 break;
2389 case P_A64:
2390 valid &= 64;
2391 break;
2392 case P_ASP:
2393 valid &= (addrbits == 32) ? 16 : 32;
2394 break;
2395 default:
2396 break;
2397 }
2398
2399 for (j = 0; j < ins->operands; j++) {
2400 if (!(MEMORY & ~ins->oprs[j].type)) {
2401 int32_t i, b;
2402
2403 /* Verify as Register */
2404 if (ins->oprs[j].indexreg < EXPR_REG_START
2405 || ins->oprs[j].indexreg >= REG_ENUM_LIMIT)
2406 i = 0;
2407 else
2408 i = nasm_reg_flags[ins->oprs[j].indexreg];
2409
2410 /* Verify as Register */
2411 if (ins->oprs[j].basereg < EXPR_REG_START
2412 || ins->oprs[j].basereg >= REG_ENUM_LIMIT)
2413 b = 0;
2414 else
2415 b = nasm_reg_flags[ins->oprs[j].basereg];
2416
2417 if (ins->oprs[j].scale == 0)
2418 i = 0;
2419
2420 if (!i && !b) {
2421 int ds = ins->oprs[j].disp_size;
2422 if ((addrbits != 64 && ds > 8) ||
2423 (addrbits == 64 && ds == 16))
2424 valid &= ds;
2425 } else {
2426 if (!(REG16 & ~b))
2427 valid &= 16;
2428 if (!(REG32 & ~b))
2429 valid &= 32;
2430 if (!(REG64 & ~b))
2431 valid &= 64;
2432
2433 if (!(REG16 & ~i))
2434 valid &= 16;
2435 if (!(REG32 & ~i))
2436 valid &= 32;
2437 if (!(REG64 & ~i))
2438 valid &= 64;
2439 }
2440 }
2441 }
2442
2443 if (valid & addrbits) {
2444 ins->addr_size = addrbits;
2445 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2446 /* Add an address size prefix */
2447 enum prefixes pref = (addrbits == 32) ? P_A16 : P_A32;
2448 ins->prefixes[PPS_ASIZE] = pref;
2449 ins->addr_size = (addrbits == 32) ? 16 : 32;
2450 } else {
2451 /* Impossible... */
2452 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2453 ins->addr_size = addrbits; /* Error recovery */
2454 }
2455
2456 defdisp = ins->addr_size == 16 ? 16 : 32;
2457
2458 for (j = 0; j < ins->operands; j++) {
2459 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2460 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp)
2461 != ins->addr_size) {
2462 /* mem_offs sizes must match the address size; if not,
2463 strip the MEM_OFFS bit and match only EA instructions */
2464 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2465 }
2466 }
2467 }
The Netwide Assembler