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assemble.c: remove stray debugging code
[nasm.git] / assemble.c
blob5a50e1986fd47bb409d213f51d8bbf3a18a9866a
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2011 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - a signed byte immediate operand, from operand 0..3
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \140..\143 - an immediate word or signed byte for operand 0..3
64 * \144..\147 - or 2 (s-field) into opcode byte if operand 0..3
65 * is a signed byte rather than a word. Opcode byte follows.
66 * \150..\153 - an immediate dword or signed byte for operand 0..3
67 * \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
68 * is a signed byte rather than a dword. Opcode byte follows.
69 * \172\ab - the register number from operand a in bits 7..4, with
70 * the 4-bit immediate from operand b in bits 3..0.
71 * \173\xab - the register number from operand a in bits 7..4, with
72 * the value b in bits 3..0.
73 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
74 * an arbitrary value in bits 3..0 (assembled as zero.)
75 * \2ab - a ModRM, calculated on EA in operand a, with the spare
76 * field equal to digit b.
77 * \250..\253 - same as \150..\153, except warn if the 64-bit operand
78 * is not equal to the truncated and sign-extended 32-bit
79 * operand; used for 32-bit immediates in 64-bit mode.
80 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
81 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
82 * V field taken from operand 0..3.
83 * \270 - this instruction uses VEX/XOP rather than REX, with the
84 * V field set to 1111b.
85 *
86 * VEX/XOP prefixes are followed by the sequence:
87 * \tmm\wlp where mm is the M field; and wlp is:
88 * 00 wwl lpp
89 * [l0] ll = 0 for L = 0 (.128, .lz)
90 * [l1] ll = 1 for L = 1 (.256)
91 * [lig] ll = 2 for L don't care (always assembled as 0)
92 *
93 * [w0] ww = 0 for W = 0
94 * [w1 ] ww = 1 for W = 1
95 * [wig] ww = 2 for W don't care (always assembled as 0)
96 * [ww] ww = 3 for W used as REX.W
97 *
98 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
99 *
100 * \274..\277 - a signed byte immediate operand, from operand 0..3,
101 * which is to be extended to the operand size.
102 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
103 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
104 * \312 - (disassembler only) invalid with non-default address size.
105 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
106 * \314 - (disassembler only) invalid with REX.B
107 * \315 - (disassembler only) invalid with REX.X
108 * \316 - (disassembler only) invalid with REX.R
109 * \317 - (disassembler only) invalid with REX.W
110 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
111 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
112 * \322 - indicates that this instruction is only valid when the
113 * operand size is the default (instruction to disassembler,
114 * generates no code in the assembler)
115 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
116 * \324 - indicates 64-bit operand size requiring REX prefix.
117 * \325 - instruction which always uses spl/bpl/sil/dil
118 * \330 - a literal byte follows in the code stream, to be added
119 * to the condition code value of the instruction.
120 * \331 - instruction not valid with REP prefix. Hint for
121 * disassembler only; for SSE instructions.
122 * \332 - REP prefix (0xF2 byte) used as opcode extension.
123 * \333 - REP prefix (0xF3 byte) used as opcode extension.
124 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
125 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
126 * \336 - force a REP(E) prefix (0xF2) even if not specified.
127 * \337 - force a REPNE prefix (0xF3) even if not specified.
128 * \336-\337 are still listed as prefixes in the disassembler.
129 * \340 - reserve <operand 0> bytes of uninitialized storage.
130 * Operand 0 had better be a segmentless constant.
131 * \341 - this instruction needs a WAIT "prefix"
132 * \344,\345 - the PUSH/POP (respectively) codes for CS, DS, ES, SS
133 * (POP is never used for CS) depending on operand 0
134 * \346,\347 - the second byte of PUSH/POP codes for FS, GS, depending
135 * on operand 0
136 * \360 - no SSE prefix (== \364\331)
137 * \361 - 66 SSE prefix (== \366\331)
138 * \362 - F2 SSE prefix (== \364\332)
139 * \363 - F3 SSE prefix (== \364\333)
140 * \364 - operand-size prefix (0x66) not permitted
141 * \365 - address-size prefix (0x67) not permitted
142 * \366 - operand-size prefix (0x66) used as opcode extension
143 * \367 - address-size prefix (0x67) used as opcode extension
144 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
145 * 370 is used for Jcc, 371 is used for JMP.
146 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
147 * used for conditional jump over longer jump
148 * \374 - this instruction takes an XMM VSIB memory EA
149 * \375 - this instruction takes an YMM VSIB memory EA
150 */
151
152 #include "compiler.h"
153
154 #include <stdio.h>
155 #include <string.h>
156 #include <inttypes.h>
157
158 #include "nasm.h"
159 #include "nasmlib.h"
160 #include "assemble.h"
161 #include "insns.h"
162 #include "tables.h"
163
164 enum match_result {
165 /*
166 * Matching errors. These should be sorted so that more specific
167 * errors come later in the sequence.
168 */
169 MERR_INVALOP,
170 MERR_OPSIZEMISSING,
171 MERR_OPSIZEMISMATCH,
172 MERR_BADCPU,
173 MERR_BADMODE,
174 /*
175 * Matching success; the conditional ones first
176 */
177 MOK_JUMP, /* Matching OK but needs jmp_match() */
178 MOK_GOOD /* Matching unconditionally OK */
179 };
180
181 typedef struct {
182 enum ea_type type; /* what kind of EA is this? */
183 int sib_present; /* is a SIB byte necessary? */
184 int bytes; /* # of bytes of offset needed */
185 int size; /* lazy - this is sib+bytes+1 */
186 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
187 } ea;
188
189 static uint32_t cpu; /* cpu level received from nasm.c */
190 static efunc errfunc;
191 static struct ofmt *outfmt;
192 static ListGen *list;
193
194 static int64_t calcsize(int32_t, int64_t, int, insn *, const uint8_t *);
195 static void gencode(int32_t segment, int64_t offset, int bits,
196 insn * ins, const struct itemplate *temp,
197 int64_t insn_end);
198 static enum match_result find_match(const struct itemplate **tempp,
199 insn *instruction,
200 int32_t segment, int64_t offset, int bits);
201 static enum match_result matches(const struct itemplate *, insn *, int bits);
202 static opflags_t regflag(const operand *);
203 static int32_t regval(const operand *);
204 static int rexflags(int, opflags_t, int);
205 static int op_rexflags(const operand *, int);
206 static void add_asp(insn *, int);
207
208 static enum ea_type process_ea(operand *, ea *, int, int, int, opflags_t);
209
210 static int has_prefix(insn * ins, enum prefix_pos pos, enum prefixes prefix)
211 {
212 return ins->prefixes[pos] == prefix;
213 }
214
215 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
216 {
217 if (ins->prefixes[pos])
218 errfunc(ERR_NONFATAL, "invalid %s prefix",
219 prefix_name(ins->prefixes[pos]));
220 }
221
222 static const char *size_name(int size)
223 {
224 switch (size) {
225 case 1:
226 return "byte";
227 case 2:
228 return "word";
229 case 4:
230 return "dword";
231 case 8:
232 return "qword";
233 case 10:
234 return "tword";
235 case 16:
236 return "oword";
237 case 32:
238 return "yword";
239 default:
240 return "???";
241 }
242 }
243
244 static void warn_overflow(int pass, int size)
245 {
246 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
247 "%s data exceeds bounds", size_name(size));
248 }
249
250 static void warn_overflow_const(int64_t data, int size)
251 {
252 if (overflow_general(data, size))
253 warn_overflow(ERR_PASS1, size);
254 }
255
256 static void warn_overflow_opd(const struct operand *o, int size)
257 {
258 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
259 if (overflow_general(o->offset, size))
260 warn_overflow(ERR_PASS2, size);
261 }
262 }
263
264 /*
265 * This routine wrappers the real output format's output routine,
266 * in order to pass a copy of the data off to the listing file
267 * generator at the same time.
268 */
269 static void out(int64_t offset, int32_t segto, const void *data,
270 enum out_type type, uint64_t size,
271 int32_t segment, int32_t wrt)
272 {
273 static int32_t lineno = 0; /* static!!! */
274 static char *lnfname = NULL;
275 uint8_t p[8];
276
277 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
278 /*
279 * This is a non-relocated address, and we're going to
280 * convert it into RAWDATA format.
281 */
282 uint8_t *q = p;
283
284 if (size > 8) {
285 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
286 return;
287 }
288
289 WRITEADDR(q, *(int64_t *)data, size);
290 data = p;
291 type = OUT_RAWDATA;
292 }
293
294 list->output(offset, data, type, size);
295
296 /*
297 * this call to src_get determines when we call the
298 * debug-format-specific "linenum" function
299 * it updates lineno and lnfname to the current values
300 * returning 0 if "same as last time", -2 if lnfname
301 * changed, and the amount by which lineno changed,
302 * if it did. thus, these variables must be static
303 */
304
305 if (src_get(&lineno, &lnfname))
306 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
307
308 outfmt->output(segto, data, type, size, segment, wrt);
309 }
310
311 static bool jmp_match(int32_t segment, int64_t offset, int bits,
312 insn * ins, const uint8_t *code)
313 {
314 int64_t isize;
315 uint8_t c = code[0];
316
317 if ((c != 0370 && c != 0371) || (ins->oprs[0].type & STRICT))
318 return false;
319 if (!optimizing)
320 return false;
321 if (optimizing < 0 && c == 0371)
322 return false;
323
324 isize = calcsize(segment, offset, bits, ins, code);
325
326 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
327 /* Be optimistic in pass 1 */
328 return true;
329
330 if (ins->oprs[0].segment != segment)
331 return false;
332
333 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
334 return (isize >= -128 && isize <= 127); /* is it byte size? */
335 }
336
337 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
338 insn * instruction, struct ofmt *output, efunc error,
339 ListGen * listgen)
340 {
341 const struct itemplate *temp;
342 int j;
343 enum match_result m;
344 int64_t insn_end;
345 int32_t itimes;
346 int64_t start = offset;
347 int64_t wsize; /* size for DB etc. */
348
349 errfunc = error; /* to pass to other functions */
350 cpu = cp;
351 outfmt = output; /* likewise */
352 list = listgen; /* and again */
353
354 wsize = idata_bytes(instruction->opcode);
355 if (wsize == -1)
356 return 0;
357
358 if (wsize) {
359 extop *e;
360 int32_t t = instruction->times;
361 if (t < 0)
362 errfunc(ERR_PANIC,
363 "instruction->times < 0 (%ld) in assemble()", t);
364
365 while (t--) { /* repeat TIMES times */
366 list_for_each(e, instruction->eops) {
367 if (e->type == EOT_DB_NUMBER) {
368 if (wsize > 8) {
369 errfunc(ERR_NONFATAL,
370 "integer supplied to a DT, DO or DY"
371 " instruction");
372 } else {
373 out(offset, segment, &e->offset,
374 OUT_ADDRESS, wsize, e->segment, e->wrt);
375 offset += wsize;
376 }
377 } else if (e->type == EOT_DB_STRING ||
378 e->type == EOT_DB_STRING_FREE) {
379 int align;
380
381 out(offset, segment, e->stringval,
382 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
383 align = e->stringlen % wsize;
384
385 if (align) {
386 align = wsize - align;
387 out(offset, segment, zero_buffer,
388 OUT_RAWDATA, align, NO_SEG, NO_SEG);
389 }
390 offset += e->stringlen + align;
391 }
392 }
393 if (t > 0 && t == instruction->times - 1) {
394 /*
395 * Dummy call to list->output to give the offset to the
396 * listing module.
397 */
398 list->output(offset, NULL, OUT_RAWDATA, 0);
399 list->uplevel(LIST_TIMES);
400 }
401 }
402 if (instruction->times > 1)
403 list->downlevel(LIST_TIMES);
404 return offset - start;
405 }
406
407 if (instruction->opcode == I_INCBIN) {
408 const char *fname = instruction->eops->stringval;
409 FILE *fp;
410
411 fp = fopen(fname, "rb");
412 if (!fp) {
413 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
414 fname);
415 } else if (fseek(fp, 0L, SEEK_END) < 0) {
416 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
417 fname);
418 } else {
419 static char buf[4096];
420 size_t t = instruction->times;
421 size_t base = 0;
422 size_t len;
423
424 len = ftell(fp);
425 if (instruction->eops->next) {
426 base = instruction->eops->next->offset;
427 len -= base;
428 if (instruction->eops->next->next &&
429 len > (size_t)instruction->eops->next->next->offset)
430 len = (size_t)instruction->eops->next->next->offset;
431 }
432 /*
433 * Dummy call to list->output to give the offset to the
434 * listing module.
435 */
436 list->output(offset, NULL, OUT_RAWDATA, 0);
437 list->uplevel(LIST_INCBIN);
438 while (t--) {
439 size_t l;
440
441 fseek(fp, base, SEEK_SET);
442 l = len;
443 while (l > 0) {
444 int32_t m;
445 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
446 if (!m) {
447 /*
448 * This shouldn't happen unless the file
449 * actually changes while we are reading
450 * it.
451 */
452 error(ERR_NONFATAL,
453 "`incbin': unexpected EOF while"
454 " reading file `%s'", fname);
455 t = 0; /* Try to exit cleanly */
456 break;
457 }
458 out(offset, segment, buf, OUT_RAWDATA, m,
459 NO_SEG, NO_SEG);
460 l -= m;
461 }
462 }
463 list->downlevel(LIST_INCBIN);
464 if (instruction->times > 1) {
465 /*
466 * Dummy call to list->output to give the offset to the
467 * listing module.
468 */
469 list->output(offset, NULL, OUT_RAWDATA, 0);
470 list->uplevel(LIST_TIMES);
471 list->downlevel(LIST_TIMES);
472 }
473 fclose(fp);
474 return instruction->times * len;
475 }
476 return 0; /* if we're here, there's an error */
477 }
478
479 /* Check to see if we need an address-size prefix */
480 add_asp(instruction, bits);
481
482 m = find_match(&temp, instruction, segment, offset, bits);
483
484 if (m == MOK_GOOD) {
485 /* Matches! */
486 int64_t insn_size = calcsize(segment, offset, bits,
487 instruction, temp->code);
488 itimes = instruction->times;
489 if (insn_size < 0) /* shouldn't be, on pass two */
490 error(ERR_PANIC, "errors made it through from pass one");
491 else
492 while (itimes--) {
493 for (j = 0; j < MAXPREFIX; j++) {
494 uint8_t c = 0;
495 switch (instruction->prefixes[j]) {
496 case P_WAIT:
497 c = 0x9B;
498 break;
499 case P_LOCK:
500 c = 0xF0;
501 break;
502 case P_REPNE:
503 case P_REPNZ:
504 c = 0xF2;
505 break;
506 case P_REPE:
507 case P_REPZ:
508 case P_REP:
509 c = 0xF3;
510 break;
511 case R_CS:
512 if (bits == 64) {
513 error(ERR_WARNING | ERR_PASS2,
514 "cs segment base generated, but will be ignored in 64-bit mode");
515 }
516 c = 0x2E;
517 break;
518 case R_DS:
519 if (bits == 64) {
520 error(ERR_WARNING | ERR_PASS2,
521 "ds segment base generated, but will be ignored in 64-bit mode");
522 }
523 c = 0x3E;
524 break;
525 case R_ES:
526 if (bits == 64) {
527 error(ERR_WARNING | ERR_PASS2,
528 "es segment base generated, but will be ignored in 64-bit mode");
529 }
530 c = 0x26;
531 break;
532 case R_FS:
533 c = 0x64;
534 break;
535 case R_GS:
536 c = 0x65;
537 break;
538 case R_SS:
539 if (bits == 64) {
540 error(ERR_WARNING | ERR_PASS2,
541 "ss segment base generated, but will be ignored in 64-bit mode");
542 }
543 c = 0x36;
544 break;
545 case R_SEGR6:
546 case R_SEGR7:
547 error(ERR_NONFATAL,
548 "segr6 and segr7 cannot be used as prefixes");
549 break;
550 case P_A16:
551 if (bits == 64) {
552 error(ERR_NONFATAL,
553 "16-bit addressing is not supported "
554 "in 64-bit mode");
555 } else if (bits != 16)
556 c = 0x67;
557 break;
558 case P_A32:
559 if (bits != 32)
560 c = 0x67;
561 break;
562 case P_A64:
563 if (bits != 64) {
564 error(ERR_NONFATAL,
565 "64-bit addressing is only supported "
566 "in 64-bit mode");
567 }
568 break;
569 case P_ASP:
570 c = 0x67;
571 break;
572 case P_O16:
573 if (bits != 16)
574 c = 0x66;
575 break;
576 case P_O32:
577 if (bits == 16)
578 c = 0x66;
579 break;
580 case P_O64:
581 /* REX.W */
582 break;
583 case P_OSP:
584 c = 0x66;
585 break;
586 case P_none:
587 break;
588 default:
589 error(ERR_PANIC, "invalid instruction prefix");
590 }
591 if (c != 0) {
592 out(offset, segment, &c, OUT_RAWDATA, 1,
593 NO_SEG, NO_SEG);
594 offset++;
595 }
596 }
597 insn_end = offset + insn_size;
598 gencode(segment, offset, bits, instruction,
599 temp, insn_end);
600 offset += insn_size;
601 if (itimes > 0 && itimes == instruction->times - 1) {
602 /*
603 * Dummy call to list->output to give the offset to the
604 * listing module.
605 */
606 list->output(offset, NULL, OUT_RAWDATA, 0);
607 list->uplevel(LIST_TIMES);
608 }
609 }
610 if (instruction->times > 1)
611 list->downlevel(LIST_TIMES);
612 return offset - start;
613 } else {
614 /* No match */
615 switch (m) {
616 case MERR_OPSIZEMISSING:
617 error(ERR_NONFATAL, "operation size not specified");
618 break;
619 case MERR_OPSIZEMISMATCH:
620 error(ERR_NONFATAL, "mismatch in operand sizes");
621 break;
622 case MERR_BADCPU:
623 error(ERR_NONFATAL, "no instruction for this cpu level");
624 break;
625 case MERR_BADMODE:
626 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
627 bits);
628 break;
629 default:
630 error(ERR_NONFATAL,
631 "invalid combination of opcode and operands");
632 break;
633 }
634 }
635 return 0;
636 }
637
638 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
639 insn * instruction, efunc error)
640 {
641 const struct itemplate *temp;
642 enum match_result m;
643
644 errfunc = error; /* to pass to other functions */
645 cpu = cp;
646
647 if (instruction->opcode == I_none)
648 return 0;
649
650 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
651 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
652 instruction->opcode == I_DT || instruction->opcode == I_DO ||
653 instruction->opcode == I_DY) {
654 extop *e;
655 int32_t isize, osize, wsize;
656
657 isize = 0;
658 wsize = idata_bytes(instruction->opcode);
659
660 list_for_each(e, instruction->eops) {
661 int32_t align;
662
663 osize = 0;
664 if (e->type == EOT_DB_NUMBER) {
665 osize = 1;
666 warn_overflow_const(e->offset, wsize);
667 } else if (e->type == EOT_DB_STRING ||
668 e->type == EOT_DB_STRING_FREE)
669 osize = e->stringlen;
670
671 align = (-osize) % wsize;
672 if (align < 0)
673 align += wsize;
674 isize += osize + align;
675 }
676 return isize * instruction->times;
677 }
678
679 if (instruction->opcode == I_INCBIN) {
680 const char *fname = instruction->eops->stringval;
681 FILE *fp;
682 int64_t val = 0;
683 size_t len;
684
685 fp = fopen(fname, "rb");
686 if (!fp)
687 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
688 fname);
689 else if (fseek(fp, 0L, SEEK_END) < 0)
690 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
691 fname);
692 else {
693 len = ftell(fp);
694 if (instruction->eops->next) {
695 len -= instruction->eops->next->offset;
696 if (instruction->eops->next->next &&
697 len > (size_t)instruction->eops->next->next->offset) {
698 len = (size_t)instruction->eops->next->next->offset;
699 }
700 }
701 val = instruction->times * len;
702 }
703 if (fp)
704 fclose(fp);
705 return val;
706 }
707
708 /* Check to see if we need an address-size prefix */
709 add_asp(instruction, bits);
710
711 m = find_match(&temp, instruction, segment, offset, bits);
712 if (m == MOK_GOOD) {
713 /* we've matched an instruction. */
714 int64_t isize;
715 const uint8_t *codes = temp->code;
716 int j;
717
718 isize = calcsize(segment, offset, bits, instruction, codes);
719 if (isize < 0)
720 return -1;
721 for (j = 0; j < MAXPREFIX; j++) {
722 switch (instruction->prefixes[j]) {
723 case P_A16:
724 if (bits != 16)
725 isize++;
726 break;
727 case P_A32:
728 if (bits != 32)
729 isize++;
730 break;
731 case P_O16:
732 if (bits != 16)
733 isize++;
734 break;
735 case P_O32:
736 if (bits == 16)
737 isize++;
738 break;
739 case P_A64:
740 case P_O64:
741 case P_none:
742 break;
743 default:
744 isize++;
745 break;
746 }
747 }
748 return isize * instruction->times;
749 } else {
750 return -1; /* didn't match any instruction */
751 }
752 }
753
754 static bool possible_sbyte(operand *o)
755 {
756 return o->wrt == NO_SEG && o->segment == NO_SEG &&
757 !(o->opflags & OPFLAG_UNKNOWN) &&
758 optimizing >= 0 && !(o->type & STRICT);
759 }
760
761 /* check that opn[op] is a signed byte of size 16 or 32 */
762 static bool is_sbyte16(operand *o)
763 {
764 int16_t v;
765
766 if (!possible_sbyte(o))
767 return false;
768
769 v = o->offset;
770 return v >= -128 && v <= 127;
771 }
772
773 static bool is_sbyte32(operand *o)
774 {
775 int32_t v;
776
777 if (!possible_sbyte(o))
778 return false;
779
780 v = o->offset;
781 return v >= -128 && v <= 127;
782 }
783
784 /* Common construct */
785 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
786
787 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
788 insn * ins, const uint8_t *codes)
789 {
790 int64_t length = 0;
791 uint8_t c;
792 int rex_mask = ~0;
793 int op1, op2;
794 struct operand *opx;
795 uint8_t opex = 0;
796 enum ea_type eat;
797
798 ins->rex = 0; /* Ensure REX is reset */
799 eat = EA_SCALAR; /* Expect a scalar EA */
800
801 if (ins->prefixes[PPS_OSIZE] == P_O64)
802 ins->rex |= REX_W;
803
804 (void)segment; /* Don't warn that this parameter is unused */
805 (void)offset; /* Don't warn that this parameter is unused */
806
807 while (*codes) {
808 c = *codes++;
809 op1 = (c & 3) + ((opex & 1) << 2);
810 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
811 opx = &ins->oprs[op1];
812 opex = 0; /* For the next iteration */
813
814 switch (c) {
815 case 01:
816 case 02:
817 case 03:
818 case 04:
819 codes += c, length += c;
820 break;
821
822 case 05:
823 case 06:
824 case 07:
825 opex = c;
826 break;
827
828 case4(010):
829 ins->rex |=
830 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
831 codes++, length++;
832 break;
833
834 case4(014):
835 case4(020):
836 case4(024):
837 length++;
838 break;
839
840 case4(030):
841 length += 2;
842 break;
843
844 case4(034):
845 if (opx->type & (BITS16 | BITS32 | BITS64))
846 length += (opx->type & BITS16) ? 2 : 4;
847 else
848 length += (bits == 16) ? 2 : 4;
849 break;
850
851 case4(040):
852 length += 4;
853 break;
854
855 case4(044):
856 length += ins->addr_size >> 3;
857 break;
858
859 case4(050):
860 length++;
861 break;
862
863 case4(054):
864 length += 8; /* MOV reg64/imm */
865 break;
866
867 case4(060):
868 length += 2;
869 break;
870
871 case4(064):
872 if (opx->type & (BITS16 | BITS32 | BITS64))
873 length += (opx->type & BITS16) ? 2 : 4;
874 else
875 length += (bits == 16) ? 2 : 4;
876 break;
877
878 case4(070):
879 length += 4;
880 break;
881
882 case4(074):
883 length += 2;
884 break;
885
886 case4(0140):
887 length += is_sbyte16(opx) ? 1 : 2;
888 break;
889
890 case4(0144):
891 codes++;
892 length++;
893 break;
894
895 case4(0150):
896 length += is_sbyte32(opx) ? 1 : 4;
897 break;
898
899 case4(0154):
900 codes++;
901 length++;
902 break;
903
904 case 0172:
905 case 0173:
906 codes++;
907 length++;
908 break;
909
910 case4(0174):
911 length++;
912 break;
913
914 case4(0250):
915 length += is_sbyte32(opx) ? 1 : 4;
916 break;
917
918 case4(0254):
919 length += 4;
920 break;
921
922 case4(0260):
923 ins->rex |= REX_V;
924 ins->vexreg = regval(opx);
925 ins->vex_cm = *codes++;
926 ins->vex_wlp = *codes++;
927 break;
928
929 case 0270:
930 ins->rex |= REX_V;
931 ins->vexreg = 0;
932 ins->vex_cm = *codes++;
933 ins->vex_wlp = *codes++;
934 break;
935
936 case4(0274):
937 length++;
938 break;
939
940 case4(0300):
941 break;
942
943 case 0310:
944 if (bits == 64)
945 return -1;
946 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
947 break;
948
949 case 0311:
950 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
951 break;
952
953 case 0312:
954 break;
955
956 case 0313:
957 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
958 has_prefix(ins, PPS_ASIZE, P_A32))
959 return -1;
960 break;
961
962 case4(0314):
963 break;
964
965 case 0320:
966 {
967 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
968 if (pfx == P_O16)
969 break;
970 if (pfx != P_none)
971 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
972 else
973 ins->prefixes[PPS_OSIZE] = P_O16;
974 break;
975 }
976
977 case 0321:
978 {
979 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
980 if (pfx == P_O32)
981 break;
982 if (pfx != P_none)
983 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
984 else
985 ins->prefixes[PPS_OSIZE] = P_O32;
986 break;
987 }
988
989 case 0322:
990 break;
991
992 case 0323:
993 rex_mask &= ~REX_W;
994 break;
995
996 case 0324:
997 ins->rex |= REX_W;
998 break;
999
1000 case 0325:
1001 ins->rex |= REX_NH;
1002 break;
1003
1004 case 0330:
1005 codes++, length++;
1006 break;
1007
1008 case 0331:
1009 break;
1010
1011 case 0332:
1012 case 0333:
1013 length++;
1014 break;
1015
1016 case 0334:
1017 ins->rex |= REX_L;
1018 break;
1019
1020 case 0335:
1021 break;
1022
1023 case 0336:
1024 if (!ins->prefixes[PPS_LREP])
1025 ins->prefixes[PPS_LREP] = P_REP;
1026 break;
1027
1028 case 0337:
1029 if (!ins->prefixes[PPS_LREP])
1030 ins->prefixes[PPS_LREP] = P_REPNE;
1031 break;
1032
1033 case 0340:
1034 if (ins->oprs[0].segment != NO_SEG)
1035 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1036 " quantity of BSS space");
1037 else
1038 length += ins->oprs[0].offset;
1039 break;
1040
1041 case 0341:
1042 if (!ins->prefixes[PPS_WAIT])
1043 ins->prefixes[PPS_WAIT] = P_WAIT;
1044 break;
1045
1046 case4(0344):
1047 length++;
1048 break;
1049
1050 case 0360:
1051 break;
1052
1053 case 0361:
1054 case 0362:
1055 case 0363:
1056 length++;
1057 break;
1058
1059 case 0364:
1060 case 0365:
1061 break;
1062
1063 case 0366:
1064 case 0367:
1065 length++;
1066 break;
1067
1068 case 0370:
1069 case 0371:
1070 case 0372:
1071 break;
1072
1073 case 0373:
1074 length++;
1075 break;
1076
1077 case 0374:
1078 eat = EA_XMMVSIB;
1079 break;
1080
1081 case 0375:
1082 eat = EA_YMMVSIB;
1083 break;
1084
1085 case4(0100):
1086 case4(0110):
1087 case4(0120):
1088 case4(0130):
1089 case4(0200):
1090 case4(0204):
1091 case4(0210):
1092 case4(0214):
1093 case4(0220):
1094 case4(0224):
1095 case4(0230):
1096 case4(0234):
1097 {
1098 ea ea_data;
1099 int rfield;
1100 opflags_t rflags;
1101 struct operand *opy = &ins->oprs[op2];
1102
1103 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1104
1105 if (c <= 0177) {
1106 /* pick rfield from operand b (opx) */
1107 rflags = regflag(opx);
1108 rfield = nasm_regvals[opx->basereg];
1109 } else {
1110 rflags = 0;
1111 rfield = c & 7;
1112 }
1113 if (process_ea(opy, &ea_data, bits,ins->addr_size,
1114 rfield, rflags) != eat) {
1115 errfunc(ERR_NONFATAL, "invalid effective address");
1116 return -1;
1117 } else {
1118 ins->rex |= ea_data.rex;
1119 length += ea_data.size;
1120 }
1121 }
1122 break;
1123
1124 default:
1125 errfunc(ERR_PANIC, "internal instruction table corrupt"
1126 ": instruction code \\%o (0x%02X) given", c, c);
1127 break;
1128 }
1129 }
1130
1131 ins->rex &= rex_mask;
1132
1133 if (ins->rex & REX_NH) {
1134 if (ins->rex & REX_H) {
1135 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1136 return -1;
1137 }
1138 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1139 }
1140
1141 if (ins->rex & REX_V) {
1142 int bad32 = REX_R|REX_W|REX_X|REX_B;
1143
1144 if (ins->rex & REX_H) {
1145 errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
1146 return -1;
1147 }
1148 switch (ins->vex_wlp & 060) {
1149 case 000:
1150 case 040:
1151 ins->rex &= ~REX_W;
1152 break;
1153 case 020:
1154 ins->rex |= REX_W;
1155 bad32 &= ~REX_W;
1156 break;
1157 case 060:
1158 /* Follow REX_W */
1159 break;
1160 }
1161
1162 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1163 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1164 return -1;
1165 }
1166 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1167 length += 3;
1168 else
1169 length += 2;
1170 } else if (ins->rex & REX_REAL) {
1171 if (ins->rex & REX_H) {
1172 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1173 return -1;
1174 } else if (bits == 64) {
1175 length++;
1176 } else if ((ins->rex & REX_L) &&
1177 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1178 cpu >= IF_X86_64) {
1179 /* LOCK-as-REX.R */
1180 assert_no_prefix(ins, PPS_LREP);
1181 length++;
1182 } else {
1183 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1184 return -1;
1185 }
1186 }
1187
1188 return length;
1189 }
1190
1191 #define EMIT_REX() \
1192 if (!(ins->rex & REX_V) && (ins->rex & REX_REAL) && (bits == 64)) { \
1193 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1194 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1195 ins->rex = 0; \
1196 offset += 1; \
1197 }
1198
1199 static void gencode(int32_t segment, int64_t offset, int bits,
1200 insn * ins, const struct itemplate *temp,
1201 int64_t insn_end)
1202 {
1203 static const char condval[] = { /* conditional opcodes */
1204 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1205 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1206 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1207 };
1208 uint8_t c;
1209 uint8_t bytes[4];
1210 int64_t size;
1211 int64_t data;
1212 int op1, op2;
1213 struct operand *opx;
1214 const uint8_t *codes = temp->code;
1215 uint8_t opex = 0;
1216 enum ea_type eat = EA_SCALAR;
1217
1218 while (*codes) {
1219 c = *codes++;
1220 op1 = (c & 3) + ((opex & 1) << 2);
1221 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1222 opx = &ins->oprs[op1];
1223 opex = 0; /* For the next iteration */
1224
1225 switch (c) {
1226 case 01:
1227 case 02:
1228 case 03:
1229 case 04:
1230 EMIT_REX();
1231 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1232 codes += c;
1233 offset += c;
1234 break;
1235
1236 case 05:
1237 case 06:
1238 case 07:
1239 opex = c;
1240 break;
1241
1242 case4(010):
1243 EMIT_REX();
1244 bytes[0] = *codes++ + (regval(opx) & 7);
1245 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1246 offset += 1;
1247 break;
1248
1249 case4(014):
1250 /*
1251 * The test for BITS8 and SBYTE here is intended to avoid
1252 * warning on optimizer actions due to SBYTE, while still
1253 * warn on explicit BYTE directives. Also warn, obviously,
1254 * if the optimizer isn't enabled.
1255 */
1256 if (((opx->type & BITS8) ||
1257 !(opx->type & temp->opd[op1] & BYTENESS)) &&
1258 (opx->offset < -128 || opx->offset > 127)) {
1259 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1260 "signed byte value exceeds bounds");
1261 }
1262 if (opx->segment != NO_SEG) {
1263 data = opx->offset;
1264 out(offset, segment, &data, OUT_ADDRESS, 1,
1265 opx->segment, opx->wrt);
1266 } else {
1267 bytes[0] = opx->offset;
1268 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1269 NO_SEG);
1270 }
1271 offset += 1;
1272 break;
1273
1274 case4(020):
1275 if (opx->offset < -256 || opx->offset > 255) {
1276 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1277 "byte value exceeds bounds");
1278 }
1279 if (opx->segment != NO_SEG) {
1280 data = opx->offset;
1281 out(offset, segment, &data, OUT_ADDRESS, 1,
1282 opx->segment, opx->wrt);
1283 } else {
1284 bytes[0] = opx->offset;
1285 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1286 NO_SEG);
1287 }
1288 offset += 1;
1289 break;
1290
1291 case4(024):
1292 if (opx->offset < 0 || opx->offset > 255)
1293 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1294 "unsigned byte value exceeds bounds");
1295 if (opx->segment != NO_SEG) {
1296 data = opx->offset;
1297 out(offset, segment, &data, OUT_ADDRESS, 1,
1298 opx->segment, opx->wrt);
1299 } else {
1300 bytes[0] = opx->offset;
1301 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1302 NO_SEG);
1303 }
1304 offset += 1;
1305 break;
1306
1307 case4(030):
1308 warn_overflow_opd(opx, 2);
1309 data = opx->offset;
1310 out(offset, segment, &data, OUT_ADDRESS, 2,
1311 opx->segment, opx->wrt);
1312 offset += 2;
1313 break;
1314
1315 case4(034):
1316 if (opx->type & (BITS16 | BITS32))
1317 size = (opx->type & BITS16) ? 2 : 4;
1318 else
1319 size = (bits == 16) ? 2 : 4;
1320 warn_overflow_opd(opx, size);
1321 data = opx->offset;
1322 out(offset, segment, &data, OUT_ADDRESS, size,
1323 opx->segment, opx->wrt);
1324 offset += size;
1325 break;
1326
1327 case4(040):
1328 warn_overflow_opd(opx, 4);
1329 data = opx->offset;
1330 out(offset, segment, &data, OUT_ADDRESS, 4,
1331 opx->segment, opx->wrt);
1332 offset += 4;
1333 break;
1334
1335 case4(044):
1336 data = opx->offset;
1337 size = ins->addr_size >> 3;
1338 warn_overflow_opd(opx, size);
1339 out(offset, segment, &data, OUT_ADDRESS, size,
1340 opx->segment, opx->wrt);
1341 offset += size;
1342 break;
1343
1344 case4(050):
1345 if (opx->segment != segment) {
1346 data = opx->offset;
1347 out(offset, segment, &data,
1348 OUT_REL1ADR, insn_end - offset,
1349 opx->segment, opx->wrt);
1350 } else {
1351 data = opx->offset - insn_end;
1352 if (data > 127 || data < -128)
1353 errfunc(ERR_NONFATAL, "short jump is out of range");
1354 out(offset, segment, &data,
1355 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1356 }
1357 offset += 1;
1358 break;
1359
1360 case4(054):
1361 data = (int64_t)opx->offset;
1362 out(offset, segment, &data, OUT_ADDRESS, 8,
1363 opx->segment, opx->wrt);
1364 offset += 8;
1365 break;
1366
1367 case4(060):
1368 if (opx->segment != segment) {
1369 data = opx->offset;
1370 out(offset, segment, &data,
1371 OUT_REL2ADR, insn_end - offset,
1372 opx->segment, opx->wrt);
1373 } else {
1374 data = opx->offset - insn_end;
1375 out(offset, segment, &data,
1376 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1377 }
1378 offset += 2;
1379 break;
1380
1381 case4(064):
1382 if (opx->type & (BITS16 | BITS32 | BITS64))
1383 size = (opx->type & BITS16) ? 2 : 4;
1384 else
1385 size = (bits == 16) ? 2 : 4;
1386 if (opx->segment != segment) {
1387 data = opx->offset;
1388 out(offset, segment, &data,
1389 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1390 insn_end - offset, opx->segment, opx->wrt);
1391 } else {
1392 data = opx->offset - insn_end;
1393 out(offset, segment, &data,
1394 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1395 }
1396 offset += size;
1397 break;
1398
1399 case4(070):
1400 if (opx->segment != segment) {
1401 data = opx->offset;
1402 out(offset, segment, &data,
1403 OUT_REL4ADR, insn_end - offset,
1404 opx->segment, opx->wrt);
1405 } else {
1406 data = opx->offset - insn_end;
1407 out(offset, segment, &data,
1408 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1409 }
1410 offset += 4;
1411 break;
1412
1413 case4(074):
1414 if (opx->segment == NO_SEG)
1415 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1416 " relocatable");
1417 data = 0;
1418 out(offset, segment, &data, OUT_ADDRESS, 2,
1419 outfmt->segbase(1 + opx->segment),
1420 opx->wrt);
1421 offset += 2;
1422 break;
1423
1424 case4(0140):
1425 data = opx->offset;
1426 warn_overflow_opd(opx, 2);
1427 if (is_sbyte16(opx)) {
1428 bytes[0] = data;
1429 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1430 NO_SEG);
1431 offset++;
1432 } else {
1433 out(offset, segment, &data, OUT_ADDRESS, 2,
1434 opx->segment, opx->wrt);
1435 offset += 2;
1436 }
1437 break;
1438
1439 case4(0144):
1440 EMIT_REX();
1441 bytes[0] = *codes++;
1442 if (is_sbyte16(opx))
1443 bytes[0] |= 2; /* s-bit */
1444 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1445 offset++;
1446 break;
1447
1448 case4(0150):
1449 data = opx->offset;
1450 warn_overflow_opd(opx, 4);
1451 if (is_sbyte32(opx)) {
1452 bytes[0] = data;
1453 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1454 NO_SEG);
1455 offset++;
1456 } else {
1457 out(offset, segment, &data, OUT_ADDRESS, 4,
1458 opx->segment, opx->wrt);
1459 offset += 4;
1460 }
1461 break;
1462
1463 case4(0154):
1464 EMIT_REX();
1465 bytes[0] = *codes++;
1466 if (is_sbyte32(opx))
1467 bytes[0] |= 2; /* s-bit */
1468 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1469 offset++;
1470 break;
1471
1472 case 0172:
1473 c = *codes++;
1474 opx = &ins->oprs[c >> 3];
1475 bytes[0] = nasm_regvals[opx->basereg] << 4;
1476 opx = &ins->oprs[c & 7];
1477 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1478 errfunc(ERR_NONFATAL,
1479 "non-absolute expression not permitted as argument %d",
1480 c & 7);
1481 } else {
1482 if (opx->offset & ~15) {
1483 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1484 "four-bit argument exceeds bounds");
1485 }
1486 bytes[0] |= opx->offset & 15;
1487 }
1488 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1489 offset++;
1490 break;
1491
1492 case 0173:
1493 c = *codes++;
1494 opx = &ins->oprs[c >> 4];
1495 bytes[0] = nasm_regvals[opx->basereg] << 4;
1496 bytes[0] |= c & 15;
1497 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1498 offset++;
1499 break;
1500
1501 case4(0174):
1502 bytes[0] = nasm_regvals[opx->basereg] << 4;
1503 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1504 offset++;
1505 break;
1506
1507 case4(0250):
1508 data = opx->offset;
1509 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1510 (int32_t)data != (int64_t)data) {
1511 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1512 "signed dword immediate exceeds bounds");
1513 }
1514 if (is_sbyte32(opx)) {
1515 bytes[0] = data;
1516 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1517 NO_SEG);
1518 offset++;
1519 } else {
1520 out(offset, segment, &data, OUT_ADDRESS, 4,
1521 opx->segment, opx->wrt);
1522 offset += 4;
1523 }
1524 break;
1525
1526 case4(0254):
1527 data = opx->offset;
1528 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1529 (int32_t)data != (int64_t)data) {
1530 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1531 "signed dword immediate exceeds bounds");
1532 }
1533 out(offset, segment, &data, OUT_ADDRESS, 4,
1534 opx->segment, opx->wrt);
1535 offset += 4;
1536 break;
1537
1538 case4(0260):
1539 case 0270:
1540 codes += 2;
1541 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1542 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1543 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1544 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1545 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1546 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1547 offset += 3;
1548 } else {
1549 bytes[0] = 0xc5;
1550 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1551 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1552 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1553 offset += 2;
1554 }
1555 break;
1556
1557 case4(0274):
1558 {
1559 uint64_t uv, um;
1560 int s;
1561
1562 if (ins->rex & REX_W)
1563 s = 64;
1564 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1565 s = 16;
1566 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1567 s = 32;
1568 else
1569 s = bits;
1570
1571 um = (uint64_t)2 << (s-1);
1572 uv = opx->offset;
1573
1574 if (uv > 127 && uv < (uint64_t)-128 &&
1575 (uv < um-128 || uv > um-1)) {
1576 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1577 "signed byte value exceeds bounds");
1578 }
1579 if (opx->segment != NO_SEG) {
1580 data = uv;
1581 out(offset, segment, &data, OUT_ADDRESS, 1,
1582 opx->segment, opx->wrt);
1583 } else {
1584 bytes[0] = uv;
1585 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1586 NO_SEG);
1587 }
1588 offset += 1;
1589 break;
1590 }
1591
1592 case4(0300):
1593 break;
1594
1595 case 0310:
1596 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1597 *bytes = 0x67;
1598 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1599 offset += 1;
1600 } else
1601 offset += 0;
1602 break;
1603
1604 case 0311:
1605 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1606 *bytes = 0x67;
1607 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1608 offset += 1;
1609 } else
1610 offset += 0;
1611 break;
1612
1613 case 0312:
1614 break;
1615
1616 case 0313:
1617 ins->rex = 0;
1618 break;
1619
1620 case4(0314):
1621 break;
1622
1623 case 0320:
1624 case 0321:
1625 break;
1626
1627 case 0322:
1628 case 0323:
1629 break;
1630
1631 case 0324:
1632 ins->rex |= REX_W;
1633 break;
1634
1635 case 0325:
1636 break;
1637
1638 case 0330:
1639 *bytes = *codes++ ^ condval[ins->condition];
1640 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1641 offset += 1;
1642 break;
1643
1644 case 0331:
1645 break;
1646
1647 case 0332:
1648 case 0333:
1649 *bytes = c - 0332 + 0xF2;
1650 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1651 offset += 1;
1652 break;
1653
1654 case 0334:
1655 if (ins->rex & REX_R) {
1656 *bytes = 0xF0;
1657 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1658 offset += 1;
1659 }
1660 ins->rex &= ~(REX_L|REX_R);
1661 break;
1662
1663 case 0335:
1664 break;
1665
1666 case 0336:
1667 case 0337:
1668 break;
1669
1670 case 0340:
1671 if (ins->oprs[0].segment != NO_SEG)
1672 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1673 else {
1674 int64_t size = ins->oprs[0].offset;
1675 if (size > 0)
1676 out(offset, segment, NULL,
1677 OUT_RESERVE, size, NO_SEG, NO_SEG);
1678 offset += size;
1679 }
1680 break;
1681
1682 case 0341:
1683 break;
1684
1685 case 0344:
1686 case 0345:
1687 bytes[0] = c & 1;
1688 switch (ins->oprs[0].basereg) {
1689 case R_CS:
1690 bytes[0] += 0x0E;
1691 break;
1692 case R_DS:
1693 bytes[0] += 0x1E;
1694 break;
1695 case R_ES:
1696 bytes[0] += 0x06;
1697 break;
1698 case R_SS:
1699 bytes[0] += 0x16;
1700 break;
1701 default:
1702 errfunc(ERR_PANIC,
1703 "bizarre 8086 segment register received");
1704 }
1705 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1706 offset++;
1707 break;
1708
1709 case 0346:
1710 case 0347:
1711 bytes[0] = c & 1;
1712 switch (ins->oprs[0].basereg) {
1713 case R_FS:
1714 bytes[0] += 0xA0;
1715 break;
1716 case R_GS:
1717 bytes[0] += 0xA8;
1718 break;
1719 default:
1720 errfunc(ERR_PANIC,
1721 "bizarre 386 segment register received");
1722 }
1723 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1724 offset++;
1725 break;
1726
1727 case 0360:
1728 break;
1729
1730 case 0361:
1731 bytes[0] = 0x66;
1732 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1733 offset += 1;
1734 break;
1735
1736 case 0362:
1737 case 0363:
1738 bytes[0] = c - 0362 + 0xf2;
1739 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1740 offset += 1;
1741 break;
1742
1743 case 0364:
1744 case 0365:
1745 break;
1746
1747 case 0366:
1748 case 0367:
1749 *bytes = c - 0366 + 0x66;
1750 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1751 offset += 1;
1752 break;
1753
1754 case 0370:
1755 case 0371:
1756 case 0372:
1757 break;
1758
1759 case 0373:
1760 *bytes = bits == 16 ? 3 : 5;
1761 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1762 offset += 1;
1763 break;
1764
1765 case 0374:
1766 eat = EA_XMMVSIB;
1767 break;
1768
1769 case 0375:
1770 eat = EA_YMMVSIB;
1771 break;
1772
1773 case4(0100):
1774 case4(0110):
1775 case4(0120):
1776 case4(0130):
1777 case4(0200):
1778 case4(0204):
1779 case4(0210):
1780 case4(0214):
1781 case4(0220):
1782 case4(0224):
1783 case4(0230):
1784 case4(0234):
1785 {
1786 ea ea_data;
1787 int rfield;
1788 opflags_t rflags;
1789 uint8_t *p;
1790 int32_t s;
1791 struct operand *opy = &ins->oprs[op2];
1792
1793 if (c <= 0177) {
1794 /* pick rfield from operand b (opx) */
1795 rflags = regflag(opx);
1796 rfield = nasm_regvals[opx->basereg];
1797 } else {
1798 /* rfield is constant */
1799 rflags = 0;
1800 rfield = c & 7;
1801 }
1802
1803 if (process_ea(opy, &ea_data, bits, ins->addr_size,
1804 rfield, rflags) != eat) {
1805 errfunc(ERR_NONFATAL, "invalid effective address");
1806 }
1807
1808
1809 p = bytes;
1810 *p++ = ea_data.modrm;
1811 if (ea_data.sib_present)
1812 *p++ = ea_data.sib;
1813
1814 s = p - bytes;
1815 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1816
1817 /*
1818 * Make sure the address gets the right offset in case
1819 * the line breaks in the .lst file (BR 1197827)
1820 */
1821 offset += s;
1822 s = 0;
1823
1824 switch (ea_data.bytes) {
1825 case 0:
1826 break;
1827 case 1:
1828 case 2:
1829 case 4:
1830 case 8:
1831 data = opy->offset;
1832 s += ea_data.bytes;
1833 if (ea_data.rip) {
1834 if (opy->segment == segment) {
1835 data -= insn_end;
1836 if (overflow_signed(data, ea_data.bytes))
1837 warn_overflow(ERR_PASS2, ea_data.bytes);
1838 out(offset, segment, &data, OUT_ADDRESS,
1839 ea_data.bytes, NO_SEG, NO_SEG);
1840 } else {
1841 /* overflow check in output/linker? */
1842 out(offset, segment, &data, OUT_REL4ADR,
1843 insn_end - offset, opy->segment, opy->wrt);
1844 }
1845 } else {
1846 if (overflow_general(opy->offset, ins->addr_size >> 3) ||
1847 signed_bits(opy->offset, ins->addr_size) !=
1848 signed_bits(opy->offset, ea_data.bytes * 8))
1849 warn_overflow(ERR_PASS2, ea_data.bytes);
1850
1851 out(offset, segment, &data, OUT_ADDRESS,
1852 ea_data.bytes, opy->segment, opy->wrt);
1853 }
1854 break;
1855 default:
1856 /* Impossible! */
1857 errfunc(ERR_PANIC,
1858 "Invalid amount of bytes (%d) for offset?!",
1859 ea_data.bytes);
1860 break;
1861 }
1862 offset += s;
1863 }
1864 break;
1865
1866 default:
1867 errfunc(ERR_PANIC, "internal instruction table corrupt"
1868 ": instruction code \\%o (0x%02X) given", c, c);
1869 break;
1870 }
1871 }
1872 }
1873
1874 static opflags_t regflag(const operand * o)
1875 {
1876 if (!is_register(o->basereg))
1877 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1878 return nasm_reg_flags[o->basereg];
1879 }
1880
1881 static int32_t regval(const operand * o)
1882 {
1883 if (!is_register(o->basereg))
1884 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1885 return nasm_regvals[o->basereg];
1886 }
1887
1888 static int op_rexflags(const operand * o, int mask)
1889 {
1890 opflags_t flags;
1891 int val;
1892
1893 if (!is_register(o->basereg))
1894 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1895
1896 flags = nasm_reg_flags[o->basereg];
1897 val = nasm_regvals[o->basereg];
1898
1899 return rexflags(val, flags, mask);
1900 }
1901
1902 static int rexflags(int val, opflags_t flags, int mask)
1903 {
1904 int rex = 0;
1905
1906 if (val >= 8)
1907 rex |= REX_B|REX_X|REX_R;
1908 if (flags & BITS64)
1909 rex |= REX_W;
1910 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1911 rex |= REX_H;
1912 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1913 rex |= REX_P;
1914
1915 return rex & mask;
1916 }
1917
1918 static enum match_result find_match(const struct itemplate **tempp,
1919 insn *instruction,
1920 int32_t segment, int64_t offset, int bits)
1921 {
1922 const struct itemplate *temp;
1923 enum match_result m, merr;
1924 opflags_t xsizeflags[MAX_OPERANDS];
1925 bool opsizemissing = false;
1926 int i;
1927
1928 for (i = 0; i < instruction->operands; i++)
1929 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1930
1931 merr = MERR_INVALOP;
1932
1933 for (temp = nasm_instructions[instruction->opcode];
1934 temp->opcode != I_none; temp++) {
1935 m = matches(temp, instruction, bits);
1936 if (m == MOK_JUMP) {
1937 if (jmp_match(segment, offset, bits, instruction, temp->code))
1938 m = MOK_GOOD;
1939 else
1940 m = MERR_INVALOP;
1941 } else if (m == MERR_OPSIZEMISSING &&
1942 (temp->flags & IF_SMASK) != IF_SX) {
1943 /*
1944 * Missing operand size and a candidate for fuzzy matching...
1945 */
1946 for (i = 0; i < temp->operands; i++) {
1947 if ((temp->opd[i] & SAME_AS) == 0)
1948 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
1949 }
1950 opsizemissing = true;
1951 }
1952 if (m > merr)
1953 merr = m;
1954 if (merr == MOK_GOOD)
1955 goto done;
1956 }
1957
1958 /* No match, but see if we can get a fuzzy operand size match... */
1959 if (!opsizemissing)
1960 goto done;
1961
1962 for (i = 0; i < instruction->operands; i++) {
1963 /*
1964 * We ignore extrinsic operand sizes on registers, so we should
1965 * never try to fuzzy-match on them. This also resolves the case
1966 * when we have e.g. "xmmrm128" in two different positions.
1967 */
1968 if (is_class(REGISTER, instruction->oprs[i].type))
1969 continue;
1970
1971 /* This tests if xsizeflags[i] has more than one bit set */
1972 if ((xsizeflags[i] & (xsizeflags[i]-1)))
1973 goto done; /* No luck */
1974
1975 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
1976 }
1977
1978 /* Try matching again... */
1979 for (temp = nasm_instructions[instruction->opcode];
1980 temp->opcode != I_none; temp++) {
1981 m = matches(temp, instruction, bits);
1982 if (m == MOK_JUMP) {
1983 if (jmp_match(segment, offset, bits, instruction, temp->code))
1984 m = MOK_GOOD;
1985 else
1986 m = MERR_INVALOP;
1987 }
1988 if (m > merr)
1989 merr = m;
1990 if (merr == MOK_GOOD)
1991 goto done;
1992 }
1993
1994 done:
1995 *tempp = temp;
1996 return merr;
1997 }
1998
1999 static enum match_result matches(const struct itemplate *itemp,
2000 insn *instruction, int bits)
2001 {
2002 int i, size[MAX_OPERANDS], asize, oprs;
2003 bool opsizemissing = false;
2004
2005 /*
2006 * Check the opcode
2007 */
2008 if (itemp->opcode != instruction->opcode)
2009 return MERR_INVALOP;
2010
2011 /*
2012 * Count the operands
2013 */
2014 if (itemp->operands != instruction->operands)
2015 return MERR_INVALOP;
2016
2017 /*
2018 * Is it legal?
2019 */
2020 if (!(optimizing > 0) && (itemp->flags & IF_OPT))
2021 return MERR_INVALOP;
2022
2023 /*
2024 * Check that no spurious colons or TOs are present
2025 */
2026 for (i = 0; i < itemp->operands; i++)
2027 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2028 return MERR_INVALOP;
2029
2030 /*
2031 * Process size flags
2032 */
2033 switch (itemp->flags & IF_SMASK) {
2034 case IF_SB:
2035 asize = BITS8;
2036 break;
2037 case IF_SW:
2038 asize = BITS16;
2039 break;
2040 case IF_SD:
2041 asize = BITS32;
2042 break;
2043 case IF_SQ:
2044 asize = BITS64;
2045 break;
2046 case IF_SO:
2047 asize = BITS128;
2048 break;
2049 case IF_SY:
2050 asize = BITS256;
2051 break;
2052 case IF_SZ:
2053 switch (bits) {
2054 case 16:
2055 asize = BITS16;
2056 break;
2057 case 32:
2058 asize = BITS32;
2059 break;
2060 case 64:
2061 asize = BITS64;
2062 break;
2063 default:
2064 asize = 0;
2065 break;
2066 }
2067 break;
2068 default:
2069 asize = 0;
2070 break;
2071 }
2072
2073 if (itemp->flags & IF_ARMASK) {
2074 /* S- flags only apply to a specific operand */
2075 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
2076 memset(size, 0, sizeof size);
2077 size[i] = asize;
2078 } else {
2079 /* S- flags apply to all operands */
2080 for (i = 0; i < MAX_OPERANDS; i++)
2081 size[i] = asize;
2082 }
2083
2084 /*
2085 * Check that the operand flags all match up,
2086 * it's a bit tricky so lets be verbose:
2087 *
2088 * 1) Find out the size of operand. If instruction
2089 * doesn't have one specified -- we're trying to
2090 * guess it either from template (IF_S* flag) or
2091 * from code bits.
2092 *
2093 * 2) If template operand (i) has SAME_AS flag [used for registers only]
2094 * (ie the same operand as was specified somewhere in template, and
2095 * this referred operand index is being achieved via ~SAME_AS)
2096 * we are to be sure that both registers (in template and instruction)
2097 * do exactly match.
2098 *
2099 * 3) If template operand do not match the instruction OR
2100 * template has an operand size specified AND this size differ
2101 * from which instruction has (perhaps we got it from code bits)
2102 * we are:
2103 * a) Check that only size of instruction and operand is differ
2104 * other characteristics do match
2105 * b) Perhaps it's a register specified in instruction so
2106 * for such a case we just mark that operand as "size
2107 * missing" and this will turn on fuzzy operand size
2108 * logic facility (handled by a caller)
2109 */
2110 for (i = 0; i < itemp->operands; i++) {
2111 opflags_t type = instruction->oprs[i].type;
2112 if (!(type & SIZE_MASK))
2113 type |= size[i];
2114
2115 if (itemp->opd[i] & SAME_AS) {
2116 int j = itemp->opd[i] & ~SAME_AS;
2117 if (type != instruction->oprs[j].type ||
2118 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
2119 return MERR_INVALOP;
2120 } else if (itemp->opd[i] & ~type ||
2121 ((itemp->opd[i] & SIZE_MASK) &&
2122 ((itemp->opd[i] ^ type) & SIZE_MASK))) {
2123 if ((itemp->opd[i] & ~type & ~SIZE_MASK) || (type & SIZE_MASK)) {
2124 return MERR_INVALOP;
2125 } else if (!is_class(REGISTER, type)) {
2126 /*
2127 * Note: we don't honor extrinsic operand sizes for registers,
2128 * so "missing operand size" for a register should be
2129 * considered a wildcard match rather than an error.
2130 */
2131 opsizemissing = true;
2132 }
2133 }
2134 }
2135
2136 if (opsizemissing)
2137 return MERR_OPSIZEMISSING;
2138
2139 /*
2140 * Check operand sizes
2141 */
2142 if (itemp->flags & (IF_SM | IF_SM2)) {
2143 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2144 for (i = 0; i < oprs; i++) {
2145 asize = itemp->opd[i] & SIZE_MASK;
2146 if (asize) {
2147 for (i = 0; i < oprs; i++)
2148 size[i] = asize;
2149 break;
2150 }
2151 }
2152 } else {
2153 oprs = itemp->operands;
2154 }
2155
2156 for (i = 0; i < itemp->operands; i++) {
2157 if (!(itemp->opd[i] & SIZE_MASK) &&
2158 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2159 return MERR_OPSIZEMISMATCH;
2160 }
2161
2162 /*
2163 * Check template is okay at the set cpu level
2164 */
2165 if (((itemp->flags & IF_PLEVEL) > cpu))
2166 return MERR_BADCPU;
2167
2168 /*
2169 * Verify the appropriate long mode flag.
2170 */
2171 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2172 return MERR_BADMODE;
2173
2174 /*
2175 * Check if special handling needed for Jumps
2176 */
2177 if ((itemp->code[0] & 0374) == 0370)
2178 return MOK_JUMP;
2179
2180 return MOK_GOOD;
2181 }
2182
2183 static enum ea_type process_ea(operand * input, ea * output, int bits,
2184 int addrbits, int rfield, opflags_t rflags)
2185 {
2186 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2187
2188 output->type = EA_SCALAR;
2189 output->rip = false;
2190
2191 /* REX flags for the rfield operand */
2192 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2193
2194 if (is_class(REGISTER, input->type)) { /* register direct */
2195 int i;
2196 opflags_t f;
2197
2198 if (!is_register(input->basereg))
2199 goto err;
2200 f = regflag(input);
2201 i = nasm_regvals[input->basereg];
2202
2203 if (REG_EA & ~f)
2204 goto err;
2205
2206 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2207
2208 output->sib_present = false; /* no SIB necessary */
2209 output->bytes = 0; /* no offset necessary either */
2210 output->modrm = 0xC0 | ((rfield & 7) << 3) | (i & 7);
2211 } else { /* it's a memory reference */
2212 if (input->basereg == -1 &&
2213 (input->indexreg == -1 || input->scale == 0)) {
2214 /* it's a pure offset */
2215
2216 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2217 input->segment == NO_SEG) {
2218 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2219 input->type &= ~IP_REL;
2220 input->type |= MEMORY;
2221 }
2222
2223 if (input->eaflags & EAF_BYTEOFFS ||
2224 (input->eaflags & EAF_WORDOFFS &&
2225 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2226 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2227 }
2228
2229 if (bits == 64 && (~input->type & IP_REL)) {
2230 int scale, index, base;
2231 output->sib_present = true;
2232 scale = 0;
2233 index = 4;
2234 base = 5;
2235 output->sib = (scale << 6) | (index << 3) | base;
2236 output->bytes = 4;
2237 output->modrm = 4 | ((rfield & 7) << 3);
2238 output->rip = false;
2239 } else {
2240 output->sib_present = false;
2241 output->bytes = (addrbits != 16 ? 4 : 2);
2242 output->modrm = (addrbits != 16 ? 5 : 6) | ((rfield & 7) << 3);
2243 output->rip = bits == 64;
2244 }
2245 } else { /* it's an indirection */
2246 int i = input->indexreg, b = input->basereg, s = input->scale;
2247 int32_t seg = input->segment;
2248 int hb = input->hintbase, ht = input->hinttype;
2249 int t, it, bt; /* register numbers */
2250 opflags_t x, ix, bx; /* register flags */
2251
2252 if (s == 0)
2253 i = -1; /* make this easy, at least */
2254
2255 if (is_register(i)) {
2256 it = nasm_regvals[i];
2257 ix = nasm_reg_flags[i];
2258 } else {
2259 it = -1;
2260 ix = 0;
2261 }
2262
2263 if (is_register(b)) {
2264 bt = nasm_regvals[b];
2265 bx = nasm_reg_flags[b];
2266 } else {
2267 bt = -1;
2268 bx = 0;
2269 }
2270
2271 /* if either one are a vector register... */
2272 if ((ix|bx) & (XMMREG|YMMREG) & ~REG_EA) {
2273 int32_t sok = BITS32 | BITS64;
2274 int32_t o = input->offset;
2275 int mod, scale, index, base;
2276
2277 /*
2278 * For a vector SIB, one has to be a vector and the other,
2279 * if present, a GPR. The vector must be the index operand.
2280 */
2281 if (it == -1 || (bx & (XMMREG|YMMREG) & ~REG_EA)) {
2282 if (s == 0)
2283 s = 1;
2284 else if (s != 1)
2285 goto err;
2286
2287 t = bt, bt = it, it = t;
2288 x = bx, bx = ix, ix = x;
2289 }
2290
2291 if (bt != -1) {
2292 if (REG_GPR & ~bx)
2293 goto err;
2294 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2295 sok &= bx;
2296 else
2297 goto err;
2298 }
2299
2300 /*
2301 * While we're here, ensure the user didn't specify
2302 * WORD or QWORD
2303 */
2304 if (input->disp_size == 16 || input->disp_size == 64)
2305 goto err;
2306
2307 if (addrbits == 16 ||
2308 (addrbits == 32 && !(sok & BITS32)) ||
2309 (addrbits == 64 && !(sok & BITS64)))
2310 goto err;
2311
2312 output->type = (ix & YMMREG & ~REG_EA)
2313 ? EA_YMMVSIB : EA_XMMVSIB;
2314
2315 output->rex |= rexflags(it, ix, REX_X);
2316 output->rex |= rexflags(bt, bx, REX_B);
2317
2318 index = it & 7; /* it is known to be != -1 */
2319
2320 switch (s) {
2321 case 1:
2322 scale = 0;
2323 break;
2324 case 2:
2325 scale = 1;
2326 break;
2327 case 4:
2328 scale = 2;
2329 break;
2330 case 8:
2331 scale = 3;
2332 break;
2333 default: /* then what the smeg is it? */
2334 goto err; /* panic */
2335 }
2336
2337 if (bt == -1) {
2338 base = 5;
2339 mod = 0;
2340 } else {
2341 base = (bt & 7);
2342 if (base != REG_NUM_EBP && o == 0 &&
2343 seg == NO_SEG && !forw_ref &&
2344 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2345 mod = 0;
2346 else if (input->eaflags & EAF_BYTEOFFS ||
2347 (o >= -128 && o <= 127 &&
2348 seg == NO_SEG && !forw_ref &&
2349 !(input->eaflags & EAF_WORDOFFS)))
2350 mod = 1;
2351 else
2352 mod = 2;
2353 }
2354
2355 output->sib_present = true;
2356 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2357 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2358 output->sib = (scale << 6) | (index << 3) | base;
2359 } else if ((ix|bx) & (BITS32|BITS64)) {
2360 /*
2361 * it must be a 32/64-bit memory reference. Firstly we have
2362 * to check that all registers involved are type E/Rxx.
2363 */
2364 int32_t sok = BITS32 | BITS64;
2365 int32_t o = input->offset;
2366
2367 if (it != -1) {
2368 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2369 sok &= ix;
2370 else
2371 goto err;
2372 }
2373
2374 if (bt != -1) {
2375 if (REG_GPR & ~bx)
2376 goto err; /* Invalid register */
2377 if (~sok & bx & SIZE_MASK)
2378 goto err; /* Invalid size */
2379 sok &= bx;
2380 }
2381
2382 /*
2383 * While we're here, ensure the user didn't specify
2384 * WORD or QWORD
2385 */
2386 if (input->disp_size == 16 || input->disp_size == 64)
2387 goto err;
2388
2389 if (addrbits == 16 ||
2390 (addrbits == 32 && !(sok & BITS32)) ||
2391 (addrbits == 64 && !(sok & BITS64)))
2392 goto err;
2393
2394 /* now reorganize base/index */
2395 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2396 ((hb == b && ht == EAH_NOTBASE) ||
2397 (hb == i && ht == EAH_MAKEBASE))) {
2398 /* swap if hints say so */
2399 t = bt, bt = it, it = t;
2400 x = bx, bx = ix, ix = x;
2401 }
2402 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2403 bt = -1, bx = 0, s++;
2404 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2405 /* make single reg base, unless hint */
2406 bt = it, bx = ix, it = -1, ix = 0;
2407 }
2408 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2409 s == 3 || s == 5 || s == 9) && bt == -1)
2410 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2411 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2412 (input->eaflags & EAF_TIMESTWO))
2413 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2414 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2415 if (s == 1 && it == REG_NUM_ESP) {
2416 /* swap ESP into base if scale is 1 */
2417 t = it, it = bt, bt = t;
2418 x = ix, ix = bx, bx = x;
2419 }
2420 if (it == REG_NUM_ESP ||
2421 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2422 goto err; /* wrong, for various reasons */
2423
2424 output->rex |= rexflags(it, ix, REX_X);
2425 output->rex |= rexflags(bt, bx, REX_B);
2426
2427 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2428 /* no SIB needed */
2429 int mod, rm;
2430
2431 if (bt == -1) {
2432 rm = 5;
2433 mod = 0;
2434 } else {
2435 rm = (bt & 7);
2436 if (rm != REG_NUM_EBP && o == 0 &&
2437 seg == NO_SEG && !forw_ref &&
2438 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2439 mod = 0;
2440 else if (input->eaflags & EAF_BYTEOFFS ||
2441 (o >= -128 && o <= 127 &&
2442 seg == NO_SEG && !forw_ref &&
2443 !(input->eaflags & EAF_WORDOFFS)))
2444 mod = 1;
2445 else
2446 mod = 2;
2447 }
2448
2449 output->sib_present = false;
2450 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2451 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2452 } else {
2453 /* we need a SIB */
2454 int mod, scale, index, base;
2455
2456 if (it == -1)
2457 index = 4, s = 1;
2458 else
2459 index = (it & 7);
2460
2461 switch (s) {
2462 case 1:
2463 scale = 0;
2464 break;
2465 case 2:
2466 scale = 1;
2467 break;
2468 case 4:
2469 scale = 2;
2470 break;
2471 case 8:
2472 scale = 3;
2473 break;
2474 default: /* then what the smeg is it? */
2475 goto err; /* panic */
2476 }
2477
2478 if (bt == -1) {
2479 base = 5;
2480 mod = 0;
2481 } else {
2482 base = (bt & 7);
2483 if (base != REG_NUM_EBP && o == 0 &&
2484 seg == NO_SEG && !forw_ref &&
2485 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2486 mod = 0;
2487 else if (input->eaflags & EAF_BYTEOFFS ||
2488 (o >= -128 && o <= 127 &&
2489 seg == NO_SEG && !forw_ref &&
2490 !(input->eaflags & EAF_WORDOFFS)))
2491 mod = 1;
2492 else
2493 mod = 2;
2494 }
2495
2496 output->sib_present = true;
2497 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2498 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2499 output->sib = (scale << 6) | (index << 3) | base;
2500 }
2501 } else { /* it's 16-bit */
2502 int mod, rm;
2503 int16_t o = input->offset;
2504
2505 /* check for 64-bit long mode */
2506 if (addrbits == 64)
2507 goto err;
2508
2509 /* check all registers are BX, BP, SI or DI */
2510 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2511 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2512 goto err;
2513
2514 /* ensure the user didn't specify DWORD/QWORD */
2515 if (input->disp_size == 32 || input->disp_size == 64)
2516 goto err;
2517
2518 if (s != 1 && i != -1)
2519 goto err; /* no can do, in 16-bit EA */
2520 if (b == -1 && i != -1) {
2521 int tmp = b;
2522 b = i;
2523 i = tmp;
2524 } /* swap */
2525 if ((b == R_SI || b == R_DI) && i != -1) {
2526 int tmp = b;
2527 b = i;
2528 i = tmp;
2529 }
2530 /* have BX/BP as base, SI/DI index */
2531 if (b == i)
2532 goto err; /* shouldn't ever happen, in theory */
2533 if (i != -1 && b != -1 &&
2534 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2535 goto err; /* invalid combinations */
2536 if (b == -1) /* pure offset: handled above */
2537 goto err; /* so if it gets to here, panic! */
2538
2539 rm = -1;
2540 if (i != -1)
2541 switch (i * 256 + b) {
2542 case R_SI * 256 + R_BX:
2543 rm = 0;
2544 break;
2545 case R_DI * 256 + R_BX:
2546 rm = 1;
2547 break;
2548 case R_SI * 256 + R_BP:
2549 rm = 2;
2550 break;
2551 case R_DI * 256 + R_BP:
2552 rm = 3;
2553 break;
2554 } else
2555 switch (b) {
2556 case R_SI:
2557 rm = 4;
2558 break;
2559 case R_DI:
2560 rm = 5;
2561 break;
2562 case R_BP:
2563 rm = 6;
2564 break;
2565 case R_BX:
2566 rm = 7;
2567 break;
2568 }
2569 if (rm == -1) /* can't happen, in theory */
2570 goto err; /* so panic if it does */
2571
2572 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2573 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2574 mod = 0;
2575 else if (input->eaflags & EAF_BYTEOFFS ||
2576 (o >= -128 && o <= 127 && seg == NO_SEG &&
2577 !forw_ref && !(input->eaflags & EAF_WORDOFFS)))
2578 mod = 1;
2579 else
2580 mod = 2;
2581
2582 output->sib_present = false; /* no SIB - it's 16-bit */
2583 output->bytes = mod; /* bytes of offset needed */
2584 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2585 }
2586 }
2587 }
2588
2589 output->size = 1 + output->sib_present + output->bytes;
2590 return output->type;
2591
2592 err:
2593 return output->type = EA_INVALID;
2594 }
2595
2596 static void add_asp(insn *ins, int addrbits)
2597 {
2598 int j, valid;
2599 int defdisp;
2600
2601 valid = (addrbits == 64) ? 64|32 : 32|16;
2602
2603 switch (ins->prefixes[PPS_ASIZE]) {
2604 case P_A16:
2605 valid &= 16;
2606 break;
2607 case P_A32:
2608 valid &= 32;
2609 break;
2610 case P_A64:
2611 valid &= 64;
2612 break;
2613 case P_ASP:
2614 valid &= (addrbits == 32) ? 16 : 32;
2615 break;
2616 default:
2617 break;
2618 }
2619
2620 for (j = 0; j < ins->operands; j++) {
2621 if (is_class(MEMORY, ins->oprs[j].type)) {
2622 opflags_t i, b;
2623
2624 /* Verify as Register */
2625 if (!is_register(ins->oprs[j].indexreg))
2626 i = 0;
2627 else
2628 i = nasm_reg_flags[ins->oprs[j].indexreg];
2629
2630 /* Verify as Register */
2631 if (!is_register(ins->oprs[j].basereg))
2632 b = 0;
2633 else
2634 b = nasm_reg_flags[ins->oprs[j].basereg];
2635
2636 if (ins->oprs[j].scale == 0)
2637 i = 0;
2638
2639 if (!i && !b) {
2640 int ds = ins->oprs[j].disp_size;
2641 if ((addrbits != 64 && ds > 8) ||
2642 (addrbits == 64 && ds == 16))
2643 valid &= ds;
2644 } else {
2645 if (!(REG16 & ~b))
2646 valid &= 16;
2647 if (!(REG32 & ~b))
2648 valid &= 32;
2649 if (!(REG64 & ~b))
2650 valid &= 64;
2651
2652 if (!(REG16 & ~i))
2653 valid &= 16;
2654 if (!(REG32 & ~i))
2655 valid &= 32;
2656 if (!(REG64 & ~i))
2657 valid &= 64;
2658 }
2659 }
2660 }
2661
2662 if (valid & addrbits) {
2663 ins->addr_size = addrbits;
2664 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2665 /* Add an address size prefix */
2666 enum prefixes pref = (addrbits == 32) ? P_A16 : P_A32;
2667 ins->prefixes[PPS_ASIZE] = pref;
2668 ins->addr_size = (addrbits == 32) ? 16 : 32;
2669 } else {
2670 /* Impossible... */
2671 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2672 ins->addr_size = addrbits; /* Error recovery */
2673 }
2674
2675 defdisp = ins->addr_size == 16 ? 16 : 32;
2676
2677 for (j = 0; j < ins->operands; j++) {
2678 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2679 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2680 /*
2681 * mem_offs sizes must match the address size; if not,
2682 * strip the MEM_OFFS bit and match only EA instructions
2683 */
2684 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2685 }
2686 }
2687 }
The Netwide Assembler