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AVX-512: Change the data type for instruction flags
[nasm.git] / assemble.c
blobc22075d9261aa10d96703a61c67ec38eca2c1265
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2013 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \20..\23 - a byte immediate operand, from operand 0..3
46 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
47 * \30..\33 - a word immediate operand, from operand 0..3
48 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
49 * assembly mode or the operand-size override on the operand
50 * \40..\43 - a long immediate operand, from operand 0..3
51 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
52 * depending on the address size of the instruction.
53 * \50..\53 - a byte relative operand, from operand 0..3
54 * \54..\57 - a qword immediate operand, from operand 0..3
55 * \60..\63 - a word relative operand, from operand 0..3
56 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
57 * assembly mode or the operand-size override on the operand
58 * \70..\73 - a long relative operand, from operand 0..3
59 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
60 * \1ab - a ModRM, calculated on EA in operand a, with the spare
61 * field the register value of operand b.
62 * \172\ab - the register number from operand a in bits 7..4, with
63 * the 4-bit immediate from operand b in bits 3..0.
64 * \173\xab - the register number from operand a in bits 7..4, with
65 * the value b in bits 3..0.
66 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
67 * an arbitrary value in bits 3..0 (assembled as zero.)
68 * \2ab - a ModRM, calculated on EA in operand a, with the spare
69 * field equal to digit b.
70 *
71 * \240..\243 - this instruction uses EVEX rather than REX or VEX/XOP, with the
72 * V field taken from operand 0..3.
73 * \250 - this instruction uses EVEX rather than REX or VEX/XOP, with the
74 * V field set to 1111b.
75 * EVEX prefixes are followed by the sequence:
76 * \cm\wlp\tup where cm is:
77 * cc 000 0mm
78 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
79 * and wlp is:
80 * 00 wwl lpp
81 * [l0] ll = 0 (.128, .lz)
82 * [l1] ll = 1 (.256)
83 * [l2] ll = 2 (.512)
84 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
85 *
86 * [w0] ww = 0 for W = 0
87 * [w1] ww = 1 for W = 1
88 * [wig] ww = 2 for W don't care (always assembled as 0)
89 * [ww] ww = 3 for W used as REX.W
90 *
91 * [p0] pp = 0 for no prefix
92 * [60] pp = 1 for legacy prefix 60
93 * [f3] pp = 2
94 * [f2] pp = 3
95 *
96 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
97 * (compressed displacement encoding)
98 *
99 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
100 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
101 * V field taken from operand 0..3.
102 * \270 - this instruction uses VEX/XOP rather than REX, with the
103 * V field set to 1111b.
104 *
105 * VEX/XOP prefixes are followed by the sequence:
106 * \tmm\wlp where mm is the M field; and wlp is:
107 * 00 wwl lpp
108 * [l0] ll = 0 for L = 0 (.128, .lz)
109 * [l1] ll = 1 for L = 1 (.256)
110 * [lig] ll = 2 for L don't care (always assembled as 0)
111 *
112 * [w0] ww = 0 for W = 0
113 * [w1 ] ww = 1 for W = 1
114 * [wig] ww = 2 for W don't care (always assembled as 0)
115 * [ww] ww = 3 for W used as REX.W
116 *
117 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
118 *
119 * \271 - instruction takes XRELEASE (F3) with or without lock
120 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
121 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
122 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
123 * to the operand size (if o16/o32/o64 present) or the bit size
124 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
125 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
126 * \312 - (disassembler only) invalid with non-default address size.
127 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
128 * \314 - (disassembler only) invalid with REX.B
129 * \315 - (disassembler only) invalid with REX.X
130 * \316 - (disassembler only) invalid with REX.R
131 * \317 - (disassembler only) invalid with REX.W
132 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
133 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
134 * \322 - indicates that this instruction is only valid when the
135 * operand size is the default (instruction to disassembler,
136 * generates no code in the assembler)
137 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
138 * \324 - indicates 64-bit operand size requiring REX prefix.
139 * \325 - instruction which always uses spl/bpl/sil/dil
140 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
141 disassembler only; for SSE instructions.
142 * \330 - a literal byte follows in the code stream, to be added
143 * to the condition code value of the instruction.
144 * \331 - instruction not valid with REP prefix. Hint for
145 * disassembler only; for SSE instructions.
146 * \332 - REP prefix (0xF2 byte) used as opcode extension.
147 * \333 - REP prefix (0xF3 byte) used as opcode extension.
148 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
149 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
150 * \336 - force a REP(E) prefix (0xF3) even if not specified.
151 * \337 - force a REPNE prefix (0xF2) even if not specified.
152 * \336-\337 are still listed as prefixes in the disassembler.
153 * \340 - reserve <operand 0> bytes of uninitialized storage.
154 * Operand 0 had better be a segmentless constant.
155 * \341 - this instruction needs a WAIT "prefix"
156 * \360 - no SSE prefix (== \364\331)
157 * \361 - 66 SSE prefix (== \366\331)
158 * \364 - operand-size prefix (0x66) not permitted
159 * \365 - address-size prefix (0x67) not permitted
160 * \366 - operand-size prefix (0x66) used as opcode extension
161 * \367 - address-size prefix (0x67) used as opcode extension
162 * \370,\371 - match only if operand 0 meets byte jump criteria.
163 * 370 is used for Jcc, 371 is used for JMP.
164 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
165 * used for conditional jump over longer jump
166 * \374 - this instruction takes an XMM VSIB memory EA
167 * \375 - this instruction takes an YMM VSIB memory EA
168 * \376 - this instruction takes an ZMM VSIB memory EA
169 */
170
171 #include "compiler.h"
172
173 #include <stdio.h>
174 #include <string.h>
175 #include <inttypes.h>
176
177 #include "nasm.h"
178 #include "nasmlib.h"
179 #include "assemble.h"
180 #include "insns.h"
181 #include "tables.h"
182
183 enum match_result {
184 /*
185 * Matching errors. These should be sorted so that more specific
186 * errors come later in the sequence.
187 */
188 MERR_INVALOP,
189 MERR_OPSIZEMISSING,
190 MERR_OPSIZEMISMATCH,
191 MERR_BADCPU,
192 MERR_BADMODE,
193 MERR_BADHLE,
194 /*
195 * Matching success; the conditional ones first
196 */
197 MOK_JUMP, /* Matching OK but needs jmp_match() */
198 MOK_GOOD /* Matching unconditionally OK */
199 };
200
201 typedef struct {
202 enum ea_type type; /* what kind of EA is this? */
203 int sib_present; /* is a SIB byte necessary? */
204 int bytes; /* # of bytes of offset needed */
205 int size; /* lazy - this is sib+bytes+1 */
206 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
207 int8_t disp8; /* compressed displacement for EVEX */
208 } ea;
209
210 #define GEN_SIB(scale, index, base) \
211 (((scale) << 6) | ((index) << 3) | ((base)))
212
213 #define GEN_MODRM(mod, reg, rm) \
214 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
215
216 static iflags_t cpu; /* cpu level received from nasm.c */
217 static efunc errfunc;
218 static struct ofmt *outfmt;
219 static ListGen *list;
220
221 static int64_t calcsize(int32_t, int64_t, int, insn *,
222 const struct itemplate *);
223 static void gencode(int32_t segment, int64_t offset, int bits,
224 insn * ins, const struct itemplate *temp,
225 int64_t insn_end);
226 static enum match_result find_match(const struct itemplate **tempp,
227 insn *instruction,
228 int32_t segment, int64_t offset, int bits);
229 static enum match_result matches(const struct itemplate *, insn *, int bits);
230 static opflags_t regflag(const operand *);
231 static int32_t regval(const operand *);
232 static int rexflags(int, opflags_t, int);
233 static int op_rexflags(const operand *, int);
234 static int op_evexflags(const operand *, int, uint8_t);
235 static void add_asp(insn *, int);
236
237 static enum ea_type process_ea(operand *, ea *, int, int, opflags_t, insn *);
238
239 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
240 {
241 return ins->prefixes[pos] == prefix;
242 }
243
244 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
245 {
246 if (ins->prefixes[pos])
247 errfunc(ERR_NONFATAL, "invalid %s prefix",
248 prefix_name(ins->prefixes[pos]));
249 }
250
251 static const char *size_name(int size)
252 {
253 switch (size) {
254 case 1:
255 return "byte";
256 case 2:
257 return "word";
258 case 4:
259 return "dword";
260 case 8:
261 return "qword";
262 case 10:
263 return "tword";
264 case 16:
265 return "oword";
266 case 32:
267 return "yword";
268 case 64:
269 return "zword";
270 default:
271 return "???";
272 }
273 }
274
275 static void warn_overflow(int pass, int size)
276 {
277 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
278 "%s data exceeds bounds", size_name(size));
279 }
280
281 static void warn_overflow_const(int64_t data, int size)
282 {
283 if (overflow_general(data, size))
284 warn_overflow(ERR_PASS1, size);
285 }
286
287 static void warn_overflow_opd(const struct operand *o, int size)
288 {
289 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
290 if (overflow_general(o->offset, size))
291 warn_overflow(ERR_PASS2, size);
292 }
293 }
294
295 /*
296 * This routine wrappers the real output format's output routine,
297 * in order to pass a copy of the data off to the listing file
298 * generator at the same time.
299 */
300 static void out(int64_t offset, int32_t segto, const void *data,
301 enum out_type type, uint64_t size,
302 int32_t segment, int32_t wrt)
303 {
304 static int32_t lineno = 0; /* static!!! */
305 static char *lnfname = NULL;
306 uint8_t p[8];
307
308 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
309 /*
310 * This is a non-relocated address, and we're going to
311 * convert it into RAWDATA format.
312 */
313 uint8_t *q = p;
314
315 if (size > 8) {
316 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
317 return;
318 }
319
320 WRITEADDR(q, *(int64_t *)data, size);
321 data = p;
322 type = OUT_RAWDATA;
323 }
324
325 list->output(offset, data, type, size);
326
327 /*
328 * this call to src_get determines when we call the
329 * debug-format-specific "linenum" function
330 * it updates lineno and lnfname to the current values
331 * returning 0 if "same as last time", -2 if lnfname
332 * changed, and the amount by which lineno changed,
333 * if it did. thus, these variables must be static
334 */
335
336 if (src_get(&lineno, &lnfname))
337 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
338
339 outfmt->output(segto, data, type, size, segment, wrt);
340 }
341
342 static void out_imm8(int64_t offset, int32_t segment, struct operand *opx)
343 {
344 if (opx->segment != NO_SEG) {
345 uint64_t data = opx->offset;
346 out(offset, segment, &data, OUT_ADDRESS, 1, opx->segment, opx->wrt);
347 } else {
348 uint8_t byte = opx->offset;
349 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
350 }
351 }
352
353 static bool jmp_match(int32_t segment, int64_t offset, int bits,
354 insn * ins, const struct itemplate *temp)
355 {
356 int64_t isize;
357 const uint8_t *code = temp->code;
358 uint8_t c = code[0];
359
360 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
361 return false;
362 if (!optimizing)
363 return false;
364 if (optimizing < 0 && c == 0371)
365 return false;
366
367 isize = calcsize(segment, offset, bits, ins, temp);
368
369 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
370 /* Be optimistic in pass 1 */
371 return true;
372
373 if (ins->oprs[0].segment != segment)
374 return false;
375
376 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
377 return (isize >= -128 && isize <= 127); /* is it byte size? */
378 }
379
380 int64_t assemble(int32_t segment, int64_t offset, int bits, iflags_t cp,
381 insn * instruction, struct ofmt *output, efunc error,
382 ListGen * listgen)
383 {
384 const struct itemplate *temp;
385 int j;
386 enum match_result m;
387 int64_t insn_end;
388 int32_t itimes;
389 int64_t start = offset;
390 int64_t wsize; /* size for DB etc. */
391
392 errfunc = error; /* to pass to other functions */
393 cpu = cp;
394 outfmt = output; /* likewise */
395 list = listgen; /* and again */
396
397 wsize = idata_bytes(instruction->opcode);
398 if (wsize == -1)
399 return 0;
400
401 if (wsize) {
402 extop *e;
403 int32_t t = instruction->times;
404 if (t < 0)
405 errfunc(ERR_PANIC,
406 "instruction->times < 0 (%ld) in assemble()", t);
407
408 while (t--) { /* repeat TIMES times */
409 list_for_each(e, instruction->eops) {
410 if (e->type == EOT_DB_NUMBER) {
411 if (wsize > 8) {
412 errfunc(ERR_NONFATAL,
413 "integer supplied to a DT, DO or DY"
414 " instruction");
415 } else {
416 out(offset, segment, &e->offset,
417 OUT_ADDRESS, wsize, e->segment, e->wrt);
418 offset += wsize;
419 }
420 } else if (e->type == EOT_DB_STRING ||
421 e->type == EOT_DB_STRING_FREE) {
422 int align;
423
424 out(offset, segment, e->stringval,
425 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
426 align = e->stringlen % wsize;
427
428 if (align) {
429 align = wsize - align;
430 out(offset, segment, zero_buffer,
431 OUT_RAWDATA, align, NO_SEG, NO_SEG);
432 }
433 offset += e->stringlen + align;
434 }
435 }
436 if (t > 0 && t == instruction->times - 1) {
437 /*
438 * Dummy call to list->output to give the offset to the
439 * listing module.
440 */
441 list->output(offset, NULL, OUT_RAWDATA, 0);
442 list->uplevel(LIST_TIMES);
443 }
444 }
445 if (instruction->times > 1)
446 list->downlevel(LIST_TIMES);
447 return offset - start;
448 }
449
450 if (instruction->opcode == I_INCBIN) {
451 const char *fname = instruction->eops->stringval;
452 FILE *fp;
453
454 fp = fopen(fname, "rb");
455 if (!fp) {
456 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
457 fname);
458 } else if (fseek(fp, 0L, SEEK_END) < 0) {
459 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
460 fname);
461 fclose(fp);
462 } else {
463 static char buf[4096];
464 size_t t = instruction->times;
465 size_t base = 0;
466 size_t len;
467
468 len = ftell(fp);
469 if (instruction->eops->next) {
470 base = instruction->eops->next->offset;
471 len -= base;
472 if (instruction->eops->next->next &&
473 len > (size_t)instruction->eops->next->next->offset)
474 len = (size_t)instruction->eops->next->next->offset;
475 }
476 /*
477 * Dummy call to list->output to give the offset to the
478 * listing module.
479 */
480 list->output(offset, NULL, OUT_RAWDATA, 0);
481 list->uplevel(LIST_INCBIN);
482 while (t--) {
483 size_t l;
484
485 fseek(fp, base, SEEK_SET);
486 l = len;
487 while (l > 0) {
488 int32_t m;
489 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
490 if (!m) {
491 /*
492 * This shouldn't happen unless the file
493 * actually changes while we are reading
494 * it.
495 */
496 error(ERR_NONFATAL,
497 "`incbin': unexpected EOF while"
498 " reading file `%s'", fname);
499 t = 0; /* Try to exit cleanly */
500 break;
501 }
502 out(offset, segment, buf, OUT_RAWDATA, m,
503 NO_SEG, NO_SEG);
504 l -= m;
505 }
506 }
507 list->downlevel(LIST_INCBIN);
508 if (instruction->times > 1) {
509 /*
510 * Dummy call to list->output to give the offset to the
511 * listing module.
512 */
513 list->output(offset, NULL, OUT_RAWDATA, 0);
514 list->uplevel(LIST_TIMES);
515 list->downlevel(LIST_TIMES);
516 }
517 fclose(fp);
518 return instruction->times * len;
519 }
520 return 0; /* if we're here, there's an error */
521 }
522
523 /* Check to see if we need an address-size prefix */
524 add_asp(instruction, bits);
525
526 m = find_match(&temp, instruction, segment, offset, bits);
527
528 if (m == MOK_GOOD) {
529 /* Matches! */
530 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
531 itimes = instruction->times;
532 if (insn_size < 0) /* shouldn't be, on pass two */
533 error(ERR_PANIC, "errors made it through from pass one");
534 else
535 while (itimes--) {
536 for (j = 0; j < MAXPREFIX; j++) {
537 uint8_t c = 0;
538 switch (instruction->prefixes[j]) {
539 case P_WAIT:
540 c = 0x9B;
541 break;
542 case P_LOCK:
543 c = 0xF0;
544 break;
545 case P_REPNE:
546 case P_REPNZ:
547 case P_XACQUIRE:
548 c = 0xF2;
549 break;
550 case P_REPE:
551 case P_REPZ:
552 case P_REP:
553 case P_XRELEASE:
554 c = 0xF3;
555 break;
556 case R_CS:
557 if (bits == 64) {
558 error(ERR_WARNING | ERR_PASS2,
559 "cs segment base generated, but will be ignored in 64-bit mode");
560 }
561 c = 0x2E;
562 break;
563 case R_DS:
564 if (bits == 64) {
565 error(ERR_WARNING | ERR_PASS2,
566 "ds segment base generated, but will be ignored in 64-bit mode");
567 }
568 c = 0x3E;
569 break;
570 case R_ES:
571 if (bits == 64) {
572 error(ERR_WARNING | ERR_PASS2,
573 "es segment base generated, but will be ignored in 64-bit mode");
574 }
575 c = 0x26;
576 break;
577 case R_FS:
578 c = 0x64;
579 break;
580 case R_GS:
581 c = 0x65;
582 break;
583 case R_SS:
584 if (bits == 64) {
585 error(ERR_WARNING | ERR_PASS2,
586 "ss segment base generated, but will be ignored in 64-bit mode");
587 }
588 c = 0x36;
589 break;
590 case R_SEGR6:
591 case R_SEGR7:
592 error(ERR_NONFATAL,
593 "segr6 and segr7 cannot be used as prefixes");
594 break;
595 case P_A16:
596 if (bits == 64) {
597 error(ERR_NONFATAL,
598 "16-bit addressing is not supported "
599 "in 64-bit mode");
600 } else if (bits != 16)
601 c = 0x67;
602 break;
603 case P_A32:
604 if (bits != 32)
605 c = 0x67;
606 break;
607 case P_A64:
608 if (bits != 64) {
609 error(ERR_NONFATAL,
610 "64-bit addressing is only supported "
611 "in 64-bit mode");
612 }
613 break;
614 case P_ASP:
615 c = 0x67;
616 break;
617 case P_O16:
618 if (bits != 16)
619 c = 0x66;
620 break;
621 case P_O32:
622 if (bits == 16)
623 c = 0x66;
624 break;
625 case P_O64:
626 /* REX.W */
627 break;
628 case P_OSP:
629 c = 0x66;
630 break;
631 case P_none:
632 break;
633 default:
634 error(ERR_PANIC, "invalid instruction prefix");
635 }
636 if (c != 0) {
637 out(offset, segment, &c, OUT_RAWDATA, 1,
638 NO_SEG, NO_SEG);
639 offset++;
640 }
641 }
642 insn_end = offset + insn_size;
643 gencode(segment, offset, bits, instruction,
644 temp, insn_end);
645 offset += insn_size;
646 if (itimes > 0 && itimes == instruction->times - 1) {
647 /*
648 * Dummy call to list->output to give the offset to the
649 * listing module.
650 */
651 list->output(offset, NULL, OUT_RAWDATA, 0);
652 list->uplevel(LIST_TIMES);
653 }
654 }
655 if (instruction->times > 1)
656 list->downlevel(LIST_TIMES);
657 return offset - start;
658 } else {
659 /* No match */
660 switch (m) {
661 case MERR_OPSIZEMISSING:
662 error(ERR_NONFATAL, "operation size not specified");
663 break;
664 case MERR_OPSIZEMISMATCH:
665 error(ERR_NONFATAL, "mismatch in operand sizes");
666 break;
667 case MERR_BADCPU:
668 error(ERR_NONFATAL, "no instruction for this cpu level");
669 break;
670 case MERR_BADMODE:
671 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
672 bits);
673 break;
674 default:
675 error(ERR_NONFATAL,
676 "invalid combination of opcode and operands");
677 break;
678 }
679 }
680 return 0;
681 }
682
683 int64_t insn_size(int32_t segment, int64_t offset, int bits, iflags_t cp,
684 insn * instruction, efunc error)
685 {
686 const struct itemplate *temp;
687 enum match_result m;
688
689 errfunc = error; /* to pass to other functions */
690 cpu = cp;
691
692 if (instruction->opcode == I_none)
693 return 0;
694
695 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
696 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
697 instruction->opcode == I_DT || instruction->opcode == I_DO ||
698 instruction->opcode == I_DY) {
699 extop *e;
700 int32_t isize, osize, wsize;
701
702 isize = 0;
703 wsize = idata_bytes(instruction->opcode);
704
705 list_for_each(e, instruction->eops) {
706 int32_t align;
707
708 osize = 0;
709 if (e->type == EOT_DB_NUMBER) {
710 osize = 1;
711 warn_overflow_const(e->offset, wsize);
712 } else if (e->type == EOT_DB_STRING ||
713 e->type == EOT_DB_STRING_FREE)
714 osize = e->stringlen;
715
716 align = (-osize) % wsize;
717 if (align < 0)
718 align += wsize;
719 isize += osize + align;
720 }
721 return isize * instruction->times;
722 }
723
724 if (instruction->opcode == I_INCBIN) {
725 const char *fname = instruction->eops->stringval;
726 FILE *fp;
727 int64_t val = 0;
728 size_t len;
729
730 fp = fopen(fname, "rb");
731 if (!fp)
732 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
733 fname);
734 else if (fseek(fp, 0L, SEEK_END) < 0)
735 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
736 fname);
737 else {
738 len = ftell(fp);
739 if (instruction->eops->next) {
740 len -= instruction->eops->next->offset;
741 if (instruction->eops->next->next &&
742 len > (size_t)instruction->eops->next->next->offset) {
743 len = (size_t)instruction->eops->next->next->offset;
744 }
745 }
746 val = instruction->times * len;
747 }
748 if (fp)
749 fclose(fp);
750 return val;
751 }
752
753 /* Check to see if we need an address-size prefix */
754 add_asp(instruction, bits);
755
756 m = find_match(&temp, instruction, segment, offset, bits);
757 if (m == MOK_GOOD) {
758 /* we've matched an instruction. */
759 int64_t isize;
760 int j;
761
762 isize = calcsize(segment, offset, bits, instruction, temp);
763 if (isize < 0)
764 return -1;
765 for (j = 0; j < MAXPREFIX; j++) {
766 switch (instruction->prefixes[j]) {
767 case P_A16:
768 if (bits != 16)
769 isize++;
770 break;
771 case P_A32:
772 if (bits != 32)
773 isize++;
774 break;
775 case P_O16:
776 if (bits != 16)
777 isize++;
778 break;
779 case P_O32:
780 if (bits == 16)
781 isize++;
782 break;
783 case P_A64:
784 case P_O64:
785 case P_none:
786 break;
787 default:
788 isize++;
789 break;
790 }
791 }
792 return isize * instruction->times;
793 } else {
794 return -1; /* didn't match any instruction */
795 }
796 }
797
798 static void bad_hle_warn(const insn * ins, uint8_t hleok)
799 {
800 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
801 enum whatwarn { w_none, w_lock, w_inval } ww;
802 static const enum whatwarn warn[2][4] =
803 {
804 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
805 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
806 };
807 unsigned int n;
808
809 n = (unsigned int)rep_pfx - P_XACQUIRE;
810 if (n > 1)
811 return; /* Not XACQUIRE/XRELEASE */
812
813 ww = warn[n][hleok];
814 if (!is_class(MEMORY, ins->oprs[0].type))
815 ww = w_inval; /* HLE requires operand 0 to be memory */
816
817 switch (ww) {
818 case w_none:
819 break;
820
821 case w_lock:
822 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
823 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
824 "%s with this instruction requires lock",
825 prefix_name(rep_pfx));
826 }
827 break;
828
829 case w_inval:
830 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
831 "%s invalid with this instruction",
832 prefix_name(rep_pfx));
833 break;
834 }
835 }
836
837 /* Common construct */
838 #define case3(x) case (x): case (x)+1: case (x)+2
839 #define case4(x) case3(x): case (x)+3
840
841 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
842 insn * ins, const struct itemplate *temp)
843 {
844 const uint8_t *codes = temp->code;
845 int64_t length = 0;
846 uint8_t c;
847 int rex_mask = ~0;
848 int op1, op2;
849 struct operand *opx;
850 uint8_t opex = 0;
851 enum ea_type eat;
852 uint8_t hleok = 0;
853 bool lockcheck = true;
854
855 ins->rex = 0; /* Ensure REX is reset */
856 eat = EA_SCALAR; /* Expect a scalar EA */
857 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
858
859 if (ins->prefixes[PPS_OSIZE] == P_O64)
860 ins->rex |= REX_W;
861
862 (void)segment; /* Don't warn that this parameter is unused */
863 (void)offset; /* Don't warn that this parameter is unused */
864
865 while (*codes) {
866 c = *codes++;
867 op1 = (c & 3) + ((opex & 1) << 2);
868 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
869 opx = &ins->oprs[op1];
870 opex = 0; /* For the next iteration */
871
872 switch (c) {
873 case4(01):
874 codes += c, length += c;
875 break;
876
877 case3(05):
878 opex = c;
879 break;
880
881 case4(010):
882 ins->rex |=
883 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
884 codes++, length++;
885 break;
886
887 case4(020):
888 case4(024):
889 length++;
890 break;
891
892 case4(030):
893 length += 2;
894 break;
895
896 case4(034):
897 if (opx->type & (BITS16 | BITS32 | BITS64))
898 length += (opx->type & BITS16) ? 2 : 4;
899 else
900 length += (bits == 16) ? 2 : 4;
901 break;
902
903 case4(040):
904 length += 4;
905 break;
906
907 case4(044):
908 length += ins->addr_size >> 3;
909 break;
910
911 case4(050):
912 length++;
913 break;
914
915 case4(054):
916 length += 8; /* MOV reg64/imm */
917 break;
918
919 case4(060):
920 length += 2;
921 break;
922
923 case4(064):
924 if (opx->type & (BITS16 | BITS32 | BITS64))
925 length += (opx->type & BITS16) ? 2 : 4;
926 else
927 length += (bits == 16) ? 2 : 4;
928 break;
929
930 case4(070):
931 length += 4;
932 break;
933
934 case4(074):
935 length += 2;
936 break;
937
938 case 0172:
939 case 0173:
940 codes++;
941 length++;
942 break;
943
944 case4(0174):
945 length++;
946 break;
947
948 case4(0240):
949 ins->rex |= REX_EV;
950 ins->vexreg = regval(opx);
951 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
952 ins->vex_cm = *codes++;
953 ins->vex_wlp = *codes++;
954 ins->evex_tuple = (*codes++ - 0300);
955 break;
956
957 case 0250:
958 ins->rex |= REX_EV;
959 ins->vexreg = 0;
960 ins->vex_cm = *codes++;
961 ins->vex_wlp = *codes++;
962 ins->evex_tuple = (*codes++ - 0300);
963 break;
964
965 case4(0254):
966 length += 4;
967 break;
968
969 case4(0260):
970 ins->rex |= REX_V;
971 ins->vexreg = regval(opx);
972 ins->vex_cm = *codes++;
973 ins->vex_wlp = *codes++;
974 break;
975
976 case 0270:
977 ins->rex |= REX_V;
978 ins->vexreg = 0;
979 ins->vex_cm = *codes++;
980 ins->vex_wlp = *codes++;
981 break;
982
983 case3(0271):
984 hleok = c & 3;
985 break;
986
987 case4(0274):
988 length++;
989 break;
990
991 case4(0300):
992 break;
993
994 case 0310:
995 if (bits == 64)
996 return -1;
997 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
998 break;
999
1000 case 0311:
1001 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1002 break;
1003
1004 case 0312:
1005 break;
1006
1007 case 0313:
1008 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1009 has_prefix(ins, PPS_ASIZE, P_A32))
1010 return -1;
1011 break;
1012
1013 case4(0314):
1014 break;
1015
1016 case 0320:
1017 {
1018 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1019 if (pfx == P_O16)
1020 break;
1021 if (pfx != P_none)
1022 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1023 else
1024 ins->prefixes[PPS_OSIZE] = P_O16;
1025 break;
1026 }
1027
1028 case 0321:
1029 {
1030 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1031 if (pfx == P_O32)
1032 break;
1033 if (pfx != P_none)
1034 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1035 else
1036 ins->prefixes[PPS_OSIZE] = P_O32;
1037 break;
1038 }
1039
1040 case 0322:
1041 break;
1042
1043 case 0323:
1044 rex_mask &= ~REX_W;
1045 break;
1046
1047 case 0324:
1048 ins->rex |= REX_W;
1049 break;
1050
1051 case 0325:
1052 ins->rex |= REX_NH;
1053 break;
1054
1055 case 0326:
1056 break;
1057
1058 case 0330:
1059 codes++, length++;
1060 break;
1061
1062 case 0331:
1063 break;
1064
1065 case 0332:
1066 case 0333:
1067 length++;
1068 break;
1069
1070 case 0334:
1071 ins->rex |= REX_L;
1072 break;
1073
1074 case 0335:
1075 break;
1076
1077 case 0336:
1078 if (!ins->prefixes[PPS_REP])
1079 ins->prefixes[PPS_REP] = P_REP;
1080 break;
1081
1082 case 0337:
1083 if (!ins->prefixes[PPS_REP])
1084 ins->prefixes[PPS_REP] = P_REPNE;
1085 break;
1086
1087 case 0340:
1088 if (ins->oprs[0].segment != NO_SEG)
1089 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1090 " quantity of BSS space");
1091 else
1092 length += ins->oprs[0].offset;
1093 break;
1094
1095 case 0341:
1096 if (!ins->prefixes[PPS_WAIT])
1097 ins->prefixes[PPS_WAIT] = P_WAIT;
1098 break;
1099
1100 case 0360:
1101 break;
1102
1103 case 0361:
1104 length++;
1105 break;
1106
1107 case 0364:
1108 case 0365:
1109 break;
1110
1111 case 0366:
1112 case 0367:
1113 length++;
1114 break;
1115
1116 case3(0370):
1117 break;
1118
1119 case 0373:
1120 length++;
1121 break;
1122
1123 case 0374:
1124 eat = EA_XMMVSIB;
1125 break;
1126
1127 case 0375:
1128 eat = EA_YMMVSIB;
1129 break;
1130
1131 case 0376:
1132 eat = EA_ZMMVSIB;
1133 break;
1134
1135 case4(0100):
1136 case4(0110):
1137 case4(0120):
1138 case4(0130):
1139 case4(0200):
1140 case4(0204):
1141 case4(0210):
1142 case4(0214):
1143 case4(0220):
1144 case4(0224):
1145 case4(0230):
1146 case4(0234):
1147 {
1148 ea ea_data;
1149 int rfield;
1150 opflags_t rflags;
1151 struct operand *opy = &ins->oprs[op2];
1152 struct operand *oplast;
1153
1154 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1155
1156 if (c <= 0177) {
1157 /* pick rfield from operand b (opx) */
1158 rflags = regflag(opx);
1159 rfield = nasm_regvals[opx->basereg];
1160 /* find the last SIMD operand where ER decorator resides */
1161 oplast = &ins->oprs[op1 > op2 ? op1 : op2];
1162 while (oplast && is_class(REG_CLASS_GPR, oplast->type))
1163 oplast--;
1164 } else {
1165 rflags = 0;
1166 rfield = c & 7;
1167 oplast = opy;
1168 }
1169
1170 if (oplast->decoflags & ER) {
1171 /* set EVEX.RC (rounding control) and b */
1172 ins->evex_p[2] |= (((ins->evex_rm - BRC_RN) << 5) & EVEX_P2LL) |
1173 EVEX_P2B;
1174 } else {
1175 /* set EVEX.L'L (vector length) */
1176 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1177 if ((oplast->decoflags & SAE) ||
1178 (opy->decoflags & BRDCAST_MASK)) {
1179 /* set EVEX.b */
1180 ins->evex_p[2] |= EVEX_P2B;
1181 }
1182 }
1183
1184 if (process_ea(opy, &ea_data, bits,
1185 rfield, rflags, ins) != eat) {
1186 errfunc(ERR_NONFATAL, "invalid effective address");
1187 return -1;
1188 } else {
1189 ins->rex |= ea_data.rex;
1190 length += ea_data.size;
1191 }
1192 }
1193 break;
1194
1195 default:
1196 errfunc(ERR_PANIC, "internal instruction table corrupt"
1197 ": instruction code \\%o (0x%02X) given", c, c);
1198 break;
1199 }
1200 }
1201
1202 ins->rex &= rex_mask;
1203
1204 if (ins->rex & REX_NH) {
1205 if (ins->rex & REX_H) {
1206 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1207 return -1;
1208 }
1209 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1210 }
1211
1212 if (ins->rex & (REX_V | REX_EV)) {
1213 int bad32 = REX_R|REX_W|REX_X|REX_B;
1214
1215 if (ins->rex & REX_H) {
1216 errfunc(ERR_NONFATAL, "cannot use high register in AVX instruction");
1217 return -1;
1218 }
1219 switch (ins->vex_wlp & 060) {
1220 case 000:
1221 case 040:
1222 ins->rex &= ~REX_W;
1223 break;
1224 case 020:
1225 ins->rex |= REX_W;
1226 bad32 &= ~REX_W;
1227 break;
1228 case 060:
1229 /* Follow REX_W */
1230 break;
1231 }
1232
1233 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1234 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1235 return -1;
1236 }
1237 if (ins->rex & REX_EV)
1238 length += 4;
1239 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1240 length += 3;
1241 else
1242 length += 2;
1243 } else if (ins->rex & REX_REAL) {
1244 if (ins->rex & REX_H) {
1245 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1246 return -1;
1247 } else if (bits == 64) {
1248 length++;
1249 } else if ((ins->rex & REX_L) &&
1250 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1251 cpu >= IF_X86_64) {
1252 /* LOCK-as-REX.R */
1253 assert_no_prefix(ins, PPS_LOCK);
1254 lockcheck = false; /* Already errored, no need for warning */
1255 length++;
1256 } else {
1257 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1258 return -1;
1259 }
1260 }
1261
1262 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1263 (!(temp->flags & IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1264 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1265 "instruction is not lockable");
1266 }
1267
1268 bad_hle_warn(ins, hleok);
1269
1270 return length;
1271 }
1272
1273 static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
1274 {
1275 if (bits == 64) {
1276 if ((ins->rex & REX_REAL) && !(ins->rex & (REX_V | REX_EV))) {
1277 ins->rex = (ins->rex & REX_REAL) | REX_P;
1278 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1279 ins->rex = 0;
1280 return 1;
1281 }
1282 }
1283
1284 return 0;
1285 }
1286
1287 static void gencode(int32_t segment, int64_t offset, int bits,
1288 insn * ins, const struct itemplate *temp,
1289 int64_t insn_end)
1290 {
1291 uint8_t c;
1292 uint8_t bytes[4];
1293 int64_t size;
1294 int64_t data;
1295 int op1, op2;
1296 struct operand *opx;
1297 const uint8_t *codes = temp->code;
1298 uint8_t opex = 0;
1299 enum ea_type eat = EA_SCALAR;
1300
1301 while (*codes) {
1302 c = *codes++;
1303 op1 = (c & 3) + ((opex & 1) << 2);
1304 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1305 opx = &ins->oprs[op1];
1306 opex = 0; /* For the next iteration */
1307
1308 switch (c) {
1309 case 01:
1310 case 02:
1311 case 03:
1312 case 04:
1313 offset += emit_rex(ins, segment, offset, bits);
1314 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1315 codes += c;
1316 offset += c;
1317 break;
1318
1319 case 05:
1320 case 06:
1321 case 07:
1322 opex = c;
1323 break;
1324
1325 case4(010):
1326 offset += emit_rex(ins, segment, offset, bits);
1327 bytes[0] = *codes++ + (regval(opx) & 7);
1328 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1329 offset += 1;
1330 break;
1331
1332 case4(020):
1333 if (opx->offset < -256 || opx->offset > 255) {
1334 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1335 "byte value exceeds bounds");
1336 }
1337 out_imm8(offset, segment, opx);
1338 offset += 1;
1339 break;
1340
1341 case4(024):
1342 if (opx->offset < 0 || opx->offset > 255)
1343 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1344 "unsigned byte value exceeds bounds");
1345 out_imm8(offset, segment, opx);
1346 offset += 1;
1347 break;
1348
1349 case4(030):
1350 warn_overflow_opd(opx, 2);
1351 data = opx->offset;
1352 out(offset, segment, &data, OUT_ADDRESS, 2,
1353 opx->segment, opx->wrt);
1354 offset += 2;
1355 break;
1356
1357 case4(034):
1358 if (opx->type & (BITS16 | BITS32))
1359 size = (opx->type & BITS16) ? 2 : 4;
1360 else
1361 size = (bits == 16) ? 2 : 4;
1362 warn_overflow_opd(opx, size);
1363 data = opx->offset;
1364 out(offset, segment, &data, OUT_ADDRESS, size,
1365 opx->segment, opx->wrt);
1366 offset += size;
1367 break;
1368
1369 case4(040):
1370 warn_overflow_opd(opx, 4);
1371 data = opx->offset;
1372 out(offset, segment, &data, OUT_ADDRESS, 4,
1373 opx->segment, opx->wrt);
1374 offset += 4;
1375 break;
1376
1377 case4(044):
1378 data = opx->offset;
1379 size = ins->addr_size >> 3;
1380 warn_overflow_opd(opx, size);
1381 out(offset, segment, &data, OUT_ADDRESS, size,
1382 opx->segment, opx->wrt);
1383 offset += size;
1384 break;
1385
1386 case4(050):
1387 if (opx->segment != segment) {
1388 data = opx->offset;
1389 out(offset, segment, &data,
1390 OUT_REL1ADR, insn_end - offset,
1391 opx->segment, opx->wrt);
1392 } else {
1393 data = opx->offset - insn_end;
1394 if (data > 127 || data < -128)
1395 errfunc(ERR_NONFATAL, "short jump is out of range");
1396 out(offset, segment, &data,
1397 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1398 }
1399 offset += 1;
1400 break;
1401
1402 case4(054):
1403 data = (int64_t)opx->offset;
1404 out(offset, segment, &data, OUT_ADDRESS, 8,
1405 opx->segment, opx->wrt);
1406 offset += 8;
1407 break;
1408
1409 case4(060):
1410 if (opx->segment != segment) {
1411 data = opx->offset;
1412 out(offset, segment, &data,
1413 OUT_REL2ADR, insn_end - offset,
1414 opx->segment, opx->wrt);
1415 } else {
1416 data = opx->offset - insn_end;
1417 out(offset, segment, &data,
1418 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1419 }
1420 offset += 2;
1421 break;
1422
1423 case4(064):
1424 if (opx->type & (BITS16 | BITS32 | BITS64))
1425 size = (opx->type & BITS16) ? 2 : 4;
1426 else
1427 size = (bits == 16) ? 2 : 4;
1428 if (opx->segment != segment) {
1429 data = opx->offset;
1430 out(offset, segment, &data,
1431 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1432 insn_end - offset, opx->segment, opx->wrt);
1433 } else {
1434 data = opx->offset - insn_end;
1435 out(offset, segment, &data,
1436 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1437 }
1438 offset += size;
1439 break;
1440
1441 case4(070):
1442 if (opx->segment != segment) {
1443 data = opx->offset;
1444 out(offset, segment, &data,
1445 OUT_REL4ADR, insn_end - offset,
1446 opx->segment, opx->wrt);
1447 } else {
1448 data = opx->offset - insn_end;
1449 out(offset, segment, &data,
1450 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1451 }
1452 offset += 4;
1453 break;
1454
1455 case4(074):
1456 if (opx->segment == NO_SEG)
1457 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1458 " relocatable");
1459 data = 0;
1460 out(offset, segment, &data, OUT_ADDRESS, 2,
1461 outfmt->segbase(1 + opx->segment),
1462 opx->wrt);
1463 offset += 2;
1464 break;
1465
1466 case 0172:
1467 c = *codes++;
1468 opx = &ins->oprs[c >> 3];
1469 bytes[0] = nasm_regvals[opx->basereg] << 4;
1470 opx = &ins->oprs[c & 7];
1471 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1472 errfunc(ERR_NONFATAL,
1473 "non-absolute expression not permitted as argument %d",
1474 c & 7);
1475 } else {
1476 if (opx->offset & ~15) {
1477 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1478 "four-bit argument exceeds bounds");
1479 }
1480 bytes[0] |= opx->offset & 15;
1481 }
1482 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1483 offset++;
1484 break;
1485
1486 case 0173:
1487 c = *codes++;
1488 opx = &ins->oprs[c >> 4];
1489 bytes[0] = nasm_regvals[opx->basereg] << 4;
1490 bytes[0] |= c & 15;
1491 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1492 offset++;
1493 break;
1494
1495 case4(0174):
1496 bytes[0] = nasm_regvals[opx->basereg] << 4;
1497 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1498 offset++;
1499 break;
1500
1501 case4(0254):
1502 data = opx->offset;
1503 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1504 (int32_t)data != (int64_t)data) {
1505 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1506 "signed dword immediate exceeds bounds");
1507 }
1508 out(offset, segment, &data, OUT_ADDRESS, 4,
1509 opx->segment, opx->wrt);
1510 offset += 4;
1511 break;
1512
1513 case4(0240):
1514 case 0250:
1515 codes += 3;
1516 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1517 EVEX_P2Z | EVEX_P2AAA, 2);
1518 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1519 bytes[0] = 0x62;
1520 /* EVEX.X can be set by either REX or EVEX for different reasons */
1521 bytes[1] = (~(((ins->rex & 7) << 5) |
1522 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) & 0xf0) |
1523 (ins->vex_cm & 3);
1524 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1525 ((~ins->vexreg & 15) << 3) |
1526 (1 << 2) | (ins->vex_wlp & 3);
1527 bytes[3] = ins->evex_p[2];
1528 out(offset, segment, &bytes, OUT_RAWDATA, 4, NO_SEG, NO_SEG);
1529 offset += 4;
1530 break;
1531
1532 case4(0260):
1533 case 0270:
1534 codes += 2;
1535 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1536 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1537 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1538 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1539 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1540 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1541 offset += 3;
1542 } else {
1543 bytes[0] = 0xc5;
1544 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1545 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1546 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1547 offset += 2;
1548 }
1549 break;
1550
1551 case 0271:
1552 case 0272:
1553 case 0273:
1554 break;
1555
1556 case4(0274):
1557 {
1558 uint64_t uv, um;
1559 int s;
1560
1561 if (ins->rex & REX_W)
1562 s = 64;
1563 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1564 s = 16;
1565 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1566 s = 32;
1567 else
1568 s = bits;
1569
1570 um = (uint64_t)2 << (s-1);
1571 uv = opx->offset;
1572
1573 if (uv > 127 && uv < (uint64_t)-128 &&
1574 (uv < um-128 || uv > um-1)) {
1575 /* If this wasn't explicitly byte-sized, warn as though we
1576 * had fallen through to the imm16/32/64 case.
1577 */
1578 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1579 "%s value exceeds bounds",
1580 (opx->type & BITS8) ? "signed byte" :
1581 s == 16 ? "word" :
1582 s == 32 ? "dword" :
1583 "signed dword");
1584 }
1585 if (opx->segment != NO_SEG) {
1586 data = uv;
1587 out(offset, segment, &data, OUT_ADDRESS, 1,
1588 opx->segment, opx->wrt);
1589 } else {
1590 bytes[0] = uv;
1591 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1592 NO_SEG);
1593 }
1594 offset += 1;
1595 break;
1596 }
1597
1598 case4(0300):
1599 break;
1600
1601 case 0310:
1602 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1603 *bytes = 0x67;
1604 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1605 offset += 1;
1606 } else
1607 offset += 0;
1608 break;
1609
1610 case 0311:
1611 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1612 *bytes = 0x67;
1613 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1614 offset += 1;
1615 } else
1616 offset += 0;
1617 break;
1618
1619 case 0312:
1620 break;
1621
1622 case 0313:
1623 ins->rex = 0;
1624 break;
1625
1626 case4(0314):
1627 break;
1628
1629 case 0320:
1630 case 0321:
1631 break;
1632
1633 case 0322:
1634 case 0323:
1635 break;
1636
1637 case 0324:
1638 ins->rex |= REX_W;
1639 break;
1640
1641 case 0325:
1642 break;
1643
1644 case 0326:
1645 break;
1646
1647 case 0330:
1648 *bytes = *codes++ ^ get_cond_opcode(ins->condition);
1649 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1650 offset += 1;
1651 break;
1652
1653 case 0331:
1654 break;
1655
1656 case 0332:
1657 case 0333:
1658 *bytes = c - 0332 + 0xF2;
1659 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1660 offset += 1;
1661 break;
1662
1663 case 0334:
1664 if (ins->rex & REX_R) {
1665 *bytes = 0xF0;
1666 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1667 offset += 1;
1668 }
1669 ins->rex &= ~(REX_L|REX_R);
1670 break;
1671
1672 case 0335:
1673 break;
1674
1675 case 0336:
1676 case 0337:
1677 break;
1678
1679 case 0340:
1680 if (ins->oprs[0].segment != NO_SEG)
1681 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1682 else {
1683 int64_t size = ins->oprs[0].offset;
1684 if (size > 0)
1685 out(offset, segment, NULL,
1686 OUT_RESERVE, size, NO_SEG, NO_SEG);
1687 offset += size;
1688 }
1689 break;
1690
1691 case 0341:
1692 break;
1693
1694 case 0360:
1695 break;
1696
1697 case 0361:
1698 bytes[0] = 0x66;
1699 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1700 offset += 1;
1701 break;
1702
1703 case 0364:
1704 case 0365:
1705 break;
1706
1707 case 0366:
1708 case 0367:
1709 *bytes = c - 0366 + 0x66;
1710 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1711 offset += 1;
1712 break;
1713
1714 case 0370:
1715 case 0371:
1716 break;
1717
1718 case 0373:
1719 *bytes = bits == 16 ? 3 : 5;
1720 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1721 offset += 1;
1722 break;
1723
1724 case 0374:
1725 eat = EA_XMMVSIB;
1726 break;
1727
1728 case 0375:
1729 eat = EA_YMMVSIB;
1730 break;
1731
1732 case 0376:
1733 eat = EA_ZMMVSIB;
1734 break;
1735
1736 case4(0100):
1737 case4(0110):
1738 case4(0120):
1739 case4(0130):
1740 case4(0200):
1741 case4(0204):
1742 case4(0210):
1743 case4(0214):
1744 case4(0220):
1745 case4(0224):
1746 case4(0230):
1747 case4(0234):
1748 {
1749 ea ea_data;
1750 int rfield;
1751 opflags_t rflags;
1752 uint8_t *p;
1753 int32_t s;
1754 struct operand *opy = &ins->oprs[op2];
1755
1756 if (c <= 0177) {
1757 /* pick rfield from operand b (opx) */
1758 rflags = regflag(opx);
1759 rfield = nasm_regvals[opx->basereg];
1760 } else {
1761 /* rfield is constant */
1762 rflags = 0;
1763 rfield = c & 7;
1764 }
1765
1766 if (process_ea(opy, &ea_data, bits,
1767 rfield, rflags, ins) != eat)
1768 errfunc(ERR_NONFATAL, "invalid effective address");
1769
1770 p = bytes;
1771 *p++ = ea_data.modrm;
1772 if (ea_data.sib_present)
1773 *p++ = ea_data.sib;
1774
1775 s = p - bytes;
1776 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1777
1778 /*
1779 * Make sure the address gets the right offset in case
1780 * the line breaks in the .lst file (BR 1197827)
1781 */
1782 offset += s;
1783 s = 0;
1784
1785 switch (ea_data.bytes) {
1786 case 0:
1787 break;
1788 case 1:
1789 case 2:
1790 case 4:
1791 case 8:
1792 /* use compressed displacement, if available */
1793 data = ea_data.disp8 ? ea_data.disp8 : opy->offset;
1794 s += ea_data.bytes;
1795 if (ea_data.rip) {
1796 if (opy->segment == segment) {
1797 data -= insn_end;
1798 if (overflow_signed(data, ea_data.bytes))
1799 warn_overflow(ERR_PASS2, ea_data.bytes);
1800 out(offset, segment, &data, OUT_ADDRESS,
1801 ea_data.bytes, NO_SEG, NO_SEG);
1802 } else {
1803 /* overflow check in output/linker? */
1804 out(offset, segment, &data, OUT_REL4ADR,
1805 insn_end - offset, opy->segment, opy->wrt);
1806 }
1807 } else {
1808 if (overflow_general(data, ins->addr_size >> 3) ||
1809 signed_bits(data, ins->addr_size) !=
1810 signed_bits(data, ea_data.bytes * 8))
1811 warn_overflow(ERR_PASS2, ea_data.bytes);
1812
1813 out(offset, segment, &data, OUT_ADDRESS,
1814 ea_data.bytes, opy->segment, opy->wrt);
1815 }
1816 break;
1817 default:
1818 /* Impossible! */
1819 errfunc(ERR_PANIC,
1820 "Invalid amount of bytes (%d) for offset?!",
1821 ea_data.bytes);
1822 break;
1823 }
1824 offset += s;
1825 }
1826 break;
1827
1828 default:
1829 errfunc(ERR_PANIC, "internal instruction table corrupt"
1830 ": instruction code \\%o (0x%02X) given", c, c);
1831 break;
1832 }
1833 }
1834 }
1835
1836 static opflags_t regflag(const operand * o)
1837 {
1838 if (!is_register(o->basereg))
1839 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1840 return nasm_reg_flags[o->basereg];
1841 }
1842
1843 static int32_t regval(const operand * o)
1844 {
1845 if (!is_register(o->basereg))
1846 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1847 return nasm_regvals[o->basereg];
1848 }
1849
1850 static int op_rexflags(const operand * o, int mask)
1851 {
1852 opflags_t flags;
1853 int val;
1854
1855 if (!is_register(o->basereg))
1856 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1857
1858 flags = nasm_reg_flags[o->basereg];
1859 val = nasm_regvals[o->basereg];
1860
1861 return rexflags(val, flags, mask);
1862 }
1863
1864 static int rexflags(int val, opflags_t flags, int mask)
1865 {
1866 int rex = 0;
1867
1868 if (val >= 8)
1869 rex |= REX_B|REX_X|REX_R;
1870 if (flags & BITS64)
1871 rex |= REX_W;
1872 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1873 rex |= REX_H;
1874 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1875 rex |= REX_P;
1876
1877 return rex & mask;
1878 }
1879
1880 static int evexflags(int val, decoflags_t deco,
1881 int mask, uint8_t byte)
1882 {
1883 int evex = 0;
1884
1885 switch(byte) {
1886 case 0:
1887 if (val >= 16)
1888 evex |= (EVEX_P0RP | EVEX_P0X);
1889 break;
1890 case 2:
1891 if (val >= 16)
1892 evex |= EVEX_P2VP;
1893 if (deco & Z)
1894 evex |= EVEX_P2Z;
1895 if (deco & OPMASK_MASK)
1896 evex |= deco & EVEX_P2AAA;
1897 break;
1898 }
1899 return evex & mask;
1900 }
1901
1902 static int op_evexflags(const operand * o, int mask, uint8_t byte)
1903 {
1904 int val;
1905
1906 if (!is_register(o->basereg))
1907 errfunc(ERR_PANIC, "invalid operand passed to op_evexflags()");
1908
1909 val = nasm_regvals[o->basereg];
1910
1911 return evexflags(val, o->decoflags, mask, byte);
1912 }
1913
1914 static enum match_result find_match(const struct itemplate **tempp,
1915 insn *instruction,
1916 int32_t segment, int64_t offset, int bits)
1917 {
1918 const struct itemplate *temp;
1919 enum match_result m, merr;
1920 opflags_t xsizeflags[MAX_OPERANDS];
1921 bool opsizemissing = false;
1922 int8_t broadcast = -1;
1923 int i;
1924
1925 /* find the position of broadcasting operand */
1926 for (i = 0; i < instruction->operands; i++)
1927 if (instruction->oprs[i].decoflags & BRDCAST_MASK) {
1928 broadcast = i;
1929 break;
1930 }
1931
1932 /* broadcasting uses a different data element size */
1933 for (i = 0; i < instruction->operands; i++)
1934 if (i == broadcast)
1935 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
1936 else
1937 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1938
1939 merr = MERR_INVALOP;
1940
1941 for (temp = nasm_instructions[instruction->opcode];
1942 temp->opcode != I_none; temp++) {
1943 m = matches(temp, instruction, bits);
1944 if (m == MOK_JUMP) {
1945 if (jmp_match(segment, offset, bits, instruction, temp))
1946 m = MOK_GOOD;
1947 else
1948 m = MERR_INVALOP;
1949 } else if (m == MERR_OPSIZEMISSING &&
1950 (temp->flags & IF_SMASK) != IF_SX) {
1951 /*
1952 * Missing operand size and a candidate for fuzzy matching...
1953 */
1954 for (i = 0; i < temp->operands; i++)
1955 if (i == broadcast)
1956 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
1957 else
1958 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
1959 opsizemissing = true;
1960 }
1961 if (m > merr)
1962 merr = m;
1963 if (merr == MOK_GOOD)
1964 goto done;
1965 }
1966
1967 /* No match, but see if we can get a fuzzy operand size match... */
1968 if (!opsizemissing)
1969 goto done;
1970
1971 for (i = 0; i < instruction->operands; i++) {
1972 /*
1973 * We ignore extrinsic operand sizes on registers, so we should
1974 * never try to fuzzy-match on them. This also resolves the case
1975 * when we have e.g. "xmmrm128" in two different positions.
1976 */
1977 if (is_class(REGISTER, instruction->oprs[i].type))
1978 continue;
1979
1980 /* This tests if xsizeflags[i] has more than one bit set */
1981 if ((xsizeflags[i] & (xsizeflags[i]-1)))
1982 goto done; /* No luck */
1983
1984 if (i == broadcast)
1985 instruction->oprs[i].decoflags |= xsizeflags[i];
1986 else
1987 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
1988 }
1989
1990 /* Try matching again... */
1991 for (temp = nasm_instructions[instruction->opcode];
1992 temp->opcode != I_none; temp++) {
1993 m = matches(temp, instruction, bits);
1994 if (m == MOK_JUMP) {
1995 if (jmp_match(segment, offset, bits, instruction, temp))
1996 m = MOK_GOOD;
1997 else
1998 m = MERR_INVALOP;
1999 }
2000 if (m > merr)
2001 merr = m;
2002 if (merr == MOK_GOOD)
2003 goto done;
2004 }
2005
2006 done:
2007 *tempp = temp;
2008 return merr;
2009 }
2010
2011 static enum match_result matches(const struct itemplate *itemp,
2012 insn *instruction, int bits)
2013 {
2014 opflags_t size[MAX_OPERANDS], asize;
2015 bool opsizemissing = false;
2016 int i, oprs;
2017
2018 /*
2019 * Check the opcode
2020 */
2021 if (itemp->opcode != instruction->opcode)
2022 return MERR_INVALOP;
2023
2024 /*
2025 * Count the operands
2026 */
2027 if (itemp->operands != instruction->operands)
2028 return MERR_INVALOP;
2029
2030 /*
2031 * Is it legal?
2032 */
2033 if (!(optimizing > 0) && (itemp->flags & IF_OPT))
2034 return MERR_INVALOP;
2035
2036 /*
2037 * Check that no spurious colons or TOs are present
2038 */
2039 for (i = 0; i < itemp->operands; i++)
2040 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2041 return MERR_INVALOP;
2042
2043 /*
2044 * Process size flags
2045 */
2046 switch (itemp->flags & IF_SMASK) {
2047 case IF_SB:
2048 asize = BITS8;
2049 break;
2050 case IF_SW:
2051 asize = BITS16;
2052 break;
2053 case IF_SD:
2054 asize = BITS32;
2055 break;
2056 case IF_SQ:
2057 asize = BITS64;
2058 break;
2059 case IF_SO:
2060 asize = BITS128;
2061 break;
2062 case IF_SY:
2063 asize = BITS256;
2064 break;
2065 case IF_SZ:
2066 asize = BITS512;
2067 break;
2068 case IF_SIZE:
2069 switch (bits) {
2070 case 16:
2071 asize = BITS16;
2072 break;
2073 case 32:
2074 asize = BITS32;
2075 break;
2076 case 64:
2077 asize = BITS64;
2078 break;
2079 default:
2080 asize = 0;
2081 break;
2082 }
2083 break;
2084 default:
2085 asize = 0;
2086 break;
2087 }
2088
2089 if (itemp->flags & IF_ARMASK) {
2090 /* S- flags only apply to a specific operand */
2091 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
2092 memset(size, 0, sizeof size);
2093 size[i] = asize;
2094 } else {
2095 /* S- flags apply to all operands */
2096 for (i = 0; i < MAX_OPERANDS; i++)
2097 size[i] = asize;
2098 }
2099
2100 /*
2101 * Check that the operand flags all match up,
2102 * it's a bit tricky so lets be verbose:
2103 *
2104 * 1) Find out the size of operand. If instruction
2105 * doesn't have one specified -- we're trying to
2106 * guess it either from template (IF_S* flag) or
2107 * from code bits.
2108 *
2109 * 2) If template operand do not match the instruction OR
2110 * template has an operand size specified AND this size differ
2111 * from which instruction has (perhaps we got it from code bits)
2112 * we are:
2113 * a) Check that only size of instruction and operand is differ
2114 * other characteristics do match
2115 * b) Perhaps it's a register specified in instruction so
2116 * for such a case we just mark that operand as "size
2117 * missing" and this will turn on fuzzy operand size
2118 * logic facility (handled by a caller)
2119 */
2120 for (i = 0; i < itemp->operands; i++) {
2121 opflags_t type = instruction->oprs[i].type;
2122 decoflags_t deco = instruction->oprs[i].decoflags;
2123 if (!(type & SIZE_MASK))
2124 type |= size[i];
2125
2126 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2127 (itemp->deco[i] & deco) != deco) {
2128 return MERR_INVALOP;
2129 } else if ((itemp->opd[i] & SIZE_MASK) &&
2130 (itemp->opd[i] & SIZE_MASK) != (type & SIZE_MASK)) {
2131 if (type & SIZE_MASK) {
2132 /*
2133 * when broadcasting, the element size depends on
2134 * the instruction type. decorator flag should match.
2135 */
2136 #define MATCH_BRSZ(bits) (((type & SIZE_MASK) == BITS##bits) && \
2137 ((itemp->deco[i] & BRSIZE_MASK) == BR_BITS##bits))
2138 if (!((deco & BRDCAST_MASK) &&
2139 (MATCH_BRSZ(32) || MATCH_BRSZ(64)))) {
2140 return MERR_INVALOP;
2141 }
2142 } else if (!is_class(REGISTER, type)) {
2143 /*
2144 * Note: we don't honor extrinsic operand sizes for registers,
2145 * so "missing operand size" for a register should be
2146 * considered a wildcard match rather than an error.
2147 */
2148 opsizemissing = true;
2149 }
2150 }
2151 }
2152
2153 if (opsizemissing)
2154 return MERR_OPSIZEMISSING;
2155
2156 /*
2157 * Check operand sizes
2158 */
2159 if (itemp->flags & (IF_SM | IF_SM2)) {
2160 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2161 for (i = 0; i < oprs; i++) {
2162 asize = itemp->opd[i] & SIZE_MASK;
2163 if (asize) {
2164 for (i = 0; i < oprs; i++)
2165 size[i] = asize;
2166 break;
2167 }
2168 }
2169 } else {
2170 oprs = itemp->operands;
2171 }
2172
2173 for (i = 0; i < itemp->operands; i++) {
2174 if (!(itemp->opd[i] & SIZE_MASK) &&
2175 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2176 return MERR_OPSIZEMISMATCH;
2177 }
2178
2179 /*
2180 * Check template is okay at the set cpu level
2181 */
2182 if (((itemp->flags & IF_PLEVEL) > cpu))
2183 return MERR_BADCPU;
2184
2185 /*
2186 * Verify the appropriate long mode flag.
2187 */
2188 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2189 return MERR_BADMODE;
2190
2191 /*
2192 * If we have a HLE prefix, look for the NOHLE flag
2193 */
2194 if ((itemp->flags & IF_NOHLE) &&
2195 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2196 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2197 return MERR_BADHLE;
2198
2199 /*
2200 * Check if special handling needed for Jumps
2201 */
2202 if ((itemp->code[0] & ~1) == 0370)
2203 return MOK_JUMP;
2204
2205 return MOK_GOOD;
2206 }
2207
2208 /*
2209 * Check if offset is a multiple of N with corresponding tuple type
2210 * if Disp8*N is available, compressed displacement is stored in compdisp
2211 */
2212 static bool is_disp8n(operand *input, insn *ins, int8_t *compdisp)
2213 {
2214 const uint8_t fv_n[2][2][VLMAX] = {{{16, 32, 64}, {4, 4, 4}},
2215 {{16, 32, 64}, {8, 8, 8}}};
2216 const uint8_t hv_n[2][VLMAX] = {{8, 16, 32}, {4, 4, 4}};
2217 const uint8_t dup_n[VLMAX] = {8, 32, 64};
2218
2219 bool evex_b = input->decoflags & BRDCAST_MASK;
2220 enum ttypes tuple = ins->evex_tuple;
2221 /* vex_wlp composed as [wwllpp] */
2222 enum vectlens vectlen = (ins->vex_wlp & 0x0c) >> 2;
2223 /* wig(=2) is treated as w0(=0) */
2224 bool evex_w = (ins->vex_wlp & 0x10) >> 4;
2225 int32_t off = input->offset;
2226 uint8_t n = 0;
2227 int32_t disp8;
2228
2229 switch(tuple) {
2230 case FV:
2231 n = fv_n[evex_w][evex_b][vectlen];
2232 break;
2233 case HV:
2234 n = hv_n[evex_b][vectlen];
2235 break;
2236
2237 case FVM:
2238 /* 16, 32, 64 for VL 128, 256, 512 respectively*/
2239 n = 1 << (vectlen + 4);
2240 break;
2241 case T1S8: /* N = 1 */
2242 case T1S16: /* N = 2 */
2243 n = tuple - T1S8 + 1;
2244 break;
2245 case T1S:
2246 /* N = 4 for 32bit, 8 for 64bit */
2247 n = evex_w ? 8 : 4;
2248 break;
2249 case T1F32:
2250 case T1F64:
2251 /* N = 4 for 32bit, 8 for 64bit */
2252 n = (tuple == T1F32 ? 4 : 8);
2253 break;
2254 case T2:
2255 case T4:
2256 case T8:
2257 if (vectlen + 7 <= (evex_w + 5) + (tuple - T2 + 1))
2258 n = 0;
2259 else
2260 n = 1 << (tuple - T2 + evex_w + 3);
2261 break;
2262 case HVM:
2263 case QVM:
2264 case OVM:
2265 n = 1 << (OVM - tuple + vectlen + 1);
2266 break;
2267 case M128:
2268 n = 16;
2269 break;
2270 case DUP:
2271 n = dup_n[vectlen];
2272 break;
2273
2274 default:
2275 break;
2276 }
2277
2278 if (n && !(off & (n - 1))) {
2279 disp8 = off / n;
2280 /* if it fits in Disp8 */
2281 if (disp8 >= -128 && disp8 <= 127) {
2282 *compdisp = disp8;
2283 return true;
2284 }
2285 }
2286
2287 *compdisp = 0;
2288 return false;
2289 }
2290
2291 /*
2292 * Check if ModR/M.mod should/can be 01.
2293 * - EAF_BYTEOFFS is set
2294 * - offset can fit in a byte when EVEX is not used
2295 * - offset can be compressed when EVEX is used
2296 */
2297 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2298 (o >= -128 && o <= 127 && \
2299 seg == NO_SEG && !forw_ref && \
2300 !(input->eaflags & EAF_WORDOFFS) && \
2301 !(ins->rex & REX_EV)) || \
2302 (ins->rex & REX_EV && \
2303 is_disp8n(input, ins, &output->disp8)))
2304
2305 static enum ea_type process_ea(operand *input, ea *output, int bits,
2306 int rfield, opflags_t rflags, insn *ins)
2307 {
2308 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2309 int addrbits = ins->addr_size;
2310
2311 output->type = EA_SCALAR;
2312 output->rip = false;
2313
2314 /* REX flags for the rfield operand */
2315 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2316 /* EVEX.R' flag for the REG operand */
2317 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2318
2319 if (is_class(REGISTER, input->type)) {
2320 /*
2321 * It's a direct register.
2322 */
2323 if (!is_register(input->basereg))
2324 goto err;
2325
2326 if (!is_reg_class(REG_EA, input->basereg))
2327 goto err;
2328
2329 /* broadcasting is not available with a direct register operand. */
2330 if (input->decoflags & BRDCAST_MASK) {
2331 nasm_error(ERR_NONFATAL, "Broadcasting not allowed from a register");
2332 goto err;
2333 }
2334
2335 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2336 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2337 output->sib_present = false; /* no SIB necessary */
2338 output->bytes = 0; /* no offset necessary either */
2339 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2340 } else {
2341 /*
2342 * It's a memory reference.
2343 */
2344
2345 /* Embedded rounding or SAE is not available with a mem ref operand. */
2346 if (input->decoflags & (ER | SAE)) {
2347 nasm_error(ERR_NONFATAL,
2348 "Embedded rounding is available only with reg-reg op.");
2349 return -1;
2350 }
2351
2352 if (input->basereg == -1 &&
2353 (input->indexreg == -1 || input->scale == 0)) {
2354 /*
2355 * It's a pure offset.
2356 */
2357 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2358 input->segment == NO_SEG) {
2359 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2360 input->type &= ~IP_REL;
2361 input->type |= MEMORY;
2362 }
2363
2364 if (input->eaflags & EAF_BYTEOFFS ||
2365 (input->eaflags & EAF_WORDOFFS &&
2366 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2367 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2368 }
2369
2370 if (bits == 64 && (~input->type & IP_REL)) {
2371 output->sib_present = true;
2372 output->sib = GEN_SIB(0, 4, 5);
2373 output->bytes = 4;
2374 output->modrm = GEN_MODRM(0, rfield, 4);
2375 output->rip = false;
2376 } else {
2377 output->sib_present = false;
2378 output->bytes = (addrbits != 16 ? 4 : 2);
2379 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2380 output->rip = bits == 64;
2381 }
2382 } else {
2383 /*
2384 * It's an indirection.
2385 */
2386 int i = input->indexreg, b = input->basereg, s = input->scale;
2387 int32_t seg = input->segment;
2388 int hb = input->hintbase, ht = input->hinttype;
2389 int t, it, bt; /* register numbers */
2390 opflags_t x, ix, bx; /* register flags */
2391
2392 if (s == 0)
2393 i = -1; /* make this easy, at least */
2394
2395 if (is_register(i)) {
2396 it = nasm_regvals[i];
2397 ix = nasm_reg_flags[i];
2398 } else {
2399 it = -1;
2400 ix = 0;
2401 }
2402
2403 if (is_register(b)) {
2404 bt = nasm_regvals[b];
2405 bx = nasm_reg_flags[b];
2406 } else {
2407 bt = -1;
2408 bx = 0;
2409 }
2410
2411 /* if either one are a vector register... */
2412 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2413 opflags_t sok = BITS32 | BITS64;
2414 int32_t o = input->offset;
2415 int mod, scale, index, base;
2416
2417 /*
2418 * For a vector SIB, one has to be a vector and the other,
2419 * if present, a GPR. The vector must be the index operand.
2420 */
2421 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2422 if (s == 0)
2423 s = 1;
2424 else if (s != 1)
2425 goto err;
2426
2427 t = bt, bt = it, it = t;
2428 x = bx, bx = ix, ix = x;
2429 }
2430
2431 if (bt != -1) {
2432 if (REG_GPR & ~bx)
2433 goto err;
2434 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2435 sok &= bx;
2436 else
2437 goto err;
2438 }
2439
2440 /*
2441 * While we're here, ensure the user didn't specify
2442 * WORD or QWORD
2443 */
2444 if (input->disp_size == 16 || input->disp_size == 64)
2445 goto err;
2446
2447 if (addrbits == 16 ||
2448 (addrbits == 32 && !(sok & BITS32)) ||
2449 (addrbits == 64 && !(sok & BITS64)))
2450 goto err;
2451
2452 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2453 : ((ix & YMMREG & ~REG_EA)
2454 ? EA_YMMVSIB : EA_XMMVSIB));
2455
2456 output->rex |= rexflags(it, ix, REX_X);
2457 output->rex |= rexflags(bt, bx, REX_B);
2458 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2459
2460 index = it & 7; /* it is known to be != -1 */
2461
2462 switch (s) {
2463 case 1:
2464 scale = 0;
2465 break;
2466 case 2:
2467 scale = 1;
2468 break;
2469 case 4:
2470 scale = 2;
2471 break;
2472 case 8:
2473 scale = 3;
2474 break;
2475 default: /* then what the smeg is it? */
2476 goto err; /* panic */
2477 }
2478
2479 if (bt == -1) {
2480 base = 5;
2481 mod = 0;
2482 } else {
2483 base = (bt & 7);
2484 if (base != REG_NUM_EBP && o == 0 &&
2485 seg == NO_SEG && !forw_ref &&
2486 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2487 mod = 0;
2488 else if (IS_MOD_01())
2489 mod = 1;
2490 else
2491 mod = 2;
2492 }
2493
2494 output->sib_present = true;
2495 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2496 output->modrm = GEN_MODRM(mod, rfield, 4);
2497 output->sib = GEN_SIB(scale, index, base);
2498 } else if ((ix|bx) & (BITS32|BITS64)) {
2499 /*
2500 * it must be a 32/64-bit memory reference. Firstly we have
2501 * to check that all registers involved are type E/Rxx.
2502 */
2503 opflags_t sok = BITS32 | BITS64;
2504 int32_t o = input->offset;
2505
2506 if (it != -1) {
2507 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2508 sok &= ix;
2509 else
2510 goto err;
2511 }
2512
2513 if (bt != -1) {
2514 if (REG_GPR & ~bx)
2515 goto err; /* Invalid register */
2516 if (~sok & bx & SIZE_MASK)
2517 goto err; /* Invalid size */
2518 sok &= bx;
2519 }
2520
2521 /*
2522 * While we're here, ensure the user didn't specify
2523 * WORD or QWORD
2524 */
2525 if (input->disp_size == 16 || input->disp_size == 64)
2526 goto err;
2527
2528 if (addrbits == 16 ||
2529 (addrbits == 32 && !(sok & BITS32)) ||
2530 (addrbits == 64 && !(sok & BITS64)))
2531 goto err;
2532
2533 /* now reorganize base/index */
2534 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2535 ((hb == b && ht == EAH_NOTBASE) ||
2536 (hb == i && ht == EAH_MAKEBASE))) {
2537 /* swap if hints say so */
2538 t = bt, bt = it, it = t;
2539 x = bx, bx = ix, ix = x;
2540 }
2541 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2542 bt = -1, bx = 0, s++;
2543 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2544 /* make single reg base, unless hint */
2545 bt = it, bx = ix, it = -1, ix = 0;
2546 }
2547 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2548 s == 3 || s == 5 || s == 9) && bt == -1)
2549 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2550 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2551 (input->eaflags & EAF_TIMESTWO))
2552 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2553 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2554 if (s == 1 && it == REG_NUM_ESP) {
2555 /* swap ESP into base if scale is 1 */
2556 t = it, it = bt, bt = t;
2557 x = ix, ix = bx, bx = x;
2558 }
2559 if (it == REG_NUM_ESP ||
2560 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2561 goto err; /* wrong, for various reasons */
2562
2563 output->rex |= rexflags(it, ix, REX_X);
2564 output->rex |= rexflags(bt, bx, REX_B);
2565
2566 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2567 /* no SIB needed */
2568 int mod, rm;
2569
2570 if (bt == -1) {
2571 rm = 5;
2572 mod = 0;
2573 } else {
2574 rm = (bt & 7);
2575 if (rm != REG_NUM_EBP && o == 0 &&
2576 seg == NO_SEG && !forw_ref &&
2577 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2578 mod = 0;
2579 else if (IS_MOD_01())
2580 mod = 1;
2581 else
2582 mod = 2;
2583 }
2584
2585 output->sib_present = false;
2586 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2587 output->modrm = GEN_MODRM(mod, rfield, rm);
2588 } else {
2589 /* we need a SIB */
2590 int mod, scale, index, base;
2591
2592 if (it == -1)
2593 index = 4, s = 1;
2594 else
2595 index = (it & 7);
2596
2597 switch (s) {
2598 case 1:
2599 scale = 0;
2600 break;
2601 case 2:
2602 scale = 1;
2603 break;
2604 case 4:
2605 scale = 2;
2606 break;
2607 case 8:
2608 scale = 3;
2609 break;
2610 default: /* then what the smeg is it? */
2611 goto err; /* panic */
2612 }
2613
2614 if (bt == -1) {
2615 base = 5;
2616 mod = 0;
2617 } else {
2618 base = (bt & 7);
2619 if (base != REG_NUM_EBP && o == 0 &&
2620 seg == NO_SEG && !forw_ref &&
2621 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2622 mod = 0;
2623 else if (IS_MOD_01())
2624 mod = 1;
2625 else
2626 mod = 2;
2627 }
2628
2629 output->sib_present = true;
2630 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2631 output->modrm = GEN_MODRM(mod, rfield, 4);
2632 output->sib = GEN_SIB(scale, index, base);
2633 }
2634 } else { /* it's 16-bit */
2635 int mod, rm;
2636 int16_t o = input->offset;
2637
2638 /* check for 64-bit long mode */
2639 if (addrbits == 64)
2640 goto err;
2641
2642 /* check all registers are BX, BP, SI or DI */
2643 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2644 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2645 goto err;
2646
2647 /* ensure the user didn't specify DWORD/QWORD */
2648 if (input->disp_size == 32 || input->disp_size == 64)
2649 goto err;
2650
2651 if (s != 1 && i != -1)
2652 goto err; /* no can do, in 16-bit EA */
2653 if (b == -1 && i != -1) {
2654 int tmp = b;
2655 b = i;
2656 i = tmp;
2657 } /* swap */
2658 if ((b == R_SI || b == R_DI) && i != -1) {
2659 int tmp = b;
2660 b = i;
2661 i = tmp;
2662 }
2663 /* have BX/BP as base, SI/DI index */
2664 if (b == i)
2665 goto err; /* shouldn't ever happen, in theory */
2666 if (i != -1 && b != -1 &&
2667 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2668 goto err; /* invalid combinations */
2669 if (b == -1) /* pure offset: handled above */
2670 goto err; /* so if it gets to here, panic! */
2671
2672 rm = -1;
2673 if (i != -1)
2674 switch (i * 256 + b) {
2675 case R_SI * 256 + R_BX:
2676 rm = 0;
2677 break;
2678 case R_DI * 256 + R_BX:
2679 rm = 1;
2680 break;
2681 case R_SI * 256 + R_BP:
2682 rm = 2;
2683 break;
2684 case R_DI * 256 + R_BP:
2685 rm = 3;
2686 break;
2687 } else
2688 switch (b) {
2689 case R_SI:
2690 rm = 4;
2691 break;
2692 case R_DI:
2693 rm = 5;
2694 break;
2695 case R_BP:
2696 rm = 6;
2697 break;
2698 case R_BX:
2699 rm = 7;
2700 break;
2701 }
2702 if (rm == -1) /* can't happen, in theory */
2703 goto err; /* so panic if it does */
2704
2705 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2706 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2707 mod = 0;
2708 else if (IS_MOD_01())
2709 mod = 1;
2710 else
2711 mod = 2;
2712
2713 output->sib_present = false; /* no SIB - it's 16-bit */
2714 output->bytes = mod; /* bytes of offset needed */
2715 output->modrm = GEN_MODRM(mod, rfield, rm);
2716 }
2717 }
2718 }
2719
2720 output->size = 1 + output->sib_present + output->bytes;
2721 return output->type;
2722
2723 err:
2724 return output->type = EA_INVALID;
2725 }
2726
2727 static void add_asp(insn *ins, int addrbits)
2728 {
2729 int j, valid;
2730 int defdisp;
2731
2732 valid = (addrbits == 64) ? 64|32 : 32|16;
2733
2734 switch (ins->prefixes[PPS_ASIZE]) {
2735 case P_A16:
2736 valid &= 16;
2737 break;
2738 case P_A32:
2739 valid &= 32;
2740 break;
2741 case P_A64:
2742 valid &= 64;
2743 break;
2744 case P_ASP:
2745 valid &= (addrbits == 32) ? 16 : 32;
2746 break;
2747 default:
2748 break;
2749 }
2750
2751 for (j = 0; j < ins->operands; j++) {
2752 if (is_class(MEMORY, ins->oprs[j].type)) {
2753 opflags_t i, b;
2754
2755 /* Verify as Register */
2756 if (!is_register(ins->oprs[j].indexreg))
2757 i = 0;
2758 else
2759 i = nasm_reg_flags[ins->oprs[j].indexreg];
2760
2761 /* Verify as Register */
2762 if (!is_register(ins->oprs[j].basereg))
2763 b = 0;
2764 else
2765 b = nasm_reg_flags[ins->oprs[j].basereg];
2766
2767 if (ins->oprs[j].scale == 0)
2768 i = 0;
2769
2770 if (!i && !b) {
2771 int ds = ins->oprs[j].disp_size;
2772 if ((addrbits != 64 && ds > 8) ||
2773 (addrbits == 64 && ds == 16))
2774 valid &= ds;
2775 } else {
2776 if (!(REG16 & ~b))
2777 valid &= 16;
2778 if (!(REG32 & ~b))
2779 valid &= 32;
2780 if (!(REG64 & ~b))
2781 valid &= 64;
2782
2783 if (!(REG16 & ~i))
2784 valid &= 16;
2785 if (!(REG32 & ~i))
2786 valid &= 32;
2787 if (!(REG64 & ~i))
2788 valid &= 64;
2789 }
2790 }
2791 }
2792
2793 if (valid & addrbits) {
2794 ins->addr_size = addrbits;
2795 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2796 /* Add an address size prefix */
2797 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2798 ins->addr_size = (addrbits == 32) ? 16 : 32;
2799 } else {
2800 /* Impossible... */
2801 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2802 ins->addr_size = addrbits; /* Error recovery */
2803 }
2804
2805 defdisp = ins->addr_size == 16 ? 16 : 32;
2806
2807 for (j = 0; j < ins->operands; j++) {
2808 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2809 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2810 /*
2811 * mem_offs sizes must match the address size; if not,
2812 * strip the MEM_OFFS bit and match only EA instructions
2813 */
2814 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2815 }
2816 }
2817 }
The Netwide Assembler