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AVX: implement all the convert instructions...
[nasm.git] / disasm.c
blob378596a9677924fdd9f05fd8da16c3ddccf416be
1 /* disasm.c where all the _work_ gets done in the Netwide Disassembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
7 *
8 * initial version 27/iii/95 by Simon Tatham
9 */
10
11 #include "compiler.h"
12
13 #include <stdio.h>
14 #include <string.h>
15 #include <limits.h>
16 #include <inttypes.h>
17
18 #include "nasm.h"
19 #include "disasm.h"
20 #include "sync.h"
21 #include "insns.h"
22 #include "tables.h"
23 #include "regdis.h"
24
25 /*
26 * Flags that go into the `segment' field of `insn' structures
27 * during disassembly.
28 */
29 #define SEG_RELATIVE 1
30 #define SEG_32BIT 2
31 #define SEG_RMREG 4
32 #define SEG_DISP8 8
33 #define SEG_DISP16 16
34 #define SEG_DISP32 32
35 #define SEG_NODISP 64
36 #define SEG_SIGNED 128
37 #define SEG_64BIT 256
38
39 /*
40 * Prefix information
41 */
42 struct prefix_info {
43 uint8_t osize; /* Operand size */
44 uint8_t asize; /* Address size */
45 uint8_t osp; /* Operand size prefix present */
46 uint8_t asp; /* Address size prefix present */
47 uint8_t rep; /* Rep prefix present */
48 uint8_t seg; /* Segment override prefix present */
49 uint8_t lock; /* Lock prefix present */
50 uint8_t vex[3]; /* VEX prefix present */
51 uint8_t vex_m; /* VEX.M field */
52 uint8_t vex_v;
53 uint8_t vex_lp; /* VEX.LP fields */
54 uint32_t rex; /* REX prefix present */
55 };
56
57 #define getu8(x) (*(uint8_t *)(x))
58 #if X86_MEMORY
59 /* Littleendian CPU which can handle unaligned references */
60 #define getu16(x) (*(uint16_t *)(x))
61 #define getu32(x) (*(uint32_t *)(x))
62 #define getu64(x) (*(uint64_t *)(x))
63 #else
64 static uint16_t getu16(uint8_t *data)
65 {
66 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
67 }
68 static uint32_t getu32(uint8_t *data)
69 {
70 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
71 }
72 static uint64_t getu64(uint8_t *data)
73 {
74 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
75 }
76 #endif
77
78 #define gets8(x) ((int8_t)getu8(x))
79 #define gets16(x) ((int16_t)getu16(x))
80 #define gets32(x) ((int32_t)getu32(x))
81 #define gets64(x) ((int64_t)getu64(x))
82
83 /* Important: regval must already have been adjusted for rex extensions */
84 static enum reg_enum whichreg(int32_t regflags, int regval, int rex)
85 {
86 if (!(regflags & (REGISTER|REGMEM)))
87 return 0; /* Registers not permissible?! */
88
89 regflags |= REGISTER;
90
91 if (!(REG_AL & ~regflags))
92 return R_AL;
93 if (!(REG_AX & ~regflags))
94 return R_AX;
95 if (!(REG_EAX & ~regflags))
96 return R_EAX;
97 if (!(REG_RAX & ~regflags))
98 return R_RAX;
99 if (!(REG_DL & ~regflags))
100 return R_DL;
101 if (!(REG_DX & ~regflags))
102 return R_DX;
103 if (!(REG_EDX & ~regflags))
104 return R_EDX;
105 if (!(REG_RDX & ~regflags))
106 return R_RDX;
107 if (!(REG_CL & ~regflags))
108 return R_CL;
109 if (!(REG_CX & ~regflags))
110 return R_CX;
111 if (!(REG_ECX & ~regflags))
112 return R_ECX;
113 if (!(REG_RCX & ~regflags))
114 return R_RCX;
115 if (!(FPU0 & ~regflags))
116 return R_ST0;
117 if (!(REG_CS & ~regflags))
118 return (regval == 1) ? R_CS : 0;
119 if (!(REG_DESS & ~regflags))
120 return (regval == 0 || regval == 2
121 || regval == 3 ? nasm_rd_sreg[regval] : 0);
122 if (!(REG_FSGS & ~regflags))
123 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
124 if (!(REG_SEG67 & ~regflags))
125 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
126
127 /* All the entries below look up regval in an 16-entry array */
128 if (regval < 0 || regval > 15)
129 return 0;
130
131 if (!(REG8 & ~regflags)) {
132 if (rex & REX_P)
133 return nasm_rd_reg8_rex[regval];
134 else
135 return nasm_rd_reg8[regval];
136 }
137 if (!(REG16 & ~regflags))
138 return nasm_rd_reg16[regval];
139 if (!(REG32 & ~regflags))
140 return nasm_rd_reg32[regval];
141 if (!(REG64 & ~regflags))
142 return nasm_rd_reg64[regval];
143 if (!(REG_SREG & ~regflags))
144 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
145 if (!(REG_CREG & ~regflags))
146 return nasm_rd_creg[regval];
147 if (!(REG_DREG & ~regflags))
148 return nasm_rd_dreg[regval];
149 if (!(REG_TREG & ~regflags)) {
150 if (rex & REX_P)
151 return 0; /* TR registers are ill-defined with rex */
152 return nasm_rd_treg[regval];
153 }
154 if (!(FPUREG & ~regflags))
155 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
156 if (!(MMXREG & ~regflags))
157 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
158 if (!(XMMREG & ~regflags))
159 return nasm_rd_xmmreg[regval];
160 if (!(YMMREG & ~regflags))
161 return nasm_rd_ymmreg[regval];
162
163 return 0;
164 }
165
166 /*
167 * Process a DREX suffix
168 */
169 static uint8_t *do_drex(uint8_t *data, insn *ins)
170 {
171 uint8_t drex = *data++;
172 operand *dst = &ins->oprs[ins->drexdst];
173
174 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
175 return NULL; /* OC0 mismatch */
176 ins->rex = (ins->rex & ~7) | (drex & 7);
177
178 dst->segment = SEG_RMREG;
179 dst->basereg = drex >> 4;
180 return data;
181 }
182
183
184 /*
185 * Process an effective address (ModRM) specification.
186 */
187 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
188 int segsize, operand * op, insn *ins)
189 {
190 int mod, rm, scale, index, base;
191 int rex;
192 uint8_t sib = 0;
193
194 mod = (modrm >> 6) & 03;
195 rm = modrm & 07;
196
197 if (mod != 3 && rm == 4 && asize != 16)
198 sib = *data++;
199
200 if (ins->rex & REX_D) {
201 data = do_drex(data, ins);
202 if (!data)
203 return NULL;
204 }
205 rex = ins->rex;
206
207 if (mod == 3) { /* pure register version */
208 op->basereg = rm+(rex & REX_B ? 8 : 0);
209 op->segment |= SEG_RMREG;
210 return data;
211 }
212
213 op->disp_size = 0;
214 op->eaflags = 0;
215
216 if (asize == 16) {
217 /*
218 * <mod> specifies the displacement size (none, byte or
219 * word), and <rm> specifies the register combination.
220 * Exception: mod=0,rm=6 does not specify [BP] as one might
221 * expect, but instead specifies [disp16].
222 */
223 op->indexreg = op->basereg = -1;
224 op->scale = 1; /* always, in 16 bits */
225 switch (rm) {
226 case 0:
227 op->basereg = R_BX;
228 op->indexreg = R_SI;
229 break;
230 case 1:
231 op->basereg = R_BX;
232 op->indexreg = R_DI;
233 break;
234 case 2:
235 op->basereg = R_BP;
236 op->indexreg = R_SI;
237 break;
238 case 3:
239 op->basereg = R_BP;
240 op->indexreg = R_DI;
241 break;
242 case 4:
243 op->basereg = R_SI;
244 break;
245 case 5:
246 op->basereg = R_DI;
247 break;
248 case 6:
249 op->basereg = R_BP;
250 break;
251 case 7:
252 op->basereg = R_BX;
253 break;
254 }
255 if (rm == 6 && mod == 0) { /* special case */
256 op->basereg = -1;
257 if (segsize != 16)
258 op->disp_size = 16;
259 mod = 2; /* fake disp16 */
260 }
261 switch (mod) {
262 case 0:
263 op->segment |= SEG_NODISP;
264 break;
265 case 1:
266 op->segment |= SEG_DISP8;
267 op->offset = (int8_t)*data++;
268 break;
269 case 2:
270 op->segment |= SEG_DISP16;
271 op->offset = *data++;
272 op->offset |= ((unsigned)*data++) << 8;
273 break;
274 }
275 return data;
276 } else {
277 /*
278 * Once again, <mod> specifies displacement size (this time
279 * none, byte or *dword*), while <rm> specifies the base
280 * register. Again, [EBP] is missing, replaced by a pure
281 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
282 * and RIP-relative addressing in 64-bit mode.
283 *
284 * However, rm=4
285 * indicates not a single base register, but instead the
286 * presence of a SIB byte...
287 */
288 int a64 = asize == 64;
289
290 op->indexreg = -1;
291
292 if (a64)
293 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
294 else
295 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
296
297 if (rm == 5 && mod == 0) {
298 if (segsize == 64) {
299 op->eaflags |= EAF_REL;
300 op->segment |= SEG_RELATIVE;
301 mod = 2; /* fake disp32 */
302 }
303
304 if (asize != 64)
305 op->disp_size = asize;
306
307 op->basereg = -1;
308 mod = 2; /* fake disp32 */
309 }
310
311 if (rm == 4) { /* process SIB */
312 scale = (sib >> 6) & 03;
313 index = (sib >> 3) & 07;
314 base = sib & 07;
315
316 op->scale = 1 << scale;
317
318 if (index == 4)
319 op->indexreg = -1; /* ESP/RSP/R12 cannot be an index */
320 else if (a64)
321 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
322 else
323 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
324
325 if (base == 5 && mod == 0) {
326 op->basereg = -1;
327 mod = 2; /* Fake disp32 */
328 } else if (a64)
329 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
330 else
331 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
332
333 if (segsize == 16)
334 op->disp_size = 32;
335 }
336
337 switch (mod) {
338 case 0:
339 op->segment |= SEG_NODISP;
340 break;
341 case 1:
342 op->segment |= SEG_DISP8;
343 op->offset = gets8(data);
344 data++;
345 break;
346 case 2:
347 op->segment |= SEG_DISP32;
348 op->offset = gets32(data);
349 data += 4;
350 break;
351 }
352 return data;
353 }
354 }
355
356 /*
357 * Determine whether the instruction template in t corresponds to the data
358 * stream in data. Return the number of bytes matched if so.
359 */
360 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
361
362 static int matches(const struct itemplate *t, uint8_t *data,
363 const struct prefix_info *prefix, int segsize, insn *ins)
364 {
365 uint8_t *r = (uint8_t *)(t->code);
366 uint8_t *origdata = data;
367 bool a_used = false, o_used = false;
368 enum prefixes drep = 0;
369 uint8_t lock = prefix->lock;
370 int osize = prefix->osize;
371 int asize = prefix->asize;
372 int i, c;
373 struct operand *opx;
374 int s_field_for = -1; /* No 144/154 series code encountered */
375
376 for (i = 0; i < MAX_OPERANDS; i++) {
377 ins->oprs[i].segment = ins->oprs[i].disp_size =
378 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
379 }
380 ins->condition = -1;
381 ins->rex = prefix->rex;
382 memset(ins->prefixes, 0, sizeof ins->prefixes);
383
384 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
385 return false;
386
387 if (prefix->rep == 0xF2)
388 drep = P_REPNE;
389 else if (prefix->rep == 0xF3)
390 drep = P_REP;
391
392 while ((c = *r++) != 0) {
393 opx = &ins->oprs[c & 3];
394
395 switch (c) {
396 case 01:
397 case 02:
398 case 03:
399 while (c--)
400 if (*r++ != *data++)
401 return false;
402 break;
403
404 case 04:
405 switch (*data++) {
406 case 0x07:
407 ins->oprs[0].basereg = 0;
408 break;
409 case 0x17:
410 ins->oprs[0].basereg = 2;
411 break;
412 case 0x1F:
413 ins->oprs[0].basereg = 3;
414 break;
415 default:
416 return false;
417 }
418 break;
419
420 case 05:
421 switch (*data++) {
422 case 0xA1:
423 ins->oprs[0].basereg = 4;
424 break;
425 case 0xA9:
426 ins->oprs[0].basereg = 5;
427 break;
428 default:
429 return false;
430 }
431 break;
432
433 case 06:
434 switch (*data++) {
435 case 0x06:
436 ins->oprs[0].basereg = 0;
437 break;
438 case 0x0E:
439 ins->oprs[0].basereg = 1;
440 break;
441 case 0x16:
442 ins->oprs[0].basereg = 2;
443 break;
444 case 0x1E:
445 ins->oprs[0].basereg = 3;
446 break;
447 default:
448 return false;
449 }
450 break;
451
452 case 07:
453 switch (*data++) {
454 case 0xA0:
455 ins->oprs[0].basereg = 4;
456 break;
457 case 0xA8:
458 ins->oprs[0].basereg = 5;
459 break;
460 default:
461 return false;
462 }
463 break;
464
465 case4(010):
466 {
467 int t = *r++, d = *data++;
468 if (d < t || d > t + 7)
469 return false;
470 else {
471 opx->basereg = (d-t)+
472 (ins->rex & REX_B ? 8 : 0);
473 opx->segment |= SEG_RMREG;
474 }
475 break;
476 }
477
478 case4(014):
479 opx->offset = (int8_t)*data++;
480 opx->segment |= SEG_SIGNED;
481 break;
482
483 case4(020):
484 opx->offset = *data++;
485 break;
486
487 case4(024):
488 opx->offset = *data++;
489 break;
490
491 case4(030):
492 opx->offset = getu16(data);
493 data += 2;
494 break;
495
496 case4(034):
497 if (osize == 32) {
498 opx->offset = getu32(data);
499 data += 4;
500 } else {
501 opx->offset = getu16(data);
502 data += 2;
503 }
504 if (segsize != asize)
505 opx->disp_size = asize;
506 break;
507
508 case4(040):
509 opx->offset = getu32(data);
510 data += 4;
511 break;
512
513 case4(044):
514 switch (asize) {
515 case 16:
516 opx->offset = getu16(data);
517 data += 2;
518 if (segsize != 16)
519 opx->disp_size = 16;
520 break;
521 case 32:
522 opx->offset = getu32(data);
523 data += 4;
524 if (segsize == 16)
525 opx->disp_size = 32;
526 break;
527 case 64:
528 opx->offset = getu64(data);
529 opx->disp_size = 64;
530 data += 8;
531 break;
532 }
533 break;
534
535 case4(050):
536 opx->offset = gets8(data++);
537 opx->segment |= SEG_RELATIVE;
538 break;
539
540 case4(054):
541 opx->offset = getu64(data);
542 data += 8;
543 break;
544
545 case4(060):
546 opx->offset = gets16(data);
547 data += 2;
548 opx->segment |= SEG_RELATIVE;
549 opx->segment &= ~SEG_32BIT;
550 break;
551
552 case4(064):
553 opx->segment |= SEG_RELATIVE;
554 if (osize == 16) {
555 opx->offset = gets16(data);
556 data += 2;
557 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
558 } else if (osize == 32) {
559 opx->offset = gets32(data);
560 data += 4;
561 opx->segment &= ~SEG_64BIT;
562 opx->segment |= SEG_32BIT;
563 }
564 if (segsize != osize) {
565 opx->type =
566 (opx->type & ~SIZE_MASK)
567 | ((osize == 16) ? BITS16 : BITS32);
568 }
569 break;
570
571 case4(070):
572 opx->offset = gets32(data);
573 data += 4;
574 opx->segment |= SEG_32BIT | SEG_RELATIVE;
575 break;
576
577 case4(0100):
578 case4(0110):
579 case4(0120):
580 case4(0130):
581 {
582 int modrm = *data++;
583 opx->segment |= SEG_RMREG;
584 data = do_ea(data, modrm, asize, segsize,
585 &ins->oprs[(c >> 3) & 3], ins);
586 if (!data)
587 return false;
588 opx->basereg = ((modrm >> 3)&7)+
589 (ins->rex & REX_R ? 8 : 0);
590 break;
591 }
592
593 case4(0140):
594 if (s_field_for == (c & 3)) {
595 opx->offset = gets8(data);
596 data++;
597 } else {
598 opx->offset = getu16(data);
599 data += 2;
600 }
601 break;
602
603 case4(0144):
604 case4(0154):
605 s_field_for = (*data & 0x02) ? c & 3 : -1;
606 if ((*data++ & ~0x02) != *r++)
607 return false;
608 break;
609
610 case4(0150):
611 if (s_field_for == (c & 3)) {
612 opx->offset = gets8(data);
613 data++;
614 } else {
615 opx->offset = getu32(data);
616 data += 4;
617 }
618 break;
619
620 case4(0160):
621 ins->rex |= REX_D;
622 ins->drexdst = c & 3;
623 break;
624
625 case4(0164):
626 ins->rex |= REX_D|REX_OC;
627 ins->drexdst = c & 3;
628 break;
629
630 case 0171:
631 data = do_drex(data, ins);
632 if (!data)
633 return false;
634 break;
635
636 case 0172:
637 {
638 uint8_t ximm = *data++;
639 c = *r++;
640 ins->oprs[c >> 3].basereg = ximm >> 4;
641 ins->oprs[c >> 3].segment |= SEG_RMREG;
642 ins->oprs[c & 7].offset = ximm & 15;
643 }
644 break;
645
646 case 0173:
647 {
648 uint8_t ximm = *data++;
649 c = *r++;
650
651 if ((c ^ ximm) & 15)
652 return false;
653
654 ins->oprs[c >> 4].basereg = ximm >> 4;
655 ins->oprs[c >> 4].segment |= SEG_RMREG;
656 }
657 break;
658
659 case4(0200):
660 case4(0204):
661 case4(0210):
662 case4(0214):
663 case4(0220):
664 case4(0224):
665 case4(0230):
666 case4(0234):
667 {
668 int modrm = *data++;
669 if (((modrm >> 3) & 07) != (c & 07))
670 return false; /* spare field doesn't match up */
671 data = do_ea(data, modrm, asize, segsize,
672 &ins->oprs[(c >> 3) & 07], ins);
673 if (!data)
674 return false;
675 break;
676 }
677
678 case4(0260):
679 {
680 int vexm = *r++;
681 int vexwlp = *r++;
682 ins->rex |= REX_V;
683 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
684 return false;
685
686 if ((vexm & 0x1f) != prefix->vex_m)
687 return false;
688
689 switch (vexwlp & 030) {
690 case 000:
691 if (prefix->rex & REX_W)
692 return false;
693 break;
694 case 010:
695 if (!(prefix->rex & REX_W))
696 return false;
697 break;
698 default:
699 break; /* XXX: Need to do anything special here? */
700 }
701
702 if ((vexwlp & 007) != prefix->vex_lp)
703 return false;
704
705 opx->segment |= SEG_RMREG;
706 opx->basereg = prefix->vex_v;
707 break;
708 }
709
710 case 0270:
711 {
712 int vexm = *r++;
713 int vexwlp = *r++;
714 ins->rex |= REX_V;
715 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
716 return false;
717
718 if ((vexm & 0x1f) != prefix->vex_m)
719 return false;
720
721 switch (vexwlp & 030) {
722 case 000:
723 if (ins->rex & REX_W)
724 return false;
725 break;
726 case 010:
727 if (!(ins->rex & REX_W))
728 return false;
729 break;
730 default:
731 break; /* Need to do anything special here? */
732 }
733
734 if ((vexwlp & 007) != prefix->vex_lp)
735 return false;
736
737 if (prefix->vex_v != 0)
738 return false;
739
740 break;
741 }
742
743 case 0310:
744 if (asize != 16)
745 return false;
746 else
747 a_used = true;
748 break;
749
750 case 0311:
751 if (asize == 16)
752 return false;
753 else
754 a_used = true;
755 break;
756
757 case 0312:
758 if (asize != segsize)
759 return false;
760 else
761 a_used = true;
762 break;
763
764 case 0313:
765 if (asize != 64)
766 return false;
767 else
768 a_used = true;
769 break;
770
771 case 0314:
772 if (prefix->rex & REX_B)
773 return false;
774 break;
775
776 case 0315:
777 if (prefix->rex & REX_X)
778 return false;
779 break;
780
781 case 0316:
782 if (prefix->rex & REX_R)
783 return false;
784 break;
785
786 case 0317:
787 if (prefix->rex & REX_W)
788 return false;
789 break;
790
791 case 0320:
792 if (osize != 16)
793 return false;
794 else
795 o_used = true;
796 break;
797
798 case 0321:
799 if (osize != 32)
800 return false;
801 else
802 o_used = true;
803 break;
804
805 case 0322:
806 if (osize != (segsize == 16) ? 16 : 32)
807 return false;
808 else
809 o_used = true;
810 break;
811
812 case 0323:
813 ins->rex |= REX_W; /* 64-bit only instruction */
814 osize = 64;
815 o_used = true;
816 break;
817
818 case 0324:
819 if (!(ins->rex & (REX_P|REX_W)) || osize != 64)
820 return false;
821 o_used = true;
822 break;
823
824 case 0330:
825 {
826 int t = *r++, d = *data++;
827 if (d < t || d > t + 15)
828 return false;
829 else
830 ins->condition = d - t;
831 break;
832 }
833
834 case 0331:
835 if (prefix->rep)
836 return false;
837 break;
838
839 case 0332:
840 if (prefix->rep != 0xF2)
841 return false;
842 drep = 0;
843 break;
844
845 case 0333:
846 if (prefix->rep != 0xF3)
847 return false;
848 drep = 0;
849 break;
850
851 case 0334:
852 if (lock) {
853 ins->rex |= REX_R;
854 lock = 0;
855 }
856 break;
857
858 case 0335:
859 if (drep == P_REP)
860 drep = P_REPE;
861 break;
862
863 case 0340:
864 return false;
865
866 case 0360:
867 if (prefix->osp || prefix->rep)
868 return false;
869 break;
870
871 case 0361:
872 if (!prefix->osp || prefix->rep)
873 return false;
874 break;
875
876 case 0362:
877 if (prefix->osp || prefix->rep != 0xf2)
878 return false;
879 break;
880
881 case 0363:
882 if (prefix->osp || prefix->rep != 0xf3)
883 return false;
884 break;
885
886 case 0364:
887 if (prefix->osp)
888 return false;
889 break;
890
891 case 0365:
892 if (prefix->asp)
893 return false;
894 break;
895
896 case 0366:
897 if (!prefix->osp)
898 return false;
899 o_used = true;
900 break;
901
902 case 0367:
903 if (!prefix->asp)
904 return false;
905 a_used = true;
906 break;
907
908 default:
909 return false; /* Unknown code */
910 }
911 }
912
913 /* REX cannot be combined with DREX or VEX */
914 if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
915 return false;
916
917 /*
918 * Check for unused rep or a/o prefixes.
919 */
920 for (i = 0; i < t->operands; i++) {
921 if (ins->oprs[i].segment != SEG_RMREG)
922 a_used = true;
923 }
924
925 if (lock) {
926 if (ins->prefixes[PPS_LREP])
927 return false;
928 ins->prefixes[PPS_LREP] = P_LOCK;
929 }
930 if (drep) {
931 if (ins->prefixes[PPS_LREP])
932 return false;
933 ins->prefixes[PPS_LREP] = drep;
934 }
935 if (!o_used) {
936 if (osize != ((segsize == 16) ? 16 : 32)) {
937 enum prefixes pfx = 0;
938
939 switch (osize) {
940 case 16:
941 pfx = P_O16;
942 break;
943 case 32:
944 pfx = P_O32;
945 break;
946 case 64:
947 pfx = P_O64;
948 break;
949 }
950
951 if (ins->prefixes[PPS_OSIZE])
952 return false;
953 ins->prefixes[PPS_OSIZE] = pfx;
954 }
955 }
956 if (!a_used && asize != segsize) {
957 if (ins->prefixes[PPS_ASIZE])
958 return false;
959 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
960 }
961
962 /* Fix: check for redundant REX prefixes */
963
964 return data - origdata;
965 }
966
967 /* Condition names for disassembly, sorted by x86 code */
968 static const char * const condition_name[16] = {
969 "o", "no", "c", "nc", "z", "nz", "na", "a",
970 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
971 };
972
973 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
974 int32_t offset, int autosync, uint32_t prefer)
975 {
976 const struct itemplate * const *p, * const *best_p;
977 const struct disasm_index *ix;
978 uint8_t *dp;
979 int length, best_length = 0;
980 char *segover;
981 int i, slen, colon, n;
982 uint8_t *origdata;
983 int works;
984 insn tmp_ins, ins;
985 uint32_t goodness, best;
986 int best_pref;
987 struct prefix_info prefix;
988 bool end_prefix;
989
990 memset(&ins, 0, sizeof ins);
991
992 /*
993 * Scan for prefixes.
994 */
995 memset(&prefix, 0, sizeof prefix);
996 prefix.asize = segsize;
997 prefix.osize = (segsize == 64) ? 32 : segsize;
998 segover = NULL;
999 origdata = data;
1000
1001 end_prefix = false;
1002 while (!end_prefix) {
1003 switch (*data) {
1004 case 0xF2:
1005 case 0xF3:
1006 prefix.rep = *data++;
1007 break;
1008 case 0xF0:
1009 prefix.lock = *data++;
1010 break;
1011 case 0x2E:
1012 segover = "cs", prefix.seg = *data++;
1013 break;
1014 case 0x36:
1015 segover = "ss", prefix.seg = *data++;
1016 break;
1017 case 0x3E:
1018 segover = "ds", prefix.seg = *data++;
1019 break;
1020 case 0x26:
1021 segover = "es", prefix.seg = *data++;
1022 break;
1023 case 0x64:
1024 segover = "fs", prefix.seg = *data++;
1025 break;
1026 case 0x65:
1027 segover = "gs", prefix.seg = *data++;
1028 break;
1029 case 0x66:
1030 prefix.osize = (segsize == 16) ? 32 : 16;
1031 prefix.osp = *data++;
1032 break;
1033 case 0x67:
1034 prefix.asize = (segsize == 32) ? 16 : 32;
1035 prefix.asp = *data++;
1036 break;
1037 case 0xC4:
1038 case 0xC5:
1039 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1040 prefix.vex[0] = *data++;
1041 prefix.vex[1] = *data++;
1042 if (prefix.vex[0] == 0xc4)
1043 prefix.vex[2] = *data++;
1044 }
1045 prefix.rex = REX_V;
1046 if (prefix.vex[0] == 0xc4) {
1047 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1048 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1049 prefix.vex_m = prefix.vex[1] & 0x1f;
1050 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1051 prefix.vex_lp = prefix.vex[2] & 7;
1052 } else {
1053 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1054 prefix.vex_m = 1;
1055 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1056 prefix.vex_lp = prefix.vex[1] & 7;
1057 }
1058 end_prefix = true;
1059 break;
1060 case REX_P + 0x0:
1061 case REX_P + 0x1:
1062 case REX_P + 0x2:
1063 case REX_P + 0x3:
1064 case REX_P + 0x4:
1065 case REX_P + 0x5:
1066 case REX_P + 0x6:
1067 case REX_P + 0x7:
1068 case REX_P + 0x8:
1069 case REX_P + 0x9:
1070 case REX_P + 0xA:
1071 case REX_P + 0xB:
1072 case REX_P + 0xC:
1073 case REX_P + 0xD:
1074 case REX_P + 0xE:
1075 case REX_P + 0xF:
1076 if (segsize == 64) {
1077 prefix.rex = *data++;
1078 if (prefix.rex & REX_W)
1079 prefix.osize = 64;
1080 }
1081 end_prefix = true;
1082 break;
1083 default:
1084 end_prefix = true;
1085 break;
1086 }
1087 }
1088
1089 best = -1; /* Worst possible */
1090 best_p = NULL;
1091 best_pref = INT_MAX;
1092
1093 dp = data;
1094 ix = itable + *dp++;
1095 while (ix->n == -1) {
1096 ix = (const struct disasm_index *)ix->p + *dp++;
1097 }
1098
1099 p = (const struct itemplate * const *)ix->p;
1100 for (n = ix->n; n; n--, p++) {
1101 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1102 works = true;
1103 /*
1104 * Final check to make sure the types of r/m match up.
1105 * XXX: Need to make sure this is actually correct.
1106 */
1107 for (i = 0; i < (*p)->operands; i++) {
1108 if (!((*p)->opd[i] & SAME_AS) &&
1109 (
1110 /* If it's a mem-only EA but we have a
1111 register, die. */
1112 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1113 !(MEMORY & ~(*p)->opd[i])) ||
1114 /* If it's a reg-only EA but we have a memory
1115 ref, die. */
1116 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1117 !(REG_EA & ~(*p)->opd[i]) &&
1118 !((*p)->opd[i] & REG_SMASK)) ||
1119 /* Register type mismatch (eg FS vs REG_DESS):
1120 die. */
1121 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1122 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1123 !whichreg((*p)->opd[i],
1124 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1125 )) {
1126 works = false;
1127 break;
1128 }
1129 }
1130
1131 /*
1132 * Note: we always prefer instructions which incorporate
1133 * prefixes in the instructions themselves. This is to allow
1134 * e.g. PAUSE to be preferred to REP NOP, and deal with
1135 * MMX/SSE instructions where prefixes are used to select
1136 * between MMX and SSE register sets or outright opcode
1137 * selection.
1138 */
1139 if (works) {
1140 int i, nprefix;
1141 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1142 nprefix = 0;
1143 for (i = 0; i < MAXPREFIX; i++)
1144 if (tmp_ins.prefixes[i])
1145 nprefix++;
1146 if (nprefix < best_pref ||
1147 (nprefix == best_pref && goodness < best)) {
1148 /* This is the best one found so far */
1149 best = goodness;
1150 best_p = p;
1151 best_pref = nprefix;
1152 best_length = length;
1153 ins = tmp_ins;
1154 }
1155 }
1156 }
1157 }
1158
1159 if (!best_p)
1160 return 0; /* no instruction was matched */
1161
1162 /* Pick the best match */
1163 p = best_p;
1164 length = best_length;
1165
1166 slen = 0;
1167
1168 /* TODO: snprintf returns the value that the string would have if
1169 * the buffer were long enough, and not the actual length of
1170 * the returned string, so each instance of using the return
1171 * value of snprintf should actually be checked to assure that
1172 * the return value is "sane." Maybe a macro wrapper could
1173 * be used for that purpose.
1174 */
1175 for (i = 0; i < MAXPREFIX; i++)
1176 switch (ins.prefixes[i]) {
1177 case P_LOCK:
1178 slen += snprintf(output + slen, outbufsize - slen, "lock ");
1179 break;
1180 case P_REP:
1181 slen += snprintf(output + slen, outbufsize - slen, "rep ");
1182 break;
1183 case P_REPE:
1184 slen += snprintf(output + slen, outbufsize - slen, "repe ");
1185 break;
1186 case P_REPNE:
1187 slen += snprintf(output + slen, outbufsize - slen, "repne ");
1188 break;
1189 case P_A16:
1190 slen += snprintf(output + slen, outbufsize - slen, "a16 ");
1191 break;
1192 case P_A32:
1193 slen += snprintf(output + slen, outbufsize - slen, "a32 ");
1194 break;
1195 case P_A64:
1196 slen += snprintf(output + slen, outbufsize - slen, "a64 ");
1197 break;
1198 case P_O16:
1199 slen += snprintf(output + slen, outbufsize - slen, "o16 ");
1200 break;
1201 case P_O32:
1202 slen += snprintf(output + slen, outbufsize - slen, "o32 ");
1203 break;
1204 case P_O64:
1205 slen += snprintf(output + slen, outbufsize - slen, "o64 ");
1206 break;
1207 default:
1208 break;
1209 }
1210
1211 i = (*p)->opcode;
1212 if (i >= FIRST_COND_OPCODE) {
1213 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1214 nasm_cond_insn_names[i-FIRST_COND_OPCODE],
1215 condition_name[ins.condition]);
1216 } else {
1217 slen += snprintf(output + slen, outbufsize - slen, "%s",
1218 nasm_insn_names[i]);
1219 }
1220 colon = false;
1221 length += data - origdata; /* fix up for prefixes */
1222 for (i = 0; i < (*p)->operands; i++) {
1223 opflags_t t = (*p)->opd[i];
1224 const operand *o = &ins.oprs[i];
1225 int64_t offs;
1226
1227 if (t & SAME_AS) {
1228 o = &ins.oprs[t & ~SAME_AS];
1229 t = (*p)->opd[t & ~SAME_AS];
1230 }
1231
1232 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1233
1234 offs = o->offset;
1235 if (o->segment & SEG_RELATIVE) {
1236 offs += offset + length;
1237 /*
1238 * sort out wraparound
1239 */
1240 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1241 offs &= 0xffff;
1242 else if (segsize != 64)
1243 offs &= 0xffffffff;
1244
1245 /*
1246 * add sync marker, if autosync is on
1247 */
1248 if (autosync)
1249 add_sync(offs, 0L);
1250 }
1251
1252 if (t & COLON)
1253 colon = true;
1254 else
1255 colon = false;
1256
1257 if ((t & (REGISTER | FPUREG)) ||
1258 (o->segment & SEG_RMREG)) {
1259 enum reg_enum reg;
1260 reg = whichreg(t, o->basereg, ins.rex);
1261 if (t & TO)
1262 slen += snprintf(output + slen, outbufsize - slen, "to ");
1263 slen += snprintf(output + slen, outbufsize - slen, "%s",
1264 nasm_reg_names[reg-EXPR_REG_START]);
1265 } else if (!(UNITY & ~t)) {
1266 output[slen++] = '1';
1267 } else if (t & IMMEDIATE) {
1268 if (t & BITS8) {
1269 slen +=
1270 snprintf(output + slen, outbufsize - slen, "byte ");
1271 if (o->segment & SEG_SIGNED) {
1272 if (offs < 0) {
1273 offs *= -1;
1274 output[slen++] = '-';
1275 } else
1276 output[slen++] = '+';
1277 }
1278 } else if (t & BITS16) {
1279 slen +=
1280 snprintf(output + slen, outbufsize - slen, "word ");
1281 } else if (t & BITS32) {
1282 slen +=
1283 snprintf(output + slen, outbufsize - slen, "dword ");
1284 } else if (t & BITS64) {
1285 slen +=
1286 snprintf(output + slen, outbufsize - slen, "qword ");
1287 } else if (t & NEAR) {
1288 slen +=
1289 snprintf(output + slen, outbufsize - slen, "near ");
1290 } else if (t & SHORT) {
1291 slen +=
1292 snprintf(output + slen, outbufsize - slen, "short ");
1293 }
1294 slen +=
1295 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1296 offs);
1297 } else if (!(MEM_OFFS & ~t)) {
1298 slen +=
1299 snprintf(output + slen, outbufsize - slen,
1300 "[%s%s%s0x%"PRIx64"]",
1301 (segover ? segover : ""),
1302 (segover ? ":" : ""),
1303 (o->disp_size == 64 ? "qword " :
1304 o->disp_size == 32 ? "dword " :
1305 o->disp_size == 16 ? "word " : ""), offs);
1306 segover = NULL;
1307 } else if (!(REGMEM & ~t)) {
1308 int started = false;
1309 if (t & BITS8)
1310 slen +=
1311 snprintf(output + slen, outbufsize - slen, "byte ");
1312 if (t & BITS16)
1313 slen +=
1314 snprintf(output + slen, outbufsize - slen, "word ");
1315 if (t & BITS32)
1316 slen +=
1317 snprintf(output + slen, outbufsize - slen, "dword ");
1318 if (t & BITS64)
1319 slen +=
1320 snprintf(output + slen, outbufsize - slen, "qword ");
1321 if (t & BITS80)
1322 slen +=
1323 snprintf(output + slen, outbufsize - slen, "tword ");
1324 if (t & BITS128)
1325 slen +=
1326 snprintf(output + slen, outbufsize - slen, "oword ");
1327 if (t & BITS256)
1328 slen +=
1329 snprintf(output + slen, outbufsize - slen, "yword ");
1330 if (t & FAR)
1331 slen += snprintf(output + slen, outbufsize - slen, "far ");
1332 if (t & NEAR)
1333 slen +=
1334 snprintf(output + slen, outbufsize - slen, "near ");
1335 output[slen++] = '[';
1336 if (o->disp_size)
1337 slen += snprintf(output + slen, outbufsize - slen, "%s",
1338 (o->disp_size == 64 ? "qword " :
1339 o->disp_size == 32 ? "dword " :
1340 o->disp_size == 16 ? "word " :
1341 ""));
1342 if (o->eaflags & EAF_REL)
1343 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1344 if (segover) {
1345 slen +=
1346 snprintf(output + slen, outbufsize - slen, "%s:",
1347 segover);
1348 segover = NULL;
1349 }
1350 if (o->basereg != -1) {
1351 slen += snprintf(output + slen, outbufsize - slen, "%s",
1352 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1353 started = true;
1354 }
1355 if (o->indexreg != -1) {
1356 if (started)
1357 output[slen++] = '+';
1358 slen += snprintf(output + slen, outbufsize - slen, "%s",
1359 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1360 if (o->scale > 1)
1361 slen +=
1362 snprintf(output + slen, outbufsize - slen, "*%d",
1363 o->scale);
1364 started = true;
1365 }
1366
1367
1368 if (o->segment & SEG_DISP8) {
1369 const char *prefix;
1370 uint8_t offset = offs;
1371 if ((int8_t)offset < 0) {
1372 prefix = "-";
1373 offset = -offset;
1374 } else {
1375 prefix = "+";
1376 }
1377 slen +=
1378 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1379 prefix, offset);
1380 } else if (o->segment & SEG_DISP16) {
1381 const char *prefix;
1382 uint16_t offset = offs;
1383 if ((int16_t)offset < 0 && started) {
1384 offset = -offset;
1385 prefix = "-";
1386 } else {
1387 prefix = started ? "+" : "";
1388 }
1389 slen +=
1390 snprintf(output + slen, outbufsize - slen,
1391 "%s0x%"PRIx16"", prefix, offset);
1392 } else if (o->segment & SEG_DISP32) {
1393 if (prefix.asize == 64) {
1394 const char *prefix;
1395 uint64_t offset = (int64_t)(int32_t)offs;
1396 if ((int32_t)offs < 0 && started) {
1397 offset = -offset;
1398 prefix = "-";
1399 } else {
1400 prefix = started ? "+" : "";
1401 }
1402 slen +=
1403 snprintf(output + slen, outbufsize - slen,
1404 "%s0x%"PRIx64"", prefix, offset);
1405 } else {
1406 const char *prefix;
1407 uint32_t offset = offs;
1408 if ((int32_t) offset < 0 && started) {
1409 offset = -offset;
1410 prefix = "-";
1411 } else {
1412 prefix = started ? "+" : "";
1413 }
1414 slen +=
1415 snprintf(output + slen, outbufsize - slen,
1416 "%s0x%"PRIx32"", prefix, offset);
1417 }
1418 }
1419 output[slen++] = ']';
1420 } else {
1421 slen +=
1422 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1423 i);
1424 }
1425 }
1426 output[slen] = '\0';
1427 if (segover) { /* unused segment override */
1428 char *p = output;
1429 int count = slen + 1;
1430 while (count--)
1431 p[count + 3] = p[count];
1432 strncpy(output, segover, 2);
1433 output[2] = ' ';
1434 }
1435 return length;
1436 }
1437
1438 int32_t eatbyte(uint8_t *data, char *output, int outbufsize)
1439 {
1440 snprintf(output, outbufsize, "db 0x%02X", *data);
1441 return 1;
1442 }
The Netwide Assembler