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AVX: implement all the convert instructions...
[nasm.git] / assemble.c
blob1d440ead6f45f7a1533fa7211cfd9d52bb7d4426
1 /* assemble.c code generation for the Netwide Assembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
7 *
8 * the actual codes (C syntax, i.e. octal):
9 * \0 - terminates the code. (Unless it's a literal of course.)
10 * \1, \2, \3 - that many literal bytes follow in the code stream
11 * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
12 * (POP is never used for CS) depending on operand 0
13 * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
14 * on operand 0
15 * \10..\13 - a literal byte follows in the code stream, to be added
16 * to the register value of operand 0..3
17 * \14..\17 - a signed byte immediate operand, from operand 0..3
18 * \20..\23 - a byte immediate operand, from operand 0..3
19 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
20 * \30..\33 - a word immediate operand, from operand 0..3
21 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
22 * assembly mode or the operand-size override on the operand
23 * \40..\43 - a long immediate operand, from operand 0..3
24 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
25 * depending on the address size of the instruction.
26 * \50..\53 - a byte relative operand, from operand 0..3
27 * \54..\57 - a qword immediate operand, from operand 0..3
28 * \60..\63 - a word relative operand, from operand 0..3
29 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
30 * assembly mode or the operand-size override on the operand
31 * \70..\73 - a long relative operand, from operand 0..3
32 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
33 * \1ab - a ModRM, calculated on EA in operand a, with the spare
34 * field the register value of operand b.
35 * \140..\143 - an immediate word or signed byte for operand 0..3
36 * \144..\147 - or 2 (s-field) into opcode byte if operand 0..3
37 * is a signed byte rather than a word. Opcode byte follows.
38 * \150..\153 - an immediate dword or signed byte for operand 0..3
39 * \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
40 * is a signed byte rather than a dword. Opcode byte follows.
41 * \160..\163 - this instruction uses DREX rather than REX, with the
42 * OC0 field set to 0, and the dest field taken from
43 * operand 0..3.
44 * \164..\167 - this instruction uses DREX rather than REX, with the
45 * OC0 field set to 1, and the dest field taken from
46 * operand 0..3.
47 * \171 - placement of DREX suffix in the absence of an EA
48 * \172\ab - the register number from operand a in bits 7..4, with
49 * the 4-bit immediate from operand b in bits 0..3.
50 * \173\xab - the register number from operand a in bits 7..4, with
51 * the value b in bits 0..3.
52 * \2ab - a ModRM, calculated on EA in operand a, with the spare
53 * field equal to digit b.
54 * \250..\253 - same as \150..\153, except warn if the 64-bit operand
55 * is not equal to the truncated and sign-extended 32-bit
56 * operand; used for 32-bit immediates in 64-bit mode.
57 * \260..\263 - this instruction uses VEX rather than REX, with the
58 * V field taken from operand 0..3.
59 * \270 - this instruction uses VEX rather than REX, with the
60 * V field set to 1111b.
61 *
62 * VEX prefixes are followed by the sequence:
63 * \mm\wlp where mm is the M field; and wlp is:
64 * 00 0ww lpp
65 * ww = 0 for W = 0
66 * ww = 1 for W = 1
67 * ww = 2 for W used as REX.W
68 *
69 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
70 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
71 * \312 - (disassembler only) marker on LOOP, LOOPxx instructions.
72 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
73 * \314 - (disassembler only) invalid with REX.B
74 * \315 - (disassembler only) invalid with REX.X
75 * \316 - (disassembler only) invalid with REX.R
76 * \317 - (disassembler only) invalid with REX.W
77 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
78 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
79 * \322 - indicates that this instruction is only valid when the
80 * operand size is the default (instruction to disassembler,
81 * generates no code in the assembler)
82 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
83 * \324 - indicates 64-bit operand size requiring REX prefix.
84 * \330 - a literal byte follows in the code stream, to be added
85 * to the condition code value of the instruction.
86 * \331 - instruction not valid with REP prefix. Hint for
87 * disassembler only; for SSE instructions.
88 * \332 - REP prefix (0xF2 byte) used as opcode extension.
89 * \333 - REP prefix (0xF3 byte) used as opcode extension.
90 * \334 - LOCK prefix used instead of REX.R
91 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
92 * \340 - reserve <operand 0> bytes of uninitialized storage.
93 * Operand 0 had better be a segmentless constant.
94 * \360 - no SSE prefix (== \364\331)
95 * \361 - 66 SSE prefix (== \366\331)
96 * \362 - F2 SSE prefix (== \364\332)
97 * \363 - F3 SSE prefix (== \364\333)
98 * \364 - operand-size prefix (0x66) not permitted
99 * \365 - address-size prefix (0x67) not permitted
100 * \366 - operand-size prefix (0x66) used as opcode extension
101 * \367 - address-size prefix (0x67) used as opcode extension
102 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
103 * 370 is used for Jcc, 371 is used for JMP.
104 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
105 * used for conditional jump over longer jump
106 */
107
108 #include "compiler.h"
109
110 #include <stdio.h>
111 #include <string.h>
112 #include <inttypes.h>
113
114 #include "nasm.h"
115 #include "nasmlib.h"
116 #include "assemble.h"
117 #include "insns.h"
118 #include "preproc.h"
119 #include "tables.h"
120
121 /* Initialized to zero by the C standard */
122 static const uint8_t const_zero_buf[256];
123
124 typedef struct {
125 int sib_present; /* is a SIB byte necessary? */
126 int bytes; /* # of bytes of offset needed */
127 int size; /* lazy - this is sib+bytes+1 */
128 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
129 } ea;
130
131 static uint32_t cpu; /* cpu level received from nasm.c */
132 static efunc errfunc;
133 static struct ofmt *outfmt;
134 static ListGen *list;
135
136 static int64_t calcsize(int32_t, int64_t, int, insn *, const uint8_t *);
137 static void gencode(int32_t, int64_t, int, insn *, const uint8_t *, int64_t);
138 static int matches(const struct itemplate *, insn *, int bits);
139 static int32_t regflag(const operand *);
140 static int32_t regval(const operand *);
141 static int rexflags(int, int32_t, int);
142 static int op_rexflags(const operand *, int);
143 static ea *process_ea(operand *, ea *, int, int, int, int32_t, int);
144 static void add_asp(insn *, int);
145
146 static int has_prefix(insn * ins, enum prefix_pos pos, enum prefixes prefix)
147 {
148 return ins->prefixes[pos] == prefix;
149 }
150
151 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
152 {
153 if (ins->prefixes[pos])
154 errfunc(ERR_NONFATAL, "invalid %s prefix",
155 prefix_name(ins->prefixes[pos]));
156 }
157
158 static const char *size_name(int size)
159 {
160 switch (size) {
161 case 1:
162 return "byte";
163 case 2:
164 return "word";
165 case 4:
166 return "dword";
167 case 8:
168 return "qword";
169 case 10:
170 return "tword";
171 case 16:
172 return "oword";
173 case 32:
174 return "yword";
175 default:
176 return "???";
177 }
178 }
179
180 static void warn_overflow(int size, int64_t data)
181 {
182 if (size < 8) {
183 int64_t lim = ((int64_t)1 << (size*8))-1;
184
185 if (data < ~lim || data > lim)
186 errfunc(ERR_WARNING | ERR_WARN_NOV,
187 "%s data exceeds bounds", size_name(size));
188 }
189 }
190 /*
191 * This routine wrappers the real output format's output routine,
192 * in order to pass a copy of the data off to the listing file
193 * generator at the same time.
194 */
195 static void out(int64_t offset, int32_t segto, const void *data,
196 enum out_type type, uint64_t size,
197 int32_t segment, int32_t wrt)
198 {
199 static int32_t lineno = 0; /* static!!! */
200 static char *lnfname = NULL;
201 uint8_t p[8];
202
203 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
204 /*
205 * This is a non-relocated address, and we're going to
206 * convert it into RAWDATA format.
207 */
208 uint8_t *q = p;
209
210 if (size > 8) {
211 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
212 return;
213 }
214
215 WRITEADDR(q, *(int64_t *)data, size);
216 data = p;
217 type = OUT_RAWDATA;
218 }
219
220 list->output(offset, data, type, size);
221
222 /*
223 * this call to src_get determines when we call the
224 * debug-format-specific "linenum" function
225 * it updates lineno and lnfname to the current values
226 * returning 0 if "same as last time", -2 if lnfname
227 * changed, and the amount by which lineno changed,
228 * if it did. thus, these variables must be static
229 */
230
231 if (src_get(&lineno, &lnfname)) {
232 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
233 }
234
235 outfmt->output(segto, data, type, size, segment, wrt);
236 }
237
238 static int jmp_match(int32_t segment, int64_t offset, int bits,
239 insn * ins, const uint8_t *code)
240 {
241 int64_t isize;
242 uint8_t c = code[0];
243
244 if (c != 0370 && c != 0371)
245 return 0;
246 if (ins->oprs[0].opflags & OPFLAG_FORWARD) {
247 if ((optimizing < 0 || (ins->oprs[0].type & STRICT))
248 && c == 0370)
249 return 1;
250 else
251 return (pass0 == 0); /* match a forward reference */
252 }
253 isize = calcsize(segment, offset, bits, ins, code);
254 if (ins->oprs[0].segment != segment)
255 return 0;
256 isize = ins->oprs[0].offset - offset - isize; /* isize is now the delta */
257 if (isize >= -128L && isize <= 127L)
258 return 1; /* it is byte size */
259
260 return 0;
261 }
262
263 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
264 insn * instruction, struct ofmt *output, efunc error,
265 ListGen * listgen)
266 {
267 const struct itemplate *temp;
268 int j;
269 int size_prob;
270 int64_t insn_end;
271 int32_t itimes;
272 int64_t start = offset;
273 int64_t wsize = 0; /* size for DB etc. */
274
275 errfunc = error; /* to pass to other functions */
276 cpu = cp;
277 outfmt = output; /* likewise */
278 list = listgen; /* and again */
279
280 switch (instruction->opcode) {
281 case -1:
282 return 0;
283 case I_DB:
284 wsize = 1;
285 break;
286 case I_DW:
287 wsize = 2;
288 break;
289 case I_DD:
290 wsize = 4;
291 break;
292 case I_DQ:
293 wsize = 8;
294 break;
295 case I_DT:
296 wsize = 10;
297 break;
298 case I_DO:
299 wsize = 16;
300 break;
301 case I_DY:
302 wsize = 32;
303 break;
304 default:
305 break;
306 }
307
308 if (wsize) {
309 extop *e;
310 int32_t t = instruction->times;
311 if (t < 0)
312 errfunc(ERR_PANIC,
313 "instruction->times < 0 (%ld) in assemble()", t);
314
315 while (t--) { /* repeat TIMES times */
316 for (e = instruction->eops; e; e = e->next) {
317 if (e->type == EOT_DB_NUMBER) {
318 if (wsize == 1) {
319 if (e->segment != NO_SEG)
320 errfunc(ERR_NONFATAL,
321 "one-byte relocation attempted");
322 else {
323 uint8_t out_byte = e->offset;
324 out(offset, segment, &out_byte,
325 OUT_RAWDATA, 1, NO_SEG, NO_SEG);
326 }
327 } else if (wsize > 8) {
328 errfunc(ERR_NONFATAL,
329 "integer supplied to a DT, DO or DY"
330 " instruction");
331 } else
332 out(offset, segment, &e->offset,
333 OUT_ADDRESS, wsize, e->segment, e->wrt);
334 offset += wsize;
335 } else if (e->type == EOT_DB_STRING) {
336 int align;
337
338 out(offset, segment, e->stringval,
339 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
340 align = e->stringlen % wsize;
341
342 if (align) {
343 align = wsize - align;
344 out(offset, segment, const_zero_buf,
345 OUT_RAWDATA, align, NO_SEG, NO_SEG);
346 }
347 offset += e->stringlen + align;
348 }
349 }
350 if (t > 0 && t == instruction->times - 1) {
351 /*
352 * Dummy call to list->output to give the offset to the
353 * listing module.
354 */
355 list->output(offset, NULL, OUT_RAWDATA, 0);
356 list->uplevel(LIST_TIMES);
357 }
358 }
359 if (instruction->times > 1)
360 list->downlevel(LIST_TIMES);
361 return offset - start;
362 }
363
364 if (instruction->opcode == I_INCBIN) {
365 static char fname[FILENAME_MAX];
366 FILE *fp;
367 int32_t len;
368 char *prefix = "", *combine;
369 char **pPrevPath = NULL;
370
371 len = FILENAME_MAX - 1;
372 if (len > instruction->eops->stringlen)
373 len = instruction->eops->stringlen;
374 strncpy(fname, instruction->eops->stringval, len);
375 fname[len] = '\0';
376
377 while (1) { /* added by alexfru: 'incbin' uses include paths */
378 combine = nasm_malloc(strlen(prefix) + len + 1);
379 strcpy(combine, prefix);
380 strcat(combine, fname);
381
382 if ((fp = fopen(combine, "rb")) != NULL) {
383 nasm_free(combine);
384 break;
385 }
386
387 nasm_free(combine);
388 pPrevPath = pp_get_include_path_ptr(pPrevPath);
389 if (pPrevPath == NULL)
390 break;
391 prefix = *pPrevPath;
392 }
393
394 if (fp == NULL)
395 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
396 fname);
397 else if (fseek(fp, 0L, SEEK_END) < 0)
398 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
399 fname);
400 else {
401 static char buf[2048];
402 int32_t t = instruction->times;
403 int32_t base = 0;
404
405 len = ftell(fp);
406 if (instruction->eops->next) {
407 base = instruction->eops->next->offset;
408 len -= base;
409 if (instruction->eops->next->next &&
410 len > instruction->eops->next->next->offset)
411 len = instruction->eops->next->next->offset;
412 }
413 /*
414 * Dummy call to list->output to give the offset to the
415 * listing module.
416 */
417 list->output(offset, NULL, OUT_RAWDATA, 0);
418 list->uplevel(LIST_INCBIN);
419 while (t--) {
420 int32_t l;
421
422 fseek(fp, base, SEEK_SET);
423 l = len;
424 while (l > 0) {
425 int32_t m =
426 fread(buf, 1, (l > (int32_t) sizeof(buf) ? (int32_t) sizeof(buf) : l),
427 fp);
428 if (!m) {
429 /*
430 * This shouldn't happen unless the file
431 * actually changes while we are reading
432 * it.
433 */
434 error(ERR_NONFATAL,
435 "`incbin': unexpected EOF while"
436 " reading file `%s'", fname);
437 t = 0; /* Try to exit cleanly */
438 break;
439 }
440 out(offset, segment, buf, OUT_RAWDATA, m,
441 NO_SEG, NO_SEG);
442 l -= m;
443 }
444 }
445 list->downlevel(LIST_INCBIN);
446 if (instruction->times > 1) {
447 /*
448 * Dummy call to list->output to give the offset to the
449 * listing module.
450 */
451 list->output(offset, NULL, OUT_RAWDATA, 0);
452 list->uplevel(LIST_TIMES);
453 list->downlevel(LIST_TIMES);
454 }
455 fclose(fp);
456 return instruction->times * len;
457 }
458 return 0; /* if we're here, there's an error */
459 }
460
461 /* Check to see if we need an address-size prefix */
462 add_asp(instruction, bits);
463
464 size_prob = false;
465
466 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++){
467 int m = matches(temp, instruction, bits);
468
469 if (m == 99)
470 m += jmp_match(segment, offset, bits, instruction, temp->code);
471
472 if (m == 100) { /* matches! */
473 const uint8_t *codes = temp->code;
474 int64_t insn_size = calcsize(segment, offset, bits,
475 instruction, codes);
476 itimes = instruction->times;
477 if (insn_size < 0) /* shouldn't be, on pass two */
478 error(ERR_PANIC, "errors made it through from pass one");
479 else
480 while (itimes--) {
481 for (j = 0; j < MAXPREFIX; j++) {
482 uint8_t c = 0;
483 switch (instruction->prefixes[j]) {
484 case P_LOCK:
485 c = 0xF0;
486 break;
487 case P_REPNE:
488 case P_REPNZ:
489 c = 0xF2;
490 break;
491 case P_REPE:
492 case P_REPZ:
493 case P_REP:
494 c = 0xF3;
495 break;
496 case R_CS:
497 if (bits == 64) {
498 error(ERR_WARNING,
499 "cs segment base generated, but will be ignored in 64-bit mode");
500 }
501 c = 0x2E;
502 break;
503 case R_DS:
504 if (bits == 64) {
505 error(ERR_WARNING,
506 "ds segment base generated, but will be ignored in 64-bit mode");
507 }
508 c = 0x3E;
509 break;
510 case R_ES:
511 if (bits == 64) {
512 error(ERR_WARNING,
513 "es segment base generated, but will be ignored in 64-bit mode");
514 }
515 c = 0x26;
516 break;
517 case R_FS:
518 c = 0x64;
519 break;
520 case R_GS:
521 c = 0x65;
522 break;
523 case R_SS:
524 if (bits == 64) {
525 error(ERR_WARNING,
526 "ss segment base generated, but will be ignored in 64-bit mode");
527 }
528 c = 0x36;
529 break;
530 case R_SEGR6:
531 case R_SEGR7:
532 error(ERR_NONFATAL,
533 "segr6 and segr7 cannot be used as prefixes");
534 break;
535 case P_A16:
536 if (bits == 64) {
537 error(ERR_NONFATAL,
538 "16-bit addressing is not supported "
539 "in 64-bit mode");
540 } else if (bits != 16)
541 c = 0x67;
542 break;
543 case P_A32:
544 if (bits != 32)
545 c = 0x67;
546 break;
547 case P_A64:
548 if (bits != 64) {
549 error(ERR_NONFATAL,
550 "64-bit addressing is only supported "
551 "in 64-bit mode");
552 }
553 break;
554 case P_ASP:
555 c = 0x67;
556 break;
557 case P_O16:
558 if (bits != 16)
559 c = 0x66;
560 break;
561 case P_O32:
562 if (bits == 16)
563 c = 0x66;
564 break;
565 case P_O64:
566 /* REX.W */
567 break;
568 case P_OSP:
569 c = 0x66;
570 break;
571 case P_none:
572 break;
573 default:
574 error(ERR_PANIC, "invalid instruction prefix");
575 }
576 if (c != 0) {
577 out(offset, segment, &c, OUT_RAWDATA, 1,
578 NO_SEG, NO_SEG);
579 offset++;
580 }
581 }
582 insn_end = offset + insn_size;
583 gencode(segment, offset, bits, instruction, codes,
584 insn_end);
585 offset += insn_size;
586 if (itimes > 0 && itimes == instruction->times - 1) {
587 /*
588 * Dummy call to list->output to give the offset to the
589 * listing module.
590 */
591 list->output(offset, NULL, OUT_RAWDATA, 0);
592 list->uplevel(LIST_TIMES);
593 }
594 }
595 if (instruction->times > 1)
596 list->downlevel(LIST_TIMES);
597 return offset - start;
598 } else if (m > 0 && m > size_prob) {
599 size_prob = m;
600 }
601 // temp++;
602 }
603
604 if (temp->opcode == -1) { /* didn't match any instruction */
605 switch (size_prob) {
606 case 1:
607 error(ERR_NONFATAL, "operation size not specified");
608 break;
609 case 2:
610 error(ERR_NONFATAL, "mismatch in operand sizes");
611 break;
612 case 3:
613 error(ERR_NONFATAL, "no instruction for this cpu level");
614 break;
615 case 4:
616 error(ERR_NONFATAL, "instruction not supported in 64-bit mode");
617 break;
618 default:
619 error(ERR_NONFATAL,
620 "invalid combination of opcode and operands");
621 break;
622 }
623 }
624 return 0;
625 }
626
627 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
628 insn * instruction, efunc error)
629 {
630 const struct itemplate *temp;
631
632 errfunc = error; /* to pass to other functions */
633 cpu = cp;
634
635 if (instruction->opcode == -1)
636 return 0;
637
638 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
639 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
640 instruction->opcode == I_DT || instruction->opcode == I_DO ||
641 instruction->opcode == I_DY) {
642 extop *e;
643 int32_t isize, osize, wsize = 0; /* placate gcc */
644
645 isize = 0;
646 switch (instruction->opcode) {
647 case I_DB:
648 wsize = 1;
649 break;
650 case I_DW:
651 wsize = 2;
652 break;
653 case I_DD:
654 wsize = 4;
655 break;
656 case I_DQ:
657 wsize = 8;
658 break;
659 case I_DT:
660 wsize = 10;
661 break;
662 case I_DO:
663 wsize = 16;
664 break;
665 case I_DY:
666 wsize = 32;
667 break;
668 default:
669 break;
670 }
671
672 for (e = instruction->eops; e; e = e->next) {
673 int32_t align;
674
675 osize = 0;
676 if (e->type == EOT_DB_NUMBER)
677 osize = 1;
678 else if (e->type == EOT_DB_STRING)
679 osize = e->stringlen;
680
681 align = (-osize) % wsize;
682 if (align < 0)
683 align += wsize;
684 isize += osize + align;
685 }
686 return isize * instruction->times;
687 }
688
689 if (instruction->opcode == I_INCBIN) {
690 char fname[FILENAME_MAX];
691 FILE *fp;
692 int32_t len;
693 char *prefix = "", *combine;
694 char **pPrevPath = NULL;
695
696 len = FILENAME_MAX - 1;
697 if (len > instruction->eops->stringlen)
698 len = instruction->eops->stringlen;
699 strncpy(fname, instruction->eops->stringval, len);
700 fname[len] = '\0';
701
702 /* added by alexfru: 'incbin' uses include paths */
703 while (1) {
704 combine = nasm_malloc(strlen(prefix) + len + 1);
705 strcpy(combine, prefix);
706 strcat(combine, fname);
707
708 if ((fp = fopen(combine, "rb")) != NULL) {
709 nasm_free(combine);
710 break;
711 }
712
713 nasm_free(combine);
714 pPrevPath = pp_get_include_path_ptr(pPrevPath);
715 if (pPrevPath == NULL)
716 break;
717 prefix = *pPrevPath;
718 }
719
720 if (fp == NULL)
721 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
722 fname);
723 else if (fseek(fp, 0L, SEEK_END) < 0)
724 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
725 fname);
726 else {
727 len = ftell(fp);
728 fclose(fp);
729 if (instruction->eops->next) {
730 len -= instruction->eops->next->offset;
731 if (instruction->eops->next->next &&
732 len > instruction->eops->next->next->offset) {
733 len = instruction->eops->next->next->offset;
734 }
735 }
736 return instruction->times * len;
737 }
738 return 0; /* if we're here, there's an error */
739 }
740
741 /* Check to see if we need an address-size prefix */
742 add_asp(instruction, bits);
743
744 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++) {
745 int m = matches(temp, instruction, bits);
746 if (m == 99)
747 m += jmp_match(segment, offset, bits, instruction, temp->code);
748
749 if (m == 100) {
750 /* we've matched an instruction. */
751 int64_t isize;
752 const uint8_t *codes = temp->code;
753 int j;
754
755 isize = calcsize(segment, offset, bits, instruction, codes);
756 if (isize < 0)
757 return -1;
758 for (j = 0; j < MAXPREFIX; j++) {
759 switch (instruction->prefixes[j]) {
760 case P_A16:
761 if (bits != 16)
762 isize++;
763 break;
764 case P_A32:
765 if (bits != 32)
766 isize++;
767 break;
768 case P_O16:
769 if (bits != 16)
770 isize++;
771 break;
772 case P_O32:
773 if (bits == 16)
774 isize++;
775 break;
776 case P_A64:
777 case P_O64:
778 case P_none:
779 break;
780 default:
781 isize++;
782 break;
783 }
784 }
785 return isize * instruction->times;
786 }
787 }
788 return -1; /* didn't match any instruction */
789 }
790
791 static bool possible_sbyte(insn * ins, int op)
792 {
793 return !(ins->forw_ref && ins->oprs[op].opflags) &&
794 optimizing >= 0 &&
795 !(ins->oprs[op].type & STRICT) &&
796 ins->oprs[op].wrt == NO_SEG && ins->oprs[op].segment == NO_SEG;
797 }
798
799 /* check that opn[op] is a signed byte of size 16 or 32 */
800 static bool is_sbyte16(insn * ins, int op)
801 {
802 int16_t v;
803
804 if (!possible_sbyte(ins, op))
805 return false;
806
807 v = ins->oprs[op].offset;
808 return v >= -128 && v <= 127;
809 }
810
811 static bool is_sbyte32(insn * ins, int op)
812 {
813 int32_t v;
814
815 if (!possible_sbyte(ins, op))
816 return false;
817
818 v = ins->oprs[op].offset;
819 return v >= -128 && v <= 127;
820 }
821
822 /* check that opn[op] is a signed byte of size 32; warn if this is not
823 the original value when extended to 64 bits */
824 static bool is_sbyte64(insn * ins, int op)
825 {
826 int64_t v64;
827 int32_t v32;
828
829 /* dead in the water on forward reference or External */
830 if (!possible_sbyte(ins, op))
831 return false;
832
833 v64 = ins->oprs[op].offset;
834 v32 = (int32_t)v64;
835
836 warn_overflow(32, v64);
837
838 return v32 >= -128 && v32 <= 127;
839 }
840 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
841 insn * ins, const uint8_t *codes)
842 {
843 int64_t length = 0;
844 uint8_t c;
845 int rex_mask = ~0;
846 struct operand *opx;
847
848 ins->rex = 0; /* Ensure REX is reset */
849
850 if (ins->prefixes[PPS_OSIZE] == P_O64)
851 ins->rex |= REX_W;
852
853 (void)segment; /* Don't warn that this parameter is unused */
854 (void)offset; /* Don't warn that this parameter is unused */
855
856 while (*codes) {
857 c = *codes++;
858 opx = &ins->oprs[c & 3];
859 switch (c) {
860 case 01:
861 case 02:
862 case 03:
863 codes += c, length += c;
864 break;
865 case 04:
866 case 05:
867 case 06:
868 case 07:
869 length++;
870 break;
871 case 010:
872 case 011:
873 case 012:
874 case 013:
875 ins->rex |=
876 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
877 codes++, length++;
878 break;
879 case 014:
880 case 015:
881 case 016:
882 case 017:
883 length++;
884 break;
885 case 020:
886 case 021:
887 case 022:
888 case 023:
889 length++;
890 break;
891 case 024:
892 case 025:
893 case 026:
894 case 027:
895 length++;
896 break;
897 case 030:
898 case 031:
899 case 032:
900 case 033:
901 length += 2;
902 break;
903 case 034:
904 case 035:
905 case 036:
906 case 037:
907 if (opx->type & (BITS16 | BITS32 | BITS64))
908 length += (opx->type & BITS16) ? 2 : 4;
909 else
910 length += (bits == 16) ? 2 : 4;
911 break;
912 case 040:
913 case 041:
914 case 042:
915 case 043:
916 length += 4;
917 break;
918 case 044:
919 case 045:
920 case 046:
921 case 047:
922 length += ins->addr_size >> 3;
923 break;
924 case 050:
925 case 051:
926 case 052:
927 case 053:
928 length++;
929 break;
930 case 054:
931 case 055:
932 case 056:
933 case 057:
934 length += 8; /* MOV reg64/imm */
935 break;
936 case 060:
937 case 061:
938 case 062:
939 case 063:
940 length += 2;
941 break;
942 case 064:
943 case 065:
944 case 066:
945 case 067:
946 if (opx->type & (BITS16 | BITS32 | BITS64))
947 length += (opx->type & BITS16) ? 2 : 4;
948 else
949 length += (bits == 16) ? 2 : 4;
950 break;
951 case 070:
952 case 071:
953 case 072:
954 case 073:
955 length += 4;
956 break;
957 case 074:
958 case 075:
959 case 076:
960 case 077:
961 length += 2;
962 break;
963 case 0140:
964 case 0141:
965 case 0142:
966 case 0143:
967 length += is_sbyte16(ins, c & 3) ? 1 : 2;
968 break;
969 case 0144:
970 case 0145:
971 case 0146:
972 case 0147:
973 codes++;
974 length++;
975 break;
976 case 0150:
977 case 0151:
978 case 0152:
979 case 0153:
980 length += is_sbyte32(ins, c & 3) ? 1 : 4;
981 break;
982 case 0154:
983 case 0155:
984 case 0156:
985 case 0157:
986 codes++;
987 length++;
988 break;
989 case 0160:
990 case 0161:
991 case 0162:
992 case 0163:
993 length++;
994 ins->rex |= REX_D;
995 ins->drexdst = regval(opx);
996 break;
997 case 0164:
998 case 0165:
999 case 0166:
1000 case 0167:
1001 length++;
1002 ins->rex |= REX_D|REX_OC;
1003 ins->drexdst = regval(opx);
1004 break;
1005 case 0171:
1006 break;
1007 case 0172:
1008 case 0173:
1009 codes++;
1010 length++;
1011 break;
1012 case 0250:
1013 case 0251:
1014 case 0252:
1015 case 0253:
1016 length += is_sbyte64(ins, c & 3) ? 1 : 4;
1017 break;
1018 case 0260:
1019 case 0261:
1020 case 0262:
1021 case 0263:
1022 length += 2;
1023 ins->rex |= REX_V;
1024 ins->drexdst = regval(opx);
1025 ins->vex_m = *codes++;
1026 ins->vex_wlp = *codes++;
1027 break;
1028 case 0270:
1029 length += 2;
1030 ins->rex |= REX_V;
1031 ins->drexdst = 0;
1032 ins->vex_m = *codes++;
1033 ins->vex_wlp = *codes++;
1034 break;
1035 case 0300:
1036 case 0301:
1037 case 0302:
1038 case 0303:
1039 break;
1040 case 0310:
1041 if (bits == 64)
1042 return -1;
1043 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1044 break;
1045 case 0311:
1046 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1047 break;
1048 case 0312:
1049 break;
1050 case 0313:
1051 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1052 has_prefix(ins, PPS_ASIZE, P_A32))
1053 return -1;
1054 break;
1055 case 0314:
1056 case 0315:
1057 case 0316:
1058 case 0317:
1059 break;
1060 case 0320:
1061 length += (bits != 16);
1062 break;
1063 case 0321:
1064 length += (bits == 16);
1065 break;
1066 case 0322:
1067 break;
1068 case 0323:
1069 rex_mask &= ~REX_W;
1070 break;
1071 case 0324:
1072 ins->rex |= REX_W;
1073 break;
1074 case 0330:
1075 codes++, length++;
1076 break;
1077 case 0331:
1078 break;
1079 case 0332:
1080 case 0333:
1081 length++;
1082 break;
1083 case 0334:
1084 ins->rex |= REX_L;
1085 break;
1086 case 0335:
1087 break;
1088 case 0340:
1089 if (ins->oprs[0].segment != NO_SEG)
1090 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1091 " quantity of BSS space");
1092 else
1093 length += ins->oprs[0].offset;
1094 break;
1095 case 0360:
1096 break;
1097 case 0361:
1098 case 0362:
1099 case 0363:
1100 length++;
1101 break;
1102 case 0364:
1103 case 0365:
1104 break;
1105 case 0366:
1106 case 0367:
1107 length++;
1108 break;
1109 case 0370:
1110 case 0371:
1111 case 0372:
1112 break;
1113 case 0373:
1114 length++;
1115 break;
1116 default: /* can't do it by 'case' statements */
1117 if (c >= 0100 && c <= 0277) { /* it's an EA */
1118 ea ea_data;
1119 int rfield;
1120 int32_t rflags;
1121 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1122
1123 if (c <= 0177) {
1124 /* pick rfield from operand b */
1125 rflags = regflag(&ins->oprs[c & 7]);
1126 rfield = nasm_regvals[ins->oprs[c & 7].basereg];
1127 } else {
1128 rflags = 0;
1129 rfield = c & 7;
1130 }
1131
1132 if (!process_ea
1133 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1134 ins->addr_size, rfield, rflags, ins->forw_ref)) {
1135 errfunc(ERR_NONFATAL, "invalid effective address");
1136 return -1;
1137 } else {
1138 ins->rex |= ea_data.rex;
1139 length += ea_data.size;
1140 }
1141 } else {
1142 errfunc(ERR_PANIC, "internal instruction table corrupt"
1143 ": instruction code 0x%02X given", c);
1144 }
1145 }
1146 }
1147
1148 ins->rex &= rex_mask;
1149
1150 if (ins->rex & REX_V) {
1151 int bad32 = REX_R|REX_W|REX_X|REX_B;
1152
1153 if (ins->rex & REX_H) {
1154 errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
1155 return -1;
1156 }
1157 switch (ins->vex_wlp & 030) {
1158 case 000:
1159 ins->rex &= ~REX_W;
1160 break;
1161 case 010:
1162 ins->rex |= REX_W;
1163 bad32 &= ~REX_W;
1164 break;
1165 default:
1166 /* Follow REX_W */
1167 break;
1168 }
1169
1170 if (bits != 64 && ((ins->rex & bad32) || ins->drexdst > 7)) {
1171 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1172 return -1;
1173 }
1174 if (ins->vex_m != 1 || (ins->rex & (REX_W|REX_R|REX_B)))
1175 length += 3;
1176 else
1177 length += 2;
1178 } else if (ins->rex & REX_D) {
1179 if (ins->rex & REX_H) {
1180 errfunc(ERR_NONFATAL, "cannot use high register in drex instruction");
1181 return -1;
1182 }
1183 if (bits != 64 && ((ins->rex & (REX_R|REX_W|REX_X|REX_B)) ||
1184 ins->drexdst > 7)) {
1185 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1186 return -1;
1187 }
1188 length++;
1189 } else if (ins->rex & REX_REAL) {
1190 if (ins->rex & REX_H) {
1191 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1192 return -1;
1193 } else if (bits == 64) {
1194 length++;
1195 } else if ((ins->rex & REX_L) &&
1196 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1197 cpu >= IF_X86_64) {
1198 /* LOCK-as-REX.R */
1199 assert_no_prefix(ins, PPS_LREP);
1200 length++;
1201 } else {
1202 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1203 return -1;
1204 }
1205 }
1206
1207 return length;
1208 }
1209
1210 #define EMIT_REX() \
1211 if (!(ins->rex & (REX_D|REX_V)) && (ins->rex & REX_REAL) && (bits == 64)) { \
1212 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1213 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1214 ins->rex = 0; \
1215 offset += 1; \
1216 }
1217
1218 static void gencode(int32_t segment, int64_t offset, int bits,
1219 insn * ins, const uint8_t *codes, int64_t insn_end)
1220 {
1221 static char condval[] = { /* conditional opcodes */
1222 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1223 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1224 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1225 };
1226 uint8_t c;
1227 uint8_t bytes[4];
1228 int64_t size;
1229 int64_t data;
1230 struct operand *opx;
1231
1232 while (*codes) {
1233 c = *codes++;
1234 opx = &ins->oprs[c & 3];
1235 switch (c) {
1236 case 01:
1237 case 02:
1238 case 03:
1239 EMIT_REX();
1240 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1241 codes += c;
1242 offset += c;
1243 break;
1244
1245 case 04:
1246 case 06:
1247 switch (ins->oprs[0].basereg) {
1248 case R_CS:
1249 bytes[0] = 0x0E + (c == 0x04 ? 1 : 0);
1250 break;
1251 case R_DS:
1252 bytes[0] = 0x1E + (c == 0x04 ? 1 : 0);
1253 break;
1254 case R_ES:
1255 bytes[0] = 0x06 + (c == 0x04 ? 1 : 0);
1256 break;
1257 case R_SS:
1258 bytes[0] = 0x16 + (c == 0x04 ? 1 : 0);
1259 break;
1260 default:
1261 errfunc(ERR_PANIC,
1262 "bizarre 8086 segment register received");
1263 }
1264 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1265 offset++;
1266 break;
1267
1268 case 05:
1269 case 07:
1270 switch (ins->oprs[0].basereg) {
1271 case R_FS:
1272 bytes[0] = 0xA0 + (c == 0x05 ? 1 : 0);
1273 break;
1274 case R_GS:
1275 bytes[0] = 0xA8 + (c == 0x05 ? 1 : 0);
1276 break;
1277 default:
1278 errfunc(ERR_PANIC,
1279 "bizarre 386 segment register received");
1280 }
1281 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1282 offset++;
1283 break;
1284
1285 case 010:
1286 case 011:
1287 case 012:
1288 case 013:
1289 EMIT_REX();
1290 bytes[0] = *codes++ + ((regval(opx)) & 7);
1291 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1292 offset += 1;
1293 break;
1294
1295 case 014:
1296 case 015:
1297 case 016:
1298 case 017:
1299 /* XXX: warns for legitimate optimizer actions */
1300 if (opx->offset < -128 || opx->offset > 127) {
1301 errfunc(ERR_WARNING | ERR_WARN_NOV,
1302 "signed byte value exceeds bounds");
1303 }
1304
1305 if (opx->segment != NO_SEG) {
1306 data = opx->offset;
1307 out(offset, segment, &data, OUT_ADDRESS, 1,
1308 opx->segment, opx->wrt);
1309 } else {
1310 bytes[0] = opx->offset;
1311 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1312 NO_SEG);
1313 }
1314 offset += 1;
1315 break;
1316
1317 case 020:
1318 case 021:
1319 case 022:
1320 case 023:
1321 if (opx->offset < -256 || opx->offset > 255) {
1322 errfunc(ERR_WARNING | ERR_WARN_NOV,
1323 "byte value exceeds bounds");
1324 }
1325 if (opx->segment != NO_SEG) {
1326 data = opx->offset;
1327 out(offset, segment, &data, OUT_ADDRESS, 1,
1328 opx->segment, opx->wrt);
1329 } else {
1330 bytes[0] = opx->offset;
1331 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1332 NO_SEG);
1333 }
1334 offset += 1;
1335 break;
1336
1337 case 024:
1338 case 025:
1339 case 026:
1340 case 027:
1341 if (opx->offset < 0 || opx->offset > 255)
1342 errfunc(ERR_WARNING | ERR_WARN_NOV,
1343 "unsigned byte value exceeds bounds");
1344 if (opx->segment != NO_SEG) {
1345 data = opx->offset;
1346 out(offset, segment, &data, OUT_ADDRESS, 1,
1347 opx->segment, opx->wrt);
1348 } else {
1349 bytes[0] = opx->offset;
1350 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1351 NO_SEG);
1352 }
1353 offset += 1;
1354 break;
1355
1356 case 030:
1357 case 031:
1358 case 032:
1359 case 033:
1360 data = opx->offset;
1361 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1362 warn_overflow(2, data);
1363 out(offset, segment, &data, OUT_ADDRESS, 2,
1364 opx->segment, opx->wrt);
1365 offset += 2;
1366 break;
1367
1368 case 034:
1369 case 035:
1370 case 036:
1371 case 037:
1372 if (opx->type & (BITS16 | BITS32))
1373 size = (opx->type & BITS16) ? 2 : 4;
1374 else
1375 size = (bits == 16) ? 2 : 4;
1376 data = opx->offset;
1377 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1378 warn_overflow(size, data);
1379 out(offset, segment, &data, OUT_ADDRESS, size,
1380 opx->segment, opx->wrt);
1381 offset += size;
1382 break;
1383
1384 case 040:
1385 case 041:
1386 case 042:
1387 case 043:
1388 data = opx->offset;
1389 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1390 warn_overflow(4, data);
1391 out(offset, segment, &data, OUT_ADDRESS, 4,
1392 opx->segment, opx->wrt);
1393 offset += 4;
1394 break;
1395
1396 case 044:
1397 case 045:
1398 case 046:
1399 case 047:
1400 data = opx->offset;
1401 size = ins->addr_size >> 3;
1402 if (opx->segment == NO_SEG &&
1403 opx->wrt == NO_SEG)
1404 warn_overflow(size, data);
1405 out(offset, segment, &data, OUT_ADDRESS, size,
1406 opx->segment, opx->wrt);
1407 offset += size;
1408 break;
1409
1410 case 050:
1411 case 051:
1412 case 052:
1413 case 053:
1414 if (opx->segment != segment)
1415 errfunc(ERR_NONFATAL,
1416 "short relative jump outside segment");
1417 data = opx->offset - insn_end;
1418 if (data > 127 || data < -128)
1419 errfunc(ERR_NONFATAL, "short jump is out of range");
1420 bytes[0] = data;
1421 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1422 offset += 1;
1423 break;
1424
1425 case 054:
1426 case 055:
1427 case 056:
1428 case 057:
1429 data = (int64_t)opx->offset;
1430 out(offset, segment, &data, OUT_ADDRESS, 8,
1431 opx->segment, opx->wrt);
1432 offset += 8;
1433 break;
1434
1435 case 060:
1436 case 061:
1437 case 062:
1438 case 063:
1439 if (opx->segment != segment) {
1440 data = opx->offset;
1441 out(offset, segment, &data,
1442 OUT_REL2ADR, insn_end - offset,
1443 opx->segment, opx->wrt);
1444 } else {
1445 data = opx->offset - insn_end;
1446 out(offset, segment, &data,
1447 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1448 }
1449 offset += 2;
1450 break;
1451
1452 case 064:
1453 case 065:
1454 case 066:
1455 case 067:
1456 if (opx->type & (BITS16 | BITS32 | BITS64))
1457 size = (opx->type & BITS16) ? 2 : 4;
1458 else
1459 size = (bits == 16) ? 2 : 4;
1460 if (opx->segment != segment) {
1461 data = opx->offset;
1462 out(offset, segment, &data,
1463 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1464 insn_end - offset, opx->segment, opx->wrt);
1465 } else {
1466 data = opx->offset - insn_end;
1467 out(offset, segment, &data,
1468 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1469 }
1470 offset += size;
1471 break;
1472
1473 case 070:
1474 case 071:
1475 case 072:
1476 case 073:
1477 if (opx->segment != segment) {
1478 data = opx->offset;
1479 out(offset, segment, &data,
1480 OUT_REL4ADR, insn_end - offset,
1481 opx->segment, opx->wrt);
1482 } else {
1483 data = opx->offset - insn_end;
1484 out(offset, segment, &data,
1485 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1486 }
1487 offset += 4;
1488 break;
1489
1490 case 074:
1491 case 075:
1492 case 076:
1493 case 077:
1494 if (opx->segment == NO_SEG)
1495 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1496 " relocatable");
1497 data = 0;
1498 out(offset, segment, &data, OUT_ADDRESS, 2,
1499 outfmt->segbase(1 + opx->segment),
1500 opx->wrt);
1501 offset += 2;
1502 break;
1503
1504 case 0140:
1505 case 0141:
1506 case 0142:
1507 case 0143:
1508 data = opx->offset;
1509 if (is_sbyte16(ins, c & 3)) {
1510 bytes[0] = data;
1511 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1512 NO_SEG);
1513 offset++;
1514 } else {
1515 if (opx->segment == NO_SEG &&
1516 opx->wrt == NO_SEG)
1517 warn_overflow(2, data);
1518 out(offset, segment, &data, OUT_ADDRESS, 2,
1519 opx->segment, opx->wrt);
1520 offset += 2;
1521 }
1522 break;
1523
1524 case 0144:
1525 case 0145:
1526 case 0146:
1527 case 0147:
1528 EMIT_REX();
1529 bytes[0] = *codes++;
1530 if (is_sbyte16(ins, c & 3))
1531 bytes[0] |= 2; /* s-bit */
1532 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1533 offset++;
1534 break;
1535
1536 case 0150:
1537 case 0151:
1538 case 0152:
1539 case 0153:
1540 data = opx->offset;
1541 if (is_sbyte32(ins, c & 3)) {
1542 bytes[0] = data;
1543 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1544 NO_SEG);
1545 offset++;
1546 } else {
1547 out(offset, segment, &data, OUT_ADDRESS, 4,
1548 opx->segment, opx->wrt);
1549 offset += 4;
1550 }
1551 break;
1552
1553 case 0154:
1554 case 0155:
1555 case 0156:
1556 case 0157:
1557 EMIT_REX();
1558 bytes[0] = *codes++;
1559 if (is_sbyte32(ins, c & 3))
1560 bytes[0] |= 2; /* s-bit */
1561 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1562 offset++;
1563 break;
1564
1565 case 0160:
1566 case 0161:
1567 case 0162:
1568 case 0163:
1569 case 0164:
1570 case 0165:
1571 case 0166:
1572 case 0167:
1573 break;
1574
1575 case 0171:
1576 bytes[0] =
1577 (ins->drexdst << 4) |
1578 (ins->rex & REX_OC ? 0x08 : 0) |
1579 (ins->rex & (REX_R|REX_X|REX_B));
1580 ins->rex = 0;
1581 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1582 offset++;
1583 break;
1584
1585 case 0172:
1586 c = *codes++;
1587 opx = &ins->oprs[c >> 3];
1588 bytes[0] = nasm_regvals[opx->basereg] << 4;
1589 opx = &ins->oprs[c & 7];
1590 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1591 errfunc(ERR_NONFATAL,
1592 "non-absolute expression not permitted as argument %d",
1593 c & 7);
1594 } else {
1595 if (opx->offset & ~15) {
1596 errfunc(ERR_WARNING | ERR_WARN_NOV,
1597 "four-bit argument exceeds bounds");
1598 }
1599 bytes[0] |= opx->offset & 15;
1600 }
1601 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1602 offset++;
1603 break;
1604
1605 case 0173:
1606 c = *codes++;
1607 opx = &ins->oprs[c >> 4];
1608 bytes[0] = nasm_regvals[opx->basereg] << 4;
1609 bytes[0] |= c & 15;
1610 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1611 offset++;
1612 break;
1613
1614 case 0250:
1615 case 0251:
1616 case 0252:
1617 case 0253:
1618 data = opx->offset;
1619 /* is_sbyte32() is right here, we have already warned */
1620 if (is_sbyte32(ins, c & 3)) {
1621 bytes[0] = data;
1622 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1623 NO_SEG);
1624 offset++;
1625 } else {
1626 out(offset, segment, &data, OUT_ADDRESS, 4,
1627 opx->segment, opx->wrt);
1628 offset += 4;
1629 }
1630 break;
1631
1632 case 0260:
1633 case 0261:
1634 case 0262:
1635 case 0263:
1636 case 0270:
1637 codes += 2;
1638 if (ins->vex_m != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1639 bytes[0] = 0xc4;
1640 bytes[1] = ins->vex_m | ((~ins->rex & 7) << 5);
1641 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1642 ((~ins->drexdst & 15)<< 3) | (ins->vex_wlp & 07);
1643 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1644 offset += 3;
1645 } else {
1646 bytes[0] = 0xc5;
1647 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1648 ((~ins->drexdst & 15) << 3) | (ins->vex_wlp & 07);
1649 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1650 offset += 2;
1651 }
1652 break;
1653
1654 case 0300:
1655 case 0301:
1656 case 0302:
1657 case 0303:
1658 break;
1659
1660 case 0310:
1661 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1662 *bytes = 0x67;
1663 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1664 offset += 1;
1665 } else
1666 offset += 0;
1667 break;
1668
1669 case 0311:
1670 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1671 *bytes = 0x67;
1672 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1673 offset += 1;
1674 } else
1675 offset += 0;
1676 break;
1677
1678 case 0312:
1679 break;
1680
1681 case 0313:
1682 ins->rex = 0;
1683 break;
1684
1685 case 0314:
1686 case 0315:
1687 case 0316:
1688 case 0317:
1689 break;
1690
1691 case 0320:
1692 if (bits != 16) {
1693 *bytes = 0x66;
1694 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1695 offset += 1;
1696 } else
1697 offset += 0;
1698 break;
1699
1700 case 0321:
1701 if (bits == 16) {
1702 *bytes = 0x66;
1703 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1704 offset += 1;
1705 } else
1706 offset += 0;
1707 break;
1708
1709 case 0322:
1710 case 0323:
1711 break;
1712
1713 case 0324:
1714 ins->rex |= REX_W;
1715 break;
1716
1717 case 0330:
1718 *bytes = *codes++ ^ condval[ins->condition];
1719 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1720 offset += 1;
1721 break;
1722
1723 case 0331:
1724 break;
1725
1726 case 0332:
1727 case 0333:
1728 *bytes = c - 0332 + 0xF2;
1729 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1730 offset += 1;
1731 break;
1732
1733 case 0334:
1734 if (ins->rex & REX_R) {
1735 *bytes = 0xF0;
1736 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1737 offset += 1;
1738 }
1739 ins->rex &= ~(REX_L|REX_R);
1740 break;
1741
1742 case 0335:
1743 break;
1744
1745 case 0340:
1746 if (ins->oprs[0].segment != NO_SEG)
1747 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1748 else {
1749 int64_t size = ins->oprs[0].offset;
1750 if (size > 0)
1751 out(offset, segment, NULL,
1752 OUT_RESERVE, size, NO_SEG, NO_SEG);
1753 offset += size;
1754 }
1755 break;
1756
1757 case 0360:
1758 break;
1759
1760 case 0361:
1761 bytes[0] = 0x66;
1762 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1763 offset += 1;
1764 break;
1765
1766 case 0362:
1767 case 0363:
1768 bytes[0] = c - 0362 + 0xf2;
1769 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1770 offset += 1;
1771 break;
1772
1773 case 0364:
1774 case 0365:
1775 break;
1776
1777 case 0366:
1778 case 0367:
1779 *bytes = c - 0366 + 0x66;
1780 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1781 offset += 1;
1782 break;
1783
1784 case 0370:
1785 case 0371:
1786 case 0372:
1787 break;
1788
1789 case 0373:
1790 *bytes = bits == 16 ? 3 : 5;
1791 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1792 offset += 1;
1793 break;
1794
1795 default: /* can't do it by 'case' statements */
1796 if (c >= 0100 && c <= 0277) { /* it's an EA */
1797 ea ea_data;
1798 int rfield;
1799 int32_t rflags;
1800 uint8_t *p;
1801 int32_t s;
1802
1803 if (c <= 0177) {
1804 /* pick rfield from operand b */
1805 rflags = regflag(&ins->oprs[c & 7]);
1806 rfield = nasm_regvals[ins->oprs[c & 7].basereg];
1807 } else {
1808 /* rfield is constant */
1809 rflags = 0;
1810 rfield = c & 7;
1811 }
1812
1813 if (!process_ea
1814 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1815 ins->addr_size, rfield, rflags, ins->forw_ref)) {
1816 errfunc(ERR_NONFATAL, "invalid effective address");
1817 }
1818
1819
1820 p = bytes;
1821 *p++ = ea_data.modrm;
1822 if (ea_data.sib_present)
1823 *p++ = ea_data.sib;
1824
1825 /* DREX suffixes come between the SIB and the displacement */
1826 if (ins->rex & REX_D) {
1827 *p++ =
1828 (ins->drexdst << 4) |
1829 (ins->rex & REX_OC ? 0x08 : 0) |
1830 (ins->rex & (REX_R|REX_X|REX_B));
1831 ins->rex = 0;
1832 }
1833
1834 s = p - bytes;
1835 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1836
1837 switch (ea_data.bytes) {
1838 case 0:
1839 break;
1840 case 1:
1841 if (ins->oprs[(c >> 3) & 7].segment != NO_SEG) {
1842 data = ins->oprs[(c >> 3) & 7].offset;
1843 out(offset, segment, &data, OUT_ADDRESS, 1,
1844 ins->oprs[(c >> 3) & 7].segment,
1845 ins->oprs[(c >> 3) & 7].wrt);
1846 } else {
1847 *bytes = ins->oprs[(c >> 3) & 7].offset;
1848 out(offset, segment, bytes, OUT_RAWDATA, 1,
1849 NO_SEG, NO_SEG);
1850 }
1851 s++;
1852 break;
1853 case 8:
1854 case 2:
1855 case 4:
1856 data = ins->oprs[(c >> 3) & 7].offset;
1857 warn_overflow(ea_data.bytes, data);
1858 out(offset, segment, &data,
1859 ea_data.rip ? OUT_REL4ADR : OUT_ADDRESS,
1860 ea_data.bytes,
1861 ins->oprs[(c >> 3) & 7].segment,
1862 ins->oprs[(c >> 3) & 7].wrt);
1863 s += ea_data.bytes;
1864 break;
1865 }
1866 offset += s;
1867 } else {
1868 errfunc(ERR_PANIC, "internal instruction table corrupt"
1869 ": instruction code 0x%02X given", c);
1870 }
1871 }
1872 }
1873 }
1874
1875 static int32_t regflag(const operand * o)
1876 {
1877 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1878 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1879 }
1880 return nasm_reg_flags[o->basereg];
1881 }
1882
1883 static int32_t regval(const operand * o)
1884 {
1885 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1886 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1887 }
1888 return nasm_regvals[o->basereg];
1889 }
1890
1891 static int op_rexflags(const operand * o, int mask)
1892 {
1893 int32_t flags;
1894 int val;
1895
1896 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1897 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1898 }
1899
1900 flags = nasm_reg_flags[o->basereg];
1901 val = nasm_regvals[o->basereg];
1902
1903 return rexflags(val, flags, mask);
1904 }
1905
1906 static int rexflags(int val, int32_t flags, int mask)
1907 {
1908 int rex = 0;
1909
1910 if (val >= 8)
1911 rex |= REX_B|REX_X|REX_R;
1912 if (flags & BITS64)
1913 rex |= REX_W;
1914 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1915 rex |= REX_H;
1916 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1917 rex |= REX_P;
1918
1919 return rex & mask;
1920 }
1921
1922 static int matches(const struct itemplate *itemp, insn * instruction, int bits)
1923 {
1924 int i, size[MAX_OPERANDS], asize, oprs, ret;
1925
1926 ret = 100;
1927
1928 /*
1929 * Check the opcode
1930 */
1931 if (itemp->opcode != instruction->opcode)
1932 return 0;
1933
1934 /*
1935 * Count the operands
1936 */
1937 if (itemp->operands != instruction->operands)
1938 return 0;
1939
1940 /*
1941 * Check that no spurious colons or TOs are present
1942 */
1943 for (i = 0; i < itemp->operands; i++)
1944 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1945 return 0;
1946
1947 /*
1948 * Process size flags
1949 */
1950 if (itemp->flags & IF_ARMASK) {
1951 memset(size, 0, sizeof size);
1952
1953 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
1954
1955 switch (itemp->flags & IF_SMASK) {
1956 case IF_SB:
1957 size[i] = BITS8;
1958 break;
1959 case IF_SW:
1960 size[i] = BITS16;
1961 break;
1962 case IF_SD:
1963 size[i] = BITS32;
1964 break;
1965 case IF_SQ:
1966 size[i] = BITS64;
1967 break;
1968 case IF_SO:
1969 size[i] = BITS128;
1970 break;
1971 case IF_SY:
1972 size[i] = BITS256;
1973 break;
1974 case IF_SZ:
1975 switch (bits) {
1976 case 16:
1977 size[i] = BITS16;
1978 break;
1979 case 32:
1980 size[i] = BITS32;
1981 break;
1982 case 64:
1983 size[i] = BITS64;
1984 break;
1985 }
1986 break;
1987 default:
1988 break;
1989 }
1990 } else {
1991 asize = 0;
1992 switch (itemp->flags & IF_SMASK) {
1993 case IF_SB:
1994 asize = BITS8;
1995 break;
1996 case IF_SW:
1997 asize = BITS16;
1998 break;
1999 case IF_SD:
2000 asize = BITS32;
2001 break;
2002 case IF_SQ:
2003 asize = BITS64;
2004 break;
2005 case IF_SO:
2006 asize = BITS128;
2007 break;
2008 case IF_SY:
2009 asize = BITS256;
2010 break;
2011 case IF_SZ:
2012 switch (bits) {
2013 case 16:
2014 asize = BITS16;
2015 break;
2016 case 32:
2017 asize = BITS32;
2018 break;
2019 case 64:
2020 asize = BITS64;
2021 break;
2022 }
2023 break;
2024 default:
2025 break;
2026 }
2027 for (i = 0; i < MAX_OPERANDS; i++)
2028 size[i] = asize;
2029 }
2030
2031 /*
2032 * Check that the operand flags all match up
2033 */
2034 for (i = 0; i < itemp->operands; i++) {
2035 int32_t type = instruction->oprs[i].type;
2036 if (!(type & SIZE_MASK))
2037 type |= size[i];
2038
2039 if (itemp->opd[i] & SAME_AS) {
2040 int j = itemp->opd[i] & ~SAME_AS;
2041 if (type != instruction->oprs[j].type ||
2042 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
2043 return 0;
2044 } else if (itemp->opd[i] & ~type ||
2045 ((itemp->opd[i] & SIZE_MASK) &&
2046 ((itemp->opd[i] ^ type) & SIZE_MASK))) {
2047 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2048 (type & SIZE_MASK))
2049 return 0;
2050 else
2051 return 1;
2052 }
2053 }
2054
2055 /*
2056 * Check operand sizes
2057 */
2058 if (itemp->flags & (IF_SM | IF_SM2)) {
2059 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2060 asize = 0;
2061 for (i = 0; i < oprs; i++) {
2062 if ((asize = itemp->opd[i] & SIZE_MASK) != 0) {
2063 int j;
2064 for (j = 0; j < oprs; j++)
2065 size[j] = asize;
2066 break;
2067 }
2068 }
2069 } else {
2070 oprs = itemp->operands;
2071 }
2072
2073 for (i = 0; i < itemp->operands; i++) {
2074 if (!(itemp->opd[i] & SIZE_MASK) &&
2075 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2076 return 2;
2077 }
2078
2079 /*
2080 * Check template is okay at the set cpu level
2081 */
2082 if (((itemp->flags & IF_PLEVEL) > cpu))
2083 return 3;
2084
2085 /*
2086 * Check if instruction is available in long mode
2087 */
2088 if ((itemp->flags & IF_NOLONG) && (bits == 64))
2089 return 4;
2090
2091 /*
2092 * Check if special handling needed for Jumps
2093 */
2094 if ((uint8_t)(itemp->code[0]) >= 0370)
2095 return 99;
2096
2097 return ret;
2098 }
2099
2100 static ea *process_ea(operand * input, ea * output, int bits,
2101 int addrbits, int rfield, int32_t rflags, int forw_ref)
2102 {
2103 output->rip = false;
2104
2105 /* REX flags for the rfield operand */
2106 output->rex |= rexflags(rfield, rflags, REX_R|REX_P|REX_W|REX_H);
2107
2108 if (!(REGISTER & ~input->type)) { /* register direct */
2109 int i;
2110 int32_t f;
2111
2112 if (input->basereg < EXPR_REG_START /* Verify as Register */
2113 || input->basereg >= REG_ENUM_LIMIT)
2114 return NULL;
2115 f = regflag(input);
2116 i = nasm_regvals[input->basereg];
2117
2118 if (REG_EA & ~f)
2119 return NULL; /* Invalid EA register */
2120
2121 output->rex |= op_rexflags(input, REX_B|REX_P|REX_W|REX_H);
2122
2123 output->sib_present = false; /* no SIB necessary */
2124 output->bytes = 0; /* no offset necessary either */
2125 output->modrm = 0xC0 | ((rfield & 7) << 3) | (i & 7);
2126 } else { /* it's a memory reference */
2127 if (input->basereg == -1
2128 && (input->indexreg == -1 || input->scale == 0)) {
2129 /* it's a pure offset */
2130 if (bits == 64 && (~input->type & IP_REL)) {
2131 int scale, index, base;
2132 output->sib_present = true;
2133 scale = 0;
2134 index = 4;
2135 base = 5;
2136 output->sib = (scale << 6) | (index << 3) | base;
2137 output->bytes = 4;
2138 output->modrm = 4 | ((rfield & 7) << 3);
2139 output->rip = false;
2140 } else {
2141 output->sib_present = false;
2142 output->bytes = (addrbits != 16 ? 4 : 2);
2143 output->modrm = (addrbits != 16 ? 5 : 6) | ((rfield & 7) << 3);
2144 output->rip = bits == 64;
2145 }
2146 } else { /* it's an indirection */
2147 int i = input->indexreg, b = input->basereg, s = input->scale;
2148 int32_t o = input->offset, seg = input->segment;
2149 int hb = input->hintbase, ht = input->hinttype;
2150 int t;
2151 int it, bt;
2152 int32_t ix, bx; /* register flags */
2153
2154 if (s == 0)
2155 i = -1; /* make this easy, at least */
2156
2157 if (i >= EXPR_REG_START && i < REG_ENUM_LIMIT) {
2158 it = nasm_regvals[i];
2159 ix = nasm_reg_flags[i];
2160 } else {
2161 it = -1;
2162 ix = 0;
2163 }
2164
2165 if (b >= EXPR_REG_START && b < REG_ENUM_LIMIT) {
2166 bt = nasm_regvals[b];
2167 bx = nasm_reg_flags[b];
2168 } else {
2169 bt = -1;
2170 bx = 0;
2171 }
2172
2173 /* check for a 32/64-bit memory reference... */
2174 if ((ix|bx) & (BITS32|BITS64)) {
2175 /* it must be a 32/64-bit memory reference. Firstly we have
2176 * to check that all registers involved are type E/Rxx. */
2177 int32_t sok = BITS32|BITS64;
2178
2179 if (it != -1) {
2180 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2181 sok &= ix;
2182 else
2183 return NULL;
2184 }
2185
2186 if (bt != -1) {
2187 if (REG_GPR & ~bx)
2188 return NULL; /* Invalid register */
2189 if (~sok & bx & SIZE_MASK)
2190 return NULL; /* Invalid size */
2191 sok &= bx;
2192 }
2193
2194 /* While we're here, ensure the user didn't specify
2195 WORD or QWORD. */
2196 if (input->disp_size == 16 || input->disp_size == 64)
2197 return NULL;
2198
2199 if (addrbits == 16 ||
2200 (addrbits == 32 && !(sok & BITS32)) ||
2201 (addrbits == 64 && !(sok & BITS64)))
2202 return NULL;
2203
2204 /* now reorganize base/index */
2205 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2206 ((hb == b && ht == EAH_NOTBASE)
2207 || (hb == i && ht == EAH_MAKEBASE))) {
2208 /* swap if hints say so */
2209 t = bt, bt = it, it = t;
2210 t = bx, bx = ix, ix = t;
2211 }
2212 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2213 bt = -1, bx = 0, s++;
2214 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2215 /* make single reg base, unless hint */
2216 bt = it, bx = ix, it = -1, ix = 0;
2217 }
2218 if (((s == 2 && it != REG_NUM_ESP
2219 && !(input->eaflags & EAF_TIMESTWO)) || s == 3
2220 || s == 5 || s == 9) && bt == -1)
2221 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2222 if (it == -1 && (bt & 7) != REG_NUM_ESP
2223 && (input->eaflags & EAF_TIMESTWO))
2224 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2225 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2226 if (s == 1 && it == REG_NUM_ESP) {
2227 /* swap ESP into base if scale is 1 */
2228 t = it, it = bt, bt = t;
2229 t = ix, ix = bx, bx = t;
2230 }
2231 if (it == REG_NUM_ESP
2232 || (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2233 return NULL; /* wrong, for various reasons */
2234
2235 output->rex |= rexflags(it, ix, REX_X);
2236 output->rex |= rexflags(bt, bx, REX_B);
2237
2238 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2239 /* no SIB needed */
2240 int mod, rm;
2241
2242 if (bt == -1) {
2243 rm = 5;
2244 mod = 0;
2245 } else {
2246 rm = (bt & 7);
2247 if (rm != REG_NUM_EBP && o == 0 &&
2248 seg == NO_SEG && !forw_ref &&
2249 !(input->eaflags &
2250 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2251 mod = 0;
2252 else if (input->eaflags & EAF_BYTEOFFS ||
2253 (o >= -128 && o <= 127 && seg == NO_SEG
2254 && !forw_ref
2255 && !(input->eaflags & EAF_WORDOFFS)))
2256 mod = 1;
2257 else
2258 mod = 2;
2259 }
2260
2261 output->sib_present = false;
2262 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2263 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2264 } else {
2265 /* we need a SIB */
2266 int mod, scale, index, base;
2267
2268 if (it == -1)
2269 index = 4, s = 1;
2270 else
2271 index = (it & 7);
2272
2273 switch (s) {
2274 case 1:
2275 scale = 0;
2276 break;
2277 case 2:
2278 scale = 1;
2279 break;
2280 case 4:
2281 scale = 2;
2282 break;
2283 case 8:
2284 scale = 3;
2285 break;
2286 default: /* then what the smeg is it? */
2287 return NULL; /* panic */
2288 }
2289
2290 if (bt == -1) {
2291 base = 5;
2292 mod = 0;
2293 } else {
2294 base = (bt & 7);
2295 if (base != REG_NUM_EBP && o == 0 &&
2296 seg == NO_SEG && !forw_ref &&
2297 !(input->eaflags &
2298 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2299 mod = 0;
2300 else if (input->eaflags & EAF_BYTEOFFS ||
2301 (o >= -128 && o <= 127 && seg == NO_SEG
2302 && !forw_ref
2303 && !(input->eaflags & EAF_WORDOFFS)))
2304 mod = 1;
2305 else
2306 mod = 2;
2307 }
2308
2309 output->sib_present = true;
2310 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2311 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2312 output->sib = (scale << 6) | (index << 3) | base;
2313 }
2314 } else { /* it's 16-bit */
2315 int mod, rm;
2316
2317 /* check for 64-bit long mode */
2318 if (addrbits == 64)
2319 return NULL;
2320
2321 /* check all registers are BX, BP, SI or DI */
2322 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI
2323 && b != R_DI) || (i != -1 && i != R_BP && i != R_BX
2324 && i != R_SI && i != R_DI))
2325 return NULL;
2326
2327 /* ensure the user didn't specify DWORD/QWORD */
2328 if (input->disp_size == 32 || input->disp_size == 64)
2329 return NULL;
2330
2331 if (s != 1 && i != -1)
2332 return NULL; /* no can do, in 16-bit EA */
2333 if (b == -1 && i != -1) {
2334 int tmp = b;
2335 b = i;
2336 i = tmp;
2337 } /* swap */
2338 if ((b == R_SI || b == R_DI) && i != -1) {
2339 int tmp = b;
2340 b = i;
2341 i = tmp;
2342 }
2343 /* have BX/BP as base, SI/DI index */
2344 if (b == i)
2345 return NULL; /* shouldn't ever happen, in theory */
2346 if (i != -1 && b != -1 &&
2347 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2348 return NULL; /* invalid combinations */
2349 if (b == -1) /* pure offset: handled above */
2350 return NULL; /* so if it gets to here, panic! */
2351
2352 rm = -1;
2353 if (i != -1)
2354 switch (i * 256 + b) {
2355 case R_SI * 256 + R_BX:
2356 rm = 0;
2357 break;
2358 case R_DI * 256 + R_BX:
2359 rm = 1;
2360 break;
2361 case R_SI * 256 + R_BP:
2362 rm = 2;
2363 break;
2364 case R_DI * 256 + R_BP:
2365 rm = 3;
2366 break;
2367 } else
2368 switch (b) {
2369 case R_SI:
2370 rm = 4;
2371 break;
2372 case R_DI:
2373 rm = 5;
2374 break;
2375 case R_BP:
2376 rm = 6;
2377 break;
2378 case R_BX:
2379 rm = 7;
2380 break;
2381 }
2382 if (rm == -1) /* can't happen, in theory */
2383 return NULL; /* so panic if it does */
2384
2385 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2386 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2387 mod = 0;
2388 else if (input->eaflags & EAF_BYTEOFFS ||
2389 (o >= -128 && o <= 127 && seg == NO_SEG
2390 && !forw_ref
2391 && !(input->eaflags & EAF_WORDOFFS)))
2392 mod = 1;
2393 else
2394 mod = 2;
2395
2396 output->sib_present = false; /* no SIB - it's 16-bit */
2397 output->bytes = mod; /* bytes of offset needed */
2398 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2399 }
2400 }
2401 }
2402
2403 output->size = 1 + output->sib_present + output->bytes;
2404 return output;
2405 }
2406
2407 static void add_asp(insn *ins, int addrbits)
2408 {
2409 int j, valid;
2410 int defdisp;
2411
2412 valid = (addrbits == 64) ? 64|32 : 32|16;
2413
2414 switch (ins->prefixes[PPS_ASIZE]) {
2415 case P_A16:
2416 valid &= 16;
2417 break;
2418 case P_A32:
2419 valid &= 32;
2420 break;
2421 case P_A64:
2422 valid &= 64;
2423 break;
2424 case P_ASP:
2425 valid &= (addrbits == 32) ? 16 : 32;
2426 break;
2427 default:
2428 break;
2429 }
2430
2431 for (j = 0; j < ins->operands; j++) {
2432 if (!(MEMORY & ~ins->oprs[j].type)) {
2433 int32_t i, b;
2434
2435 /* Verify as Register */
2436 if (ins->oprs[j].indexreg < EXPR_REG_START
2437 || ins->oprs[j].indexreg >= REG_ENUM_LIMIT)
2438 i = 0;
2439 else
2440 i = nasm_reg_flags[ins->oprs[j].indexreg];
2441
2442 /* Verify as Register */
2443 if (ins->oprs[j].basereg < EXPR_REG_START
2444 || ins->oprs[j].basereg >= REG_ENUM_LIMIT)
2445 b = 0;
2446 else
2447 b = nasm_reg_flags[ins->oprs[j].basereg];
2448
2449 if (ins->oprs[j].scale == 0)
2450 i = 0;
2451
2452 if (!i && !b) {
2453 int ds = ins->oprs[j].disp_size;
2454 if ((addrbits != 64 && ds > 8) ||
2455 (addrbits == 64 && ds == 16))
2456 valid &= ds;
2457 } else {
2458 if (!(REG16 & ~b))
2459 valid &= 16;
2460 if (!(REG32 & ~b))
2461 valid &= 32;
2462 if (!(REG64 & ~b))
2463 valid &= 64;
2464
2465 if (!(REG16 & ~i))
2466 valid &= 16;
2467 if (!(REG32 & ~i))
2468 valid &= 32;
2469 if (!(REG64 & ~i))
2470 valid &= 64;
2471 }
2472 }
2473 }
2474
2475 if (valid & addrbits) {
2476 ins->addr_size = addrbits;
2477 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2478 /* Add an address size prefix */
2479 enum prefixes pref = (addrbits == 32) ? P_A16 : P_A32;
2480 ins->prefixes[PPS_ASIZE] = pref;
2481 ins->addr_size = (addrbits == 32) ? 16 : 32;
2482 } else {
2483 /* Impossible... */
2484 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2485 ins->addr_size = addrbits; /* Error recovery */
2486 }
2487
2488 defdisp = ins->addr_size == 16 ? 16 : 32;
2489
2490 for (j = 0; j < ins->operands; j++) {
2491 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2492 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp)
2493 != ins->addr_size) {
2494 /* mem_offs sizes must match the address size; if not,
2495 strip the MEM_OFFS bit and match only EA instructions */
2496 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2497 }
2498 }
2499 }
The Netwide Assembler