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test/reldef.asm: add some global symbols
[nasm.git] / asm / assemble.c
blob9b720772f94b78240bf58e45d9b3065c9b298503
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2017 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * Bytecode specification
38 * ----------------------
39 *
40 *
41 * Codes Mnemonic Explanation
42 *
43 * \0 terminates the code. (Unless it's a literal of course.)
44 * \1..\4 that many literal bytes follow in the code stream
45 * \5 add 4 to the primary operand number (b, low octdigit)
46 * \6 add 4 to the secondary operand number (a, middle octdigit)
47 * \7 add 4 to both the primary and the secondary operand number
48 * \10..\13 a literal byte follows in the code stream, to be added
49 * to the register value of operand 0..3
50 * \14..\17 the position of index register operand in MIB (BND insns)
51 * \20..\23 ib a byte immediate operand, from operand 0..3
52 * \24..\27 ib,u a zero-extended byte immediate operand, from operand 0..3
53 * \30..\33 iw a word immediate operand, from operand 0..3
54 * \34..\37 iwd select between \3[0-3] and \4[0-3] depending on 16/32 bit
55 * assembly mode or the operand-size override on the operand
56 * \40..\43 id a long immediate operand, from operand 0..3
57 * \44..\47 iwdq select between \3[0-3], \4[0-3] and \5[4-7]
58 * depending on the address size of the instruction.
59 * \50..\53 rel8 a byte relative operand, from operand 0..3
60 * \54..\57 iq a qword immediate operand, from operand 0..3
61 * \60..\63 rel16 a word relative operand, from operand 0..3
62 * \64..\67 rel select between \6[0-3] and \7[0-3] depending on 16/32 bit
63 * assembly mode or the operand-size override on the operand
64 * \70..\73 rel32 a long relative operand, from operand 0..3
65 * \74..\77 seg a word constant, from the _segment_ part of operand 0..3
66 * \1ab a ModRM, calculated on EA in operand a, with the spare
67 * field the register value of operand b.
68 * \172\ab the register number from operand a in bits 7..4, with
69 * the 4-bit immediate from operand b in bits 3..0.
70 * \173\xab the register number from operand a in bits 7..4, with
71 * the value b in bits 3..0.
72 * \174..\177 the register number from operand 0..3 in bits 7..4, and
73 * an arbitrary value in bits 3..0 (assembled as zero.)
74 * \2ab a ModRM, calculated on EA in operand a, with the spare
75 * field equal to digit b.
76 *
77 * \240..\243 this instruction uses EVEX rather than REX or VEX/XOP, with the
78 * V field taken from operand 0..3.
79 * \250 this instruction uses EVEX rather than REX or VEX/XOP, with the
80 * V field set to 1111b.
81 *
82 * EVEX prefixes are followed by the sequence:
83 * \cm\wlp\tup where cm is:
84 * cc 00m mmm
85 * c = 2 for EVEX and mmmm is the M field (EVEX.P0[3:0])
86 * and wlp is:
87 * 00 wwl lpp
88 * [l0] ll = 0 (.128, .lz)
89 * [l1] ll = 1 (.256)
90 * [l2] ll = 2 (.512)
91 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
92 *
93 * [w0] ww = 0 for W = 0
94 * [w1] ww = 1 for W = 1
95 * [wig] ww = 2 for W don't care (always assembled as 0)
96 * [ww] ww = 3 for W used as REX.W
97 *
98 * [p0] pp = 0 for no prefix
99 * [60] pp = 1 for legacy prefix 60
100 * [f3] pp = 2
101 * [f2] pp = 3
102 *
103 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
104 * (compressed displacement encoding)
105 *
106 * \254..\257 id,s a signed 32-bit operand to be extended to 64 bits.
107 * \260..\263 this instruction uses VEX/XOP rather than REX, with the
108 * V field taken from operand 0..3.
109 * \270 this instruction uses VEX/XOP rather than REX, with the
110 * V field set to 1111b.
111 *
112 * VEX/XOP prefixes are followed by the sequence:
113 * \tmm\wlp where mm is the M field; and wlp is:
114 * 00 wwl lpp
115 * [l0] ll = 0 for L = 0 (.128, .lz)
116 * [l1] ll = 1 for L = 1 (.256)
117 * [lig] ll = 2 for L don't care (always assembled as 0)
118 *
119 * [w0] ww = 0 for W = 0
120 * [w1 ] ww = 1 for W = 1
121 * [wig] ww = 2 for W don't care (always assembled as 0)
122 * [ww] ww = 3 for W used as REX.W
123 *
124 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
125 *
126 * \271 hlexr instruction takes XRELEASE (F3) with or without lock
127 * \272 hlenl instruction takes XACQUIRE/XRELEASE with or without lock
128 * \273 hle instruction takes XACQUIRE/XRELEASE with lock only
129 * \274..\277 ib,s a byte immediate operand, from operand 0..3, sign-extended
130 * to the operand size (if o16/o32/o64 present) or the bit size
131 * \310 a16 indicates fixed 16-bit address size, i.e. optional 0x67.
132 * \311 a32 indicates fixed 32-bit address size, i.e. optional 0x67.
133 * \312 adf (disassembler only) invalid with non-default address size.
134 * \313 a64 indicates fixed 64-bit address size, 0x67 invalid.
135 * \314 norexb (disassembler only) invalid with REX.B
136 * \315 norexx (disassembler only) invalid with REX.X
137 * \316 norexr (disassembler only) invalid with REX.R
138 * \317 norexw (disassembler only) invalid with REX.W
139 * \320 o16 indicates fixed 16-bit operand size, i.e. optional 0x66.
140 * \321 o32 indicates fixed 32-bit operand size, i.e. optional 0x66.
141 * \322 odf indicates that this instruction is only valid when the
142 * operand size is the default (instruction to disassembler,
143 * generates no code in the assembler)
144 * \323 o64nw indicates fixed 64-bit operand size, REX on extensions only.
145 * \324 o64 indicates 64-bit operand size requiring REX prefix.
146 * \325 nohi instruction which always uses spl/bpl/sil/dil
147 * \326 nof3 instruction not valid with 0xF3 REP prefix. Hint for
148 disassembler only; for SSE instructions.
149 * \330 a literal byte follows in the code stream, to be added
150 * to the condition code value of the instruction.
151 * \331 norep instruction not valid with REP prefix. Hint for
152 * disassembler only; for SSE instructions.
153 * \332 f2i REP prefix (0xF2 byte) used as opcode extension.
154 * \333 f3i REP prefix (0xF3 byte) used as opcode extension.
155 * \334 rex.l LOCK prefix used as REX.R (used in non-64-bit mode)
156 * \335 repe disassemble a rep (0xF3 byte) prefix as repe not rep.
157 * \336 mustrep force a REP(E) prefix (0xF3) even if not specified.
158 * \337 mustrepne force a REPNE prefix (0xF2) even if not specified.
159 * \336-\337 are still listed as prefixes in the disassembler.
160 * \340 resb reserve <operand 0> bytes of uninitialized storage.
161 * Operand 0 had better be a segmentless constant.
162 * \341 wait this instruction needs a WAIT "prefix"
163 * \360 np no SSE prefix (== \364\331)
164 * \361 66 SSE prefix (== \366\331)
165 * \364 !osp operand-size prefix (0x66) not permitted
166 * \365 !asp address-size prefix (0x67) not permitted
167 * \366 operand-size prefix (0x66) used as opcode extension
168 * \367 address-size prefix (0x67) used as opcode extension
169 * \370,\371 jcc8 match only if operand 0 meets byte jump criteria.
170 * jmp8 370 is used for Jcc, 371 is used for JMP.
171 * \373 jlen assemble 0x03 if bits==16, 0x05 if bits==32;
172 * used for conditional jump over longer jump
173 * \374 vsibx|vm32x|vm64x this instruction takes an XMM VSIB memory EA
174 * \375 vsiby|vm32y|vm64y this instruction takes an YMM VSIB memory EA
175 * \376 vsibz|vm32z|vm64z this instruction takes an ZMM VSIB memory EA
176 */
177
178 #include "compiler.h"
179
180 #include <stdio.h>
181 #include <string.h>
182 #include <stdlib.h>
183
184 #include "nasm.h"
185 #include "nasmlib.h"
186 #include "error.h"
187 #include "assemble.h"
188 #include "insns.h"
189 #include "tables.h"
190 #include "disp8.h"
191 #include "listing.h"
192
193 enum match_result {
194 /*
195 * Matching errors. These should be sorted so that more specific
196 * errors come later in the sequence.
197 */
198 MERR_INVALOP,
199 MERR_OPSIZEMISSING,
200 MERR_OPSIZEMISMATCH,
201 MERR_BRNOTHERE,
202 MERR_BRNUMMISMATCH,
203 MERR_MASKNOTHERE,
204 MERR_BADCPU,
205 MERR_BADMODE,
206 MERR_BADHLE,
207 MERR_ENCMISMATCH,
208 MERR_BADBND,
209 MERR_BADREPNE,
210 /*
211 * Matching success; the conditional ones first
212 */
213 MOK_JUMP, /* Matching OK but needs jmp_match() */
214 MOK_GOOD /* Matching unconditionally OK */
215 };
216
217 typedef struct {
218 enum ea_type type; /* what kind of EA is this? */
219 int sib_present; /* is a SIB byte necessary? */
220 int bytes; /* # of bytes of offset needed */
221 int size; /* lazy - this is sib+bytes+1 */
222 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
223 int8_t disp8; /* compressed displacement for EVEX */
224 } ea;
225
226 #define GEN_SIB(scale, index, base) \
227 (((scale) << 6) | ((index) << 3) | ((base)))
228
229 #define GEN_MODRM(mod, reg, rm) \
230 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
231
232 static int64_t calcsize(int32_t, int64_t, int, insn *,
233 const struct itemplate *);
234 static int emit_prefix(struct out_data *data, const int bits, insn *ins);
235 static void gencode(struct out_data *data, insn *ins);
236 static enum match_result find_match(const struct itemplate **tempp,
237 insn *instruction,
238 int32_t segment, int64_t offset, int bits);
239 static enum match_result matches(const struct itemplate *, insn *, int bits);
240 static opflags_t regflag(const operand *);
241 static int32_t regval(const operand *);
242 static int rexflags(int, opflags_t, int);
243 static int op_rexflags(const operand *, int);
244 static int op_evexflags(const operand *, int, uint8_t);
245 static void add_asp(insn *, int);
246
247 static enum ea_type process_ea(operand *, ea *, int, int,
248 opflags_t, insn *, const char **);
249
250 static inline bool absolute_op(const struct operand *o)
251 {
252 return o->segment == NO_SEG && o->wrt == NO_SEG &&
253 !(o->opflags & OPFLAG_RELATIVE);
254 }
255
256 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
257 {
258 return ins->prefixes[pos] == prefix;
259 }
260
261 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
262 {
263 if (ins->prefixes[pos])
264 nasm_error(ERR_NONFATAL, "invalid %s prefix",
265 prefix_name(ins->prefixes[pos]));
266 }
267
268 static const char *size_name(int size)
269 {
270 switch (size) {
271 case 1:
272 return "byte";
273 case 2:
274 return "word";
275 case 4:
276 return "dword";
277 case 8:
278 return "qword";
279 case 10:
280 return "tword";
281 case 16:
282 return "oword";
283 case 32:
284 return "yword";
285 case 64:
286 return "zword";
287 default:
288 return "???";
289 }
290 }
291
292 static void warn_overflow(int size)
293 {
294 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
295 "%s data exceeds bounds", size_name(size));
296 }
297
298 static void warn_overflow_const(int64_t data, int size)
299 {
300 if (overflow_general(data, size))
301 warn_overflow(size);
302 }
303
304 static void warn_overflow_opd(const struct operand *o, int size)
305 {
306 if (absolute_op(o)) {
307 if (overflow_general(o->offset, size))
308 warn_overflow(size);
309 }
310 }
311
312 static void warn_overflow_out(int64_t data, int size, enum out_sign sign)
313 {
314 bool err;
315
316 switch (sign) {
317 case OUT_WRAP:
318 err = overflow_general(data, size);
319 break;
320 case OUT_SIGNED:
321 err = overflow_signed(data, size);
322 break;
323 case OUT_UNSIGNED:
324 err = overflow_unsigned(data, size);
325 break;
326 default:
327 panic();
328 break;
329 }
330
331 if (err)
332 warn_overflow(size);
333 }
334
335 /*
336 * This routine wrappers the real output format's output routine,
337 * in order to pass a copy of the data off to the listing file
338 * generator at the same time, flatten unnecessary relocations,
339 * and verify backend compatibility.
340 */
341 static void out(struct out_data *data)
342 {
343 static int32_t lineno = 0; /* static!!! */
344 static const char *lnfname = NULL;
345 int asize;
346 const int amax = ofmt->maxbits >> 3; /* Maximum address size in bytes */
347 union {
348 uint8_t b[8];
349 uint64_t q;
350 } xdata;
351 uint64_t size = data->size;
352 int64_t addrval;
353 int32_t fixseg; /* Segment for which to produce fixed data */
354
355 if (!data->size)
356 return; /* Nothing to do */
357
358 /*
359 * Convert addresses to RAWDATA if possible
360 * XXX: not all backends want this for global symbols!!!!
361 */
362 switch (data->type) {
363 case OUT_ADDRESS:
364 addrval = data->toffset;
365 fixseg = NO_SEG; /* Absolute address is fixed data */
366 goto address;
367
368 case OUT_RELADDR:
369 addrval = data->toffset - data->relbase;
370 fixseg = data->segment; /* Our own segment is fixed data */
371 goto address;
372
373 address:
374 asize = data->size;
375 nasm_assert(asize <= 8);
376 if (data->tsegment == fixseg && data->twrt == NO_SEG) {
377 uint8_t *q = xdata.b;
378
379 warn_overflow_out(addrval, asize, data->sign);
380
381 WRITEADDR(q, addrval, asize);
382 data->data = xdata.b;
383 data->type = OUT_RAWDATA;
384 asize = 0; /* No longer an address */
385 }
386 break;
387
388 default:
389 asize = 0; /* Not an address */
390 break;
391 }
392
393 lfmt->output(data);
394
395 /*
396 * this call to src_get determines when we call the
397 * debug-format-specific "linenum" function
398 * it updates lineno and lnfname to the current values
399 * returning 0 if "same as last time", -2 if lnfname
400 * changed, and the amount by which lineno changed,
401 * if it did. thus, these variables must be static
402 */
403
404 if (src_get(&lineno, &lnfname))
405 dfmt->linenum(lnfname, lineno, data->segment);
406
407 if (asize && asize > amax) {
408 if (data->type != OUT_ADDRESS || data->sign == OUT_SIGNED) {
409 nasm_error(ERR_NONFATAL,
410 "%d-bit signed relocation unsupported by output format %s\n",
411 asize << 3, ofmt->shortname);
412 } else {
413 nasm_error(ERR_WARNING | ERR_WARN_ZEXTRELOC,
414 "%d-bit unsigned relocation zero-extended from %d bits\n",
415 asize << 3, ofmt->maxbits);
416 data->size = amax;
417 ofmt->output(data);
418 data->insoffs += amax;
419 data->offset += amax;
420 data->size = size = asize - amax;
421 }
422 data->data = zero_buffer;
423 data->type = OUT_RAWDATA;
424 }
425
426 ofmt->output(data);
427 data->offset += size;
428 data->insoffs += size;
429 }
430
431 static inline void out_rawdata(struct out_data *data, const void *rawdata,
432 size_t size)
433 {
434 data->type = OUT_RAWDATA;
435 data->data = rawdata;
436 data->size = size;
437 out(data);
438 }
439
440 static void out_rawbyte(struct out_data *data, uint8_t byte)
441 {
442 data->type = OUT_RAWDATA;
443 data->data = &byte;
444 data->size = 1;
445 out(data);
446 }
447
448 static inline void out_reserve(struct out_data *data, uint64_t size)
449 {
450 data->type = OUT_RESERVE;
451 data->size = size;
452 out(data);
453 }
454
455 static inline void out_imm(struct out_data *data, const struct operand *opx,
456 int size, enum out_sign sign)
457 {
458 data->type =
459 (opx->opflags & OPFLAG_RELATIVE) ? OUT_RELADDR : OUT_ADDRESS;
460 data->sign = sign;
461 data->size = size;
462 data->toffset = opx->offset;
463 data->tsegment = opx->segment;
464 data->twrt = opx->wrt;
465 /*
466 * XXX: improve this if at some point in the future we can
467 * distinguish the subtrahend in expressions like [foo - bar]
468 * where bar is a symbol in the current segment. However, at the
469 * current point, if OPFLAG_RELATIVE is set that subtraction has
470 * already occurred.
471 */
472 data->relbase = 0;
473 out(data);
474 }
475
476 static void out_reladdr(struct out_data *data, const struct operand *opx,
477 int size)
478 {
479 if (opx->opflags & OPFLAG_RELATIVE)
480 nasm_error(ERR_NONFATAL, "invalid use of self-relative expression");
481
482 data->type = OUT_RELADDR;
483 data->sign = OUT_SIGNED;
484 data->size = size;
485 data->toffset = opx->offset;
486 data->tsegment = opx->segment;
487 data->twrt = opx->wrt;
488 data->relbase = data->offset + (data->inslen - data->insoffs);
489 out(data);
490 }
491
492 static inline void out_segment(struct out_data *data,
493 const struct operand *opx)
494 {
495 data->type = OUT_SEGMENT;
496 data->sign = OUT_UNSIGNED;
497 data->size = 2;
498 data->toffset = opx->offset; /* Is this really needed/wanted? */
499 data->tsegment = ofmt->segbase(opx->segment + 1);
500 data->twrt = opx->wrt;
501 out(data);
502 }
503
504 static bool jmp_match(int32_t segment, int64_t offset, int bits,
505 insn * ins, const struct itemplate *temp)
506 {
507 int64_t isize;
508 const uint8_t *code = temp->code;
509 uint8_t c = code[0];
510 bool is_byte;
511
512 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
513 return false;
514 if (!optimizing)
515 return false;
516 if (optimizing < 0 && c == 0371)
517 return false;
518
519 isize = calcsize(segment, offset, bits, ins, temp);
520
521 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
522 /* Be optimistic in pass 1 */
523 return true;
524
525 if (ins->oprs[0].segment != segment)
526 return false;
527
528 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
529 is_byte = (isize >= -128 && isize <= 127); /* is it byte size? */
530
531 if (is_byte && c == 0371 && ins->prefixes[PPS_REP] == P_BND) {
532 /* jmp short (opcode eb) cannot be used with bnd prefix. */
533 ins->prefixes[PPS_REP] = P_none;
534 nasm_error(ERR_WARNING | ERR_WARN_BND | ERR_PASS2 ,
535 "jmp short does not init bnd regs - bnd prefix dropped.");
536 }
537
538 return is_byte;
539 }
540
541 /* This is totally just a wild guess what is reasonable... */
542 #define INCBIN_MAX_BUF (ZERO_BUF_SIZE * 16)
543
544 int64_t assemble(int32_t segment, int64_t start, int bits, insn *instruction)
545 {
546 struct out_data data;
547 const struct itemplate *temp;
548 enum match_result m;
549 int64_t wsize; /* size for DB etc. */
550
551 nasm_zero(data);
552 data.offset = start;
553 data.segment = segment;
554 data.itemp = NULL;
555 data.sign = OUT_WRAP;
556 data.bits = bits;
557
558 wsize = idata_bytes(instruction->opcode);
559 if (wsize == -1)
560 return 0;
561
562 if (wsize) {
563 extop *e;
564
565 list_for_each(e, instruction->eops) {
566 if (e->type == EOT_DB_NUMBER) {
567 if (wsize > 8) {
568 nasm_error(ERR_NONFATAL,
569 "integer supplied to a DT, DO, DY or DZ"
570 " instruction");
571 } else {
572 data.insoffs = 0;
573 data.type = e->relative ? OUT_RELADDR : OUT_ADDRESS;
574 data.inslen = data.size = wsize;
575 data.toffset = e->offset;
576 data.tsegment = e->segment;
577 data.twrt = e->wrt;
578 data.relbase = 0;
579 out(&data);
580 }
581 } else if (e->type == EOT_DB_STRING ||
582 e->type == EOT_DB_STRING_FREE) {
583 int align = e->stringlen % wsize;
584 if (align)
585 align = wsize - align;
586
587 data.insoffs = 0;
588 data.inslen = e->stringlen + align;
589
590 out_rawdata(&data, e->stringval, e->stringlen);
591 out_rawdata(&data, zero_buffer, align);
592 }
593 }
594 } else if (instruction->opcode == I_INCBIN) {
595 const char *fname = instruction->eops->stringval;
596 FILE *fp;
597 size_t t = instruction->times; /* INCBIN handles TIMES by itself */
598 off_t base = 0;
599 off_t len;
600 const void *map = NULL;
601 char *buf = NULL;
602 size_t blk = 0; /* Buffered I/O block size */
603 size_t m = 0; /* Bytes last read */
604
605 fp = nasm_open_read(fname, NF_BINARY|NF_FORMAP);
606 if (!fp) {
607 nasm_error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
608 fname);
609 goto done;
610 }
611
612 len = nasm_file_size(fp);
613
614 if (len == (off_t)-1) {
615 nasm_error(ERR_NONFATAL, "`incbin': unable to get length of file `%s'",
616 fname);
617 goto close_done;
618 }
619
620 if (instruction->eops->next) {
621 base = instruction->eops->next->offset;
622 if (base >= len) {
623 len = 0;
624 } else {
625 len -= base;
626 if (instruction->eops->next->next &&
627 len > (off_t)instruction->eops->next->next->offset)
628 len = (off_t)instruction->eops->next->next->offset;
629 }
630 }
631
632 lfmt->set_offset(data.offset);
633 lfmt->uplevel(LIST_INCBIN);
634
635 if (!len)
636 goto end_incbin;
637
638 /* Try to map file data */
639 map = nasm_map_file(fp, base, len);
640 if (!map) {
641 blk = len < (off_t)INCBIN_MAX_BUF ? (size_t)len : INCBIN_MAX_BUF;
642 buf = nasm_malloc(blk);
643 }
644
645 while (t--) {
646 /*
647 * Consider these irrelevant for INCBIN, since it is fully
648 * possible that these might be (way) bigger than an int
649 * can hold; there is, however, no reason to widen these
650 * types just for INCBIN. data.inslen == 0 signals to the
651 * backend that these fields are meaningless, if at all
652 * needed.
653 */
654 data.insoffs = 0;
655 data.inslen = 0;
656
657 if (map) {
658 out_rawdata(&data, map, len);
659 } else if ((off_t)m == len) {
660 out_rawdata(&data, buf, len);
661 } else {
662 off_t l = len;
663
664 if (fseeko(fp, base, SEEK_SET) < 0 || ferror(fp)) {
665 nasm_error(ERR_NONFATAL,
666 "`incbin': unable to seek on file `%s'",
667 fname);
668 goto end_incbin;
669 }
670 while (l > 0) {
671 m = fread(buf, 1, l < (off_t)blk ? (size_t)l : blk, fp);
672 if (!m || feof(fp)) {
673 /*
674 * This shouldn't happen unless the file
675 * actually changes while we are reading
676 * it.
677 */
678 nasm_error(ERR_NONFATAL,
679 "`incbin': unexpected EOF while"
680 " reading file `%s'", fname);
681 goto end_incbin;
682 }
683 out_rawdata(&data, buf, m);
684 l -= m;
685 }
686 }
687 }
688 end_incbin:
689 lfmt->downlevel(LIST_INCBIN);
690 if (instruction->times > 1) {
691 lfmt->set_offset(start);
692 lfmt->uplevel(LIST_TIMES);
693 lfmt->downlevel(LIST_TIMES);
694 }
695 if (ferror(fp)) {
696 nasm_error(ERR_NONFATAL,
697 "`incbin': error while"
698 " reading file `%s'", fname);
699 }
700 close_done:
701 if (buf)
702 nasm_free(buf);
703 if (map)
704 nasm_unmap_file(map, len);
705 fclose(fp);
706 done:
707 instruction->times = 1; /* Tell the upper layer not to iterate */
708 ;
709 } else {
710 /* "Real" instruction */
711
712 /* Check to see if we need an address-size prefix */
713 add_asp(instruction, bits);
714
715 m = find_match(&temp, instruction, data.segment, data.offset, bits);
716
717 if (m == MOK_GOOD) {
718 /* Matches! */
719 int64_t insn_size = calcsize(data.segment, data.offset,
720 bits, instruction, temp);
721 nasm_assert(insn_size >= 0);
722
723 data.itemp = temp;
724 data.bits = bits;
725 data.insoffs = 0;
726 data.inslen = insn_size;
727
728 gencode(&data, instruction);
729 nasm_assert(data.insoffs == insn_size);
730 } else {
731 /* No match */
732 switch (m) {
733 case MERR_OPSIZEMISSING:
734 nasm_error(ERR_NONFATAL, "operation size not specified");
735 break;
736 case MERR_OPSIZEMISMATCH:
737 nasm_error(ERR_NONFATAL, "mismatch in operand sizes");
738 break;
739 case MERR_BRNOTHERE:
740 nasm_error(ERR_NONFATAL,
741 "broadcast not permitted on this operand");
742 break;
743 case MERR_BRNUMMISMATCH:
744 nasm_error(ERR_NONFATAL,
745 "mismatch in the number of broadcasting elements");
746 break;
747 case MERR_MASKNOTHERE:
748 nasm_error(ERR_NONFATAL,
749 "mask not permitted on this operand");
750 break;
751 case MERR_BADCPU:
752 nasm_error(ERR_NONFATAL, "no instruction for this cpu level");
753 break;
754 case MERR_BADMODE:
755 nasm_error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
756 bits);
757 break;
758 case MERR_ENCMISMATCH:
759 nasm_error(ERR_NONFATAL, "specific encoding scheme not available");
760 break;
761 case MERR_BADBND:
762 nasm_error(ERR_NONFATAL, "bnd prefix is not allowed");
763 break;
764 case MERR_BADREPNE:
765 nasm_error(ERR_NONFATAL, "%s prefix is not allowed",
766 (has_prefix(instruction, PPS_REP, P_REPNE) ?
767 "repne" : "repnz"));
768 break;
769 default:
770 nasm_error(ERR_NONFATAL,
771 "invalid combination of opcode and operands");
772 break;
773 }
774
775 instruction->times = 1; /* Avoid repeated error messages */
776 }
777 }
778 return data.offset - start;
779 }
780
781 int64_t insn_size(int32_t segment, int64_t offset, int bits, insn *instruction)
782 {
783 const struct itemplate *temp;
784 enum match_result m;
785
786 if (instruction->opcode == I_none)
787 return 0;
788
789 if (opcode_is_db(instruction->opcode)) {
790 extop *e;
791 int32_t isize, osize, wsize;
792
793 isize = 0;
794 wsize = idata_bytes(instruction->opcode);
795 nasm_assert(wsize > 0);
796
797 list_for_each(e, instruction->eops) {
798 int32_t align;
799
800 osize = 0;
801 if (e->type == EOT_DB_NUMBER) {
802 osize = 1;
803 warn_overflow_const(e->offset, wsize);
804 } else if (e->type == EOT_DB_STRING ||
805 e->type == EOT_DB_STRING_FREE)
806 osize = e->stringlen;
807
808 align = (-osize) % wsize;
809 if (align < 0)
810 align += wsize;
811 isize += osize + align;
812 }
813 return isize;
814 }
815
816 if (instruction->opcode == I_INCBIN) {
817 const char *fname = instruction->eops->stringval;
818 off_t len;
819
820 len = nasm_file_size_by_path(fname);
821 if (len == (off_t)-1) {
822 nasm_error(ERR_NONFATAL, "`incbin': unable to get length of file `%s'",
823 fname);
824 return 0;
825 }
826
827 if (instruction->eops->next) {
828 if (len <= (off_t)instruction->eops->next->offset) {
829 len = 0;
830 } else {
831 len -= instruction->eops->next->offset;
832 if (instruction->eops->next->next &&
833 len > (off_t)instruction->eops->next->next->offset) {
834 len = (off_t)instruction->eops->next->next->offset;
835 }
836 }
837 }
838
839 len *= instruction->times;
840 instruction->times = 1; /* Tell the upper layer to not iterate */
841
842 return len;
843 }
844
845 /* Check to see if we need an address-size prefix */
846 add_asp(instruction, bits);
847
848 m = find_match(&temp, instruction, segment, offset, bits);
849 if (m == MOK_GOOD) {
850 /* we've matched an instruction. */
851 return calcsize(segment, offset, bits, instruction, temp);
852 } else {
853 return -1; /* didn't match any instruction */
854 }
855 }
856
857 static void bad_hle_warn(const insn * ins, uint8_t hleok)
858 {
859 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
860 enum whatwarn { w_none, w_lock, w_inval } ww;
861 static const enum whatwarn warn[2][4] =
862 {
863 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
864 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
865 };
866 unsigned int n;
867
868 n = (unsigned int)rep_pfx - P_XACQUIRE;
869 if (n > 1)
870 return; /* Not XACQUIRE/XRELEASE */
871
872 ww = warn[n][hleok];
873 if (!is_class(MEMORY, ins->oprs[0].type))
874 ww = w_inval; /* HLE requires operand 0 to be memory */
875
876 switch (ww) {
877 case w_none:
878 break;
879
880 case w_lock:
881 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
882 nasm_error(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
883 "%s with this instruction requires lock",
884 prefix_name(rep_pfx));
885 }
886 break;
887
888 case w_inval:
889 nasm_error(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
890 "%s invalid with this instruction",
891 prefix_name(rep_pfx));
892 break;
893 }
894 }
895
896 /* Common construct */
897 #define case3(x) case (x): case (x)+1: case (x)+2
898 #define case4(x) case3(x): case (x)+3
899
900 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
901 insn * ins, const struct itemplate *temp)
902 {
903 const uint8_t *codes = temp->code;
904 int64_t length = 0;
905 uint8_t c;
906 int rex_mask = ~0;
907 int op1, op2;
908 struct operand *opx;
909 uint8_t opex = 0;
910 enum ea_type eat;
911 uint8_t hleok = 0;
912 bool lockcheck = true;
913 enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
914 const char *errmsg;
915
916 ins->rex = 0; /* Ensure REX is reset */
917 eat = EA_SCALAR; /* Expect a scalar EA */
918 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
919
920 if (ins->prefixes[PPS_OSIZE] == P_O64)
921 ins->rex |= REX_W;
922
923 (void)segment; /* Don't warn that this parameter is unused */
924 (void)offset; /* Don't warn that this parameter is unused */
925
926 while (*codes) {
927 c = *codes++;
928 op1 = (c & 3) + ((opex & 1) << 2);
929 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
930 opx = &ins->oprs[op1];
931 opex = 0; /* For the next iteration */
932
933 switch (c) {
934 case4(01):
935 codes += c, length += c;
936 break;
937
938 case3(05):
939 opex = c;
940 break;
941
942 case4(010):
943 ins->rex |=
944 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
945 codes++, length++;
946 break;
947
948 case4(014):
949 /* this is an index reg of MIB operand */
950 mib_index = opx->basereg;
951 break;
952
953 case4(020):
954 case4(024):
955 length++;
956 break;
957
958 case4(030):
959 length += 2;
960 break;
961
962 case4(034):
963 if (opx->type & (BITS16 | BITS32 | BITS64))
964 length += (opx->type & BITS16) ? 2 : 4;
965 else
966 length += (bits == 16) ? 2 : 4;
967 break;
968
969 case4(040):
970 length += 4;
971 break;
972
973 case4(044):
974 length += ins->addr_size >> 3;
975 break;
976
977 case4(050):
978 length++;
979 break;
980
981 case4(054):
982 length += 8; /* MOV reg64/imm */
983 break;
984
985 case4(060):
986 length += 2;
987 break;
988
989 case4(064):
990 if (opx->type & (BITS16 | BITS32 | BITS64))
991 length += (opx->type & BITS16) ? 2 : 4;
992 else
993 length += (bits == 16) ? 2 : 4;
994 break;
995
996 case4(070):
997 length += 4;
998 break;
999
1000 case4(074):
1001 length += 2;
1002 break;
1003
1004 case 0172:
1005 case 0173:
1006 codes++;
1007 length++;
1008 break;
1009
1010 case4(0174):
1011 length++;
1012 break;
1013
1014 case4(0240):
1015 ins->rex |= REX_EV;
1016 ins->vexreg = regval(opx);
1017 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
1018 ins->vex_cm = *codes++;
1019 ins->vex_wlp = *codes++;
1020 ins->evex_tuple = (*codes++ - 0300);
1021 break;
1022
1023 case 0250:
1024 ins->rex |= REX_EV;
1025 ins->vexreg = 0;
1026 ins->vex_cm = *codes++;
1027 ins->vex_wlp = *codes++;
1028 ins->evex_tuple = (*codes++ - 0300);
1029 break;
1030
1031 case4(0254):
1032 length += 4;
1033 break;
1034
1035 case4(0260):
1036 ins->rex |= REX_V;
1037 ins->vexreg = regval(opx);
1038 ins->vex_cm = *codes++;
1039 ins->vex_wlp = *codes++;
1040 break;
1041
1042 case 0270:
1043 ins->rex |= REX_V;
1044 ins->vexreg = 0;
1045 ins->vex_cm = *codes++;
1046 ins->vex_wlp = *codes++;
1047 break;
1048
1049 case3(0271):
1050 hleok = c & 3;
1051 break;
1052
1053 case4(0274):
1054 length++;
1055 break;
1056
1057 case4(0300):
1058 break;
1059
1060 case 0310:
1061 if (bits == 64)
1062 return -1;
1063 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1064 break;
1065
1066 case 0311:
1067 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1068 break;
1069
1070 case 0312:
1071 break;
1072
1073 case 0313:
1074 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1075 has_prefix(ins, PPS_ASIZE, P_A32))
1076 return -1;
1077 break;
1078
1079 case4(0314):
1080 break;
1081
1082 case 0320:
1083 {
1084 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1085 if (pfx == P_O16)
1086 break;
1087 if (pfx != P_none)
1088 nasm_error(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1089 else
1090 ins->prefixes[PPS_OSIZE] = P_O16;
1091 break;
1092 }
1093
1094 case 0321:
1095 {
1096 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1097 if (pfx == P_O32)
1098 break;
1099 if (pfx != P_none)
1100 nasm_error(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1101 else
1102 ins->prefixes[PPS_OSIZE] = P_O32;
1103 break;
1104 }
1105
1106 case 0322:
1107 break;
1108
1109 case 0323:
1110 rex_mask &= ~REX_W;
1111 break;
1112
1113 case 0324:
1114 ins->rex |= REX_W;
1115 break;
1116
1117 case 0325:
1118 ins->rex |= REX_NH;
1119 break;
1120
1121 case 0326:
1122 break;
1123
1124 case 0330:
1125 codes++, length++;
1126 break;
1127
1128 case 0331:
1129 break;
1130
1131 case 0332:
1132 case 0333:
1133 length++;
1134 break;
1135
1136 case 0334:
1137 ins->rex |= REX_L;
1138 break;
1139
1140 case 0335:
1141 break;
1142
1143 case 0336:
1144 if (!ins->prefixes[PPS_REP])
1145 ins->prefixes[PPS_REP] = P_REP;
1146 break;
1147
1148 case 0337:
1149 if (!ins->prefixes[PPS_REP])
1150 ins->prefixes[PPS_REP] = P_REPNE;
1151 break;
1152
1153 case 0340:
1154 if (!absolute_op(&ins->oprs[0]))
1155 nasm_error(ERR_NONFATAL, "attempt to reserve non-constant"
1156 " quantity of BSS space");
1157 else if (ins->oprs[0].opflags & OPFLAG_FORWARD)
1158 nasm_error(ERR_WARNING | ERR_PASS1,
1159 "forward reference in RESx can have unpredictable results");
1160 else
1161 length += ins->oprs[0].offset;
1162 break;
1163
1164 case 0341:
1165 if (!ins->prefixes[PPS_WAIT])
1166 ins->prefixes[PPS_WAIT] = P_WAIT;
1167 break;
1168
1169 case 0360:
1170 break;
1171
1172 case 0361:
1173 length++;
1174 break;
1175
1176 case 0364:
1177 case 0365:
1178 break;
1179
1180 case 0366:
1181 case 0367:
1182 length++;
1183 break;
1184
1185 case 0370:
1186 case 0371:
1187 break;
1188
1189 case 0373:
1190 length++;
1191 break;
1192
1193 case 0374:
1194 eat = EA_XMMVSIB;
1195 break;
1196
1197 case 0375:
1198 eat = EA_YMMVSIB;
1199 break;
1200
1201 case 0376:
1202 eat = EA_ZMMVSIB;
1203 break;
1204
1205 case4(0100):
1206 case4(0110):
1207 case4(0120):
1208 case4(0130):
1209 case4(0200):
1210 case4(0204):
1211 case4(0210):
1212 case4(0214):
1213 case4(0220):
1214 case4(0224):
1215 case4(0230):
1216 case4(0234):
1217 {
1218 ea ea_data;
1219 int rfield;
1220 opflags_t rflags;
1221 struct operand *opy = &ins->oprs[op2];
1222 struct operand *op_er_sae;
1223
1224 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1225
1226 if (c <= 0177) {
1227 /* pick rfield from operand b (opx) */
1228 rflags = regflag(opx);
1229 rfield = nasm_regvals[opx->basereg];
1230 } else {
1231 rflags = 0;
1232 rfield = c & 7;
1233 }
1234
1235 /* EVEX.b1 : evex_brerop contains the operand position */
1236 op_er_sae = (ins->evex_brerop >= 0 ?
1237 &ins->oprs[ins->evex_brerop] : NULL);
1238
1239 if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
1240 /* set EVEX.b */
1241 ins->evex_p[2] |= EVEX_P2B;
1242 if (op_er_sae->decoflags & ER) {
1243 /* set EVEX.RC (rounding control) */
1244 ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
1245 & EVEX_P2RC;
1246 }
1247 } else {
1248 /* set EVEX.L'L (vector length) */
1249 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1250 ins->evex_p[1] |= ((ins->vex_wlp << (7 - 4)) & EVEX_P1W);
1251 if (opy->decoflags & BRDCAST_MASK) {
1252 /* set EVEX.b */
1253 ins->evex_p[2] |= EVEX_P2B;
1254 }
1255 }
1256
1257 if (itemp_has(temp, IF_MIB)) {
1258 opy->eaflags |= EAF_MIB;
1259 /*
1260 * if a separate form of MIB (ICC style) is used,
1261 * the index reg info is merged into mem operand
1262 */
1263 if (mib_index != R_none) {
1264 opy->indexreg = mib_index;
1265 opy->scale = 1;
1266 opy->hintbase = mib_index;
1267 opy->hinttype = EAH_NOTBASE;
1268 }
1269 }
1270
1271 if (process_ea(opy, &ea_data, bits,
1272 rfield, rflags, ins, &errmsg) != eat) {
1273 nasm_error(ERR_NONFATAL, "%s", errmsg);
1274 return -1;
1275 } else {
1276 ins->rex |= ea_data.rex;
1277 length += ea_data.size;
1278 }
1279 }
1280 break;
1281
1282 default:
1283 nasm_panic(0, "internal instruction table corrupt"
1284 ": instruction code \\%o (0x%02X) given", c, c);
1285 break;
1286 }
1287 }
1288
1289 ins->rex &= rex_mask;
1290
1291 if (ins->rex & REX_NH) {
1292 if (ins->rex & REX_H) {
1293 nasm_error(ERR_NONFATAL, "instruction cannot use high registers");
1294 return -1;
1295 }
1296 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1297 }
1298
1299 switch (ins->prefixes[PPS_VEX]) {
1300 case P_EVEX:
1301 if (!(ins->rex & REX_EV))
1302 return -1;
1303 break;
1304 case P_VEX3:
1305 case P_VEX2:
1306 if (!(ins->rex & REX_V))
1307 return -1;
1308 break;
1309 default:
1310 break;
1311 }
1312
1313 if (ins->rex & (REX_V | REX_EV)) {
1314 int bad32 = REX_R|REX_W|REX_X|REX_B;
1315
1316 if (ins->rex & REX_H) {
1317 nasm_error(ERR_NONFATAL, "cannot use high register in AVX instruction");
1318 return -1;
1319 }
1320 switch (ins->vex_wlp & 060) {
1321 case 000:
1322 case 040:
1323 ins->rex &= ~REX_W;
1324 break;
1325 case 020:
1326 ins->rex |= REX_W;
1327 bad32 &= ~REX_W;
1328 break;
1329 case 060:
1330 /* Follow REX_W */
1331 break;
1332 }
1333
1334 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1335 nasm_error(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1336 return -1;
1337 } else if (!(ins->rex & REX_EV) &&
1338 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1339 nasm_error(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1340 return -1;
1341 }
1342 if (ins->rex & REX_EV)
1343 length += 4;
1344 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1345 ins->prefixes[PPS_VEX] == P_VEX3)
1346 length += 3;
1347 else
1348 length += 2;
1349 } else if (ins->rex & REX_MASK) {
1350 if (ins->rex & REX_H) {
1351 nasm_error(ERR_NONFATAL, "cannot use high register in rex instruction");
1352 return -1;
1353 } else if (bits == 64) {
1354 length++;
1355 } else if ((ins->rex & REX_L) &&
1356 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1357 iflag_ffs(&cpu) >= IF_X86_64) {
1358 /* LOCK-as-REX.R */
1359 assert_no_prefix(ins, PPS_LOCK);
1360 lockcheck = false; /* Already errored, no need for warning */
1361 length++;
1362 } else {
1363 nasm_error(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1364 return -1;
1365 }
1366 }
1367
1368 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1369 (!itemp_has(temp,IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1370 nasm_error(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1371 "instruction is not lockable");
1372 }
1373
1374 bad_hle_warn(ins, hleok);
1375
1376 /*
1377 * when BND prefix is set by DEFAULT directive,
1378 * BND prefix is added to every appropriate instruction line
1379 * unless it is overridden by NOBND prefix.
1380 */
1381 if (globalbnd &&
1382 (itemp_has(temp, IF_BND) && !has_prefix(ins, PPS_REP, P_NOBND)))
1383 ins->prefixes[PPS_REP] = P_BND;
1384
1385 /*
1386 * Add length of legacy prefixes
1387 */
1388 length += emit_prefix(NULL, bits, ins);
1389
1390 return length;
1391 }
1392
1393 static inline void emit_rex(struct out_data *data, insn *ins)
1394 {
1395 if (data->bits == 64) {
1396 if ((ins->rex & REX_MASK) &&
1397 !(ins->rex & (REX_V | REX_EV)) &&
1398 !ins->rex_done) {
1399 uint8_t rex = (ins->rex & REX_MASK) | REX_P;
1400 out_rawbyte(data, rex);
1401 ins->rex_done = true;
1402 }
1403 }
1404 }
1405
1406 static int emit_prefix(struct out_data *data, const int bits, insn *ins)
1407 {
1408 int bytes = 0;
1409 int j;
1410
1411 for (j = 0; j < MAXPREFIX; j++) {
1412 uint8_t c = 0;
1413 switch (ins->prefixes[j]) {
1414 case P_WAIT:
1415 c = 0x9B;
1416 break;
1417 case P_LOCK:
1418 c = 0xF0;
1419 break;
1420 case P_REPNE:
1421 case P_REPNZ:
1422 case P_XACQUIRE:
1423 case P_BND:
1424 c = 0xF2;
1425 break;
1426 case P_REPE:
1427 case P_REPZ:
1428 case P_REP:
1429 case P_XRELEASE:
1430 c = 0xF3;
1431 break;
1432 case R_CS:
1433 if (bits == 64) {
1434 nasm_error(ERR_WARNING | ERR_PASS2,
1435 "cs segment base generated, but will be ignored in 64-bit mode");
1436 }
1437 c = 0x2E;
1438 break;
1439 case R_DS:
1440 if (bits == 64) {
1441 nasm_error(ERR_WARNING | ERR_PASS2,
1442 "ds segment base generated, but will be ignored in 64-bit mode");
1443 }
1444 c = 0x3E;
1445 break;
1446 case R_ES:
1447 if (bits == 64) {
1448 nasm_error(ERR_WARNING | ERR_PASS2,
1449 "es segment base generated, but will be ignored in 64-bit mode");
1450 }
1451 c = 0x26;
1452 break;
1453 case R_FS:
1454 c = 0x64;
1455 break;
1456 case R_GS:
1457 c = 0x65;
1458 break;
1459 case R_SS:
1460 if (bits == 64) {
1461 nasm_error(ERR_WARNING | ERR_PASS2,
1462 "ss segment base generated, but will be ignored in 64-bit mode");
1463 }
1464 c = 0x36;
1465 break;
1466 case R_SEGR6:
1467 case R_SEGR7:
1468 nasm_error(ERR_NONFATAL,
1469 "segr6 and segr7 cannot be used as prefixes");
1470 break;
1471 case P_A16:
1472 if (bits == 64) {
1473 nasm_error(ERR_NONFATAL,
1474 "16-bit addressing is not supported "
1475 "in 64-bit mode");
1476 } else if (bits != 16)
1477 c = 0x67;
1478 break;
1479 case P_A32:
1480 if (bits != 32)
1481 c = 0x67;
1482 break;
1483 case P_A64:
1484 if (bits != 64) {
1485 nasm_error(ERR_NONFATAL,
1486 "64-bit addressing is only supported "
1487 "in 64-bit mode");
1488 }
1489 break;
1490 case P_ASP:
1491 c = 0x67;
1492 break;
1493 case P_O16:
1494 if (bits != 16)
1495 c = 0x66;
1496 break;
1497 case P_O32:
1498 if (bits == 16)
1499 c = 0x66;
1500 break;
1501 case P_O64:
1502 /* REX.W */
1503 break;
1504 case P_OSP:
1505 c = 0x66;
1506 break;
1507 case P_EVEX:
1508 case P_VEX3:
1509 case P_VEX2:
1510 case P_NOBND:
1511 case P_none:
1512 break;
1513 default:
1514 nasm_panic(0, "invalid instruction prefix");
1515 }
1516 if (c) {
1517 if (data)
1518 out_rawbyte(data, c);
1519 bytes++;
1520 }
1521 }
1522 return bytes;
1523 }
1524
1525 static void gencode(struct out_data *data, insn *ins)
1526 {
1527 uint8_t c;
1528 uint8_t bytes[4];
1529 int64_t size;
1530 int op1, op2;
1531 struct operand *opx;
1532 const uint8_t *codes = data->itemp->code;
1533 uint8_t opex = 0;
1534 enum ea_type eat = EA_SCALAR;
1535 int r;
1536 const int bits = data->bits;
1537 const char *errmsg;
1538
1539 ins->rex_done = false;
1540
1541 emit_prefix(data, bits, ins);
1542
1543 while (*codes) {
1544 c = *codes++;
1545 op1 = (c & 3) + ((opex & 1) << 2);
1546 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1547 opx = &ins->oprs[op1];
1548 opex = 0; /* For the next iteration */
1549
1550
1551 switch (c) {
1552 case 01:
1553 case 02:
1554 case 03:
1555 case 04:
1556 emit_rex(data, ins);
1557 out_rawdata(data, codes, c);
1558 codes += c;
1559 break;
1560
1561 case 05:
1562 case 06:
1563 case 07:
1564 opex = c;
1565 break;
1566
1567 case4(010):
1568 emit_rex(data, ins);
1569 out_rawbyte(data, *codes++ + (regval(opx) & 7));
1570 break;
1571
1572 case4(014):
1573 break;
1574
1575 case4(020):
1576 if (opx->offset < -256 || opx->offset > 255)
1577 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1578 "byte value exceeds bounds");
1579 out_imm(data, opx, 1, OUT_WRAP);
1580 break;
1581
1582 case4(024):
1583 if (opx->offset < 0 || opx->offset > 255)
1584 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1585 "unsigned byte value exceeds bounds");
1586 out_imm(data, opx, 1, OUT_UNSIGNED);
1587 break;
1588
1589 case4(030):
1590 warn_overflow_opd(opx, 2);
1591 out_imm(data, opx, 2, OUT_WRAP);
1592 break;
1593
1594 case4(034):
1595 if (opx->type & (BITS16 | BITS32))
1596 size = (opx->type & BITS16) ? 2 : 4;
1597 else
1598 size = (bits == 16) ? 2 : 4;
1599 warn_overflow_opd(opx, size);
1600 out_imm(data, opx, size, OUT_WRAP);
1601 break;
1602
1603 case4(040):
1604 warn_overflow_opd(opx, 4);
1605 out_imm(data, opx, 4, OUT_WRAP);
1606 break;
1607
1608 case4(044):
1609 size = ins->addr_size >> 3;
1610 warn_overflow_opd(opx, size);
1611 out_imm(data, opx, size, OUT_WRAP);
1612 break;
1613
1614 case4(050):
1615 if (opx->segment == data->segment) {
1616 int64_t delta = opx->offset - data->offset
1617 - (data->inslen - data->insoffs);
1618 if (delta > 127 || delta < -128)
1619 nasm_error(ERR_NONFATAL, "short jump is out of range");
1620 }
1621 out_reladdr(data, opx, 1);
1622 break;
1623
1624 case4(054):
1625 out_imm(data, opx, 8, OUT_WRAP);
1626 break;
1627
1628 case4(060):
1629 out_reladdr(data, opx, 2);
1630 break;
1631
1632 case4(064):
1633 if (opx->type & (BITS16 | BITS32 | BITS64))
1634 size = (opx->type & BITS16) ? 2 : 4;
1635 else
1636 size = (bits == 16) ? 2 : 4;
1637
1638 out_reladdr(data, opx, size);
1639 break;
1640
1641 case4(070):
1642 out_reladdr(data, opx, 4);
1643 break;
1644
1645 case4(074):
1646 if (opx->segment == NO_SEG)
1647 nasm_error(ERR_NONFATAL, "value referenced by FAR is not"
1648 " relocatable");
1649 out_segment(data, opx);
1650 break;
1651
1652 case 0172:
1653 {
1654 int mask = ins->prefixes[PPS_VEX] == P_EVEX ? 7 : 15;
1655 const struct operand *opy;
1656
1657 c = *codes++;
1658 opx = &ins->oprs[c >> 3];
1659 opy = &ins->oprs[c & 7];
1660 if (!absolute_op(opy)) {
1661 nasm_error(ERR_NONFATAL,
1662 "non-absolute expression not permitted as argument %d",
1663 c & 7);
1664 } else if (opy->offset & ~mask) {
1665 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1666 "is4 argument exceeds bounds");
1667 }
1668 c = opy->offset & mask;
1669 goto emit_is4;
1670 }
1671
1672 case 0173:
1673 c = *codes++;
1674 opx = &ins->oprs[c >> 4];
1675 c &= 15;
1676 goto emit_is4;
1677
1678 case4(0174):
1679 c = 0;
1680 emit_is4:
1681 r = nasm_regvals[opx->basereg];
1682 out_rawbyte(data, (r << 4) | ((r & 0x10) >> 1) | c);
1683 break;
1684
1685 case4(0254):
1686 if (absolute_op(opx) &&
1687 (int32_t)opx->offset != (int64_t)opx->offset) {
1688 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1689 "signed dword immediate exceeds bounds");
1690 }
1691 out_imm(data, opx, 4, OUT_SIGNED);
1692 break;
1693
1694 case4(0240):
1695 case 0250:
1696 codes += 3;
1697 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1698 EVEX_P2Z | EVEX_P2AAA, 2);
1699 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1700 bytes[0] = 0x62;
1701 /* EVEX.X can be set by either REX or EVEX for different reasons */
1702 bytes[1] = ((((ins->rex & 7) << 5) |
1703 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) ^ 0xf0) |
1704 (ins->vex_cm & EVEX_P0MM);
1705 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1706 ((~ins->vexreg & 15) << 3) |
1707 (1 << 2) | (ins->vex_wlp & 3);
1708 bytes[3] = ins->evex_p[2];
1709 out_rawdata(data, bytes, 4);
1710 break;
1711
1712 case4(0260):
1713 case 0270:
1714 codes += 2;
1715 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1716 ins->prefixes[PPS_VEX] == P_VEX3) {
1717 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1718 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1719 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1720 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1721 out_rawdata(data, bytes, 3);
1722 } else {
1723 bytes[0] = 0xc5;
1724 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1725 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1726 out_rawdata(data, bytes, 2);
1727 }
1728 break;
1729
1730 case 0271:
1731 case 0272:
1732 case 0273:
1733 break;
1734
1735 case4(0274):
1736 {
1737 uint64_t uv, um;
1738 int s;
1739
1740 if (absolute_op(opx)) {
1741 if (ins->rex & REX_W)
1742 s = 64;
1743 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1744 s = 16;
1745 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1746 s = 32;
1747 else
1748 s = bits;
1749
1750 um = (uint64_t)2 << (s-1);
1751 uv = opx->offset;
1752
1753 if (uv > 127 && uv < (uint64_t)-128 &&
1754 (uv < um-128 || uv > um-1)) {
1755 /* If this wasn't explicitly byte-sized, warn as though we
1756 * had fallen through to the imm16/32/64 case.
1757 */
1758 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1759 "%s value exceeds bounds",
1760 (opx->type & BITS8) ? "signed byte" :
1761 s == 16 ? "word" :
1762 s == 32 ? "dword" :
1763 "signed dword");
1764 }
1765
1766 /* Output as a raw byte to avoid byte overflow check */
1767 out_rawbyte(data, (uint8_t)uv);
1768 } else {
1769 out_imm(data, opx, 1, OUT_WRAP); /* XXX: OUT_SIGNED? */
1770 }
1771 break;
1772 }
1773
1774 case4(0300):
1775 break;
1776
1777 case 0310:
1778 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16))
1779 out_rawbyte(data, 0x67);
1780 break;
1781
1782 case 0311:
1783 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32))
1784 out_rawbyte(data, 0x67);
1785 break;
1786
1787 case 0312:
1788 break;
1789
1790 case 0313:
1791 ins->rex = 0;
1792 break;
1793
1794 case4(0314):
1795 break;
1796
1797 case 0320:
1798 case 0321:
1799 break;
1800
1801 case 0322:
1802 case 0323:
1803 break;
1804
1805 case 0324:
1806 ins->rex |= REX_W;
1807 break;
1808
1809 case 0325:
1810 break;
1811
1812 case 0326:
1813 break;
1814
1815 case 0330:
1816 out_rawbyte(data, *codes++ ^ get_cond_opcode(ins->condition));
1817 break;
1818
1819 case 0331:
1820 break;
1821
1822 case 0332:
1823 case 0333:
1824 out_rawbyte(data, c - 0332 + 0xF2);
1825 break;
1826
1827 case 0334:
1828 if (ins->rex & REX_R)
1829 out_rawbyte(data, 0xF0);
1830 ins->rex &= ~(REX_L|REX_R);
1831 break;
1832
1833 case 0335:
1834 break;
1835
1836 case 0336:
1837 case 0337:
1838 break;
1839
1840 case 0340:
1841 if (ins->oprs[0].segment != NO_SEG)
1842 nasm_panic(0, "non-constant BSS size in pass two");
1843
1844 out_reserve(data, ins->oprs[0].offset);
1845 break;
1846
1847 case 0341:
1848 break;
1849
1850 case 0360:
1851 break;
1852
1853 case 0361:
1854 out_rawbyte(data, 0x66);
1855 break;
1856
1857 case 0364:
1858 case 0365:
1859 break;
1860
1861 case 0366:
1862 case 0367:
1863 out_rawbyte(data, c - 0366 + 0x66);
1864 break;
1865
1866 case3(0370):
1867 break;
1868
1869 case 0373:
1870 out_rawbyte(data, bits == 16 ? 3 : 5);
1871 break;
1872
1873 case 0374:
1874 eat = EA_XMMVSIB;
1875 break;
1876
1877 case 0375:
1878 eat = EA_YMMVSIB;
1879 break;
1880
1881 case 0376:
1882 eat = EA_ZMMVSIB;
1883 break;
1884
1885 case4(0100):
1886 case4(0110):
1887 case4(0120):
1888 case4(0130):
1889 case4(0200):
1890 case4(0204):
1891 case4(0210):
1892 case4(0214):
1893 case4(0220):
1894 case4(0224):
1895 case4(0230):
1896 case4(0234):
1897 {
1898 ea ea_data;
1899 int rfield;
1900 opflags_t rflags;
1901 uint8_t *p;
1902 struct operand *opy = &ins->oprs[op2];
1903
1904 if (c <= 0177) {
1905 /* pick rfield from operand b (opx) */
1906 rflags = regflag(opx);
1907 rfield = nasm_regvals[opx->basereg];
1908 } else {
1909 /* rfield is constant */
1910 rflags = 0;
1911 rfield = c & 7;
1912 }
1913
1914 if (process_ea(opy, &ea_data, bits,
1915 rfield, rflags, ins, &errmsg) != eat)
1916 nasm_error(ERR_NONFATAL, "%s", errmsg);
1917
1918 p = bytes;
1919 *p++ = ea_data.modrm;
1920 if (ea_data.sib_present)
1921 *p++ = ea_data.sib;
1922 out_rawdata(data, bytes, p - bytes);
1923
1924 /*
1925 * Make sure the address gets the right offset in case
1926 * the line breaks in the .lst file (BR 1197827)
1927 */
1928
1929 if (ea_data.bytes) {
1930 /* use compressed displacement, if available */
1931 if (ea_data.disp8) {
1932 out_rawbyte(data, ea_data.disp8);
1933 } else if (ea_data.rip) {
1934 out_reladdr(data, opy, ea_data.bytes);
1935 } else {
1936 int asize = ins->addr_size >> 3;
1937
1938 if (overflow_general(opy->offset, asize) ||
1939 signed_bits(opy->offset, ins->addr_size) !=
1940 signed_bits(opy->offset, ea_data.bytes << 3))
1941 warn_overflow(ea_data.bytes);
1942
1943 out_imm(data, opy, ea_data.bytes,
1944 (asize > ea_data.bytes)
1945 ? OUT_SIGNED : OUT_WRAP);
1946 }
1947 }
1948 }
1949 break;
1950
1951 default:
1952 nasm_panic(0, "internal instruction table corrupt"
1953 ": instruction code \\%o (0x%02X) given", c, c);
1954 break;
1955 }
1956 }
1957 }
1958
1959 static opflags_t regflag(const operand * o)
1960 {
1961 if (!is_register(o->basereg))
1962 nasm_panic(0, "invalid operand passed to regflag()");
1963 return nasm_reg_flags[o->basereg];
1964 }
1965
1966 static int32_t regval(const operand * o)
1967 {
1968 if (!is_register(o->basereg))
1969 nasm_panic(0, "invalid operand passed to regval()");
1970 return nasm_regvals[o->basereg];
1971 }
1972
1973 static int op_rexflags(const operand * o, int mask)
1974 {
1975 opflags_t flags;
1976 int val;
1977
1978 if (!is_register(o->basereg))
1979 nasm_panic(0, "invalid operand passed to op_rexflags()");
1980
1981 flags = nasm_reg_flags[o->basereg];
1982 val = nasm_regvals[o->basereg];
1983
1984 return rexflags(val, flags, mask);
1985 }
1986
1987 static int rexflags(int val, opflags_t flags, int mask)
1988 {
1989 int rex = 0;
1990
1991 if (val >= 0 && (val & 8))
1992 rex |= REX_B|REX_X|REX_R;
1993 if (flags & BITS64)
1994 rex |= REX_W;
1995 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1996 rex |= REX_H;
1997 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1998 rex |= REX_P;
1999
2000 return rex & mask;
2001 }
2002
2003 static int evexflags(int val, decoflags_t deco,
2004 int mask, uint8_t byte)
2005 {
2006 int evex = 0;
2007
2008 switch (byte) {
2009 case 0:
2010 if (val >= 0 && (val & 16))
2011 evex |= (EVEX_P0RP | EVEX_P0X);
2012 break;
2013 case 2:
2014 if (val >= 0 && (val & 16))
2015 evex |= EVEX_P2VP;
2016 if (deco & Z)
2017 evex |= EVEX_P2Z;
2018 if (deco & OPMASK_MASK)
2019 evex |= deco & EVEX_P2AAA;
2020 break;
2021 }
2022 return evex & mask;
2023 }
2024
2025 static int op_evexflags(const operand * o, int mask, uint8_t byte)
2026 {
2027 int val;
2028
2029 val = nasm_regvals[o->basereg];
2030
2031 return evexflags(val, o->decoflags, mask, byte);
2032 }
2033
2034 static enum match_result find_match(const struct itemplate **tempp,
2035 insn *instruction,
2036 int32_t segment, int64_t offset, int bits)
2037 {
2038 const struct itemplate *temp;
2039 enum match_result m, merr;
2040 opflags_t xsizeflags[MAX_OPERANDS];
2041 bool opsizemissing = false;
2042 int8_t broadcast = instruction->evex_brerop;
2043 int i;
2044
2045 /* broadcasting uses a different data element size */
2046 for (i = 0; i < instruction->operands; i++)
2047 if (i == broadcast)
2048 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
2049 else
2050 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
2051
2052 merr = MERR_INVALOP;
2053
2054 for (temp = nasm_instructions[instruction->opcode];
2055 temp->opcode != I_none; temp++) {
2056 m = matches(temp, instruction, bits);
2057 if (m == MOK_JUMP) {
2058 if (jmp_match(segment, offset, bits, instruction, temp))
2059 m = MOK_GOOD;
2060 else
2061 m = MERR_INVALOP;
2062 } else if (m == MERR_OPSIZEMISSING && !itemp_has(temp, IF_SX)) {
2063 /*
2064 * Missing operand size and a candidate for fuzzy matching...
2065 */
2066 for (i = 0; i < temp->operands; i++)
2067 if (i == broadcast)
2068 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
2069 else
2070 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
2071 opsizemissing = true;
2072 }
2073 if (m > merr)
2074 merr = m;
2075 if (merr == MOK_GOOD)
2076 goto done;
2077 }
2078
2079 /* No match, but see if we can get a fuzzy operand size match... */
2080 if (!opsizemissing)
2081 goto done;
2082
2083 for (i = 0; i < instruction->operands; i++) {
2084 /*
2085 * We ignore extrinsic operand sizes on registers, so we should
2086 * never try to fuzzy-match on them. This also resolves the case
2087 * when we have e.g. "xmmrm128" in two different positions.
2088 */
2089 if (is_class(REGISTER, instruction->oprs[i].type))
2090 continue;
2091
2092 /* This tests if xsizeflags[i] has more than one bit set */
2093 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2094 goto done; /* No luck */
2095
2096 if (i == broadcast) {
2097 instruction->oprs[i].decoflags |= xsizeflags[i];
2098 instruction->oprs[i].type |= (xsizeflags[i] == BR_BITS32 ?
2099 BITS32 : BITS64);
2100 } else {
2101 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2102 }
2103 }
2104
2105 /* Try matching again... */
2106 for (temp = nasm_instructions[instruction->opcode];
2107 temp->opcode != I_none; temp++) {
2108 m = matches(temp, instruction, bits);
2109 if (m == MOK_JUMP) {
2110 if (jmp_match(segment, offset, bits, instruction, temp))
2111 m = MOK_GOOD;
2112 else
2113 m = MERR_INVALOP;
2114 }
2115 if (m > merr)
2116 merr = m;
2117 if (merr == MOK_GOOD)
2118 goto done;
2119 }
2120
2121 done:
2122 *tempp = temp;
2123 return merr;
2124 }
2125
2126 static uint8_t get_broadcast_num(opflags_t opflags, opflags_t brsize)
2127 {
2128 unsigned int opsize = (opflags & SIZE_MASK) >> SIZE_SHIFT;
2129 uint8_t brcast_num;
2130
2131 if (brsize > BITS64)
2132 nasm_error(ERR_FATAL,
2133 "size of broadcasting element is greater than 64 bits");
2134
2135 /*
2136 * The shift term is to take care of the extra BITS80 inserted
2137 * between BITS64 and BITS128.
2138 */
2139 brcast_num = ((opsize / (BITS64 >> SIZE_SHIFT)) * (BITS64 / brsize))
2140 >> (opsize > (BITS64 >> SIZE_SHIFT));
2141
2142 return brcast_num;
2143 }
2144
2145 static enum match_result matches(const struct itemplate *itemp,
2146 insn *instruction, int bits)
2147 {
2148 opflags_t size[MAX_OPERANDS], asize;
2149 bool opsizemissing = false;
2150 int i, oprs;
2151
2152 /*
2153 * Check the opcode
2154 */
2155 if (itemp->opcode != instruction->opcode)
2156 return MERR_INVALOP;
2157
2158 /*
2159 * Count the operands
2160 */
2161 if (itemp->operands != instruction->operands)
2162 return MERR_INVALOP;
2163
2164 /*
2165 * Is it legal?
2166 */
2167 if (!(optimizing > 0) && itemp_has(itemp, IF_OPT))
2168 return MERR_INVALOP;
2169
2170 /*
2171 * {evex} available?
2172 */
2173 switch (instruction->prefixes[PPS_VEX]) {
2174 case P_EVEX:
2175 if (!itemp_has(itemp, IF_EVEX))
2176 return MERR_ENCMISMATCH;
2177 break;
2178 case P_VEX3:
2179 case P_VEX2:
2180 if (!itemp_has(itemp, IF_VEX))
2181 return MERR_ENCMISMATCH;
2182 break;
2183 default:
2184 break;
2185 }
2186
2187 /*
2188 * Check that no spurious colons or TOs are present
2189 */
2190 for (i = 0; i < itemp->operands; i++)
2191 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2192 return MERR_INVALOP;
2193
2194 /*
2195 * Process size flags
2196 */
2197 switch (itemp_smask(itemp)) {
2198 case IF_GENBIT(IF_SB):
2199 asize = BITS8;
2200 break;
2201 case IF_GENBIT(IF_SW):
2202 asize = BITS16;
2203 break;
2204 case IF_GENBIT(IF_SD):
2205 asize = BITS32;
2206 break;
2207 case IF_GENBIT(IF_SQ):
2208 asize = BITS64;
2209 break;
2210 case IF_GENBIT(IF_SO):
2211 asize = BITS128;
2212 break;
2213 case IF_GENBIT(IF_SY):
2214 asize = BITS256;
2215 break;
2216 case IF_GENBIT(IF_SZ):
2217 asize = BITS512;
2218 break;
2219 case IF_GENBIT(IF_SIZE):
2220 switch (bits) {
2221 case 16:
2222 asize = BITS16;
2223 break;
2224 case 32:
2225 asize = BITS32;
2226 break;
2227 case 64:
2228 asize = BITS64;
2229 break;
2230 default:
2231 asize = 0;
2232 break;
2233 }
2234 break;
2235 default:
2236 asize = 0;
2237 break;
2238 }
2239
2240 if (itemp_armask(itemp)) {
2241 /* S- flags only apply to a specific operand */
2242 i = itemp_arg(itemp);
2243 memset(size, 0, sizeof size);
2244 size[i] = asize;
2245 } else {
2246 /* S- flags apply to all operands */
2247 for (i = 0; i < MAX_OPERANDS; i++)
2248 size[i] = asize;
2249 }
2250
2251 /*
2252 * Check that the operand flags all match up,
2253 * it's a bit tricky so lets be verbose:
2254 *
2255 * 1) Find out the size of operand. If instruction
2256 * doesn't have one specified -- we're trying to
2257 * guess it either from template (IF_S* flag) or
2258 * from code bits.
2259 *
2260 * 2) If template operand do not match the instruction OR
2261 * template has an operand size specified AND this size differ
2262 * from which instruction has (perhaps we got it from code bits)
2263 * we are:
2264 * a) Check that only size of instruction and operand is differ
2265 * other characteristics do match
2266 * b) Perhaps it's a register specified in instruction so
2267 * for such a case we just mark that operand as "size
2268 * missing" and this will turn on fuzzy operand size
2269 * logic facility (handled by a caller)
2270 */
2271 for (i = 0; i < itemp->operands; i++) {
2272 opflags_t type = instruction->oprs[i].type;
2273 decoflags_t deco = instruction->oprs[i].decoflags;
2274 decoflags_t ideco = itemp->deco[i];
2275 bool is_broadcast = deco & BRDCAST_MASK;
2276 uint8_t brcast_num = 0;
2277 opflags_t template_opsize, insn_opsize;
2278
2279 if (!(type & SIZE_MASK))
2280 type |= size[i];
2281
2282 insn_opsize = type & SIZE_MASK;
2283 if (!is_broadcast) {
2284 template_opsize = itemp->opd[i] & SIZE_MASK;
2285 } else {
2286 decoflags_t deco_brsize = ideco & BRSIZE_MASK;
2287
2288 if (~ideco & BRDCAST_MASK)
2289 return MERR_BRNOTHERE;
2290
2291 /*
2292 * when broadcasting, the element size depends on
2293 * the instruction type. decorator flag should match.
2294 */
2295 if (deco_brsize) {
2296 template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
2297 /* calculate the proper number : {1to<brcast_num>} */
2298 brcast_num = get_broadcast_num(itemp->opd[i], template_opsize);
2299 } else {
2300 template_opsize = 0;
2301 }
2302 }
2303
2304 if (~ideco & deco & OPMASK_MASK)
2305 return MERR_MASKNOTHERE;
2306
2307 if (itemp->opd[i] & ~type & ~SIZE_MASK) {
2308 return MERR_INVALOP;
2309 } else if (template_opsize) {
2310 if (template_opsize != insn_opsize) {
2311 if (insn_opsize) {
2312 return MERR_INVALOP;
2313 } else if (!is_class(REGISTER, type)) {
2314 /*
2315 * Note: we don't honor extrinsic operand sizes for registers,
2316 * so "missing operand size" for a register should be
2317 * considered a wildcard match rather than an error.
2318 */
2319 opsizemissing = true;
2320 }
2321 } else if (is_broadcast &&
2322 (brcast_num !=
2323 (2U << ((deco & BRNUM_MASK) >> BRNUM_SHIFT)))) {
2324 /*
2325 * broadcasting opsize matches but the number of repeated memory
2326 * element does not match.
2327 * if 64b double precision float is broadcasted to ymm (256b),
2328 * broadcasting decorator must be {1to4}.
2329 */
2330 return MERR_BRNUMMISMATCH;
2331 }
2332 }
2333 }
2334
2335 if (opsizemissing)
2336 return MERR_OPSIZEMISSING;
2337
2338 /*
2339 * Check operand sizes
2340 */
2341 if (itemp_has(itemp, IF_SM) || itemp_has(itemp, IF_SM2)) {
2342 oprs = (itemp_has(itemp, IF_SM2) ? 2 : itemp->operands);
2343 for (i = 0; i < oprs; i++) {
2344 asize = itemp->opd[i] & SIZE_MASK;
2345 if (asize) {
2346 for (i = 0; i < oprs; i++)
2347 size[i] = asize;
2348 break;
2349 }
2350 }
2351 } else {
2352 oprs = itemp->operands;
2353 }
2354
2355 for (i = 0; i < itemp->operands; i++) {
2356 if (!(itemp->opd[i] & SIZE_MASK) &&
2357 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2358 return MERR_OPSIZEMISMATCH;
2359 }
2360
2361 /*
2362 * Check template is okay at the set cpu level
2363 */
2364 if (iflag_cmp_cpu_level(&insns_flags[itemp->iflag_idx], &cpu) > 0)
2365 return MERR_BADCPU;
2366
2367 /*
2368 * Verify the appropriate long mode flag.
2369 */
2370 if (itemp_has(itemp, (bits == 64 ? IF_NOLONG : IF_LONG)))
2371 return MERR_BADMODE;
2372
2373 /*
2374 * If we have a HLE prefix, look for the NOHLE flag
2375 */
2376 if (itemp_has(itemp, IF_NOHLE) &&
2377 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2378 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2379 return MERR_BADHLE;
2380
2381 /*
2382 * Check if special handling needed for Jumps
2383 */
2384 if ((itemp->code[0] & ~1) == 0370)
2385 return MOK_JUMP;
2386
2387 /*
2388 * Check if BND prefix is allowed.
2389 * Other 0xF2 (REPNE/REPNZ) prefix is prohibited.
2390 */
2391 if (!itemp_has(itemp, IF_BND) &&
2392 (has_prefix(instruction, PPS_REP, P_BND) ||
2393 has_prefix(instruction, PPS_REP, P_NOBND)))
2394 return MERR_BADBND;
2395 else if (itemp_has(itemp, IF_BND) &&
2396 (has_prefix(instruction, PPS_REP, P_REPNE) ||
2397 has_prefix(instruction, PPS_REP, P_REPNZ)))
2398 return MERR_BADREPNE;
2399
2400 return MOK_GOOD;
2401 }
2402
2403 /*
2404 * Check if ModR/M.mod should/can be 01.
2405 * - EAF_BYTEOFFS is set
2406 * - offset can fit in a byte when EVEX is not used
2407 * - offset can be compressed when EVEX is used
2408 */
2409 #define IS_MOD_01() (!(input->eaflags & EAF_WORDOFFS) && \
2410 (ins->rex & REX_EV ? seg == NO_SEG && !forw_ref && \
2411 is_disp8n(input, ins, &output->disp8) : \
2412 input->eaflags & EAF_BYTEOFFS || (o >= -128 && \
2413 o <= 127 && seg == NO_SEG && !forw_ref)))
2414
2415 static enum ea_type process_ea(operand *input, ea *output, int bits,
2416 int rfield, opflags_t rflags, insn *ins,
2417 const char **errmsg)
2418 {
2419 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2420 int addrbits = ins->addr_size;
2421 int eaflags = input->eaflags;
2422
2423 *errmsg = "invalid effective address"; /* Default error message */
2424
2425 output->type = EA_SCALAR;
2426 output->rip = false;
2427 output->disp8 = 0;
2428
2429 /* REX flags for the rfield operand */
2430 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2431 /* EVEX.R' flag for the REG operand */
2432 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2433
2434 if (is_class(REGISTER, input->type)) {
2435 /*
2436 * It's a direct register.
2437 */
2438 if (!is_register(input->basereg))
2439 goto err;
2440
2441 if (!is_reg_class(REG_EA, input->basereg))
2442 goto err;
2443
2444 /* broadcasting is not available with a direct register operand. */
2445 if (input->decoflags & BRDCAST_MASK) {
2446 *errmsg = "broadcast not allowed with register operand";
2447 goto err;
2448 }
2449
2450 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2451 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2452 output->sib_present = false; /* no SIB necessary */
2453 output->bytes = 0; /* no offset necessary either */
2454 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2455 } else {
2456 /*
2457 * It's a memory reference.
2458 */
2459
2460 /* Embedded rounding or SAE is not available with a mem ref operand. */
2461 if (input->decoflags & (ER | SAE)) {
2462 *errmsg = "embedded rounding is available only with "
2463 "register-register operations";
2464 goto err;
2465 }
2466
2467 if (input->basereg == -1 &&
2468 (input->indexreg == -1 || input->scale == 0)) {
2469 /*
2470 * It's a pure offset.
2471 */
2472 if (bits == 64 && ((input->type & IP_REL) == IP_REL)) {
2473 if (input->segment == NO_SEG ||
2474 (input->opflags & OPFLAG_RELATIVE)) {
2475 nasm_error(ERR_WARNING | ERR_PASS2,
2476 "absolute address can not be RIP-relative");
2477 input->type &= ~IP_REL;
2478 input->type |= MEMORY;
2479 }
2480 }
2481
2482 if (bits == 64 &&
2483 !(IP_REL & ~input->type) && (eaflags & EAF_MIB)) {
2484 *errmsg = "RIP-relative addressing is prohibited for MIB";
2485 goto err;
2486 }
2487
2488 if (eaflags & EAF_BYTEOFFS ||
2489 (eaflags & EAF_WORDOFFS &&
2490 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2491 nasm_error(ERR_WARNING | ERR_PASS1,
2492 "displacement size ignored on absolute address");
2493 }
2494
2495 if (bits == 64 && (~input->type & IP_REL)) {
2496 output->sib_present = true;
2497 output->sib = GEN_SIB(0, 4, 5);
2498 output->bytes = 4;
2499 output->modrm = GEN_MODRM(0, rfield, 4);
2500 output->rip = false;
2501 } else {
2502 output->sib_present = false;
2503 output->bytes = (addrbits != 16 ? 4 : 2);
2504 output->modrm = GEN_MODRM(0, rfield,
2505 (addrbits != 16 ? 5 : 6));
2506 output->rip = bits == 64;
2507 }
2508 } else {
2509 /*
2510 * It's an indirection.
2511 */
2512 int i = input->indexreg, b = input->basereg, s = input->scale;
2513 int32_t seg = input->segment;
2514 int hb = input->hintbase, ht = input->hinttype;
2515 int t, it, bt; /* register numbers */
2516 opflags_t x, ix, bx; /* register flags */
2517
2518 if (s == 0)
2519 i = -1; /* make this easy, at least */
2520
2521 if (is_register(i)) {
2522 it = nasm_regvals[i];
2523 ix = nasm_reg_flags[i];
2524 } else {
2525 it = -1;
2526 ix = 0;
2527 }
2528
2529 if (is_register(b)) {
2530 bt = nasm_regvals[b];
2531 bx = nasm_reg_flags[b];
2532 } else {
2533 bt = -1;
2534 bx = 0;
2535 }
2536
2537 /* if either one are a vector register... */
2538 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2539 opflags_t sok = BITS32 | BITS64;
2540 int32_t o = input->offset;
2541 int mod, scale, index, base;
2542
2543 /*
2544 * For a vector SIB, one has to be a vector and the other,
2545 * if present, a GPR. The vector must be the index operand.
2546 */
2547 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2548 if (s == 0)
2549 s = 1;
2550 else if (s != 1)
2551 goto err;
2552
2553 t = bt, bt = it, it = t;
2554 x = bx, bx = ix, ix = x;
2555 }
2556
2557 if (bt != -1) {
2558 if (REG_GPR & ~bx)
2559 goto err;
2560 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2561 sok &= bx;
2562 else
2563 goto err;
2564 }
2565
2566 /*
2567 * While we're here, ensure the user didn't specify
2568 * WORD or QWORD
2569 */
2570 if (input->disp_size == 16 || input->disp_size == 64)
2571 goto err;
2572
2573 if (addrbits == 16 ||
2574 (addrbits == 32 && !(sok & BITS32)) ||
2575 (addrbits == 64 && !(sok & BITS64)))
2576 goto err;
2577
2578 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2579 : ((ix & YMMREG & ~REG_EA)
2580 ? EA_YMMVSIB : EA_XMMVSIB));
2581
2582 output->rex |= rexflags(it, ix, REX_X);
2583 output->rex |= rexflags(bt, bx, REX_B);
2584 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2585
2586 index = it & 7; /* it is known to be != -1 */
2587
2588 switch (s) {
2589 case 1:
2590 scale = 0;
2591 break;
2592 case 2:
2593 scale = 1;
2594 break;
2595 case 4:
2596 scale = 2;
2597 break;
2598 case 8:
2599 scale = 3;
2600 break;
2601 default: /* then what the smeg is it? */
2602 goto err; /* panic */
2603 }
2604
2605 if (bt == -1) {
2606 base = 5;
2607 mod = 0;
2608 } else {
2609 base = (bt & 7);
2610 if (base != REG_NUM_EBP && o == 0 &&
2611 seg == NO_SEG && !forw_ref &&
2612 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2613 mod = 0;
2614 else if (IS_MOD_01())
2615 mod = 1;
2616 else
2617 mod = 2;
2618 }
2619
2620 output->sib_present = true;
2621 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2622 output->modrm = GEN_MODRM(mod, rfield, 4);
2623 output->sib = GEN_SIB(scale, index, base);
2624 } else if ((ix|bx) & (BITS32|BITS64)) {
2625 /*
2626 * it must be a 32/64-bit memory reference. Firstly we have
2627 * to check that all registers involved are type E/Rxx.
2628 */
2629 opflags_t sok = BITS32 | BITS64;
2630 int32_t o = input->offset;
2631
2632 if (it != -1) {
2633 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2634 sok &= ix;
2635 else
2636 goto err;
2637 }
2638
2639 if (bt != -1) {
2640 if (REG_GPR & ~bx)
2641 goto err; /* Invalid register */
2642 if (~sok & bx & SIZE_MASK)
2643 goto err; /* Invalid size */
2644 sok &= bx;
2645 }
2646
2647 /*
2648 * While we're here, ensure the user didn't specify
2649 * WORD or QWORD
2650 */
2651 if (input->disp_size == 16 || input->disp_size == 64)
2652 goto err;
2653
2654 if (addrbits == 16 ||
2655 (addrbits == 32 && !(sok & BITS32)) ||
2656 (addrbits == 64 && !(sok & BITS64)))
2657 goto err;
2658
2659 /* now reorganize base/index */
2660 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2661 ((hb == b && ht == EAH_NOTBASE) ||
2662 (hb == i && ht == EAH_MAKEBASE))) {
2663 /* swap if hints say so */
2664 t = bt, bt = it, it = t;
2665 x = bx, bx = ix, ix = x;
2666 }
2667
2668 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
2669 /* make single reg base, unless hint */
2670 bt = it, bx = ix, it = -1, ix = 0;
2671 }
2672 if (eaflags & EAF_MIB) {
2673 /* only for mib operands */
2674 if (it == -1 && (hb == b && ht == EAH_NOTBASE)) {
2675 /*
2676 * make a single reg index [reg*1].
2677 * gas uses this form for an explicit index register.
2678 */
2679 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2680 }
2681 if ((ht == EAH_SUMMED) && bt == -1) {
2682 /* separate once summed index into [base, index] */
2683 bt = it, bx = ix, s--;
2684 }
2685 } else {
2686 if (((s == 2 && it != REG_NUM_ESP &&
2687 (!(eaflags & EAF_TIMESTWO) || (ht == EAH_SUMMED))) ||
2688 s == 3 || s == 5 || s == 9) && bt == -1) {
2689 /* convert 3*EAX to EAX+2*EAX */
2690 bt = it, bx = ix, s--;
2691 }
2692 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2693 (eaflags & EAF_TIMESTWO) &&
2694 (hb == b && ht == EAH_NOTBASE)) {
2695 /*
2696 * convert [NOSPLIT EAX*1]
2697 * to sib format with 0x0 displacement - [EAX*1+0].
2698 */
2699 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2700 }
2701 }
2702 if (s == 1 && it == REG_NUM_ESP) {
2703 /* swap ESP into base if scale is 1 */
2704 t = it, it = bt, bt = t;
2705 x = ix, ix = bx, bx = x;
2706 }
2707 if (it == REG_NUM_ESP ||
2708 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2709 goto err; /* wrong, for various reasons */
2710
2711 output->rex |= rexflags(it, ix, REX_X);
2712 output->rex |= rexflags(bt, bx, REX_B);
2713
2714 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2715 /* no SIB needed */
2716 int mod, rm;
2717
2718 if (bt == -1) {
2719 rm = 5;
2720 mod = 0;
2721 } else {
2722 rm = (bt & 7);
2723 if (rm != REG_NUM_EBP && o == 0 &&
2724 seg == NO_SEG && !forw_ref &&
2725 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2726 mod = 0;
2727 else if (IS_MOD_01())
2728 mod = 1;
2729 else
2730 mod = 2;
2731 }
2732
2733 output->sib_present = false;
2734 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2735 output->modrm = GEN_MODRM(mod, rfield, rm);
2736 } else {
2737 /* we need a SIB */
2738 int mod, scale, index, base;
2739
2740 if (it == -1)
2741 index = 4, s = 1;
2742 else
2743 index = (it & 7);
2744
2745 switch (s) {
2746 case 1:
2747 scale = 0;
2748 break;
2749 case 2:
2750 scale = 1;
2751 break;
2752 case 4:
2753 scale = 2;
2754 break;
2755 case 8:
2756 scale = 3;
2757 break;
2758 default: /* then what the smeg is it? */
2759 goto err; /* panic */
2760 }
2761
2762 if (bt == -1) {
2763 base = 5;
2764 mod = 0;
2765 } else {
2766 base = (bt & 7);
2767 if (base != REG_NUM_EBP && o == 0 &&
2768 seg == NO_SEG && !forw_ref &&
2769 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2770 mod = 0;
2771 else if (IS_MOD_01())
2772 mod = 1;
2773 else
2774 mod = 2;
2775 }
2776
2777 output->sib_present = true;
2778 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2779 output->modrm = GEN_MODRM(mod, rfield, 4);
2780 output->sib = GEN_SIB(scale, index, base);
2781 }
2782 } else { /* it's 16-bit */
2783 int mod, rm;
2784 int16_t o = input->offset;
2785
2786 /* check for 64-bit long mode */
2787 if (addrbits == 64)
2788 goto err;
2789
2790 /* check all registers are BX, BP, SI or DI */
2791 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2792 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2793 goto err;
2794
2795 /* ensure the user didn't specify DWORD/QWORD */
2796 if (input->disp_size == 32 || input->disp_size == 64)
2797 goto err;
2798
2799 if (s != 1 && i != -1)
2800 goto err; /* no can do, in 16-bit EA */
2801 if (b == -1 && i != -1) {
2802 int tmp = b;
2803 b = i;
2804 i = tmp;
2805 } /* swap */
2806 if ((b == R_SI || b == R_DI) && i != -1) {
2807 int tmp = b;
2808 b = i;
2809 i = tmp;
2810 }
2811 /* have BX/BP as base, SI/DI index */
2812 if (b == i)
2813 goto err; /* shouldn't ever happen, in theory */
2814 if (i != -1 && b != -1 &&
2815 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2816 goto err; /* invalid combinations */
2817 if (b == -1) /* pure offset: handled above */
2818 goto err; /* so if it gets to here, panic! */
2819
2820 rm = -1;
2821 if (i != -1)
2822 switch (i * 256 + b) {
2823 case R_SI * 256 + R_BX:
2824 rm = 0;
2825 break;
2826 case R_DI * 256 + R_BX:
2827 rm = 1;
2828 break;
2829 case R_SI * 256 + R_BP:
2830 rm = 2;
2831 break;
2832 case R_DI * 256 + R_BP:
2833 rm = 3;
2834 break;
2835 } else
2836 switch (b) {
2837 case R_SI:
2838 rm = 4;
2839 break;
2840 case R_DI:
2841 rm = 5;
2842 break;
2843 case R_BP:
2844 rm = 6;
2845 break;
2846 case R_BX:
2847 rm = 7;
2848 break;
2849 }
2850 if (rm == -1) /* can't happen, in theory */
2851 goto err; /* so panic if it does */
2852
2853 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2854 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2855 mod = 0;
2856 else if (IS_MOD_01())
2857 mod = 1;
2858 else
2859 mod = 2;
2860
2861 output->sib_present = false; /* no SIB - it's 16-bit */
2862 output->bytes = mod; /* bytes of offset needed */
2863 output->modrm = GEN_MODRM(mod, rfield, rm);
2864 }
2865 }
2866 }
2867
2868 output->size = 1 + output->sib_present + output->bytes;
2869 return output->type;
2870
2871 err:
2872 return output->type = EA_INVALID;
2873 }
2874
2875 static void add_asp(insn *ins, int addrbits)
2876 {
2877 int j, valid;
2878 int defdisp;
2879
2880 valid = (addrbits == 64) ? 64|32 : 32|16;
2881
2882 switch (ins->prefixes[PPS_ASIZE]) {
2883 case P_A16:
2884 valid &= 16;
2885 break;
2886 case P_A32:
2887 valid &= 32;
2888 break;
2889 case P_A64:
2890 valid &= 64;
2891 break;
2892 case P_ASP:
2893 valid &= (addrbits == 32) ? 16 : 32;
2894 break;
2895 default:
2896 break;
2897 }
2898
2899 for (j = 0; j < ins->operands; j++) {
2900 if (is_class(MEMORY, ins->oprs[j].type)) {
2901 opflags_t i, b;
2902
2903 /* Verify as Register */
2904 if (!is_register(ins->oprs[j].indexreg))
2905 i = 0;
2906 else
2907 i = nasm_reg_flags[ins->oprs[j].indexreg];
2908
2909 /* Verify as Register */
2910 if (!is_register(ins->oprs[j].basereg))
2911 b = 0;
2912 else
2913 b = nasm_reg_flags[ins->oprs[j].basereg];
2914
2915 if (ins->oprs[j].scale == 0)
2916 i = 0;
2917
2918 if (!i && !b) {
2919 int ds = ins->oprs[j].disp_size;
2920 if ((addrbits != 64 && ds > 8) ||
2921 (addrbits == 64 && ds == 16))
2922 valid &= ds;
2923 } else {
2924 if (!(REG16 & ~b))
2925 valid &= 16;
2926 if (!(REG32 & ~b))
2927 valid &= 32;
2928 if (!(REG64 & ~b))
2929 valid &= 64;
2930
2931 if (!(REG16 & ~i))
2932 valid &= 16;
2933 if (!(REG32 & ~i))
2934 valid &= 32;
2935 if (!(REG64 & ~i))
2936 valid &= 64;
2937 }
2938 }
2939 }
2940
2941 if (valid & addrbits) {
2942 ins->addr_size = addrbits;
2943 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2944 /* Add an address size prefix */
2945 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2946 ins->addr_size = (addrbits == 32) ? 16 : 32;
2947 } else {
2948 /* Impossible... */
2949 nasm_error(ERR_NONFATAL, "impossible combination of address sizes");
2950 ins->addr_size = addrbits; /* Error recovery */
2951 }
2952
2953 defdisp = ins->addr_size == 16 ? 16 : 32;
2954
2955 for (j = 0; j < ins->operands; j++) {
2956 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2957 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2958 /*
2959 * mem_offs sizes must match the address size; if not,
2960 * strip the MEM_OFFS bit and match only EA instructions
2961 */
2962 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2963 }
2964 }
2965 }
The Netwide Assembler