1 /* assemble.c code generation for the Netwide Assembler
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
8 * the actual codes (C syntax, i.e. octal):
9 * \0 - terminates the code. (Unless it's a literal of course.)
10 * \1, \2, \3 - that many literal bytes follow in the code stream
11 * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
12 * (POP is never used for CS) depending on operand 0
13 * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
15 * \10..\13 - a literal byte follows in the code stream, to be added
16 * to the register value of operand 0..3
17 * \14..\17 - a signed byte immediate operand, from operand 0..3
18 * \20..\23 - a byte immediate operand, from operand 0..3
19 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
20 * \30..\33 - a word immediate operand, from operand 0..3
21 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
22 * assembly mode or the operand-size override on the operand
23 * \40..\43 - a long immediate operand, from operand 0..3
24 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
25 * depending on the address size of the instruction.
26 * \50..\53 - a byte relative operand, from operand 0..3
27 * \54..\57 - a qword immediate operand, from operand 0..3
28 * \60..\63 - a word relative operand, from operand 0..3
29 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
30 * assembly mode or the operand-size override on the operand
31 * \70..\73 - a long relative operand, from operand 0..3
32 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
33 * \1ab - a ModRM, calculated on EA in operand a, with the spare
34 * field the register value of operand b.
35 * \140..\143 - an immediate word or signed byte for operand 0..3
36 * \144..\147 - or 2 (s-field) into opcode byte if operand 0..3
37 * is a signed byte rather than a word. Opcode byte follows.
38 * \150..\153 - an immediate dword or signed byte for operand 0..3
39 * \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
40 * is a signed byte rather than a word. Opcode byte follows.
41 * \160..\163 - this instruction uses DREX rather than REX, with the
42 * OC0 field set to 0, and the dest field taken from
44 * \164..\167 - this instruction uses DREX rather than REX, with the
45 * OC0 field set to 1, and the dest field taken from
47 * \170 - encodes the literal byte 0. (Some compilers don't take
48 * kindly to a zero byte in the _middle_ of a compile time
49 * string constant, so I had to put this hack in.)
50 * \171 - placement of DREX suffix in the absence of an EA
51 * \2ab - a ModRM, calculated on EA in operand a, with the spare
52 * field equal to digit b.
53 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
54 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
55 * \312 - (disassembler only) marker on LOOP, LOOPxx instructions.
56 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
57 * \314 - (disassembler only) invalid with REX.B
58 * \315 - (disassembler only) invalid with REX.X
59 * \316 - (disassembler only) invalid with REX.R
60 * \317 - (disassembler only) invalid with REX.W
61 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
62 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
63 * \322 - indicates that this instruction is only valid when the
64 * operand size is the default (instruction to disassembler,
65 * generates no code in the assembler)
66 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
67 * \324 - indicates 64-bit operand size requiring REX prefix.
68 * \330 - a literal byte follows in the code stream, to be added
69 * to the condition code value of the instruction.
70 * \331 - instruction not valid with REP prefix. Hint for
71 * disassembler only; for SSE instructions.
72 * \332 - REP prefix (0xF2 byte) used as opcode extension.
73 * \333 - REP prefix (0xF3 byte) used as opcode extension.
74 * \334 - LOCK prefix used instead of REX.R
75 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
76 * \340 - reserve <operand 0> bytes of uninitialized storage.
77 * Operand 0 had better be a segmentless constant.
78 * \364 - operand-size prefix (0x66) not permitted
79 * \365 - address-size prefix (0x67) not permitted
80 * \366 - operand-size prefix (0x66) used as opcode extension
81 * \367 - address-size prefix (0x67) used as opcode extension
82 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
83 * 370 is used for Jcc, 371 is used for JMP.
84 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
85 * used for conditional jump over longer jump
103 int sib_present
; /* is a SIB byte necessary? */
104 int bytes
; /* # of bytes of offset needed */
105 int size
; /* lazy - this is sib+bytes+1 */
106 uint8_t modrm
, sib
, rex
, rip
; /* the bytes themselves */
109 static uint32_t cpu
; /* cpu level received from nasm.c */
110 static efunc errfunc
;
111 static struct ofmt
*outfmt
;
112 static ListGen
*list
;
114 static int64_t calcsize(int32_t, int64_t, int, insn
*, const char *);
115 static void gencode(int32_t, int64_t, int, insn
*, const char *, int64_t);
116 static int matches(const struct itemplate
*, insn
*, int bits
);
117 static int32_t regflag(const operand
*);
118 static int32_t regval(const operand
*);
119 static int rexflags(int, int32_t, int);
120 static int op_rexflags(const operand
*, int);
121 static ea
*process_ea(operand
*, ea
*, int, int, int, int32_t, int);
122 static void add_asp(insn
*, int);
124 static int has_prefix(insn
* ins
, enum prefix_pos pos
, enum prefixes prefix
)
126 return ins
->prefixes
[pos
] == prefix
;
129 static void assert_no_prefix(insn
* ins
, enum prefix_pos pos
)
131 if (ins
->prefixes
[pos
])
132 errfunc(ERR_NONFATAL
, "invalid %s prefix",
133 prefix_name(ins
->prefixes
[pos
]));
136 static const char *size_name(int size
)
156 static void warn_overflow(int size
, int64_t data
)
159 int64_t lim
= ((int64_t)1 << (size
*8))-1;
161 if (data
< ~lim
|| data
> lim
)
162 errfunc(ERR_WARNING
| ERR_WARN_NOV
, "%s data exceeds bounds", size_name(size
));
166 * This routine wrappers the real output format's output routine,
167 * in order to pass a copy of the data off to the listing file
168 * generator at the same time.
170 static void out(int64_t offset
, int32_t segto
, const void *data
,
171 enum out_type type
, uint64_t size
,
172 int32_t segment
, int32_t wrt
)
174 static int32_t lineno
= 0; /* static!!! */
175 static char *lnfname
= NULL
;
178 if (type
== OUT_ADDRESS
&& segment
== NO_SEG
&& wrt
== NO_SEG
) {
180 * This is a non-relocated address, and we're going to
181 * convert it into RAWDATA format.
186 errfunc(ERR_PANIC
, "OUT_ADDRESS with size > 8");
190 WRITEADDR(q
, *(int64_t *)data
, size
);
195 list
->output(offset
, data
, type
, size
);
198 * this call to src_get determines when we call the
199 * debug-format-specific "linenum" function
200 * it updates lineno and lnfname to the current values
201 * returning 0 if "same as last time", -2 if lnfname
202 * changed, and the amount by which lineno changed,
203 * if it did. thus, these variables must be static
206 if (src_get(&lineno
, &lnfname
)) {
207 outfmt
->current_dfmt
->linenum(lnfname
, lineno
, segto
);
210 outfmt
->output(segto
, data
, type
, size
, segment
, wrt
);
213 static int jmp_match(int32_t segment
, int64_t offset
, int bits
,
214 insn
* ins
, const char *code
)
219 if (c
!= 0370 && c
!= 0371)
221 if (ins
->oprs
[0].opflags
& OPFLAG_FORWARD
) {
222 if ((optimizing
< 0 || (ins
->oprs
[0].type
& STRICT
))
226 return (pass0
== 0); /* match a forward reference */
228 isize
= calcsize(segment
, offset
, bits
, ins
, code
);
229 if (ins
->oprs
[0].segment
!= segment
)
231 isize
= ins
->oprs
[0].offset
- offset
- isize
; /* isize is now the delta */
232 if (isize
>= -128L && isize
<= 127L)
233 return 1; /* it is byte size */
238 int64_t assemble(int32_t segment
, int64_t offset
, int bits
, uint32_t cp
,
239 insn
* instruction
, struct ofmt
*output
, efunc error
,
242 const struct itemplate
*temp
;
247 int64_t start
= offset
;
248 int64_t wsize
= 0; /* size for DB etc. */
250 errfunc
= error
; /* to pass to other functions */
252 outfmt
= output
; /* likewise */
253 list
= listgen
; /* and again */
255 switch (instruction
->opcode
) {
282 int32_t t
= instruction
->times
;
285 "instruction->times < 0 (%ld) in assemble()", t
);
287 while (t
--) { /* repeat TIMES times */
288 for (e
= instruction
->eops
; e
; e
= e
->next
) {
289 if (e
->type
== EOT_DB_NUMBER
) {
291 if (e
->segment
!= NO_SEG
)
292 errfunc(ERR_NONFATAL
,
293 "one-byte relocation attempted");
295 uint8_t out_byte
= e
->offset
;
296 out(offset
, segment
, &out_byte
,
297 OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
299 } else if (wsize
> 8) {
300 errfunc(ERR_NONFATAL
, "integer supplied to a DT or DO"
303 out(offset
, segment
, &e
->offset
,
304 OUT_ADDRESS
, wsize
, e
->segment
, e
->wrt
);
306 } else if (e
->type
== EOT_DB_STRING
) {
309 out(offset
, segment
, e
->stringval
,
310 OUT_RAWDATA
, e
->stringlen
, NO_SEG
, NO_SEG
);
311 align
= e
->stringlen
% wsize
;
314 align
= wsize
- align
;
315 out(offset
, segment
, "\0\0\0\0\0\0\0\0",
316 OUT_RAWDATA
, align
, NO_SEG
, NO_SEG
);
318 offset
+= e
->stringlen
+ align
;
321 if (t
> 0 && t
== instruction
->times
- 1) {
323 * Dummy call to list->output to give the offset to the
326 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
327 list
->uplevel(LIST_TIMES
);
330 if (instruction
->times
> 1)
331 list
->downlevel(LIST_TIMES
);
332 return offset
- start
;
335 if (instruction
->opcode
== I_INCBIN
) {
336 static char fname
[FILENAME_MAX
];
339 char *prefix
= "", *combine
;
340 char **pPrevPath
= NULL
;
342 len
= FILENAME_MAX
- 1;
343 if (len
> instruction
->eops
->stringlen
)
344 len
= instruction
->eops
->stringlen
;
345 strncpy(fname
, instruction
->eops
->stringval
, len
);
348 while (1) { /* added by alexfru: 'incbin' uses include paths */
349 combine
= nasm_malloc(strlen(prefix
) + len
+ 1);
350 strcpy(combine
, prefix
);
351 strcat(combine
, fname
);
353 if ((fp
= fopen(combine
, "rb")) != NULL
) {
359 pPrevPath
= pp_get_include_path_ptr(pPrevPath
);
360 if (pPrevPath
== NULL
)
366 error(ERR_NONFATAL
, "`incbin': unable to open file `%s'",
368 else if (fseek(fp
, 0L, SEEK_END
) < 0)
369 error(ERR_NONFATAL
, "`incbin': unable to seek on file `%s'",
372 static char buf
[2048];
373 int32_t t
= instruction
->times
;
377 if (instruction
->eops
->next
) {
378 base
= instruction
->eops
->next
->offset
;
380 if (instruction
->eops
->next
->next
&&
381 len
> instruction
->eops
->next
->next
->offset
)
382 len
= instruction
->eops
->next
->next
->offset
;
385 * Dummy call to list->output to give the offset to the
388 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
389 list
->uplevel(LIST_INCBIN
);
393 fseek(fp
, base
, SEEK_SET
);
397 fread(buf
, 1, (l
> (int32_t) sizeof(buf
) ? (int32_t) sizeof(buf
) : l
),
401 * This shouldn't happen unless the file
402 * actually changes while we are reading
406 "`incbin': unexpected EOF while"
407 " reading file `%s'", fname
);
408 t
= 0; /* Try to exit cleanly */
411 out(offset
, segment
, buf
, OUT_RAWDATA
, m
,
416 list
->downlevel(LIST_INCBIN
);
417 if (instruction
->times
> 1) {
419 * Dummy call to list->output to give the offset to the
422 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
423 list
->uplevel(LIST_TIMES
);
424 list
->downlevel(LIST_TIMES
);
427 return instruction
->times
* len
;
429 return 0; /* if we're here, there's an error */
432 /* Check to see if we need an address-size prefix */
433 add_asp(instruction
, bits
);
437 for (temp
= nasm_instructions
[instruction
->opcode
]; temp
->opcode
!= -1; temp
++){
438 int m
= matches(temp
, instruction
, bits
);
441 m
+= jmp_match(segment
, offset
, bits
, instruction
, temp
->code
);
443 if (m
== 100) { /* matches! */
444 const char *codes
= temp
->code
;
445 int64_t insn_size
= calcsize(segment
, offset
, bits
,
447 itimes
= instruction
->times
;
448 if (insn_size
< 0) /* shouldn't be, on pass two */
449 error(ERR_PANIC
, "errors made it through from pass one");
452 for (j
= 0; j
< MAXPREFIX
; j
++) {
454 switch (instruction
->prefixes
[j
]) {
470 "cs segment base generated, but will be ignored in 64-bit mode");
477 "ds segment base generated, but will be ignored in 64-bit mode");
484 "es segment base generated, but will be ignored in 64-bit mode");
497 "ss segment base generated, but will be ignored in 64-bit mode");
504 "segr6 and segr7 cannot be used as prefixes");
509 "16-bit addressing is not supported "
511 } else if (bits
!= 16)
521 "64-bit addressing is only supported "
545 error(ERR_PANIC
, "invalid instruction prefix");
548 out(offset
, segment
, &c
, OUT_RAWDATA
, 1,
553 insn_end
= offset
+ insn_size
;
554 gencode(segment
, offset
, bits
, instruction
, codes
,
557 if (itimes
> 0 && itimes
== instruction
->times
- 1) {
559 * Dummy call to list->output to give the offset to the
562 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
563 list
->uplevel(LIST_TIMES
);
566 if (instruction
->times
> 1)
567 list
->downlevel(LIST_TIMES
);
568 return offset
- start
;
569 } else if (m
> 0 && m
> size_prob
) {
575 if (temp
->opcode
== -1) { /* didn't match any instruction */
578 error(ERR_NONFATAL
, "operation size not specified");
581 error(ERR_NONFATAL
, "mismatch in operand sizes");
584 error(ERR_NONFATAL
, "no instruction for this cpu level");
587 error(ERR_NONFATAL
, "instruction not supported in 64-bit mode");
591 "invalid combination of opcode and operands");
598 int64_t insn_size(int32_t segment
, int64_t offset
, int bits
, uint32_t cp
,
599 insn
* instruction
, efunc error
)
601 const struct itemplate
*temp
;
603 errfunc
= error
; /* to pass to other functions */
606 if (instruction
->opcode
== -1)
609 if (instruction
->opcode
== I_DB
|| instruction
->opcode
== I_DW
||
610 instruction
->opcode
== I_DD
|| instruction
->opcode
== I_DQ
||
611 instruction
->opcode
== I_DT
|| instruction
->opcode
== I_DO
) {
613 int32_t isize
, osize
, wsize
= 0; /* placate gcc */
616 switch (instruction
->opcode
) {
639 for (e
= instruction
->eops
; e
; e
= e
->next
) {
643 if (e
->type
== EOT_DB_NUMBER
)
645 else if (e
->type
== EOT_DB_STRING
)
646 osize
= e
->stringlen
;
648 align
= (-osize
) % wsize
;
651 isize
+= osize
+ align
;
653 return isize
* instruction
->times
;
656 if (instruction
->opcode
== I_INCBIN
) {
657 char fname
[FILENAME_MAX
];
660 char *prefix
= "", *combine
;
661 char **pPrevPath
= NULL
;
663 len
= FILENAME_MAX
- 1;
664 if (len
> instruction
->eops
->stringlen
)
665 len
= instruction
->eops
->stringlen
;
666 strncpy(fname
, instruction
->eops
->stringval
, len
);
669 /* added by alexfru: 'incbin' uses include paths */
671 combine
= nasm_malloc(strlen(prefix
) + len
+ 1);
672 strcpy(combine
, prefix
);
673 strcat(combine
, fname
);
675 if ((fp
= fopen(combine
, "rb")) != NULL
) {
681 pPrevPath
= pp_get_include_path_ptr(pPrevPath
);
682 if (pPrevPath
== NULL
)
688 error(ERR_NONFATAL
, "`incbin': unable to open file `%s'",
690 else if (fseek(fp
, 0L, SEEK_END
) < 0)
691 error(ERR_NONFATAL
, "`incbin': unable to seek on file `%s'",
696 if (instruction
->eops
->next
) {
697 len
-= instruction
->eops
->next
->offset
;
698 if (instruction
->eops
->next
->next
&&
699 len
> instruction
->eops
->next
->next
->offset
) {
700 len
= instruction
->eops
->next
->next
->offset
;
703 return instruction
->times
* len
;
705 return 0; /* if we're here, there's an error */
708 /* Check to see if we need an address-size prefix */
709 add_asp(instruction
, bits
);
711 for (temp
= nasm_instructions
[instruction
->opcode
]; temp
->opcode
!= -1; temp
++) {
712 int m
= matches(temp
, instruction
, bits
);
714 m
+= jmp_match(segment
, offset
, bits
, instruction
, temp
->code
);
717 /* we've matched an instruction. */
719 const char *codes
= temp
->code
;
722 isize
= calcsize(segment
, offset
, bits
, instruction
, codes
);
725 for (j
= 0; j
< MAXPREFIX
; j
++) {
726 switch (instruction
->prefixes
[j
]) {
752 return isize
* instruction
->times
;
755 return -1; /* didn't match any instruction */
758 /* check that opn[op] is a signed byte of size 16 or 32,
759 and return the signed value*/
760 static int is_sbyte(insn
* ins
, int op
, int size
)
765 ret
= !(ins
->forw_ref
&& ins
->oprs
[op
].opflags
) && /* dead in the water on forward reference or External */
767 !(ins
->oprs
[op
].type
& STRICT
) &&
768 ins
->oprs
[op
].wrt
== NO_SEG
&& ins
->oprs
[op
].segment
== NO_SEG
;
770 v
= ins
->oprs
[op
].offset
;
772 v
= (int16_t)v
; /* sign extend if 16 bits */
774 return ret
&& v
>= -128L && v
<= 127L;
777 static int64_t calcsize(int32_t segment
, int64_t offset
, int bits
,
778 insn
* ins
, const char *codes
)
785 ins
->rex
= 0; /* Ensure REX is reset */
787 if (ins
->prefixes
[PPS_OSIZE
] == P_O64
)
790 (void)segment
; /* Don't warn that this parameter is unused */
791 (void)offset
; /* Don't warn that this parameter is unused */
795 opx
= &ins
->oprs
[c
& 3];
800 codes
+= c
, length
+= c
;
813 op_rexflags(opx
, REX_B
|REX_H
|REX_P
|REX_W
);
844 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
845 length
+= (opx
->type
& BITS16
) ? 2 : 4;
847 length
+= (bits
== 16) ? 2 : 4;
859 length
+= ins
->addr_size
>> 3;
871 length
+= 8; /* MOV reg64/imm */
883 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
884 length
+= (opx
->type
& BITS16
) ? 2 : 4;
886 length
+= (bits
== 16) ? 2 : 4;
904 length
+= is_sbyte(ins
, c
& 3, 16) ? 1 : 2;
917 length
+= is_sbyte(ins
, c
& 3, 32) ? 1 : 4;
932 ins
->drexdst
= regval(&ins
->oprs
[c
& 3]);
939 ins
->rex
|= REX_D
|REX_OC
;
940 ins
->drexdst
= regval(&ins
->oprs
[c
& 3]);
955 length
+= (bits
!= 16) && !has_prefix(ins
, PPS_ASIZE
, P_A16
);
958 length
+= (bits
!= 32) && !has_prefix(ins
, PPS_ASIZE
, P_A32
);
963 if (bits
!= 64 || has_prefix(ins
, PPS_ASIZE
, P_A16
) ||
964 has_prefix(ins
, PPS_ASIZE
, P_A32
))
973 length
+= (bits
!= 16);
976 length
+= (bits
== 16);
1001 if (ins
->oprs
[0].segment
!= NO_SEG
)
1002 errfunc(ERR_NONFATAL
, "attempt to reserve non-constant"
1003 " quantity of BSS space");
1005 length
+= ins
->oprs
[0].offset
;
1021 default: /* can't do it by 'case' statements */
1022 if (c
>= 0100 && c
<= 0277) { /* it's an EA */
1026 ea_data
.rex
= 0; /* Ensure ea.REX is initially 0 */
1029 /* pick rfield from operand b */
1030 rflags
= regflag(&ins
->oprs
[c
& 7]);
1031 rfield
= regvals
[ins
->oprs
[c
& 7].basereg
];
1038 (&ins
->oprs
[(c
>> 3) & 7], &ea_data
, bits
,
1039 ins
->addr_size
, rfield
, rflags
, ins
->forw_ref
)) {
1040 errfunc(ERR_NONFATAL
, "invalid effective address");
1043 ins
->rex
|= ea_data
.rex
;
1044 length
+= ea_data
.size
;
1047 errfunc(ERR_PANIC
, "internal instruction table corrupt"
1048 ": instruction code 0x%02X given", c
);
1053 ins
->rex
&= rex_mask
;
1055 if (ins
->rex
& REX_D
) {
1056 if (ins
->rex
& REX_H
) {
1057 errfunc(ERR_NONFATAL
, "cannot use high register in drex instruction");
1060 if (bits
!= 64 && ((ins
->rex
& (REX_W
|REX_X
|REX_B
)) ||
1061 ins
->drexdst
> 7)) {
1062 errfunc(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1066 } else if (ins
->rex
& REX_REAL
) {
1067 if (ins
->rex
& REX_H
) {
1068 errfunc(ERR_NONFATAL
, "cannot use high register in rex instruction");
1070 } else if (bits
== 64) {
1072 } else if ((ins
->rex
& REX_L
) &&
1073 !(ins
->rex
& (REX_P
|REX_W
|REX_X
|REX_B
)) &&
1076 assert_no_prefix(ins
, PPS_LREP
);
1079 errfunc(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1087 #define EMIT_REX() \
1088 if (!(ins->rex & REX_D) && (ins->rex & REX_REAL) && (bits == 64)) { \
1089 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1090 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1095 static void gencode(int32_t segment
, int64_t offset
, int bits
,
1096 insn
* ins
, const char *codes
, int64_t insn_end
)
1098 static char condval
[] = { /* conditional opcodes */
1099 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1100 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1101 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1107 struct operand
*opx
;
1111 opx
= &ins
->oprs
[c
& 3];
1117 out(offset
, segment
, codes
, OUT_RAWDATA
, c
, NO_SEG
, NO_SEG
);
1124 switch (ins
->oprs
[0].basereg
) {
1126 bytes
[0] = 0x0E + (c
== 0x04 ? 1 : 0);
1129 bytes
[0] = 0x1E + (c
== 0x04 ? 1 : 0);
1132 bytes
[0] = 0x06 + (c
== 0x04 ? 1 : 0);
1135 bytes
[0] = 0x16 + (c
== 0x04 ? 1 : 0);
1139 "bizarre 8086 segment register received");
1141 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1147 switch (ins
->oprs
[0].basereg
) {
1149 bytes
[0] = 0xA0 + (c
== 0x05 ? 1 : 0);
1152 bytes
[0] = 0xA8 + (c
== 0x05 ? 1 : 0);
1156 "bizarre 386 segment register received");
1158 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1167 bytes
[0] = *codes
++ + ((regval(opx
)) & 7);
1168 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1176 if (opx
->offset
< -128 || opx
->offset
> 127) {
1177 errfunc(ERR_WARNING
| ERR_WARN_NOV
,
1178 "signed byte value exceeds bounds");
1181 if (opx
->segment
!= NO_SEG
) {
1183 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1184 opx
->segment
, opx
->wrt
);
1186 bytes
[0] = opx
->offset
;
1187 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1197 if (opx
->offset
< -256 || opx
->offset
> 255) {
1198 errfunc(ERR_WARNING
| ERR_WARN_NOV
,
1199 "byte value exceeds bounds");
1201 if (opx
->segment
!= NO_SEG
) {
1203 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1204 opx
->segment
, opx
->wrt
);
1206 bytes
[0] = opx
->offset
;
1207 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1217 if (opx
->offset
< 0 || opx
->offset
> 255)
1218 errfunc(ERR_WARNING
| ERR_WARN_NOV
,
1219 "unsigned byte value exceeds bounds");
1220 if (opx
->segment
!= NO_SEG
) {
1222 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1223 opx
->segment
, opx
->wrt
);
1225 bytes
[0] = opx
->offset
;
1226 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1237 if (opx
->segment
== NO_SEG
&& opx
->wrt
== NO_SEG
)
1238 warn_overflow(2, data
);
1239 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1240 opx
->segment
, opx
->wrt
);
1248 if (opx
->type
& (BITS16
| BITS32
))
1249 size
= (opx
->type
& BITS16
) ? 2 : 4;
1251 size
= (bits
== 16) ? 2 : 4;
1253 if (opx
->segment
== NO_SEG
&& opx
->wrt
== NO_SEG
)
1254 warn_overflow(size
, data
);
1255 out(offset
, segment
, &data
, OUT_ADDRESS
, size
,
1256 opx
->segment
, opx
->wrt
);
1265 if (opx
->segment
== NO_SEG
&& opx
->wrt
== NO_SEG
)
1266 warn_overflow(4, data
);
1267 out(offset
, segment
, &data
, OUT_ADDRESS
, 4,
1268 opx
->segment
, opx
->wrt
);
1277 size
= ins
->addr_size
>> 3;
1278 if (opx
->segment
== NO_SEG
&&
1280 warn_overflow(size
, data
);
1281 out(offset
, segment
, &data
, OUT_ADDRESS
, size
,
1282 opx
->segment
, opx
->wrt
);
1290 if (opx
->segment
!= segment
)
1291 errfunc(ERR_NONFATAL
,
1292 "short relative jump outside segment");
1293 data
= opx
->offset
- insn_end
;
1294 if (data
> 127 || data
< -128)
1295 errfunc(ERR_NONFATAL
, "short jump is out of range");
1297 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1305 data
= (int64_t)opx
->offset
;
1306 out(offset
, segment
, &data
, OUT_ADDRESS
, 8,
1307 opx
->segment
, opx
->wrt
);
1315 if (opx
->segment
!= segment
) {
1317 out(offset
, segment
, &data
,
1318 OUT_REL2ADR
, insn_end
- offset
,
1319 opx
->segment
, opx
->wrt
);
1321 data
= opx
->offset
- insn_end
;
1322 out(offset
, segment
, &data
,
1323 OUT_ADDRESS
, 2, NO_SEG
, NO_SEG
);
1332 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
1333 size
= (opx
->type
& BITS16
) ? 2 : 4;
1335 size
= (bits
== 16) ? 2 : 4;
1336 if (opx
->segment
!= segment
) {
1338 out(offset
, segment
, &data
,
1339 size
== 2 ? OUT_REL2ADR
: OUT_REL4ADR
,
1340 insn_end
- offset
, opx
->segment
, opx
->wrt
);
1342 data
= opx
->offset
- insn_end
;
1343 out(offset
, segment
, &data
,
1344 OUT_ADDRESS
, size
, NO_SEG
, NO_SEG
);
1353 if (opx
->segment
!= segment
) {
1355 out(offset
, segment
, &data
,
1356 OUT_REL4ADR
, insn_end
- offset
,
1357 opx
->segment
, opx
->wrt
);
1359 data
= opx
->offset
- insn_end
;
1360 out(offset
, segment
, &data
,
1361 OUT_ADDRESS
, 4, NO_SEG
, NO_SEG
);
1370 if (opx
->segment
== NO_SEG
)
1371 errfunc(ERR_NONFATAL
, "value referenced by FAR is not"
1374 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1375 outfmt
->segbase(1 + opx
->segment
),
1385 if (is_sbyte(ins
, c
& 3, 16)) {
1387 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1391 if (opx
->segment
== NO_SEG
&&
1393 warn_overflow(2, data
);
1394 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1395 opx
->segment
, opx
->wrt
);
1405 bytes
[0] = *codes
++;
1406 if (is_sbyte(ins
, c
& 3, 16))
1407 bytes
[0] |= 2; /* s-bit */
1408 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1417 if (is_sbyte(ins
, c
& 3, 32)) {
1419 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1423 out(offset
, segment
, &data
, OUT_ADDRESS
, 4,
1424 opx
->segment
, opx
->wrt
);
1434 bytes
[0] = *codes
++;
1435 if (is_sbyte(ins
, c
& 3, 32))
1436 bytes
[0] |= 2; /* s-bit */
1437 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1454 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1460 (ins
->drexdst
<< 4) |
1461 (ins
->rex
& REX_OC
? 0x08 : 0) |
1462 (ins
->rex
& (REX_R
|REX_X
|REX_B
));
1464 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1475 if (bits
== 32 && !has_prefix(ins
, PPS_ASIZE
, P_A16
)) {
1477 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1484 if (bits
!= 32 && !has_prefix(ins
, PPS_ASIZE
, P_A32
)) {
1486 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1508 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1517 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1532 *bytes
= *codes
++ ^ condval
[ins
->condition
];
1533 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1542 *bytes
= c
- 0332 + 0xF2;
1543 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1548 if (ins
->rex
& REX_R
) {
1550 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1553 ins
->rex
&= ~(REX_L
|REX_R
);
1560 if (ins
->oprs
[0].segment
!= NO_SEG
)
1561 errfunc(ERR_PANIC
, "non-constant BSS size in pass two");
1563 int64_t size
= ins
->oprs
[0].offset
;
1565 out(offset
, segment
, NULL
,
1566 OUT_RESERVE
, size
, NO_SEG
, NO_SEG
);
1577 *bytes
= c
- 0366 + 0x66;
1578 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1588 *bytes
= bits
== 16 ? 3 : 5;
1589 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1593 default: /* can't do it by 'case' statements */
1594 if (c
>= 0100 && c
<= 0277) { /* it's an EA */
1602 /* pick rfield from operand b */
1603 rflags
= regflag(&ins
->oprs
[c
& 7]);
1604 rfield
= regvals
[ins
->oprs
[c
& 7].basereg
];
1606 /* rfield is constant */
1612 (&ins
->oprs
[(c
>> 3) & 7], &ea_data
, bits
,
1613 ins
->addr_size
, rfield
, rflags
, ins
->forw_ref
)) {
1614 errfunc(ERR_NONFATAL
, "invalid effective address");
1619 *p
++ = ea_data
.modrm
;
1620 if (ea_data
.sib_present
)
1623 /* DREX suffixes come between the SIB and the displacement */
1624 if (ins
->rex
& REX_D
) {
1626 (ins
->drexdst
<< 4) |
1627 (ins
->rex
& REX_OC
? 0x08 : 0) |
1628 (ins
->rex
& (REX_R
|REX_X
|REX_B
));
1633 out(offset
, segment
, bytes
, OUT_RAWDATA
, s
, NO_SEG
, NO_SEG
);
1635 switch (ea_data
.bytes
) {
1639 if (ins
->oprs
[(c
>> 3) & 7].segment
!= NO_SEG
) {
1640 data
= ins
->oprs
[(c
>> 3) & 7].offset
;
1641 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1642 ins
->oprs
[(c
>> 3) & 7].segment
,
1643 ins
->oprs
[(c
>> 3) & 7].wrt
);
1645 *bytes
= ins
->oprs
[(c
>> 3) & 7].offset
;
1646 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1,
1654 data
= ins
->oprs
[(c
>> 3) & 7].offset
;
1655 warn_overflow(ea_data
.bytes
, data
);
1656 out(offset
, segment
, &data
,
1657 ea_data
.rip
? OUT_REL4ADR
: OUT_ADDRESS
,
1659 ins
->oprs
[(c
>> 3) & 7].segment
,
1660 ins
->oprs
[(c
>> 3) & 7].wrt
);
1666 errfunc(ERR_PANIC
, "internal instruction table corrupt"
1667 ": instruction code 0x%02X given", c
);
1673 static int32_t regflag(const operand
* o
)
1675 if (o
->basereg
< EXPR_REG_START
|| o
->basereg
>= REG_ENUM_LIMIT
) {
1676 errfunc(ERR_PANIC
, "invalid operand passed to regflag()");
1678 return reg_flags
[o
->basereg
];
1681 static int32_t regval(const operand
* o
)
1683 if (o
->basereg
< EXPR_REG_START
|| o
->basereg
>= REG_ENUM_LIMIT
) {
1684 errfunc(ERR_PANIC
, "invalid operand passed to regval()");
1686 return regvals
[o
->basereg
];
1689 static int op_rexflags(const operand
* o
, int mask
)
1694 if (o
->basereg
< EXPR_REG_START
|| o
->basereg
>= REG_ENUM_LIMIT
) {
1695 errfunc(ERR_PANIC
, "invalid operand passed to op_rexflags()");
1698 flags
= reg_flags
[o
->basereg
];
1699 val
= regvals
[o
->basereg
];
1701 return rexflags(val
, flags
, mask
);
1704 static int rexflags(int val
, int32_t flags
, int mask
)
1709 rex
|= REX_B
|REX_X
|REX_R
;
1712 if (!(REG_HIGH
& ~flags
)) /* AH, CH, DH, BH */
1714 else if (!(REG8
& ~flags
) && val
>= 4) /* SPL, BPL, SIL, DIL */
1720 static int matches(const struct itemplate
*itemp
, insn
* instruction
, int bits
)
1722 int i
, size
[MAX_OPERANDS
], asize
, oprs
, ret
;
1729 if (itemp
->opcode
!= instruction
->opcode
)
1733 * Count the operands
1735 if (itemp
->operands
!= instruction
->operands
)
1739 * Check that no spurious colons or TOs are present
1741 for (i
= 0; i
< itemp
->operands
; i
++)
1742 if (instruction
->oprs
[i
].type
& ~itemp
->opd
[i
] & (COLON
| TO
))
1746 * Check that the operand flags all match up
1748 for (i
= 0; i
< itemp
->operands
; i
++) {
1749 if (itemp
->opd
[i
] & SAME_AS
) {
1750 int j
= itemp
->opd
[i
] & ~SAME_AS
;
1751 if (instruction
->oprs
[i
].type
!= instruction
->oprs
[j
].type
||
1752 instruction
->oprs
[i
].basereg
!= instruction
->oprs
[j
].basereg
)
1754 } else if (itemp
->opd
[i
] & ~instruction
->oprs
[i
].type
||
1755 ((itemp
->opd
[i
] & SIZE_MASK
) &&
1756 ((itemp
->opd
[i
] ^ instruction
->oprs
[i
].type
) & SIZE_MASK
))) {
1757 if ((itemp
->opd
[i
] & ~instruction
->oprs
[i
].type
& ~SIZE_MASK
) ||
1758 (instruction
->oprs
[i
].type
& SIZE_MASK
))
1766 * Check operand sizes
1768 if (itemp
->flags
& IF_ARMASK
) {
1769 memset(size
, 0, sizeof size
);
1771 switch (itemp
->flags
& IF_ARMASK
) {
1785 break; /* Shouldn't happen */
1787 switch (itemp
->flags
& IF_SMASK
) {
1808 switch (itemp
->flags
& IF_SMASK
) {
1811 oprs
= itemp
->operands
;
1815 oprs
= itemp
->operands
;
1819 oprs
= itemp
->operands
;
1823 oprs
= itemp
->operands
;
1827 oprs
= itemp
->operands
;
1832 for (i
= 0; i
< MAX_OPERANDS
; i
++)
1836 if (itemp
->flags
& (IF_SM
| IF_SM2
)) {
1837 oprs
= (itemp
->flags
& IF_SM2
? 2 : itemp
->operands
);
1839 for (i
= 0; i
< oprs
; i
++) {
1840 if ((asize
= itemp
->opd
[i
] & SIZE_MASK
) != 0) {
1842 for (j
= 0; j
< oprs
; j
++)
1848 oprs
= itemp
->operands
;
1851 for (i
= 0; i
< itemp
->operands
; i
++) {
1852 if (!(itemp
->opd
[i
] & SIZE_MASK
) &&
1853 (instruction
->oprs
[i
].type
& SIZE_MASK
& ~size
[i
]))
1858 * Check template is okay at the set cpu level
1860 if (((itemp
->flags
& IF_PLEVEL
) > cpu
))
1864 * Check if instruction is available in long mode
1866 if ((itemp
->flags
& IF_NOLONG
) && (bits
== 64))
1870 * Check if special handling needed for Jumps
1872 if ((uint8_t)(itemp
->code
[0]) >= 0370)
1878 static ea
*process_ea(operand
* input
, ea
* output
, int bits
,
1879 int addrbits
, int rfield
, int32_t rflags
, int forw_ref
)
1881 output
->rip
= false;
1883 /* REX flags for the rfield operand */
1884 output
->rex
|= rexflags(rfield
, rflags
, REX_R
|REX_P
|REX_W
|REX_H
);
1886 if (!(REGISTER
& ~input
->type
)) { /* register direct */
1890 if (input
->basereg
< EXPR_REG_START
/* Verify as Register */
1891 || input
->basereg
>= REG_ENUM_LIMIT
)
1894 i
= regvals
[input
->basereg
];
1897 return NULL
; /* Invalid EA register */
1899 output
->rex
|= op_rexflags(input
, REX_B
|REX_P
|REX_W
|REX_H
);
1901 output
->sib_present
= false; /* no SIB necessary */
1902 output
->bytes
= 0; /* no offset necessary either */
1903 output
->modrm
= 0xC0 | ((rfield
& 7) << 3) | (i
& 7);
1904 } else { /* it's a memory reference */
1905 if (input
->basereg
== -1
1906 && (input
->indexreg
== -1 || input
->scale
== 0)) {
1907 /* it's a pure offset */
1908 if (bits
== 64 && (~input
->type
& IP_REL
)) {
1909 int scale
, index
, base
;
1910 output
->sib_present
= true;
1914 output
->sib
= (scale
<< 6) | (index
<< 3) | base
;
1916 output
->modrm
= 4 | ((rfield
& 7) << 3);
1917 output
->rip
= false;
1919 output
->sib_present
= false;
1920 output
->bytes
= (addrbits
!= 16 ? 4 : 2);
1921 output
->modrm
= (addrbits
!= 16 ? 5 : 6) | ((rfield
& 7) << 3);
1922 output
->rip
= bits
== 64;
1924 } else { /* it's an indirection */
1925 int i
= input
->indexreg
, b
= input
->basereg
, s
= input
->scale
;
1926 int32_t o
= input
->offset
, seg
= input
->segment
;
1927 int hb
= input
->hintbase
, ht
= input
->hinttype
;
1930 int32_t ix
, bx
; /* register flags */
1933 i
= -1; /* make this easy, at least */
1935 if (i
>= EXPR_REG_START
&& i
< REG_ENUM_LIMIT
) {
1943 if (b
>= EXPR_REG_START
&& b
< REG_ENUM_LIMIT
) {
1951 /* check for a 32/64-bit memory reference... */
1952 if ((ix
|bx
) & (BITS32
|BITS64
)) {
1953 /* it must be a 32/64-bit memory reference. Firstly we have
1954 * to check that all registers involved are type E/Rxx. */
1955 int32_t sok
= BITS32
|BITS64
;
1958 if (!(REG64
& ~ix
) || !(REG32
& ~ix
))
1966 return NULL
; /* Invalid register */
1967 if (~sok
& bx
& SIZE_MASK
)
1968 return NULL
; /* Invalid size */
1972 /* While we're here, ensure the user didn't specify
1974 if (input
->disp_size
== 16 || input
->disp_size
== 64)
1977 if (addrbits
== 16 ||
1978 (addrbits
== 32 && !(sok
& BITS32
)) ||
1979 (addrbits
== 64 && !(sok
& BITS64
)))
1982 /* now reorganize base/index */
1983 if (s
== 1 && bt
!= it
&& bt
!= -1 && it
!= -1 &&
1984 ((hb
== b
&& ht
== EAH_NOTBASE
)
1985 || (hb
== i
&& ht
== EAH_MAKEBASE
))) {
1986 /* swap if hints say so */
1987 t
= bt
, bt
= it
, it
= t
;
1988 t
= bx
, bx
= ix
, ix
= t
;
1990 if (bt
== it
) /* convert EAX+2*EAX to 3*EAX */
1991 bt
= -1, bx
= 0, s
++;
1992 if (bt
== -1 && s
== 1 && !(hb
== it
&& ht
== EAH_NOTBASE
)) {
1993 /* make single reg base, unless hint */
1994 bt
= it
, bx
= ix
, it
= -1, ix
= 0;
1996 if (((s
== 2 && it
!= REG_NUM_ESP
1997 && !(input
->eaflags
& EAF_TIMESTWO
)) || s
== 3
1998 || s
== 5 || s
== 9) && bt
== -1)
1999 bt
= it
, bx
= ix
, s
--; /* convert 3*EAX to EAX+2*EAX */
2000 if (it
== -1 && (bt
& 7) != REG_NUM_ESP
2001 && (input
->eaflags
& EAF_TIMESTWO
))
2002 it
= bt
, ix
= bx
, bt
= -1, bx
= 0, s
= 1;
2003 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2004 if (s
== 1 && it
== REG_NUM_ESP
) {
2005 /* swap ESP into base if scale is 1 */
2006 t
= it
, it
= bt
, bt
= t
;
2007 t
= ix
, ix
= bx
, bx
= t
;
2009 if (it
== REG_NUM_ESP
2010 || (s
!= 1 && s
!= 2 && s
!= 4 && s
!= 8 && it
!= -1))
2011 return NULL
; /* wrong, for various reasons */
2013 output
->rex
|= rexflags(it
, ix
, REX_X
);
2014 output
->rex
|= rexflags(bt
, bx
, REX_B
);
2016 if (it
== -1 && (bt
& 7) != REG_NUM_ESP
) {
2025 if (rm
!= REG_NUM_EBP
&& o
== 0 &&
2026 seg
== NO_SEG
&& !forw_ref
&&
2028 (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2030 else if (input
->eaflags
& EAF_BYTEOFFS
||
2031 (o
>= -128 && o
<= 127 && seg
== NO_SEG
2033 && !(input
->eaflags
& EAF_WORDOFFS
)))
2039 output
->sib_present
= false;
2040 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2041 output
->modrm
= (mod
<< 6) | ((rfield
& 7) << 3) | rm
;
2044 int mod
, scale
, index
, base
;
2064 default: /* then what the smeg is it? */
2065 return NULL
; /* panic */
2073 if (base
!= REG_NUM_EBP
&& o
== 0 &&
2074 seg
== NO_SEG
&& !forw_ref
&&
2076 (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2078 else if (input
->eaflags
& EAF_BYTEOFFS
||
2079 (o
>= -128 && o
<= 127 && seg
== NO_SEG
2081 && !(input
->eaflags
& EAF_WORDOFFS
)))
2087 output
->sib_present
= true;
2088 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2089 output
->modrm
= (mod
<< 6) | ((rfield
& 7) << 3) | 4;
2090 output
->sib
= (scale
<< 6) | (index
<< 3) | base
;
2092 } else { /* it's 16-bit */
2095 /* check for 64-bit long mode */
2099 /* check all registers are BX, BP, SI or DI */
2100 if ((b
!= -1 && b
!= R_BP
&& b
!= R_BX
&& b
!= R_SI
2101 && b
!= R_DI
) || (i
!= -1 && i
!= R_BP
&& i
!= R_BX
2102 && i
!= R_SI
&& i
!= R_DI
))
2105 /* ensure the user didn't specify DWORD/QWORD */
2106 if (input
->disp_size
== 32 || input
->disp_size
== 64)
2109 if (s
!= 1 && i
!= -1)
2110 return NULL
; /* no can do, in 16-bit EA */
2111 if (b
== -1 && i
!= -1) {
2116 if ((b
== R_SI
|| b
== R_DI
) && i
!= -1) {
2121 /* have BX/BP as base, SI/DI index */
2123 return NULL
; /* shouldn't ever happen, in theory */
2124 if (i
!= -1 && b
!= -1 &&
2125 (i
== R_BP
|| i
== R_BX
|| b
== R_SI
|| b
== R_DI
))
2126 return NULL
; /* invalid combinations */
2127 if (b
== -1) /* pure offset: handled above */
2128 return NULL
; /* so if it gets to here, panic! */
2132 switch (i
* 256 + b
) {
2133 case R_SI
* 256 + R_BX
:
2136 case R_DI
* 256 + R_BX
:
2139 case R_SI
* 256 + R_BP
:
2142 case R_DI
* 256 + R_BP
:
2160 if (rm
== -1) /* can't happen, in theory */
2161 return NULL
; /* so panic if it does */
2163 if (o
== 0 && seg
== NO_SEG
&& !forw_ref
&& rm
!= 6 &&
2164 !(input
->eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2166 else if (input
->eaflags
& EAF_BYTEOFFS
||
2167 (o
>= -128 && o
<= 127 && seg
== NO_SEG
2169 && !(input
->eaflags
& EAF_WORDOFFS
)))
2174 output
->sib_present
= false; /* no SIB - it's 16-bit */
2175 output
->bytes
= mod
; /* bytes of offset needed */
2176 output
->modrm
= (mod
<< 6) | ((rfield
& 7) << 3) | rm
;
2181 output
->size
= 1 + output
->sib_present
+ output
->bytes
;
2185 static void add_asp(insn
*ins
, int addrbits
)
2190 valid
= (addrbits
== 64) ? 64|32 : 32|16;
2192 switch (ins
->prefixes
[PPS_ASIZE
]) {
2203 valid
&= (addrbits
== 32) ? 16 : 32;
2209 for (j
= 0; j
< ins
->operands
; j
++) {
2210 if (!(MEMORY
& ~ins
->oprs
[j
].type
)) {
2213 /* Verify as Register */
2214 if (ins
->oprs
[j
].indexreg
< EXPR_REG_START
2215 || ins
->oprs
[j
].indexreg
>= REG_ENUM_LIMIT
)
2218 i
= reg_flags
[ins
->oprs
[j
].indexreg
];
2220 /* Verify as Register */
2221 if (ins
->oprs
[j
].basereg
< EXPR_REG_START
2222 || ins
->oprs
[j
].basereg
>= REG_ENUM_LIMIT
)
2225 b
= reg_flags
[ins
->oprs
[j
].basereg
];
2227 if (ins
->oprs
[j
].scale
== 0)
2231 int ds
= ins
->oprs
[j
].disp_size
;
2232 if ((addrbits
!= 64 && ds
> 8) ||
2233 (addrbits
== 64 && ds
== 16))
2253 if (valid
& addrbits
) {
2254 ins
->addr_size
= addrbits
;
2255 } else if (valid
& ((addrbits
== 32) ? 16 : 32)) {
2256 /* Add an address size prefix */
2257 enum prefixes pref
= (addrbits
== 32) ? P_A16
: P_A32
;
2258 ins
->prefixes
[PPS_ASIZE
] = pref
;
2259 ins
->addr_size
= (addrbits
== 32) ? 16 : 32;
2262 errfunc(ERR_NONFATAL
, "impossible combination of address sizes");
2263 ins
->addr_size
= addrbits
; /* Error recovery */
2266 defdisp
= ins
->addr_size
== 16 ? 16 : 32;
2268 for (j
= 0; j
< ins
->operands
; j
++) {
2269 if (!(MEM_OFFS
& ~ins
->oprs
[j
].type
) &&
2270 (ins
->oprs
[j
].disp_size
? ins
->oprs
[j
].disp_size
: defdisp
)
2271 != ins
->addr_size
) {
2272 /* mem_offs sizes must match the address size; if not,
2273 strip the MEM_OFFS bit and match only EA instructions */
2274 ins
->oprs
[j
].type
&= ~(MEM_OFFS
& ~MEMORY
);