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AVX-512: Add OPMASK instructions
[nasm.git] / assemble.c
blob6ea8be65b2fedd4e5ebfa1517945b8d1f97916e7
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2013 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \20..\23 - a byte immediate operand, from operand 0..3
46 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
47 * \30..\33 - a word immediate operand, from operand 0..3
48 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
49 * assembly mode or the operand-size override on the operand
50 * \40..\43 - a long immediate operand, from operand 0..3
51 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
52 * depending on the address size of the instruction.
53 * \50..\53 - a byte relative operand, from operand 0..3
54 * \54..\57 - a qword immediate operand, from operand 0..3
55 * \60..\63 - a word relative operand, from operand 0..3
56 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
57 * assembly mode or the operand-size override on the operand
58 * \70..\73 - a long relative operand, from operand 0..3
59 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
60 * \1ab - a ModRM, calculated on EA in operand a, with the spare
61 * field the register value of operand b.
62 * \172\ab - the register number from operand a in bits 7..4, with
63 * the 4-bit immediate from operand b in bits 3..0.
64 * \173\xab - the register number from operand a in bits 7..4, with
65 * the value b in bits 3..0.
66 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
67 * an arbitrary value in bits 3..0 (assembled as zero.)
68 * \2ab - a ModRM, calculated on EA in operand a, with the spare
69 * field equal to digit b.
70 *
71 * \240..\243 - this instruction uses EVEX rather than REX or VEX/XOP, with the
72 * V field taken from operand 0..3.
73 * \250 - this instruction uses EVEX rather than REX or VEX/XOP, with the
74 * V field set to 1111b.
75 * EVEX prefixes are followed by the sequence:
76 * \cm\wlp\tup where cm is:
77 * cc 000 0mm
78 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
79 * and wlp is:
80 * 00 wwl lpp
81 * [l0] ll = 0 (.128, .lz)
82 * [l1] ll = 1 (.256)
83 * [l2] ll = 2 (.512)
84 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
85 *
86 * [w0] ww = 0 for W = 0
87 * [w1] ww = 1 for W = 1
88 * [wig] ww = 2 for W don't care (always assembled as 0)
89 * [ww] ww = 3 for W used as REX.W
90 *
91 * [p0] pp = 0 for no prefix
92 * [60] pp = 1 for legacy prefix 60
93 * [f3] pp = 2
94 * [f2] pp = 3
95 *
96 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
97 * (compressed displacement encoding)
98 *
99 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
100 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
101 * V field taken from operand 0..3.
102 * \270 - this instruction uses VEX/XOP rather than REX, with the
103 * V field set to 1111b.
104 *
105 * VEX/XOP prefixes are followed by the sequence:
106 * \tmm\wlp where mm is the M field; and wlp is:
107 * 00 wwl lpp
108 * [l0] ll = 0 for L = 0 (.128, .lz)
109 * [l1] ll = 1 for L = 1 (.256)
110 * [lig] ll = 2 for L don't care (always assembled as 0)
111 *
112 * [w0] ww = 0 for W = 0
113 * [w1 ] ww = 1 for W = 1
114 * [wig] ww = 2 for W don't care (always assembled as 0)
115 * [ww] ww = 3 for W used as REX.W
116 *
117 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
118 *
119 * \271 - instruction takes XRELEASE (F3) with or without lock
120 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
121 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
122 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
123 * to the operand size (if o16/o32/o64 present) or the bit size
124 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
125 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
126 * \312 - (disassembler only) invalid with non-default address size.
127 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
128 * \314 - (disassembler only) invalid with REX.B
129 * \315 - (disassembler only) invalid with REX.X
130 * \316 - (disassembler only) invalid with REX.R
131 * \317 - (disassembler only) invalid with REX.W
132 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
133 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
134 * \322 - indicates that this instruction is only valid when the
135 * operand size is the default (instruction to disassembler,
136 * generates no code in the assembler)
137 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
138 * \324 - indicates 64-bit operand size requiring REX prefix.
139 * \325 - instruction which always uses spl/bpl/sil/dil
140 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
141 disassembler only; for SSE instructions.
142 * \330 - a literal byte follows in the code stream, to be added
143 * to the condition code value of the instruction.
144 * \331 - instruction not valid with REP prefix. Hint for
145 * disassembler only; for SSE instructions.
146 * \332 - REP prefix (0xF2 byte) used as opcode extension.
147 * \333 - REP prefix (0xF3 byte) used as opcode extension.
148 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
149 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
150 * \336 - force a REP(E) prefix (0xF3) even if not specified.
151 * \337 - force a REPNE prefix (0xF2) even if not specified.
152 * \336-\337 are still listed as prefixes in the disassembler.
153 * \340 - reserve <operand 0> bytes of uninitialized storage.
154 * Operand 0 had better be a segmentless constant.
155 * \341 - this instruction needs a WAIT "prefix"
156 * \360 - no SSE prefix (== \364\331)
157 * \361 - 66 SSE prefix (== \366\331)
158 * \364 - operand-size prefix (0x66) not permitted
159 * \365 - address-size prefix (0x67) not permitted
160 * \366 - operand-size prefix (0x66) used as opcode extension
161 * \367 - address-size prefix (0x67) used as opcode extension
162 * \370,\371 - match only if operand 0 meets byte jump criteria.
163 * 370 is used for Jcc, 371 is used for JMP.
164 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
165 * used for conditional jump over longer jump
166 * \374 - this instruction takes an XMM VSIB memory EA
167 * \375 - this instruction takes an YMM VSIB memory EA
168 * \376 - this instruction takes an ZMM VSIB memory EA
169 */
170
171 #include "compiler.h"
172
173 #include <stdio.h>
174 #include <string.h>
175 #include <inttypes.h>
176
177 #include "nasm.h"
178 #include "nasmlib.h"
179 #include "assemble.h"
180 #include "insns.h"
181 #include "tables.h"
182
183 enum match_result {
184 /*
185 * Matching errors. These should be sorted so that more specific
186 * errors come later in the sequence.
187 */
188 MERR_INVALOP,
189 MERR_OPSIZEMISSING,
190 MERR_OPSIZEMISMATCH,
191 MERR_BADCPU,
192 MERR_BADMODE,
193 MERR_BADHLE,
194 MERR_ENCMISMATCH,
195 /*
196 * Matching success; the conditional ones first
197 */
198 MOK_JUMP, /* Matching OK but needs jmp_match() */
199 MOK_GOOD /* Matching unconditionally OK */
200 };
201
202 typedef struct {
203 enum ea_type type; /* what kind of EA is this? */
204 int sib_present; /* is a SIB byte necessary? */
205 int bytes; /* # of bytes of offset needed */
206 int size; /* lazy - this is sib+bytes+1 */
207 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
208 int8_t disp8; /* compressed displacement for EVEX */
209 } ea;
210
211 #define GEN_SIB(scale, index, base) \
212 (((scale) << 6) | ((index) << 3) | ((base)))
213
214 #define GEN_MODRM(mod, reg, rm) \
215 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
216
217 static iflags_t cpu; /* cpu level received from nasm.c */
218 static efunc errfunc;
219 static struct ofmt *outfmt;
220 static ListGen *list;
221
222 static int64_t calcsize(int32_t, int64_t, int, insn *,
223 const struct itemplate *);
224 static void gencode(int32_t segment, int64_t offset, int bits,
225 insn * ins, const struct itemplate *temp,
226 int64_t insn_end);
227 static enum match_result find_match(const struct itemplate **tempp,
228 insn *instruction,
229 int32_t segment, int64_t offset, int bits);
230 static enum match_result matches(const struct itemplate *, insn *, int bits);
231 static opflags_t regflag(const operand *);
232 static int32_t regval(const operand *);
233 static int rexflags(int, opflags_t, int);
234 static int op_rexflags(const operand *, int);
235 static int op_evexflags(const operand *, int, uint8_t);
236 static void add_asp(insn *, int);
237
238 static enum ea_type process_ea(operand *, ea *, int, int, opflags_t, insn *);
239
240 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
241 {
242 return ins->prefixes[pos] == prefix;
243 }
244
245 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
246 {
247 if (ins->prefixes[pos])
248 errfunc(ERR_NONFATAL, "invalid %s prefix",
249 prefix_name(ins->prefixes[pos]));
250 }
251
252 static const char *size_name(int size)
253 {
254 switch (size) {
255 case 1:
256 return "byte";
257 case 2:
258 return "word";
259 case 4:
260 return "dword";
261 case 8:
262 return "qword";
263 case 10:
264 return "tword";
265 case 16:
266 return "oword";
267 case 32:
268 return "yword";
269 case 64:
270 return "zword";
271 default:
272 return "???";
273 }
274 }
275
276 static void warn_overflow(int pass, int size)
277 {
278 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
279 "%s data exceeds bounds", size_name(size));
280 }
281
282 static void warn_overflow_const(int64_t data, int size)
283 {
284 if (overflow_general(data, size))
285 warn_overflow(ERR_PASS1, size);
286 }
287
288 static void warn_overflow_opd(const struct operand *o, int size)
289 {
290 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
291 if (overflow_general(o->offset, size))
292 warn_overflow(ERR_PASS2, size);
293 }
294 }
295
296 /*
297 * This routine wrappers the real output format's output routine,
298 * in order to pass a copy of the data off to the listing file
299 * generator at the same time.
300 */
301 static void out(int64_t offset, int32_t segto, const void *data,
302 enum out_type type, uint64_t size,
303 int32_t segment, int32_t wrt)
304 {
305 static int32_t lineno = 0; /* static!!! */
306 static char *lnfname = NULL;
307 uint8_t p[8];
308
309 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
310 /*
311 * This is a non-relocated address, and we're going to
312 * convert it into RAWDATA format.
313 */
314 uint8_t *q = p;
315
316 if (size > 8) {
317 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
318 return;
319 }
320
321 WRITEADDR(q, *(int64_t *)data, size);
322 data = p;
323 type = OUT_RAWDATA;
324 }
325
326 list->output(offset, data, type, size);
327
328 /*
329 * this call to src_get determines when we call the
330 * debug-format-specific "linenum" function
331 * it updates lineno and lnfname to the current values
332 * returning 0 if "same as last time", -2 if lnfname
333 * changed, and the amount by which lineno changed,
334 * if it did. thus, these variables must be static
335 */
336
337 if (src_get(&lineno, &lnfname))
338 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
339
340 outfmt->output(segto, data, type, size, segment, wrt);
341 }
342
343 static void out_imm8(int64_t offset, int32_t segment, struct operand *opx)
344 {
345 if (opx->segment != NO_SEG) {
346 uint64_t data = opx->offset;
347 out(offset, segment, &data, OUT_ADDRESS, 1, opx->segment, opx->wrt);
348 } else {
349 uint8_t byte = opx->offset;
350 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
351 }
352 }
353
354 static bool jmp_match(int32_t segment, int64_t offset, int bits,
355 insn * ins, const struct itemplate *temp)
356 {
357 int64_t isize;
358 const uint8_t *code = temp->code;
359 uint8_t c = code[0];
360
361 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
362 return false;
363 if (!optimizing)
364 return false;
365 if (optimizing < 0 && c == 0371)
366 return false;
367
368 isize = calcsize(segment, offset, bits, ins, temp);
369
370 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
371 /* Be optimistic in pass 1 */
372 return true;
373
374 if (ins->oprs[0].segment != segment)
375 return false;
376
377 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
378 return (isize >= -128 && isize <= 127); /* is it byte size? */
379 }
380
381 int64_t assemble(int32_t segment, int64_t offset, int bits, iflags_t cp,
382 insn * instruction, struct ofmt *output, efunc error,
383 ListGen * listgen)
384 {
385 const struct itemplate *temp;
386 int j;
387 enum match_result m;
388 int64_t insn_end;
389 int32_t itimes;
390 int64_t start = offset;
391 int64_t wsize; /* size for DB etc. */
392
393 errfunc = error; /* to pass to other functions */
394 cpu = cp;
395 outfmt = output; /* likewise */
396 list = listgen; /* and again */
397
398 wsize = idata_bytes(instruction->opcode);
399 if (wsize == -1)
400 return 0;
401
402 if (wsize) {
403 extop *e;
404 int32_t t = instruction->times;
405 if (t < 0)
406 errfunc(ERR_PANIC,
407 "instruction->times < 0 (%ld) in assemble()", t);
408
409 while (t--) { /* repeat TIMES times */
410 list_for_each(e, instruction->eops) {
411 if (e->type == EOT_DB_NUMBER) {
412 if (wsize > 8) {
413 errfunc(ERR_NONFATAL,
414 "integer supplied to a DT, DO or DY"
415 " instruction");
416 } else {
417 out(offset, segment, &e->offset,
418 OUT_ADDRESS, wsize, e->segment, e->wrt);
419 offset += wsize;
420 }
421 } else if (e->type == EOT_DB_STRING ||
422 e->type == EOT_DB_STRING_FREE) {
423 int align;
424
425 out(offset, segment, e->stringval,
426 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
427 align = e->stringlen % wsize;
428
429 if (align) {
430 align = wsize - align;
431 out(offset, segment, zero_buffer,
432 OUT_RAWDATA, align, NO_SEG, NO_SEG);
433 }
434 offset += e->stringlen + align;
435 }
436 }
437 if (t > 0 && t == instruction->times - 1) {
438 /*
439 * Dummy call to list->output to give the offset to the
440 * listing module.
441 */
442 list->output(offset, NULL, OUT_RAWDATA, 0);
443 list->uplevel(LIST_TIMES);
444 }
445 }
446 if (instruction->times > 1)
447 list->downlevel(LIST_TIMES);
448 return offset - start;
449 }
450
451 if (instruction->opcode == I_INCBIN) {
452 const char *fname = instruction->eops->stringval;
453 FILE *fp;
454
455 fp = fopen(fname, "rb");
456 if (!fp) {
457 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
458 fname);
459 } else if (fseek(fp, 0L, SEEK_END) < 0) {
460 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
461 fname);
462 fclose(fp);
463 } else {
464 static char buf[4096];
465 size_t t = instruction->times;
466 size_t base = 0;
467 size_t len;
468
469 len = ftell(fp);
470 if (instruction->eops->next) {
471 base = instruction->eops->next->offset;
472 len -= base;
473 if (instruction->eops->next->next &&
474 len > (size_t)instruction->eops->next->next->offset)
475 len = (size_t)instruction->eops->next->next->offset;
476 }
477 /*
478 * Dummy call to list->output to give the offset to the
479 * listing module.
480 */
481 list->output(offset, NULL, OUT_RAWDATA, 0);
482 list->uplevel(LIST_INCBIN);
483 while (t--) {
484 size_t l;
485
486 fseek(fp, base, SEEK_SET);
487 l = len;
488 while (l > 0) {
489 int32_t m;
490 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
491 if (!m) {
492 /*
493 * This shouldn't happen unless the file
494 * actually changes while we are reading
495 * it.
496 */
497 error(ERR_NONFATAL,
498 "`incbin': unexpected EOF while"
499 " reading file `%s'", fname);
500 t = 0; /* Try to exit cleanly */
501 break;
502 }
503 out(offset, segment, buf, OUT_RAWDATA, m,
504 NO_SEG, NO_SEG);
505 l -= m;
506 }
507 }
508 list->downlevel(LIST_INCBIN);
509 if (instruction->times > 1) {
510 /*
511 * Dummy call to list->output to give the offset to the
512 * listing module.
513 */
514 list->output(offset, NULL, OUT_RAWDATA, 0);
515 list->uplevel(LIST_TIMES);
516 list->downlevel(LIST_TIMES);
517 }
518 fclose(fp);
519 return instruction->times * len;
520 }
521 return 0; /* if we're here, there's an error */
522 }
523
524 /* Check to see if we need an address-size prefix */
525 add_asp(instruction, bits);
526
527 m = find_match(&temp, instruction, segment, offset, bits);
528
529 if (m == MOK_GOOD) {
530 /* Matches! */
531 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
532 itimes = instruction->times;
533 if (insn_size < 0) /* shouldn't be, on pass two */
534 error(ERR_PANIC, "errors made it through from pass one");
535 else
536 while (itimes--) {
537 for (j = 0; j < MAXPREFIX; j++) {
538 uint8_t c = 0;
539 switch (instruction->prefixes[j]) {
540 case P_WAIT:
541 c = 0x9B;
542 break;
543 case P_LOCK:
544 c = 0xF0;
545 break;
546 case P_REPNE:
547 case P_REPNZ:
548 case P_XACQUIRE:
549 c = 0xF2;
550 break;
551 case P_REPE:
552 case P_REPZ:
553 case P_REP:
554 case P_XRELEASE:
555 c = 0xF3;
556 break;
557 case R_CS:
558 if (bits == 64) {
559 error(ERR_WARNING | ERR_PASS2,
560 "cs segment base generated, but will be ignored in 64-bit mode");
561 }
562 c = 0x2E;
563 break;
564 case R_DS:
565 if (bits == 64) {
566 error(ERR_WARNING | ERR_PASS2,
567 "ds segment base generated, but will be ignored in 64-bit mode");
568 }
569 c = 0x3E;
570 break;
571 case R_ES:
572 if (bits == 64) {
573 error(ERR_WARNING | ERR_PASS2,
574 "es segment base generated, but will be ignored in 64-bit mode");
575 }
576 c = 0x26;
577 break;
578 case R_FS:
579 c = 0x64;
580 break;
581 case R_GS:
582 c = 0x65;
583 break;
584 case R_SS:
585 if (bits == 64) {
586 error(ERR_WARNING | ERR_PASS2,
587 "ss segment base generated, but will be ignored in 64-bit mode");
588 }
589 c = 0x36;
590 break;
591 case R_SEGR6:
592 case R_SEGR7:
593 error(ERR_NONFATAL,
594 "segr6 and segr7 cannot be used as prefixes");
595 break;
596 case P_A16:
597 if (bits == 64) {
598 error(ERR_NONFATAL,
599 "16-bit addressing is not supported "
600 "in 64-bit mode");
601 } else if (bits != 16)
602 c = 0x67;
603 break;
604 case P_A32:
605 if (bits != 32)
606 c = 0x67;
607 break;
608 case P_A64:
609 if (bits != 64) {
610 error(ERR_NONFATAL,
611 "64-bit addressing is only supported "
612 "in 64-bit mode");
613 }
614 break;
615 case P_ASP:
616 c = 0x67;
617 break;
618 case P_O16:
619 if (bits != 16)
620 c = 0x66;
621 break;
622 case P_O32:
623 if (bits == 16)
624 c = 0x66;
625 break;
626 case P_O64:
627 /* REX.W */
628 break;
629 case P_OSP:
630 c = 0x66;
631 break;
632 case P_none:
633 break;
634 default:
635 error(ERR_PANIC, "invalid instruction prefix");
636 }
637 if (c != 0) {
638 out(offset, segment, &c, OUT_RAWDATA, 1,
639 NO_SEG, NO_SEG);
640 offset++;
641 }
642 }
643 insn_end = offset + insn_size;
644 gencode(segment, offset, bits, instruction,
645 temp, insn_end);
646 offset += insn_size;
647 if (itimes > 0 && itimes == instruction->times - 1) {
648 /*
649 * Dummy call to list->output to give the offset to the
650 * listing module.
651 */
652 list->output(offset, NULL, OUT_RAWDATA, 0);
653 list->uplevel(LIST_TIMES);
654 }
655 }
656 if (instruction->times > 1)
657 list->downlevel(LIST_TIMES);
658 return offset - start;
659 } else {
660 /* No match */
661 switch (m) {
662 case MERR_OPSIZEMISSING:
663 error(ERR_NONFATAL, "operation size not specified");
664 break;
665 case MERR_OPSIZEMISMATCH:
666 error(ERR_NONFATAL, "mismatch in operand sizes");
667 break;
668 case MERR_BADCPU:
669 error(ERR_NONFATAL, "no instruction for this cpu level");
670 break;
671 case MERR_BADMODE:
672 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
673 bits);
674 break;
675 default:
676 error(ERR_NONFATAL,
677 "invalid combination of opcode and operands");
678 break;
679 }
680 }
681 return 0;
682 }
683
684 int64_t insn_size(int32_t segment, int64_t offset, int bits, iflags_t cp,
685 insn * instruction, efunc error)
686 {
687 const struct itemplate *temp;
688 enum match_result m;
689
690 errfunc = error; /* to pass to other functions */
691 cpu = cp;
692
693 if (instruction->opcode == I_none)
694 return 0;
695
696 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
697 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
698 instruction->opcode == I_DT || instruction->opcode == I_DO ||
699 instruction->opcode == I_DY) {
700 extop *e;
701 int32_t isize, osize, wsize;
702
703 isize = 0;
704 wsize = idata_bytes(instruction->opcode);
705
706 list_for_each(e, instruction->eops) {
707 int32_t align;
708
709 osize = 0;
710 if (e->type == EOT_DB_NUMBER) {
711 osize = 1;
712 warn_overflow_const(e->offset, wsize);
713 } else if (e->type == EOT_DB_STRING ||
714 e->type == EOT_DB_STRING_FREE)
715 osize = e->stringlen;
716
717 align = (-osize) % wsize;
718 if (align < 0)
719 align += wsize;
720 isize += osize + align;
721 }
722 return isize * instruction->times;
723 }
724
725 if (instruction->opcode == I_INCBIN) {
726 const char *fname = instruction->eops->stringval;
727 FILE *fp;
728 int64_t val = 0;
729 size_t len;
730
731 fp = fopen(fname, "rb");
732 if (!fp)
733 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
734 fname);
735 else if (fseek(fp, 0L, SEEK_END) < 0)
736 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
737 fname);
738 else {
739 len = ftell(fp);
740 if (instruction->eops->next) {
741 len -= instruction->eops->next->offset;
742 if (instruction->eops->next->next &&
743 len > (size_t)instruction->eops->next->next->offset) {
744 len = (size_t)instruction->eops->next->next->offset;
745 }
746 }
747 val = instruction->times * len;
748 }
749 if (fp)
750 fclose(fp);
751 return val;
752 }
753
754 /* Check to see if we need an address-size prefix */
755 add_asp(instruction, bits);
756
757 m = find_match(&temp, instruction, segment, offset, bits);
758 if (m == MOK_GOOD) {
759 /* we've matched an instruction. */
760 int64_t isize;
761 int j;
762
763 isize = calcsize(segment, offset, bits, instruction, temp);
764 if (isize < 0)
765 return -1;
766 for (j = 0; j < MAXPREFIX; j++) {
767 switch (instruction->prefixes[j]) {
768 case P_A16:
769 if (bits != 16)
770 isize++;
771 break;
772 case P_A32:
773 if (bits != 32)
774 isize++;
775 break;
776 case P_O16:
777 if (bits != 16)
778 isize++;
779 break;
780 case P_O32:
781 if (bits == 16)
782 isize++;
783 break;
784 case P_A64:
785 case P_O64:
786 case P_none:
787 break;
788 default:
789 isize++;
790 break;
791 }
792 }
793 return isize * instruction->times;
794 } else {
795 return -1; /* didn't match any instruction */
796 }
797 }
798
799 static void bad_hle_warn(const insn * ins, uint8_t hleok)
800 {
801 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
802 enum whatwarn { w_none, w_lock, w_inval } ww;
803 static const enum whatwarn warn[2][4] =
804 {
805 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
806 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
807 };
808 unsigned int n;
809
810 n = (unsigned int)rep_pfx - P_XACQUIRE;
811 if (n > 1)
812 return; /* Not XACQUIRE/XRELEASE */
813
814 ww = warn[n][hleok];
815 if (!is_class(MEMORY, ins->oprs[0].type))
816 ww = w_inval; /* HLE requires operand 0 to be memory */
817
818 switch (ww) {
819 case w_none:
820 break;
821
822 case w_lock:
823 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
824 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
825 "%s with this instruction requires lock",
826 prefix_name(rep_pfx));
827 }
828 break;
829
830 case w_inval:
831 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
832 "%s invalid with this instruction",
833 prefix_name(rep_pfx));
834 break;
835 }
836 }
837
838 /* Common construct */
839 #define case3(x) case (x): case (x)+1: case (x)+2
840 #define case4(x) case3(x): case (x)+3
841
842 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
843 insn * ins, const struct itemplate *temp)
844 {
845 const uint8_t *codes = temp->code;
846 int64_t length = 0;
847 uint8_t c;
848 int rex_mask = ~0;
849 int op1, op2;
850 struct operand *opx;
851 uint8_t opex = 0;
852 enum ea_type eat;
853 uint8_t hleok = 0;
854 bool lockcheck = true;
855
856 ins->rex = 0; /* Ensure REX is reset */
857 eat = EA_SCALAR; /* Expect a scalar EA */
858 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
859
860 if (ins->prefixes[PPS_OSIZE] == P_O64)
861 ins->rex |= REX_W;
862
863 (void)segment; /* Don't warn that this parameter is unused */
864 (void)offset; /* Don't warn that this parameter is unused */
865
866 while (*codes) {
867 c = *codes++;
868 op1 = (c & 3) + ((opex & 1) << 2);
869 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
870 opx = &ins->oprs[op1];
871 opex = 0; /* For the next iteration */
872
873 switch (c) {
874 case4(01):
875 codes += c, length += c;
876 break;
877
878 case3(05):
879 opex = c;
880 break;
881
882 case4(010):
883 ins->rex |=
884 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
885 codes++, length++;
886 break;
887
888 case4(020):
889 case4(024):
890 length++;
891 break;
892
893 case4(030):
894 length += 2;
895 break;
896
897 case4(034):
898 if (opx->type & (BITS16 | BITS32 | BITS64))
899 length += (opx->type & BITS16) ? 2 : 4;
900 else
901 length += (bits == 16) ? 2 : 4;
902 break;
903
904 case4(040):
905 length += 4;
906 break;
907
908 case4(044):
909 length += ins->addr_size >> 3;
910 break;
911
912 case4(050):
913 length++;
914 break;
915
916 case4(054):
917 length += 8; /* MOV reg64/imm */
918 break;
919
920 case4(060):
921 length += 2;
922 break;
923
924 case4(064):
925 if (opx->type & (BITS16 | BITS32 | BITS64))
926 length += (opx->type & BITS16) ? 2 : 4;
927 else
928 length += (bits == 16) ? 2 : 4;
929 break;
930
931 case4(070):
932 length += 4;
933 break;
934
935 case4(074):
936 length += 2;
937 break;
938
939 case 0172:
940 case 0173:
941 codes++;
942 length++;
943 break;
944
945 case4(0174):
946 length++;
947 break;
948
949 case4(0240):
950 ins->rex |= REX_EV;
951 ins->vexreg = regval(opx);
952 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
953 ins->vex_cm = *codes++;
954 ins->vex_wlp = *codes++;
955 ins->evex_tuple = (*codes++ - 0300);
956 break;
957
958 case 0250:
959 ins->rex |= REX_EV;
960 ins->vexreg = 0;
961 ins->vex_cm = *codes++;
962 ins->vex_wlp = *codes++;
963 ins->evex_tuple = (*codes++ - 0300);
964 break;
965
966 case4(0254):
967 length += 4;
968 break;
969
970 case4(0260):
971 ins->rex |= REX_V;
972 ins->vexreg = regval(opx);
973 ins->vex_cm = *codes++;
974 ins->vex_wlp = *codes++;
975 break;
976
977 case 0270:
978 ins->rex |= REX_V;
979 ins->vexreg = 0;
980 ins->vex_cm = *codes++;
981 ins->vex_wlp = *codes++;
982 break;
983
984 case3(0271):
985 hleok = c & 3;
986 break;
987
988 case4(0274):
989 length++;
990 break;
991
992 case4(0300):
993 break;
994
995 case 0310:
996 if (bits == 64)
997 return -1;
998 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
999 break;
1000
1001 case 0311:
1002 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1003 break;
1004
1005 case 0312:
1006 break;
1007
1008 case 0313:
1009 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1010 has_prefix(ins, PPS_ASIZE, P_A32))
1011 return -1;
1012 break;
1013
1014 case4(0314):
1015 break;
1016
1017 case 0320:
1018 {
1019 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1020 if (pfx == P_O16)
1021 break;
1022 if (pfx != P_none)
1023 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1024 else
1025 ins->prefixes[PPS_OSIZE] = P_O16;
1026 break;
1027 }
1028
1029 case 0321:
1030 {
1031 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1032 if (pfx == P_O32)
1033 break;
1034 if (pfx != P_none)
1035 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1036 else
1037 ins->prefixes[PPS_OSIZE] = P_O32;
1038 break;
1039 }
1040
1041 case 0322:
1042 break;
1043
1044 case 0323:
1045 rex_mask &= ~REX_W;
1046 break;
1047
1048 case 0324:
1049 ins->rex |= REX_W;
1050 break;
1051
1052 case 0325:
1053 ins->rex |= REX_NH;
1054 break;
1055
1056 case 0326:
1057 break;
1058
1059 case 0330:
1060 codes++, length++;
1061 break;
1062
1063 case 0331:
1064 break;
1065
1066 case 0332:
1067 case 0333:
1068 length++;
1069 break;
1070
1071 case 0334:
1072 ins->rex |= REX_L;
1073 break;
1074
1075 case 0335:
1076 break;
1077
1078 case 0336:
1079 if (!ins->prefixes[PPS_REP])
1080 ins->prefixes[PPS_REP] = P_REP;
1081 break;
1082
1083 case 0337:
1084 if (!ins->prefixes[PPS_REP])
1085 ins->prefixes[PPS_REP] = P_REPNE;
1086 break;
1087
1088 case 0340:
1089 if (ins->oprs[0].segment != NO_SEG)
1090 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1091 " quantity of BSS space");
1092 else
1093 length += ins->oprs[0].offset;
1094 break;
1095
1096 case 0341:
1097 if (!ins->prefixes[PPS_WAIT])
1098 ins->prefixes[PPS_WAIT] = P_WAIT;
1099 break;
1100
1101 case 0360:
1102 break;
1103
1104 case 0361:
1105 length++;
1106 break;
1107
1108 case 0364:
1109 case 0365:
1110 break;
1111
1112 case 0366:
1113 case 0367:
1114 length++;
1115 break;
1116
1117 case3(0370):
1118 break;
1119
1120 case 0373:
1121 length++;
1122 break;
1123
1124 case 0374:
1125 eat = EA_XMMVSIB;
1126 break;
1127
1128 case 0375:
1129 eat = EA_YMMVSIB;
1130 break;
1131
1132 case 0376:
1133 eat = EA_ZMMVSIB;
1134 break;
1135
1136 case4(0100):
1137 case4(0110):
1138 case4(0120):
1139 case4(0130):
1140 case4(0200):
1141 case4(0204):
1142 case4(0210):
1143 case4(0214):
1144 case4(0220):
1145 case4(0224):
1146 case4(0230):
1147 case4(0234):
1148 {
1149 ea ea_data;
1150 int rfield;
1151 opflags_t rflags;
1152 struct operand *opy = &ins->oprs[op2];
1153 struct operand *op_er_sae;
1154
1155 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1156
1157 if (c <= 0177) {
1158 /* pick rfield from operand b (opx) */
1159 rflags = regflag(opx);
1160 rfield = nasm_regvals[opx->basereg];
1161 } else {
1162 rflags = 0;
1163 rfield = c & 7;
1164 }
1165
1166 /* EVEX.b1 : evex_brerop contains the operand position */
1167 op_er_sae = (ins->evex_brerop >= 0 ?
1168 &ins->oprs[ins->evex_brerop] : NULL);
1169
1170 if (op_er_sae && (op_er_sae->decoflags & ER)) {
1171 /* set EVEX.RC (rounding control) and b */
1172 ins->evex_p[2] |= (((ins->evex_rm - BRC_RN) << 5) & EVEX_P2LL) |
1173 EVEX_P2B;
1174 } else {
1175 /* set EVEX.L'L (vector length) */
1176 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1177 if ((op_er_sae && (op_er_sae->decoflags & SAE)) ||
1178 (opy->decoflags & BRDCAST_MASK)) {
1179 /* set EVEX.b */
1180 ins->evex_p[2] |= EVEX_P2B;
1181 }
1182 }
1183
1184 if (process_ea(opy, &ea_data, bits,
1185 rfield, rflags, ins) != eat) {
1186 errfunc(ERR_NONFATAL, "invalid effective address");
1187 return -1;
1188 } else {
1189 ins->rex |= ea_data.rex;
1190 length += ea_data.size;
1191 }
1192 }
1193 break;
1194
1195 default:
1196 errfunc(ERR_PANIC, "internal instruction table corrupt"
1197 ": instruction code \\%o (0x%02X) given", c, c);
1198 break;
1199 }
1200 }
1201
1202 ins->rex &= rex_mask;
1203
1204 if (ins->rex & REX_NH) {
1205 if (ins->rex & REX_H) {
1206 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1207 return -1;
1208 }
1209 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1210 }
1211
1212 if (ins->rex & (REX_V | REX_EV)) {
1213 int bad32 = REX_R|REX_W|REX_X|REX_B;
1214
1215 if (ins->rex & REX_H) {
1216 errfunc(ERR_NONFATAL, "cannot use high register in AVX instruction");
1217 return -1;
1218 }
1219 switch (ins->vex_wlp & 060) {
1220 case 000:
1221 case 040:
1222 ins->rex &= ~REX_W;
1223 break;
1224 case 020:
1225 ins->rex |= REX_W;
1226 bad32 &= ~REX_W;
1227 break;
1228 case 060:
1229 /* Follow REX_W */
1230 break;
1231 }
1232
1233 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1234 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1235 return -1;
1236 } else if (!(ins->rex & REX_EV) &&
1237 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1238 errfunc(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1239 return -1;
1240 }
1241 if (ins->rex & REX_EV)
1242 length += 4;
1243 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1244 length += 3;
1245 else
1246 length += 2;
1247 } else if (ins->rex & REX_REAL) {
1248 if (ins->rex & REX_H) {
1249 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1250 return -1;
1251 } else if (bits == 64) {
1252 length++;
1253 } else if ((ins->rex & REX_L) &&
1254 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1255 cpu >= IF_X86_64) {
1256 /* LOCK-as-REX.R */
1257 assert_no_prefix(ins, PPS_LOCK);
1258 lockcheck = false; /* Already errored, no need for warning */
1259 length++;
1260 } else {
1261 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1262 return -1;
1263 }
1264 }
1265
1266 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1267 (!(temp->flags & IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1268 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1269 "instruction is not lockable");
1270 }
1271
1272 bad_hle_warn(ins, hleok);
1273
1274 return length;
1275 }
1276
1277 static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
1278 {
1279 if (bits == 64) {
1280 if ((ins->rex & REX_REAL) && !(ins->rex & (REX_V | REX_EV))) {
1281 ins->rex = (ins->rex & REX_REAL) | REX_P;
1282 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1283 ins->rex = 0;
1284 return 1;
1285 }
1286 }
1287
1288 return 0;
1289 }
1290
1291 static void gencode(int32_t segment, int64_t offset, int bits,
1292 insn * ins, const struct itemplate *temp,
1293 int64_t insn_end)
1294 {
1295 uint8_t c;
1296 uint8_t bytes[4];
1297 int64_t size;
1298 int64_t data;
1299 int op1, op2;
1300 struct operand *opx;
1301 const uint8_t *codes = temp->code;
1302 uint8_t opex = 0;
1303 enum ea_type eat = EA_SCALAR;
1304
1305 while (*codes) {
1306 c = *codes++;
1307 op1 = (c & 3) + ((opex & 1) << 2);
1308 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1309 opx = &ins->oprs[op1];
1310 opex = 0; /* For the next iteration */
1311
1312 switch (c) {
1313 case 01:
1314 case 02:
1315 case 03:
1316 case 04:
1317 offset += emit_rex(ins, segment, offset, bits);
1318 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1319 codes += c;
1320 offset += c;
1321 break;
1322
1323 case 05:
1324 case 06:
1325 case 07:
1326 opex = c;
1327 break;
1328
1329 case4(010):
1330 offset += emit_rex(ins, segment, offset, bits);
1331 bytes[0] = *codes++ + (regval(opx) & 7);
1332 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1333 offset += 1;
1334 break;
1335
1336 case4(020):
1337 if (opx->offset < -256 || opx->offset > 255) {
1338 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1339 "byte value exceeds bounds");
1340 }
1341 out_imm8(offset, segment, opx);
1342 offset += 1;
1343 break;
1344
1345 case4(024):
1346 if (opx->offset < 0 || opx->offset > 255)
1347 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1348 "unsigned byte value exceeds bounds");
1349 out_imm8(offset, segment, opx);
1350 offset += 1;
1351 break;
1352
1353 case4(030):
1354 warn_overflow_opd(opx, 2);
1355 data = opx->offset;
1356 out(offset, segment, &data, OUT_ADDRESS, 2,
1357 opx->segment, opx->wrt);
1358 offset += 2;
1359 break;
1360
1361 case4(034):
1362 if (opx->type & (BITS16 | BITS32))
1363 size = (opx->type & BITS16) ? 2 : 4;
1364 else
1365 size = (bits == 16) ? 2 : 4;
1366 warn_overflow_opd(opx, size);
1367 data = opx->offset;
1368 out(offset, segment, &data, OUT_ADDRESS, size,
1369 opx->segment, opx->wrt);
1370 offset += size;
1371 break;
1372
1373 case4(040):
1374 warn_overflow_opd(opx, 4);
1375 data = opx->offset;
1376 out(offset, segment, &data, OUT_ADDRESS, 4,
1377 opx->segment, opx->wrt);
1378 offset += 4;
1379 break;
1380
1381 case4(044):
1382 data = opx->offset;
1383 size = ins->addr_size >> 3;
1384 warn_overflow_opd(opx, size);
1385 out(offset, segment, &data, OUT_ADDRESS, size,
1386 opx->segment, opx->wrt);
1387 offset += size;
1388 break;
1389
1390 case4(050):
1391 if (opx->segment != segment) {
1392 data = opx->offset;
1393 out(offset, segment, &data,
1394 OUT_REL1ADR, insn_end - offset,
1395 opx->segment, opx->wrt);
1396 } else {
1397 data = opx->offset - insn_end;
1398 if (data > 127 || data < -128)
1399 errfunc(ERR_NONFATAL, "short jump is out of range");
1400 out(offset, segment, &data,
1401 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1402 }
1403 offset += 1;
1404 break;
1405
1406 case4(054):
1407 data = (int64_t)opx->offset;
1408 out(offset, segment, &data, OUT_ADDRESS, 8,
1409 opx->segment, opx->wrt);
1410 offset += 8;
1411 break;
1412
1413 case4(060):
1414 if (opx->segment != segment) {
1415 data = opx->offset;
1416 out(offset, segment, &data,
1417 OUT_REL2ADR, insn_end - offset,
1418 opx->segment, opx->wrt);
1419 } else {
1420 data = opx->offset - insn_end;
1421 out(offset, segment, &data,
1422 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1423 }
1424 offset += 2;
1425 break;
1426
1427 case4(064):
1428 if (opx->type & (BITS16 | BITS32 | BITS64))
1429 size = (opx->type & BITS16) ? 2 : 4;
1430 else
1431 size = (bits == 16) ? 2 : 4;
1432 if (opx->segment != segment) {
1433 data = opx->offset;
1434 out(offset, segment, &data,
1435 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1436 insn_end - offset, opx->segment, opx->wrt);
1437 } else {
1438 data = opx->offset - insn_end;
1439 out(offset, segment, &data,
1440 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1441 }
1442 offset += size;
1443 break;
1444
1445 case4(070):
1446 if (opx->segment != segment) {
1447 data = opx->offset;
1448 out(offset, segment, &data,
1449 OUT_REL4ADR, insn_end - offset,
1450 opx->segment, opx->wrt);
1451 } else {
1452 data = opx->offset - insn_end;
1453 out(offset, segment, &data,
1454 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1455 }
1456 offset += 4;
1457 break;
1458
1459 case4(074):
1460 if (opx->segment == NO_SEG)
1461 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1462 " relocatable");
1463 data = 0;
1464 out(offset, segment, &data, OUT_ADDRESS, 2,
1465 outfmt->segbase(1 + opx->segment),
1466 opx->wrt);
1467 offset += 2;
1468 break;
1469
1470 case 0172:
1471 c = *codes++;
1472 opx = &ins->oprs[c >> 3];
1473 bytes[0] = nasm_regvals[opx->basereg] << 4;
1474 opx = &ins->oprs[c & 7];
1475 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1476 errfunc(ERR_NONFATAL,
1477 "non-absolute expression not permitted as argument %d",
1478 c & 7);
1479 } else {
1480 if (opx->offset & ~15) {
1481 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1482 "four-bit argument exceeds bounds");
1483 }
1484 bytes[0] |= opx->offset & 15;
1485 }
1486 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1487 offset++;
1488 break;
1489
1490 case 0173:
1491 c = *codes++;
1492 opx = &ins->oprs[c >> 4];
1493 bytes[0] = nasm_regvals[opx->basereg] << 4;
1494 bytes[0] |= c & 15;
1495 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1496 offset++;
1497 break;
1498
1499 case4(0174):
1500 bytes[0] = nasm_regvals[opx->basereg] << 4;
1501 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1502 offset++;
1503 break;
1504
1505 case4(0254):
1506 data = opx->offset;
1507 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1508 (int32_t)data != (int64_t)data) {
1509 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1510 "signed dword immediate exceeds bounds");
1511 }
1512 out(offset, segment, &data, OUT_ADDRESS, 4,
1513 opx->segment, opx->wrt);
1514 offset += 4;
1515 break;
1516
1517 case4(0240):
1518 case 0250:
1519 codes += 3;
1520 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1521 EVEX_P2Z | EVEX_P2AAA, 2);
1522 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1523 bytes[0] = 0x62;
1524 /* EVEX.X can be set by either REX or EVEX for different reasons */
1525 bytes[1] = (~(((ins->rex & 7) << 5) |
1526 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) & 0xf0) |
1527 (ins->vex_cm & 3);
1528 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1529 ((~ins->vexreg & 15) << 3) |
1530 (1 << 2) | (ins->vex_wlp & 3);
1531 bytes[3] = ins->evex_p[2];
1532 out(offset, segment, &bytes, OUT_RAWDATA, 4, NO_SEG, NO_SEG);
1533 offset += 4;
1534 break;
1535
1536 case4(0260):
1537 case 0270:
1538 codes += 2;
1539 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1540 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1541 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1542 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1543 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1544 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1545 offset += 3;
1546 } else {
1547 bytes[0] = 0xc5;
1548 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1549 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1550 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1551 offset += 2;
1552 }
1553 break;
1554
1555 case 0271:
1556 case 0272:
1557 case 0273:
1558 break;
1559
1560 case4(0274):
1561 {
1562 uint64_t uv, um;
1563 int s;
1564
1565 if (ins->rex & REX_W)
1566 s = 64;
1567 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1568 s = 16;
1569 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1570 s = 32;
1571 else
1572 s = bits;
1573
1574 um = (uint64_t)2 << (s-1);
1575 uv = opx->offset;
1576
1577 if (uv > 127 && uv < (uint64_t)-128 &&
1578 (uv < um-128 || uv > um-1)) {
1579 /* If this wasn't explicitly byte-sized, warn as though we
1580 * had fallen through to the imm16/32/64 case.
1581 */
1582 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1583 "%s value exceeds bounds",
1584 (opx->type & BITS8) ? "signed byte" :
1585 s == 16 ? "word" :
1586 s == 32 ? "dword" :
1587 "signed dword");
1588 }
1589 if (opx->segment != NO_SEG) {
1590 data = uv;
1591 out(offset, segment, &data, OUT_ADDRESS, 1,
1592 opx->segment, opx->wrt);
1593 } else {
1594 bytes[0] = uv;
1595 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1596 NO_SEG);
1597 }
1598 offset += 1;
1599 break;
1600 }
1601
1602 case4(0300):
1603 break;
1604
1605 case 0310:
1606 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1607 *bytes = 0x67;
1608 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1609 offset += 1;
1610 } else
1611 offset += 0;
1612 break;
1613
1614 case 0311:
1615 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1616 *bytes = 0x67;
1617 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1618 offset += 1;
1619 } else
1620 offset += 0;
1621 break;
1622
1623 case 0312:
1624 break;
1625
1626 case 0313:
1627 ins->rex = 0;
1628 break;
1629
1630 case4(0314):
1631 break;
1632
1633 case 0320:
1634 case 0321:
1635 break;
1636
1637 case 0322:
1638 case 0323:
1639 break;
1640
1641 case 0324:
1642 ins->rex |= REX_W;
1643 break;
1644
1645 case 0325:
1646 break;
1647
1648 case 0326:
1649 break;
1650
1651 case 0330:
1652 *bytes = *codes++ ^ get_cond_opcode(ins->condition);
1653 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1654 offset += 1;
1655 break;
1656
1657 case 0331:
1658 break;
1659
1660 case 0332:
1661 case 0333:
1662 *bytes = c - 0332 + 0xF2;
1663 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1664 offset += 1;
1665 break;
1666
1667 case 0334:
1668 if (ins->rex & REX_R) {
1669 *bytes = 0xF0;
1670 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1671 offset += 1;
1672 }
1673 ins->rex &= ~(REX_L|REX_R);
1674 break;
1675
1676 case 0335:
1677 break;
1678
1679 case 0336:
1680 case 0337:
1681 break;
1682
1683 case 0340:
1684 if (ins->oprs[0].segment != NO_SEG)
1685 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1686 else {
1687 int64_t size = ins->oprs[0].offset;
1688 if (size > 0)
1689 out(offset, segment, NULL,
1690 OUT_RESERVE, size, NO_SEG, NO_SEG);
1691 offset += size;
1692 }
1693 break;
1694
1695 case 0341:
1696 break;
1697
1698 case 0360:
1699 break;
1700
1701 case 0361:
1702 bytes[0] = 0x66;
1703 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1704 offset += 1;
1705 break;
1706
1707 case 0364:
1708 case 0365:
1709 break;
1710
1711 case 0366:
1712 case 0367:
1713 *bytes = c - 0366 + 0x66;
1714 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1715 offset += 1;
1716 break;
1717
1718 case 0370:
1719 case 0371:
1720 break;
1721
1722 case 0373:
1723 *bytes = bits == 16 ? 3 : 5;
1724 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1725 offset += 1;
1726 break;
1727
1728 case 0374:
1729 eat = EA_XMMVSIB;
1730 break;
1731
1732 case 0375:
1733 eat = EA_YMMVSIB;
1734 break;
1735
1736 case 0376:
1737 eat = EA_ZMMVSIB;
1738 break;
1739
1740 case4(0100):
1741 case4(0110):
1742 case4(0120):
1743 case4(0130):
1744 case4(0200):
1745 case4(0204):
1746 case4(0210):
1747 case4(0214):
1748 case4(0220):
1749 case4(0224):
1750 case4(0230):
1751 case4(0234):
1752 {
1753 ea ea_data;
1754 int rfield;
1755 opflags_t rflags;
1756 uint8_t *p;
1757 int32_t s;
1758 struct operand *opy = &ins->oprs[op2];
1759
1760 if (c <= 0177) {
1761 /* pick rfield from operand b (opx) */
1762 rflags = regflag(opx);
1763 rfield = nasm_regvals[opx->basereg];
1764 } else {
1765 /* rfield is constant */
1766 rflags = 0;
1767 rfield = c & 7;
1768 }
1769
1770 if (process_ea(opy, &ea_data, bits,
1771 rfield, rflags, ins) != eat)
1772 errfunc(ERR_NONFATAL, "invalid effective address");
1773
1774 p = bytes;
1775 *p++ = ea_data.modrm;
1776 if (ea_data.sib_present)
1777 *p++ = ea_data.sib;
1778
1779 s = p - bytes;
1780 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1781
1782 /*
1783 * Make sure the address gets the right offset in case
1784 * the line breaks in the .lst file (BR 1197827)
1785 */
1786 offset += s;
1787 s = 0;
1788
1789 switch (ea_data.bytes) {
1790 case 0:
1791 break;
1792 case 1:
1793 case 2:
1794 case 4:
1795 case 8:
1796 /* use compressed displacement, if available */
1797 data = ea_data.disp8 ? ea_data.disp8 : opy->offset;
1798 s += ea_data.bytes;
1799 if (ea_data.rip) {
1800 if (opy->segment == segment) {
1801 data -= insn_end;
1802 if (overflow_signed(data, ea_data.bytes))
1803 warn_overflow(ERR_PASS2, ea_data.bytes);
1804 out(offset, segment, &data, OUT_ADDRESS,
1805 ea_data.bytes, NO_SEG, NO_SEG);
1806 } else {
1807 /* overflow check in output/linker? */
1808 out(offset, segment, &data, OUT_REL4ADR,
1809 insn_end - offset, opy->segment, opy->wrt);
1810 }
1811 } else {
1812 if (overflow_general(data, ins->addr_size >> 3) ||
1813 signed_bits(data, ins->addr_size) !=
1814 signed_bits(data, ea_data.bytes * 8))
1815 warn_overflow(ERR_PASS2, ea_data.bytes);
1816
1817 out(offset, segment, &data, OUT_ADDRESS,
1818 ea_data.bytes, opy->segment, opy->wrt);
1819 }
1820 break;
1821 default:
1822 /* Impossible! */
1823 errfunc(ERR_PANIC,
1824 "Invalid amount of bytes (%d) for offset?!",
1825 ea_data.bytes);
1826 break;
1827 }
1828 offset += s;
1829 }
1830 break;
1831
1832 default:
1833 errfunc(ERR_PANIC, "internal instruction table corrupt"
1834 ": instruction code \\%o (0x%02X) given", c, c);
1835 break;
1836 }
1837 }
1838 }
1839
1840 static opflags_t regflag(const operand * o)
1841 {
1842 if (!is_register(o->basereg))
1843 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1844 return nasm_reg_flags[o->basereg];
1845 }
1846
1847 static int32_t regval(const operand * o)
1848 {
1849 if (!is_register(o->basereg))
1850 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1851 return nasm_regvals[o->basereg];
1852 }
1853
1854 static int op_rexflags(const operand * o, int mask)
1855 {
1856 opflags_t flags;
1857 int val;
1858
1859 if (!is_register(o->basereg))
1860 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1861
1862 flags = nasm_reg_flags[o->basereg];
1863 val = nasm_regvals[o->basereg];
1864
1865 return rexflags(val, flags, mask);
1866 }
1867
1868 static int rexflags(int val, opflags_t flags, int mask)
1869 {
1870 int rex = 0;
1871
1872 if (val >= 8)
1873 rex |= REX_B|REX_X|REX_R;
1874 if (flags & BITS64)
1875 rex |= REX_W;
1876 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1877 rex |= REX_H;
1878 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1879 rex |= REX_P;
1880
1881 return rex & mask;
1882 }
1883
1884 static int evexflags(int val, decoflags_t deco,
1885 int mask, uint8_t byte)
1886 {
1887 int evex = 0;
1888
1889 switch(byte) {
1890 case 0:
1891 if (val >= 16)
1892 evex |= (EVEX_P0RP | EVEX_P0X);
1893 break;
1894 case 2:
1895 if (val >= 16)
1896 evex |= EVEX_P2VP;
1897 if (deco & Z)
1898 evex |= EVEX_P2Z;
1899 if (deco & OPMASK_MASK)
1900 evex |= deco & EVEX_P2AAA;
1901 break;
1902 }
1903 return evex & mask;
1904 }
1905
1906 static int op_evexflags(const operand * o, int mask, uint8_t byte)
1907 {
1908 int val;
1909
1910 if (!is_register(o->basereg))
1911 errfunc(ERR_PANIC, "invalid operand passed to op_evexflags()");
1912
1913 val = nasm_regvals[o->basereg];
1914
1915 return evexflags(val, o->decoflags, mask, byte);
1916 }
1917
1918 static enum match_result find_match(const struct itemplate **tempp,
1919 insn *instruction,
1920 int32_t segment, int64_t offset, int bits)
1921 {
1922 const struct itemplate *temp;
1923 enum match_result m, merr;
1924 opflags_t xsizeflags[MAX_OPERANDS];
1925 bool opsizemissing = false;
1926 int8_t broadcast = instruction->evex_brerop;
1927 int i;
1928
1929 /* broadcasting uses a different data element size */
1930 for (i = 0; i < instruction->operands; i++)
1931 if (i == broadcast)
1932 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
1933 else
1934 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1935
1936 merr = MERR_INVALOP;
1937
1938 for (temp = nasm_instructions[instruction->opcode];
1939 temp->opcode != I_none; temp++) {
1940 m = matches(temp, instruction, bits);
1941 if (m == MOK_JUMP) {
1942 if (jmp_match(segment, offset, bits, instruction, temp))
1943 m = MOK_GOOD;
1944 else
1945 m = MERR_INVALOP;
1946 } else if (m == MERR_OPSIZEMISSING &&
1947 (temp->flags & IF_SMASK) != IF_SX) {
1948 /*
1949 * Missing operand size and a candidate for fuzzy matching...
1950 */
1951 for (i = 0; i < temp->operands; i++)
1952 if (i == broadcast)
1953 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
1954 else
1955 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
1956 opsizemissing = true;
1957 }
1958 if (m > merr)
1959 merr = m;
1960 if (merr == MOK_GOOD)
1961 goto done;
1962 }
1963
1964 /* No match, but see if we can get a fuzzy operand size match... */
1965 if (!opsizemissing)
1966 goto done;
1967
1968 for (i = 0; i < instruction->operands; i++) {
1969 /*
1970 * We ignore extrinsic operand sizes on registers, so we should
1971 * never try to fuzzy-match on them. This also resolves the case
1972 * when we have e.g. "xmmrm128" in two different positions.
1973 */
1974 if (is_class(REGISTER, instruction->oprs[i].type))
1975 continue;
1976
1977 /* This tests if xsizeflags[i] has more than one bit set */
1978 if ((xsizeflags[i] & (xsizeflags[i]-1)))
1979 goto done; /* No luck */
1980
1981 if (i == broadcast)
1982 instruction->oprs[i].decoflags |= xsizeflags[i];
1983 else
1984 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
1985 }
1986
1987 /* Try matching again... */
1988 for (temp = nasm_instructions[instruction->opcode];
1989 temp->opcode != I_none; temp++) {
1990 m = matches(temp, instruction, bits);
1991 if (m == MOK_JUMP) {
1992 if (jmp_match(segment, offset, bits, instruction, temp))
1993 m = MOK_GOOD;
1994 else
1995 m = MERR_INVALOP;
1996 }
1997 if (m > merr)
1998 merr = m;
1999 if (merr == MOK_GOOD)
2000 goto done;
2001 }
2002
2003 done:
2004 *tempp = temp;
2005 return merr;
2006 }
2007
2008 static enum match_result matches(const struct itemplate *itemp,
2009 insn *instruction, int bits)
2010 {
2011 opflags_t size[MAX_OPERANDS], asize;
2012 bool opsizemissing = false;
2013 int i, oprs;
2014
2015 /*
2016 * Check the opcode
2017 */
2018 if (itemp->opcode != instruction->opcode)
2019 return MERR_INVALOP;
2020
2021 /*
2022 * Count the operands
2023 */
2024 if (itemp->operands != instruction->operands)
2025 return MERR_INVALOP;
2026
2027 /*
2028 * Is it legal?
2029 */
2030 if (!(optimizing > 0) && (itemp->flags & IF_OPT))
2031 return MERR_INVALOP;
2032
2033 /*
2034 * Check that no spurious colons or TOs are present
2035 */
2036 for (i = 0; i < itemp->operands; i++)
2037 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2038 return MERR_INVALOP;
2039
2040 /*
2041 * Process size flags
2042 */
2043 switch (itemp->flags & IF_SMASK) {
2044 case IF_SB:
2045 asize = BITS8;
2046 break;
2047 case IF_SW:
2048 asize = BITS16;
2049 break;
2050 case IF_SD:
2051 asize = BITS32;
2052 break;
2053 case IF_SQ:
2054 asize = BITS64;
2055 break;
2056 case IF_SO:
2057 asize = BITS128;
2058 break;
2059 case IF_SY:
2060 asize = BITS256;
2061 break;
2062 case IF_SZ:
2063 asize = BITS512;
2064 break;
2065 case IF_SIZE:
2066 switch (bits) {
2067 case 16:
2068 asize = BITS16;
2069 break;
2070 case 32:
2071 asize = BITS32;
2072 break;
2073 case 64:
2074 asize = BITS64;
2075 break;
2076 default:
2077 asize = 0;
2078 break;
2079 }
2080 break;
2081 default:
2082 asize = 0;
2083 break;
2084 }
2085
2086 if (itemp->flags & IF_ARMASK) {
2087 /* S- flags only apply to a specific operand */
2088 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
2089 memset(size, 0, sizeof size);
2090 size[i] = asize;
2091 } else {
2092 /* S- flags apply to all operands */
2093 for (i = 0; i < MAX_OPERANDS; i++)
2094 size[i] = asize;
2095 }
2096
2097 /*
2098 * Check that the operand flags all match up,
2099 * it's a bit tricky so lets be verbose:
2100 *
2101 * 1) Find out the size of operand. If instruction
2102 * doesn't have one specified -- we're trying to
2103 * guess it either from template (IF_S* flag) or
2104 * from code bits.
2105 *
2106 * 2) If template operand do not match the instruction OR
2107 * template has an operand size specified AND this size differ
2108 * from which instruction has (perhaps we got it from code bits)
2109 * we are:
2110 * a) Check that only size of instruction and operand is differ
2111 * other characteristics do match
2112 * b) Perhaps it's a register specified in instruction so
2113 * for such a case we just mark that operand as "size
2114 * missing" and this will turn on fuzzy operand size
2115 * logic facility (handled by a caller)
2116 */
2117 for (i = 0; i < itemp->operands; i++) {
2118 opflags_t type = instruction->oprs[i].type;
2119 decoflags_t deco = instruction->oprs[i].decoflags;
2120 if (!(type & SIZE_MASK))
2121 type |= size[i];
2122
2123 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2124 (itemp->deco[i] & deco) != deco) {
2125 return MERR_INVALOP;
2126 } else if ((itemp->opd[i] & SIZE_MASK) &&
2127 (itemp->opd[i] & SIZE_MASK) != (type & SIZE_MASK)) {
2128 if (type & SIZE_MASK) {
2129 /*
2130 * when broadcasting, the element size depends on
2131 * the instruction type. decorator flag should match.
2132 */
2133 #define MATCH_BRSZ(bits) (((type & SIZE_MASK) == BITS##bits) && \
2134 ((itemp->deco[i] & BRSIZE_MASK) == BR_BITS##bits))
2135 if (!((deco & BRDCAST_MASK) &&
2136 (MATCH_BRSZ(32) || MATCH_BRSZ(64)))) {
2137 return MERR_INVALOP;
2138 }
2139 } else if (!is_class(REGISTER, type)) {
2140 /*
2141 * Note: we don't honor extrinsic operand sizes for registers,
2142 * so "missing operand size" for a register should be
2143 * considered a wildcard match rather than an error.
2144 */
2145 opsizemissing = true;
2146 }
2147 } else if (nasm_regvals[instruction->oprs[i].basereg] >= 16 &&
2148 (itemp->flags & IF_INSMASK) != IF_AVX512) {
2149 return MERR_ENCMISMATCH;
2150 }
2151 }
2152
2153 if (opsizemissing)
2154 return MERR_OPSIZEMISSING;
2155
2156 /*
2157 * Check operand sizes
2158 */
2159 if (itemp->flags & (IF_SM | IF_SM2)) {
2160 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2161 for (i = 0; i < oprs; i++) {
2162 asize = itemp->opd[i] & SIZE_MASK;
2163 if (asize) {
2164 for (i = 0; i < oprs; i++)
2165 size[i] = asize;
2166 break;
2167 }
2168 }
2169 } else {
2170 oprs = itemp->operands;
2171 }
2172
2173 for (i = 0; i < itemp->operands; i++) {
2174 if (!(itemp->opd[i] & SIZE_MASK) &&
2175 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2176 return MERR_OPSIZEMISMATCH;
2177 }
2178
2179 /*
2180 * Check template is okay at the set cpu level
2181 */
2182 if (((itemp->flags & IF_PLEVEL) > cpu))
2183 return MERR_BADCPU;
2184
2185 /*
2186 * Verify the appropriate long mode flag.
2187 */
2188 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2189 return MERR_BADMODE;
2190
2191 /*
2192 * If we have a HLE prefix, look for the NOHLE flag
2193 */
2194 if ((itemp->flags & IF_NOHLE) &&
2195 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2196 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2197 return MERR_BADHLE;
2198
2199 /*
2200 * Check if special handling needed for Jumps
2201 */
2202 if ((itemp->code[0] & ~1) == 0370)
2203 return MOK_JUMP;
2204
2205 return MOK_GOOD;
2206 }
2207
2208 /*
2209 * Check if offset is a multiple of N with corresponding tuple type
2210 * if Disp8*N is available, compressed displacement is stored in compdisp
2211 */
2212 static bool is_disp8n(operand *input, insn *ins, int8_t *compdisp)
2213 {
2214 const uint8_t fv_n[2][2][VLMAX] = {{{16, 32, 64}, {4, 4, 4}},
2215 {{16, 32, 64}, {8, 8, 8}}};
2216 const uint8_t hv_n[2][VLMAX] = {{8, 16, 32}, {4, 4, 4}};
2217 const uint8_t dup_n[VLMAX] = {8, 32, 64};
2218
2219 bool evex_b = input->decoflags & BRDCAST_MASK;
2220 enum ttypes tuple = ins->evex_tuple;
2221 /* vex_wlp composed as [wwllpp] */
2222 enum vectlens vectlen = (ins->vex_wlp & 0x0c) >> 2;
2223 /* wig(=2) is treated as w0(=0) */
2224 bool evex_w = (ins->vex_wlp & 0x10) >> 4;
2225 int32_t off = input->offset;
2226 uint8_t n = 0;
2227 int32_t disp8;
2228
2229 switch(tuple) {
2230 case FV:
2231 n = fv_n[evex_w][evex_b][vectlen];
2232 break;
2233 case HV:
2234 n = hv_n[evex_b][vectlen];
2235 break;
2236
2237 case FVM:
2238 /* 16, 32, 64 for VL 128, 256, 512 respectively*/
2239 n = 1 << (vectlen + 4);
2240 break;
2241 case T1S8: /* N = 1 */
2242 case T1S16: /* N = 2 */
2243 n = tuple - T1S8 + 1;
2244 break;
2245 case T1S:
2246 /* N = 4 for 32bit, 8 for 64bit */
2247 n = evex_w ? 8 : 4;
2248 break;
2249 case T1F32:
2250 case T1F64:
2251 /* N = 4 for 32bit, 8 for 64bit */
2252 n = (tuple == T1F32 ? 4 : 8);
2253 break;
2254 case T2:
2255 case T4:
2256 case T8:
2257 if (vectlen + 7 <= (evex_w + 5) + (tuple - T2 + 1))
2258 n = 0;
2259 else
2260 n = 1 << (tuple - T2 + evex_w + 3);
2261 break;
2262 case HVM:
2263 case QVM:
2264 case OVM:
2265 n = 1 << (OVM - tuple + vectlen + 1);
2266 break;
2267 case M128:
2268 n = 16;
2269 break;
2270 case DUP:
2271 n = dup_n[vectlen];
2272 break;
2273
2274 default:
2275 break;
2276 }
2277
2278 if (n && !(off & (n - 1))) {
2279 disp8 = off / n;
2280 /* if it fits in Disp8 */
2281 if (disp8 >= -128 && disp8 <= 127) {
2282 *compdisp = disp8;
2283 return true;
2284 }
2285 }
2286
2287 *compdisp = 0;
2288 return false;
2289 }
2290
2291 /*
2292 * Check if ModR/M.mod should/can be 01.
2293 * - EAF_BYTEOFFS is set
2294 * - offset can fit in a byte when EVEX is not used
2295 * - offset can be compressed when EVEX is used
2296 */
2297 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2298 (o >= -128 && o <= 127 && \
2299 seg == NO_SEG && !forw_ref && \
2300 !(input->eaflags & EAF_WORDOFFS) && \
2301 !(ins->rex & REX_EV)) || \
2302 (ins->rex & REX_EV && \
2303 is_disp8n(input, ins, &output->disp8)))
2304
2305 static enum ea_type process_ea(operand *input, ea *output, int bits,
2306 int rfield, opflags_t rflags, insn *ins)
2307 {
2308 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2309 int addrbits = ins->addr_size;
2310
2311 output->type = EA_SCALAR;
2312 output->rip = false;
2313
2314 /* REX flags for the rfield operand */
2315 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2316 /* EVEX.R' flag for the REG operand */
2317 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2318
2319 if (is_class(REGISTER, input->type)) {
2320 /*
2321 * It's a direct register.
2322 */
2323 if (!is_register(input->basereg))
2324 goto err;
2325
2326 if (!is_reg_class(REG_EA, input->basereg))
2327 goto err;
2328
2329 /* broadcasting is not available with a direct register operand. */
2330 if (input->decoflags & BRDCAST_MASK) {
2331 nasm_error(ERR_NONFATAL, "Broadcasting not allowed from a register");
2332 goto err;
2333 }
2334
2335 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2336 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2337 output->sib_present = false; /* no SIB necessary */
2338 output->bytes = 0; /* no offset necessary either */
2339 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2340 } else {
2341 /*
2342 * It's a memory reference.
2343 */
2344
2345 /* Embedded rounding or SAE is not available with a mem ref operand. */
2346 if (input->decoflags & (ER | SAE)) {
2347 nasm_error(ERR_NONFATAL,
2348 "Embedded rounding is available only with reg-reg op.");
2349 return -1;
2350 }
2351
2352 if (input->basereg == -1 &&
2353 (input->indexreg == -1 || input->scale == 0)) {
2354 /*
2355 * It's a pure offset.
2356 */
2357 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2358 input->segment == NO_SEG) {
2359 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2360 input->type &= ~IP_REL;
2361 input->type |= MEMORY;
2362 }
2363
2364 if (input->eaflags & EAF_BYTEOFFS ||
2365 (input->eaflags & EAF_WORDOFFS &&
2366 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2367 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2368 }
2369
2370 if (bits == 64 && (~input->type & IP_REL)) {
2371 output->sib_present = true;
2372 output->sib = GEN_SIB(0, 4, 5);
2373 output->bytes = 4;
2374 output->modrm = GEN_MODRM(0, rfield, 4);
2375 output->rip = false;
2376 } else {
2377 output->sib_present = false;
2378 output->bytes = (addrbits != 16 ? 4 : 2);
2379 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2380 output->rip = bits == 64;
2381 }
2382 } else {
2383 /*
2384 * It's an indirection.
2385 */
2386 int i = input->indexreg, b = input->basereg, s = input->scale;
2387 int32_t seg = input->segment;
2388 int hb = input->hintbase, ht = input->hinttype;
2389 int t, it, bt; /* register numbers */
2390 opflags_t x, ix, bx; /* register flags */
2391
2392 if (s == 0)
2393 i = -1; /* make this easy, at least */
2394
2395 if (is_register(i)) {
2396 it = nasm_regvals[i];
2397 ix = nasm_reg_flags[i];
2398 } else {
2399 it = -1;
2400 ix = 0;
2401 }
2402
2403 if (is_register(b)) {
2404 bt = nasm_regvals[b];
2405 bx = nasm_reg_flags[b];
2406 } else {
2407 bt = -1;
2408 bx = 0;
2409 }
2410
2411 /* if either one are a vector register... */
2412 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2413 opflags_t sok = BITS32 | BITS64;
2414 int32_t o = input->offset;
2415 int mod, scale, index, base;
2416
2417 /*
2418 * For a vector SIB, one has to be a vector and the other,
2419 * if present, a GPR. The vector must be the index operand.
2420 */
2421 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2422 if (s == 0)
2423 s = 1;
2424 else if (s != 1)
2425 goto err;
2426
2427 t = bt, bt = it, it = t;
2428 x = bx, bx = ix, ix = x;
2429 }
2430
2431 if (bt != -1) {
2432 if (REG_GPR & ~bx)
2433 goto err;
2434 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2435 sok &= bx;
2436 else
2437 goto err;
2438 }
2439
2440 /*
2441 * While we're here, ensure the user didn't specify
2442 * WORD or QWORD
2443 */
2444 if (input->disp_size == 16 || input->disp_size == 64)
2445 goto err;
2446
2447 if (addrbits == 16 ||
2448 (addrbits == 32 && !(sok & BITS32)) ||
2449 (addrbits == 64 && !(sok & BITS64)))
2450 goto err;
2451
2452 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2453 : ((ix & YMMREG & ~REG_EA)
2454 ? EA_YMMVSIB : EA_XMMVSIB));
2455
2456 output->rex |= rexflags(it, ix, REX_X);
2457 output->rex |= rexflags(bt, bx, REX_B);
2458 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2459
2460 index = it & 7; /* it is known to be != -1 */
2461
2462 switch (s) {
2463 case 1:
2464 scale = 0;
2465 break;
2466 case 2:
2467 scale = 1;
2468 break;
2469 case 4:
2470 scale = 2;
2471 break;
2472 case 8:
2473 scale = 3;
2474 break;
2475 default: /* then what the smeg is it? */
2476 goto err; /* panic */
2477 }
2478
2479 if (bt == -1) {
2480 base = 5;
2481 mod = 0;
2482 } else {
2483 base = (bt & 7);
2484 if (base != REG_NUM_EBP && o == 0 &&
2485 seg == NO_SEG && !forw_ref &&
2486 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2487 mod = 0;
2488 else if (IS_MOD_01())
2489 mod = 1;
2490 else
2491 mod = 2;
2492 }
2493
2494 output->sib_present = true;
2495 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2496 output->modrm = GEN_MODRM(mod, rfield, 4);
2497 output->sib = GEN_SIB(scale, index, base);
2498 } else if ((ix|bx) & (BITS32|BITS64)) {
2499 /*
2500 * it must be a 32/64-bit memory reference. Firstly we have
2501 * to check that all registers involved are type E/Rxx.
2502 */
2503 opflags_t sok = BITS32 | BITS64;
2504 int32_t o = input->offset;
2505
2506 if (it != -1) {
2507 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2508 sok &= ix;
2509 else
2510 goto err;
2511 }
2512
2513 if (bt != -1) {
2514 if (REG_GPR & ~bx)
2515 goto err; /* Invalid register */
2516 if (~sok & bx & SIZE_MASK)
2517 goto err; /* Invalid size */
2518 sok &= bx;
2519 }
2520
2521 /*
2522 * While we're here, ensure the user didn't specify
2523 * WORD or QWORD
2524 */
2525 if (input->disp_size == 16 || input->disp_size == 64)
2526 goto err;
2527
2528 if (addrbits == 16 ||
2529 (addrbits == 32 && !(sok & BITS32)) ||
2530 (addrbits == 64 && !(sok & BITS64)))
2531 goto err;
2532
2533 /* now reorganize base/index */
2534 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2535 ((hb == b && ht == EAH_NOTBASE) ||
2536 (hb == i && ht == EAH_MAKEBASE))) {
2537 /* swap if hints say so */
2538 t = bt, bt = it, it = t;
2539 x = bx, bx = ix, ix = x;
2540 }
2541 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2542 bt = -1, bx = 0, s++;
2543 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2544 /* make single reg base, unless hint */
2545 bt = it, bx = ix, it = -1, ix = 0;
2546 }
2547 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2548 s == 3 || s == 5 || s == 9) && bt == -1)
2549 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2550 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2551 (input->eaflags & EAF_TIMESTWO))
2552 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2553 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2554 if (s == 1 && it == REG_NUM_ESP) {
2555 /* swap ESP into base if scale is 1 */
2556 t = it, it = bt, bt = t;
2557 x = ix, ix = bx, bx = x;
2558 }
2559 if (it == REG_NUM_ESP ||
2560 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2561 goto err; /* wrong, for various reasons */
2562
2563 output->rex |= rexflags(it, ix, REX_X);
2564 output->rex |= rexflags(bt, bx, REX_B);
2565
2566 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2567 /* no SIB needed */
2568 int mod, rm;
2569
2570 if (bt == -1) {
2571 rm = 5;
2572 mod = 0;
2573 } else {
2574 rm = (bt & 7);
2575 if (rm != REG_NUM_EBP && o == 0 &&
2576 seg == NO_SEG && !forw_ref &&
2577 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2578 mod = 0;
2579 else if (IS_MOD_01())
2580 mod = 1;
2581 else
2582 mod = 2;
2583 }
2584
2585 output->sib_present = false;
2586 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2587 output->modrm = GEN_MODRM(mod, rfield, rm);
2588 } else {
2589 /* we need a SIB */
2590 int mod, scale, index, base;
2591
2592 if (it == -1)
2593 index = 4, s = 1;
2594 else
2595 index = (it & 7);
2596
2597 switch (s) {
2598 case 1:
2599 scale = 0;
2600 break;
2601 case 2:
2602 scale = 1;
2603 break;
2604 case 4:
2605 scale = 2;
2606 break;
2607 case 8:
2608 scale = 3;
2609 break;
2610 default: /* then what the smeg is it? */
2611 goto err; /* panic */
2612 }
2613
2614 if (bt == -1) {
2615 base = 5;
2616 mod = 0;
2617 } else {
2618 base = (bt & 7);
2619 if (base != REG_NUM_EBP && o == 0 &&
2620 seg == NO_SEG && !forw_ref &&
2621 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2622 mod = 0;
2623 else if (IS_MOD_01())
2624 mod = 1;
2625 else
2626 mod = 2;
2627 }
2628
2629 output->sib_present = true;
2630 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2631 output->modrm = GEN_MODRM(mod, rfield, 4);
2632 output->sib = GEN_SIB(scale, index, base);
2633 }
2634 } else { /* it's 16-bit */
2635 int mod, rm;
2636 int16_t o = input->offset;
2637
2638 /* check for 64-bit long mode */
2639 if (addrbits == 64)
2640 goto err;
2641
2642 /* check all registers are BX, BP, SI or DI */
2643 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2644 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2645 goto err;
2646
2647 /* ensure the user didn't specify DWORD/QWORD */
2648 if (input->disp_size == 32 || input->disp_size == 64)
2649 goto err;
2650
2651 if (s != 1 && i != -1)
2652 goto err; /* no can do, in 16-bit EA */
2653 if (b == -1 && i != -1) {
2654 int tmp = b;
2655 b = i;
2656 i = tmp;
2657 } /* swap */
2658 if ((b == R_SI || b == R_DI) && i != -1) {
2659 int tmp = b;
2660 b = i;
2661 i = tmp;
2662 }
2663 /* have BX/BP as base, SI/DI index */
2664 if (b == i)
2665 goto err; /* shouldn't ever happen, in theory */
2666 if (i != -1 && b != -1 &&
2667 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2668 goto err; /* invalid combinations */
2669 if (b == -1) /* pure offset: handled above */
2670 goto err; /* so if it gets to here, panic! */
2671
2672 rm = -1;
2673 if (i != -1)
2674 switch (i * 256 + b) {
2675 case R_SI * 256 + R_BX:
2676 rm = 0;
2677 break;
2678 case R_DI * 256 + R_BX:
2679 rm = 1;
2680 break;
2681 case R_SI * 256 + R_BP:
2682 rm = 2;
2683 break;
2684 case R_DI * 256 + R_BP:
2685 rm = 3;
2686 break;
2687 } else
2688 switch (b) {
2689 case R_SI:
2690 rm = 4;
2691 break;
2692 case R_DI:
2693 rm = 5;
2694 break;
2695 case R_BP:
2696 rm = 6;
2697 break;
2698 case R_BX:
2699 rm = 7;
2700 break;
2701 }
2702 if (rm == -1) /* can't happen, in theory */
2703 goto err; /* so panic if it does */
2704
2705 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2706 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2707 mod = 0;
2708 else if (IS_MOD_01())
2709 mod = 1;
2710 else
2711 mod = 2;
2712
2713 output->sib_present = false; /* no SIB - it's 16-bit */
2714 output->bytes = mod; /* bytes of offset needed */
2715 output->modrm = GEN_MODRM(mod, rfield, rm);
2716 }
2717 }
2718 }
2719
2720 output->size = 1 + output->sib_present + output->bytes;
2721 return output->type;
2722
2723 err:
2724 return output->type = EA_INVALID;
2725 }
2726
2727 static void add_asp(insn *ins, int addrbits)
2728 {
2729 int j, valid;
2730 int defdisp;
2731
2732 valid = (addrbits == 64) ? 64|32 : 32|16;
2733
2734 switch (ins->prefixes[PPS_ASIZE]) {
2735 case P_A16:
2736 valid &= 16;
2737 break;
2738 case P_A32:
2739 valid &= 32;
2740 break;
2741 case P_A64:
2742 valid &= 64;
2743 break;
2744 case P_ASP:
2745 valid &= (addrbits == 32) ? 16 : 32;
2746 break;
2747 default:
2748 break;
2749 }
2750
2751 for (j = 0; j < ins->operands; j++) {
2752 if (is_class(MEMORY, ins->oprs[j].type)) {
2753 opflags_t i, b;
2754
2755 /* Verify as Register */
2756 if (!is_register(ins->oprs[j].indexreg))
2757 i = 0;
2758 else
2759 i = nasm_reg_flags[ins->oprs[j].indexreg];
2760
2761 /* Verify as Register */
2762 if (!is_register(ins->oprs[j].basereg))
2763 b = 0;
2764 else
2765 b = nasm_reg_flags[ins->oprs[j].basereg];
2766
2767 if (ins->oprs[j].scale == 0)
2768 i = 0;
2769
2770 if (!i && !b) {
2771 int ds = ins->oprs[j].disp_size;
2772 if ((addrbits != 64 && ds > 8) ||
2773 (addrbits == 64 && ds == 16))
2774 valid &= ds;
2775 } else {
2776 if (!(REG16 & ~b))
2777 valid &= 16;
2778 if (!(REG32 & ~b))
2779 valid &= 32;
2780 if (!(REG64 & ~b))
2781 valid &= 64;
2782
2783 if (!(REG16 & ~i))
2784 valid &= 16;
2785 if (!(REG32 & ~i))
2786 valid &= 32;
2787 if (!(REG64 & ~i))
2788 valid &= 64;
2789 }
2790 }
2791 }
2792
2793 if (valid & addrbits) {
2794 ins->addr_size = addrbits;
2795 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2796 /* Add an address size prefix */
2797 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2798 ins->addr_size = (addrbits == 32) ? 16 : 32;
2799 } else {
2800 /* Impossible... */
2801 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2802 ins->addr_size = addrbits; /* Error recovery */
2803 }
2804
2805 defdisp = ins->addr_size == 16 ? 16 : 32;
2806
2807 for (j = 0; j < ins->operands; j++) {
2808 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2809 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2810 /*
2811 * mem_offs sizes must match the address size; if not,
2812 * strip the MEM_OFFS bit and match only EA instructions
2813 */
2814 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2815 }
2816 }
2817 }
The Netwide Assembler