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Add CLFLUSHOPT instruction
[nasm.git] / disasm.c
blobbb53b4cb874cb77e5602bfe6dcbee2cb2581d077
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2012 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * disasm.c where all the _work_ gets done in the Netwide Disassembler
36 */
37
38 #include "compiler.h"
39
40 #include <stdio.h>
41 #include <string.h>
42 #include <limits.h>
43 #include <inttypes.h>
44
45 #include "nasm.h"
46 #include "disasm.h"
47 #include "sync.h"
48 #include "insns.h"
49 #include "tables.h"
50 #include "regdis.h"
51 #include "disp8.h"
52
53 /*
54 * Flags that go into the `segment' field of `insn' structures
55 * during disassembly.
56 */
57 #define SEG_RELATIVE 1
58 #define SEG_32BIT 2
59 #define SEG_RMREG 4
60 #define SEG_DISP8 8
61 #define SEG_DISP16 16
62 #define SEG_DISP32 32
63 #define SEG_NODISP 64
64 #define SEG_SIGNED 128
65 #define SEG_64BIT 256
66
67 /*
68 * Prefix information
69 */
70 struct prefix_info {
71 uint8_t osize; /* Operand size */
72 uint8_t asize; /* Address size */
73 uint8_t osp; /* Operand size prefix present */
74 uint8_t asp; /* Address size prefix present */
75 uint8_t rep; /* Rep prefix present */
76 uint8_t seg; /* Segment override prefix present */
77 uint8_t wait; /* WAIT "prefix" present */
78 uint8_t lock; /* Lock prefix present */
79 uint8_t vex[3]; /* VEX prefix present */
80 uint8_t vex_c; /* VEX "class" (VEX, XOP, ...) */
81 uint8_t vex_m; /* VEX.M field */
82 uint8_t vex_v;
83 uint8_t vex_lp; /* VEX.LP fields */
84 uint32_t rex; /* REX prefix present */
85 uint8_t evex[3]; /* EVEX prefix present */
86 };
87
88 #define getu8(x) (*(uint8_t *)(x))
89 #if X86_MEMORY
90 /* Littleendian CPU which can handle unaligned references */
91 #define getu16(x) (*(uint16_t *)(x))
92 #define getu32(x) (*(uint32_t *)(x))
93 #define getu64(x) (*(uint64_t *)(x))
94 #else
95 static uint16_t getu16(uint8_t *data)
96 {
97 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
98 }
99 static uint32_t getu32(uint8_t *data)
100 {
101 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
102 }
103 static uint64_t getu64(uint8_t *data)
104 {
105 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
106 }
107 #endif
108
109 #define gets8(x) ((int8_t)getu8(x))
110 #define gets16(x) ((int16_t)getu16(x))
111 #define gets32(x) ((int32_t)getu32(x))
112 #define gets64(x) ((int64_t)getu64(x))
113
114 /* Important: regval must already have been adjusted for rex extensions */
115 static enum reg_enum whichreg(opflags_t regflags, int regval, int rex)
116 {
117 size_t i;
118
119 static const struct {
120 opflags_t flags;
121 enum reg_enum reg;
122 } specific_registers[] = {
123 {REG_AL, R_AL},
124 {REG_AX, R_AX},
125 {REG_EAX, R_EAX},
126 {REG_RAX, R_RAX},
127 {REG_DL, R_DL},
128 {REG_DX, R_DX},
129 {REG_EDX, R_EDX},
130 {REG_RDX, R_RDX},
131 {REG_CL, R_CL},
132 {REG_CX, R_CX},
133 {REG_ECX, R_ECX},
134 {REG_RCX, R_RCX},
135 {FPU0, R_ST0},
136 {XMM0, R_XMM0},
137 {YMM0, R_YMM0},
138 {ZMM0, R_ZMM0},
139 {REG_ES, R_ES},
140 {REG_CS, R_CS},
141 {REG_SS, R_SS},
142 {REG_DS, R_DS},
143 {REG_FS, R_FS},
144 {REG_GS, R_GS},
145 {OPMASK0, R_K0},
146 };
147
148 if (!(regflags & (REGISTER|REGMEM)))
149 return 0; /* Registers not permissible?! */
150
151 regflags |= REGISTER;
152
153 for (i = 0; i < ARRAY_SIZE(specific_registers); i++)
154 if (!(specific_registers[i].flags & ~regflags))
155 return specific_registers[i].reg;
156
157 /* All the entries below look up regval in an 16-entry array */
158 if (regval < 0 || regval > (rex & REX_EV ? 31 : 15))
159 return 0;
160
161 if (!(REG8 & ~regflags)) {
162 if (rex & (REX_P|REX_NH))
163 return nasm_rd_reg8_rex[regval];
164 else
165 return nasm_rd_reg8[regval];
166 }
167 if (!(REG16 & ~regflags))
168 return nasm_rd_reg16[regval];
169 if (!(REG32 & ~regflags))
170 return nasm_rd_reg32[regval];
171 if (!(REG64 & ~regflags))
172 return nasm_rd_reg64[regval];
173 if (!(REG_SREG & ~regflags))
174 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
175 if (!(REG_CREG & ~regflags))
176 return nasm_rd_creg[regval];
177 if (!(REG_DREG & ~regflags))
178 return nasm_rd_dreg[regval];
179 if (!(REG_TREG & ~regflags)) {
180 if (regval > 7)
181 return 0; /* TR registers are ill-defined with rex */
182 return nasm_rd_treg[regval];
183 }
184 if (!(FPUREG & ~regflags))
185 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
186 if (!(MMXREG & ~regflags))
187 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
188 if (!(XMMREG & ~regflags))
189 return nasm_rd_xmmreg[regval];
190 if (!(YMMREG & ~regflags))
191 return nasm_rd_ymmreg[regval];
192 if (!(ZMMREG & ~regflags))
193 return nasm_rd_zmmreg[regval];
194 if (!(OPMASKREG & ~regflags))
195 return nasm_rd_opmaskreg[regval];
196 if (!(BNDREG & ~regflags))
197 return nasm_rd_bndreg[regval];
198
199 return 0;
200 }
201
202 static uint32_t append_evex_reg_deco(char *buf, uint32_t num,
203 decoflags_t deco, uint8_t *evex)
204 {
205 const char * const er_names[] = {"rn-sae", "rd-sae", "ru-sae", "rz-sae"};
206 uint32_t num_chars = 0;
207
208 if ((deco & MASK) && (evex[2] & EVEX_P2AAA)) {
209 enum reg_enum opmasknum = nasm_rd_opmaskreg[evex[2] & EVEX_P2AAA];
210 const char * regname = nasm_reg_names[opmasknum - EXPR_REG_START];
211
212 num_chars += snprintf(buf + num_chars, num - num_chars,
213 "{%s}", regname);
214
215 if ((deco & Z) && (evex[2] & EVEX_P2Z)) {
216 num_chars += snprintf(buf + num_chars, num - num_chars,
217 "{z}");
218 }
219 }
220
221 if (evex[2] & EVEX_P2B) {
222 if (deco & ER) {
223 uint8_t er_type = (evex[2] & EVEX_P2LL) >> 5;
224 num_chars += snprintf(buf + num_chars, num - num_chars,
225 ",{%s}", er_names[er_type]);
226 } else if (deco & SAE) {
227 num_chars += snprintf(buf + num_chars, num - num_chars,
228 ",{sae}");
229 }
230 }
231
232 return num_chars;
233 }
234
235 static uint32_t append_evex_mem_deco(char *buf, uint32_t num, opflags_t type,
236 decoflags_t deco, uint8_t *evex)
237 {
238 uint32_t num_chars = 0;
239
240 if ((evex[2] & EVEX_P2B) && (deco & BRDCAST_MASK)) {
241 decoflags_t deco_brsize = deco & BRSIZE_MASK;
242 opflags_t template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
243 uint8_t br_num = (type & SIZE_MASK) / BITS128 *
244 BITS64 / template_opsize * 2;
245
246 num_chars += snprintf(buf + num_chars, num - num_chars,
247 "{1to%d}", br_num);
248 }
249
250 if ((deco & MASK) && (evex[2] & EVEX_P2AAA)) {
251 enum reg_enum opmasknum = nasm_rd_opmaskreg[evex[2] & EVEX_P2AAA];
252 const char * regname = nasm_reg_names[opmasknum - EXPR_REG_START];
253
254 num_chars += snprintf(buf + num_chars, num - num_chars,
255 "{%s}", regname);
256
257 if ((deco & Z) && (evex[2] & EVEX_P2Z)) {
258 num_chars += snprintf(buf + num_chars, num - num_chars,
259 "{z}");
260 }
261 }
262
263
264 return num_chars;
265 }
266
267 /*
268 * Process an effective address (ModRM) specification.
269 */
270 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
271 int segsize, enum ea_type type,
272 operand *op, insn *ins)
273 {
274 int mod, rm, scale, index, base;
275 int rex;
276 uint8_t *evex;
277 uint8_t sib = 0;
278 bool is_evex = !!(ins->rex & REX_EV);
279
280 mod = (modrm >> 6) & 03;
281 rm = modrm & 07;
282
283 if (mod != 3 && asize != 16 && rm == 4)
284 sib = *data++;
285
286 rex = ins->rex;
287 evex = ins->evex_p;
288
289 if (mod == 3) { /* pure register version */
290 op->basereg = rm+(rex & REX_B ? 8 : 0);
291 op->segment |= SEG_RMREG;
292 if (is_evex && segsize == 64) {
293 op->basereg += (evex[0] & EVEX_P0X ? 0 : 16);
294 }
295 return data;
296 }
297
298 op->disp_size = 0;
299 op->eaflags = 0;
300
301 if (asize == 16) {
302 /*
303 * <mod> specifies the displacement size (none, byte or
304 * word), and <rm> specifies the register combination.
305 * Exception: mod=0,rm=6 does not specify [BP] as one might
306 * expect, but instead specifies [disp16].
307 */
308
309 if (type != EA_SCALAR)
310 return NULL;
311
312 op->indexreg = op->basereg = -1;
313 op->scale = 1; /* always, in 16 bits */
314 switch (rm) {
315 case 0:
316 op->basereg = R_BX;
317 op->indexreg = R_SI;
318 break;
319 case 1:
320 op->basereg = R_BX;
321 op->indexreg = R_DI;
322 break;
323 case 2:
324 op->basereg = R_BP;
325 op->indexreg = R_SI;
326 break;
327 case 3:
328 op->basereg = R_BP;
329 op->indexreg = R_DI;
330 break;
331 case 4:
332 op->basereg = R_SI;
333 break;
334 case 5:
335 op->basereg = R_DI;
336 break;
337 case 6:
338 op->basereg = R_BP;
339 break;
340 case 7:
341 op->basereg = R_BX;
342 break;
343 }
344 if (rm == 6 && mod == 0) { /* special case */
345 op->basereg = -1;
346 if (segsize != 16)
347 op->disp_size = 16;
348 mod = 2; /* fake disp16 */
349 }
350 switch (mod) {
351 case 0:
352 op->segment |= SEG_NODISP;
353 break;
354 case 1:
355 op->segment |= SEG_DISP8;
356 if (ins->evex_tuple != 0) {
357 op->offset = gets8(data) * get_disp8N(ins);
358 } else {
359 op->offset = gets8(data);
360 }
361 data++;
362 break;
363 case 2:
364 op->segment |= SEG_DISP16;
365 op->offset = *data++;
366 op->offset |= ((unsigned)*data++) << 8;
367 break;
368 }
369 return data;
370 } else {
371 /*
372 * Once again, <mod> specifies displacement size (this time
373 * none, byte or *dword*), while <rm> specifies the base
374 * register. Again, [EBP] is missing, replaced by a pure
375 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
376 * and RIP-relative addressing in 64-bit mode.
377 *
378 * However, rm=4
379 * indicates not a single base register, but instead the
380 * presence of a SIB byte...
381 */
382 int a64 = asize == 64;
383
384 op->indexreg = -1;
385
386 if (a64)
387 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
388 else
389 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
390
391 if (rm == 5 && mod == 0) {
392 if (segsize == 64) {
393 op->eaflags |= EAF_REL;
394 op->segment |= SEG_RELATIVE;
395 mod = 2; /* fake disp32 */
396 }
397
398 if (asize != 64)
399 op->disp_size = asize;
400
401 op->basereg = -1;
402 mod = 2; /* fake disp32 */
403 }
404
405
406 if (rm == 4) { /* process SIB */
407 uint8_t vsib_hi = 0;
408 scale = (sib >> 6) & 03;
409 index = (sib >> 3) & 07;
410 base = sib & 07;
411
412 op->scale = 1 << scale;
413
414 if (segsize == 64) {
415 vsib_hi = (rex & REX_X ? 8 : 0) |
416 (evex[2] & EVEX_P2VP ? 0 : 16);
417 }
418
419 if (type == EA_XMMVSIB)
420 op->indexreg = nasm_rd_xmmreg[index | vsib_hi];
421 else if (type == EA_YMMVSIB)
422 op->indexreg = nasm_rd_ymmreg[index | vsib_hi];
423 else if (type == EA_ZMMVSIB)
424 op->indexreg = nasm_rd_zmmreg[index | vsib_hi];
425 else if (index == 4 && !(rex & REX_X))
426 op->indexreg = -1; /* ESP/RSP cannot be an index */
427 else if (a64)
428 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
429 else
430 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
431
432 if (base == 5 && mod == 0) {
433 op->basereg = -1;
434 mod = 2; /* Fake disp32 */
435 } else if (a64)
436 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
437 else
438 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
439
440 if (segsize == 16)
441 op->disp_size = 32;
442 } else if (type != EA_SCALAR) {
443 /* Can't have VSIB without SIB */
444 return NULL;
445 }
446
447 switch (mod) {
448 case 0:
449 op->segment |= SEG_NODISP;
450 break;
451 case 1:
452 op->segment |= SEG_DISP8;
453 if (ins->evex_tuple != 0) {
454 op->offset = gets8(data) * get_disp8N(ins);
455 } else {
456 op->offset = gets8(data);
457 }
458 data++;
459 break;
460 case 2:
461 op->segment |= SEG_DISP32;
462 op->offset = gets32(data);
463 data += 4;
464 break;
465 }
466 return data;
467 }
468 }
469
470 /*
471 * Determine whether the instruction template in t corresponds to the data
472 * stream in data. Return the number of bytes matched if so.
473 */
474 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
475
476 static int matches(const struct itemplate *t, uint8_t *data,
477 const struct prefix_info *prefix, int segsize, insn *ins)
478 {
479 uint8_t *r = (uint8_t *)(t->code);
480 uint8_t *origdata = data;
481 bool a_used = false, o_used = false;
482 enum prefixes drep = 0;
483 enum prefixes dwait = 0;
484 uint8_t lock = prefix->lock;
485 int osize = prefix->osize;
486 int asize = prefix->asize;
487 int i, c;
488 int op1, op2;
489 struct operand *opx, *opy;
490 uint8_t opex = 0;
491 bool vex_ok = false;
492 int regmask = (segsize == 64) ? 15 : 7;
493 enum ea_type eat = EA_SCALAR;
494
495 for (i = 0; i < MAX_OPERANDS; i++) {
496 ins->oprs[i].segment = ins->oprs[i].disp_size =
497 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
498 }
499 ins->condition = -1;
500 ins->evex_tuple = 0;
501 ins->rex = prefix->rex;
502 memset(ins->prefixes, 0, sizeof ins->prefixes);
503
504 if (itemp_has(t, (segsize == 64 ? IF_NOLONG : IF_LONG)))
505 return false;
506
507 if (prefix->rep == 0xF2)
508 drep = (itemp_has(t, IF_BND) ? P_BND : P_REPNE);
509 else if (prefix->rep == 0xF3)
510 drep = P_REP;
511
512 dwait = prefix->wait ? P_WAIT : 0;
513
514 while ((c = *r++) != 0) {
515 op1 = (c & 3) + ((opex & 1) << 2);
516 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
517 opx = &ins->oprs[op1];
518 opy = &ins->oprs[op2];
519 opex = 0;
520
521 switch (c) {
522 case 01:
523 case 02:
524 case 03:
525 case 04:
526 while (c--)
527 if (*r++ != *data++)
528 return false;
529 break;
530
531 case 05:
532 case 06:
533 case 07:
534 opex = c;
535 break;
536
537 case4(010):
538 {
539 int t = *r++, d = *data++;
540 if (d < t || d > t + 7)
541 return false;
542 else {
543 opx->basereg = (d-t)+
544 (ins->rex & REX_B ? 8 : 0);
545 opx->segment |= SEG_RMREG;
546 }
547 break;
548 }
549
550 case4(014):
551 /* this is an separate index reg position of MIB operand (ICC) */
552 /* Disassembler uses NASM's split EA form only */
553 break;
554
555 case4(0274):
556 opx->offset = (int8_t)*data++;
557 opx->segment |= SEG_SIGNED;
558 break;
559
560 case4(020):
561 opx->offset = *data++;
562 break;
563
564 case4(024):
565 opx->offset = *data++;
566 break;
567
568 case4(030):
569 opx->offset = getu16(data);
570 data += 2;
571 break;
572
573 case4(034):
574 if (osize == 32) {
575 opx->offset = getu32(data);
576 data += 4;
577 } else {
578 opx->offset = getu16(data);
579 data += 2;
580 }
581 if (segsize != asize)
582 opx->disp_size = asize;
583 break;
584
585 case4(040):
586 opx->offset = getu32(data);
587 data += 4;
588 break;
589
590 case4(0254):
591 opx->offset = gets32(data);
592 data += 4;
593 break;
594
595 case4(044):
596 switch (asize) {
597 case 16:
598 opx->offset = getu16(data);
599 data += 2;
600 if (segsize != 16)
601 opx->disp_size = 16;
602 break;
603 case 32:
604 opx->offset = getu32(data);
605 data += 4;
606 if (segsize == 16)
607 opx->disp_size = 32;
608 break;
609 case 64:
610 opx->offset = getu64(data);
611 opx->disp_size = 64;
612 data += 8;
613 break;
614 }
615 break;
616
617 case4(050):
618 opx->offset = gets8(data++);
619 opx->segment |= SEG_RELATIVE;
620 break;
621
622 case4(054):
623 opx->offset = getu64(data);
624 data += 8;
625 break;
626
627 case4(060):
628 opx->offset = gets16(data);
629 data += 2;
630 opx->segment |= SEG_RELATIVE;
631 opx->segment &= ~SEG_32BIT;
632 break;
633
634 case4(064): /* rel */
635 opx->segment |= SEG_RELATIVE;
636 /* In long mode rel is always 32 bits, sign extended. */
637 if (segsize == 64 || osize == 32) {
638 opx->offset = gets32(data);
639 data += 4;
640 if (segsize != 64)
641 opx->segment |= SEG_32BIT;
642 opx->type = (opx->type & ~SIZE_MASK)
643 | (segsize == 64 ? BITS64 : BITS32);
644 } else {
645 opx->offset = gets16(data);
646 data += 2;
647 opx->segment &= ~SEG_32BIT;
648 opx->type = (opx->type & ~SIZE_MASK) | BITS16;
649 }
650 break;
651
652 case4(070):
653 opx->offset = gets32(data);
654 data += 4;
655 opx->segment |= SEG_32BIT | SEG_RELATIVE;
656 break;
657
658 case4(0100):
659 case4(0110):
660 case4(0120):
661 case4(0130):
662 {
663 int modrm = *data++;
664 opx->segment |= SEG_RMREG;
665 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
666 if (!data)
667 return false;
668 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
669 if ((ins->rex & REX_EV) && (segsize == 64))
670 opx->basereg += (ins->evex_p[0] & EVEX_P0RP ? 0 : 16);
671 break;
672 }
673
674 case 0172:
675 {
676 uint8_t ximm = *data++;
677 c = *r++;
678 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
679 ins->oprs[c >> 3].segment |= SEG_RMREG;
680 ins->oprs[c & 7].offset = ximm & 15;
681 }
682 break;
683
684 case 0173:
685 {
686 uint8_t ximm = *data++;
687 c = *r++;
688
689 if ((c ^ ximm) & 15)
690 return false;
691
692 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
693 ins->oprs[c >> 4].segment |= SEG_RMREG;
694 }
695 break;
696
697 case4(0174):
698 {
699 uint8_t ximm = *data++;
700
701 opx->basereg = (ximm >> 4) & regmask;
702 opx->segment |= SEG_RMREG;
703 }
704 break;
705
706 case4(0200):
707 case4(0204):
708 case4(0210):
709 case4(0214):
710 case4(0220):
711 case4(0224):
712 case4(0230):
713 case4(0234):
714 {
715 int modrm = *data++;
716 if (((modrm >> 3) & 07) != (c & 07))
717 return false; /* spare field doesn't match up */
718 data = do_ea(data, modrm, asize, segsize, eat, opy, ins);
719 if (!data)
720 return false;
721 break;
722 }
723
724 case4(0240):
725 case 0250:
726 {
727 uint8_t evexm = *r++;
728 uint8_t evexwlp = *r++;
729 ins->evex_tuple = *r++ - 0300;
730
731 ins->rex |= REX_EV;
732 if ((prefix->rex & (REX_EV|REX_V|REX_P)) != REX_EV)
733 return false;
734
735 if ((evexm & 0x1f) != prefix->vex_m)
736 return false;
737
738 switch (evexwlp & 060) {
739 case 000:
740 if (prefix->rex & REX_W)
741 return false;
742 break;
743 case 020:
744 if (!(prefix->rex & REX_W))
745 return false;
746 ins->rex |= REX_W;
747 break;
748 case 040: /* VEX.W is a don't care */
749 ins->rex &= ~REX_W;
750 break;
751 case 060:
752 break;
753 }
754
755 /* If EVEX.b is set, EVEX.L'L can be rounding control bits */
756 if ((evexwlp ^ prefix->vex_lp) &
757 ((prefix->evex[2] & EVEX_P2B) ? 0x03 : 0x0f))
758 return false;
759
760 if (c == 0250) {
761 if ((prefix->vex_v != 0) ||
762 (!(prefix->evex[2] & EVEX_P2VP) &&
763 ((eat < EA_XMMVSIB) || (eat > EA_ZMMVSIB))))
764 return false;
765 } else {
766 opx->segment |= SEG_RMREG;
767 opx->basereg = ((~prefix->evex[2] & EVEX_P2VP) << (4 - 3) ) |
768 prefix->vex_v;
769 }
770 vex_ok = true;
771 memcpy(ins->evex_p, prefix->evex, 3);
772 break;
773 }
774
775 case4(0260):
776 case 0270:
777 {
778 int vexm = *r++;
779 int vexwlp = *r++;
780
781 ins->rex |= REX_V;
782 if ((prefix->rex & (REX_V|REX_P)) != REX_V)
783 return false;
784
785 if ((vexm & 0x1f) != prefix->vex_m)
786 return false;
787
788 switch (vexwlp & 060) {
789 case 000:
790 if (prefix->rex & REX_W)
791 return false;
792 break;
793 case 020:
794 if (!(prefix->rex & REX_W))
795 return false;
796 ins->rex &= ~REX_W;
797 break;
798 case 040: /* VEX.W is a don't care */
799 ins->rex &= ~REX_W;
800 break;
801 case 060:
802 break;
803 }
804
805 /* The 010 bit of vexwlp is set if VEX.L is ignored */
806 if ((vexwlp ^ prefix->vex_lp) & ((vexwlp & 010) ? 03 : 07))
807 return false;
808
809 if (c == 0270) {
810 if (prefix->vex_v != 0)
811 return false;
812 } else {
813 opx->segment |= SEG_RMREG;
814 opx->basereg = prefix->vex_v;
815 }
816 vex_ok = true;
817 break;
818 }
819
820 case 0271:
821 if (prefix->rep == 0xF3)
822 drep = P_XRELEASE;
823 break;
824
825 case 0272:
826 if (prefix->rep == 0xF2)
827 drep = P_XACQUIRE;
828 else if (prefix->rep == 0xF3)
829 drep = P_XRELEASE;
830 break;
831
832 case 0273:
833 if (prefix->lock == 0xF0) {
834 if (prefix->rep == 0xF2)
835 drep = P_XACQUIRE;
836 else if (prefix->rep == 0xF3)
837 drep = P_XRELEASE;
838 }
839 break;
840
841 case 0310:
842 if (asize != 16)
843 return false;
844 else
845 a_used = true;
846 break;
847
848 case 0311:
849 if (asize != 32)
850 return false;
851 else
852 a_used = true;
853 break;
854
855 case 0312:
856 if (asize != segsize)
857 return false;
858 else
859 a_used = true;
860 break;
861
862 case 0313:
863 if (asize != 64)
864 return false;
865 else
866 a_used = true;
867 break;
868
869 case 0314:
870 if (prefix->rex & REX_B)
871 return false;
872 break;
873
874 case 0315:
875 if (prefix->rex & REX_X)
876 return false;
877 break;
878
879 case 0316:
880 if (prefix->rex & REX_R)
881 return false;
882 break;
883
884 case 0317:
885 if (prefix->rex & REX_W)
886 return false;
887 break;
888
889 case 0320:
890 if (osize != 16)
891 return false;
892 else
893 o_used = true;
894 break;
895
896 case 0321:
897 if (osize != 32)
898 return false;
899 else
900 o_used = true;
901 break;
902
903 case 0322:
904 if (osize != (segsize == 16) ? 16 : 32)
905 return false;
906 else
907 o_used = true;
908 break;
909
910 case 0323:
911 ins->rex |= REX_W; /* 64-bit only instruction */
912 osize = 64;
913 o_used = true;
914 break;
915
916 case 0324:
917 if (osize != 64)
918 return false;
919 o_used = true;
920 break;
921
922 case 0325:
923 ins->rex |= REX_NH;
924 break;
925
926 case 0330:
927 {
928 int t = *r++, d = *data++;
929 if (d < t || d > t + 15)
930 return false;
931 else
932 ins->condition = d - t;
933 break;
934 }
935
936 case 0326:
937 if (prefix->rep == 0xF3)
938 return false;
939 break;
940
941 case 0331:
942 if (prefix->rep)
943 return false;
944 break;
945
946 case 0332:
947 if (prefix->rep != 0xF2)
948 return false;
949 drep = 0;
950 break;
951
952 case 0333:
953 if (prefix->rep != 0xF3)
954 return false;
955 drep = 0;
956 break;
957
958 case 0334:
959 if (lock) {
960 ins->rex |= REX_R;
961 lock = 0;
962 }
963 break;
964
965 case 0335:
966 if (drep == P_REP)
967 drep = P_REPE;
968 break;
969
970 case 0336:
971 case 0337:
972 break;
973
974 case 0340:
975 return false;
976
977 case 0341:
978 if (prefix->wait != 0x9B)
979 return false;
980 dwait = 0;
981 break;
982
983 case 0360:
984 if (prefix->osp || prefix->rep)
985 return false;
986 break;
987
988 case 0361:
989 if (!prefix->osp || prefix->rep)
990 return false;
991 o_used = true;
992 break;
993
994 case 0364:
995 if (prefix->osp)
996 return false;
997 break;
998
999 case 0365:
1000 if (prefix->asp)
1001 return false;
1002 break;
1003
1004 case 0366:
1005 if (!prefix->osp)
1006 return false;
1007 o_used = true;
1008 break;
1009
1010 case 0367:
1011 if (!prefix->asp)
1012 return false;
1013 a_used = true;
1014 break;
1015
1016 case 0370:
1017 case 0371:
1018 break;
1019
1020 case 0374:
1021 eat = EA_XMMVSIB;
1022 break;
1023
1024 case 0375:
1025 eat = EA_YMMVSIB;
1026 break;
1027
1028 case 0376:
1029 eat = EA_ZMMVSIB;
1030 break;
1031
1032 default:
1033 return false; /* Unknown code */
1034 }
1035 }
1036
1037 if (!vex_ok && (ins->rex & (REX_V | REX_EV)))
1038 return false;
1039
1040 /* REX cannot be combined with VEX */
1041 if ((ins->rex & REX_V) && (prefix->rex & REX_P))
1042 return false;
1043
1044 /*
1045 * Check for unused rep or a/o prefixes.
1046 */
1047 for (i = 0; i < t->operands; i++) {
1048 if (ins->oprs[i].segment != SEG_RMREG)
1049 a_used = true;
1050 }
1051
1052 if (lock) {
1053 if (ins->prefixes[PPS_LOCK])
1054 return false;
1055 ins->prefixes[PPS_LOCK] = P_LOCK;
1056 }
1057 if (drep) {
1058 if (ins->prefixes[PPS_REP])
1059 return false;
1060 ins->prefixes[PPS_REP] = drep;
1061 }
1062 ins->prefixes[PPS_WAIT] = dwait;
1063 if (!o_used) {
1064 if (osize != ((segsize == 16) ? 16 : 32)) {
1065 enum prefixes pfx = 0;
1066
1067 switch (osize) {
1068 case 16:
1069 pfx = P_O16;
1070 break;
1071 case 32:
1072 pfx = P_O32;
1073 break;
1074 case 64:
1075 pfx = P_O64;
1076 break;
1077 }
1078
1079 if (ins->prefixes[PPS_OSIZE])
1080 return false;
1081 ins->prefixes[PPS_OSIZE] = pfx;
1082 }
1083 }
1084 if (!a_used && asize != segsize) {
1085 if (ins->prefixes[PPS_ASIZE])
1086 return false;
1087 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
1088 }
1089
1090 /* Fix: check for redundant REX prefixes */
1091
1092 return data - origdata;
1093 }
1094
1095 /* Condition names for disassembly, sorted by x86 code */
1096 static const char * const condition_name[16] = {
1097 "o", "no", "c", "nc", "z", "nz", "na", "a",
1098 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
1099 };
1100
1101 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
1102 int32_t offset, int autosync, iflag_t *prefer)
1103 {
1104 const struct itemplate * const *p, * const *best_p;
1105 const struct disasm_index *ix;
1106 uint8_t *dp;
1107 int length, best_length = 0;
1108 char *segover;
1109 int i, slen, colon, n;
1110 uint8_t *origdata;
1111 int works;
1112 insn tmp_ins, ins;
1113 iflag_t goodness, best;
1114 int best_pref;
1115 struct prefix_info prefix;
1116 bool end_prefix;
1117 bool is_evex;
1118
1119 memset(&ins, 0, sizeof ins);
1120
1121 /*
1122 * Scan for prefixes.
1123 */
1124 memset(&prefix, 0, sizeof prefix);
1125 prefix.asize = segsize;
1126 prefix.osize = (segsize == 64) ? 32 : segsize;
1127 segover = NULL;
1128 origdata = data;
1129
1130 ix = itable;
1131
1132 end_prefix = false;
1133 while (!end_prefix) {
1134 switch (*data) {
1135 case 0xF2:
1136 case 0xF3:
1137 prefix.rep = *data++;
1138 break;
1139
1140 case 0x9B:
1141 prefix.wait = *data++;
1142 break;
1143
1144 case 0xF0:
1145 prefix.lock = *data++;
1146 break;
1147
1148 case 0x2E:
1149 segover = "cs", prefix.seg = *data++;
1150 break;
1151 case 0x36:
1152 segover = "ss", prefix.seg = *data++;
1153 break;
1154 case 0x3E:
1155 segover = "ds", prefix.seg = *data++;
1156 break;
1157 case 0x26:
1158 segover = "es", prefix.seg = *data++;
1159 break;
1160 case 0x64:
1161 segover = "fs", prefix.seg = *data++;
1162 break;
1163 case 0x65:
1164 segover = "gs", prefix.seg = *data++;
1165 break;
1166
1167 case 0x66:
1168 prefix.osize = (segsize == 16) ? 32 : 16;
1169 prefix.osp = *data++;
1170 break;
1171 case 0x67:
1172 prefix.asize = (segsize == 32) ? 16 : 32;
1173 prefix.asp = *data++;
1174 break;
1175
1176 case 0xC4:
1177 case 0xC5:
1178 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1179 prefix.vex[0] = *data++;
1180 prefix.vex[1] = *data++;
1181
1182 prefix.rex = REX_V;
1183 prefix.vex_c = RV_VEX;
1184
1185 if (prefix.vex[0] == 0xc4) {
1186 prefix.vex[2] = *data++;
1187 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1188 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1189 prefix.vex_m = prefix.vex[1] & 0x1f;
1190 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1191 prefix.vex_lp = prefix.vex[2] & 7;
1192 } else {
1193 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1194 prefix.vex_m = 1;
1195 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1196 prefix.vex_lp = prefix.vex[1] & 7;
1197 }
1198
1199 ix = itable_vex[RV_VEX][prefix.vex_m][prefix.vex_lp & 3];
1200 }
1201 end_prefix = true;
1202 break;
1203
1204 case 0x62:
1205 {
1206 uint8_t evex_p0 = data[1] & 0x0f;
1207 if (segsize == 64 ||
1208 ((evex_p0 >= 0x01) && (evex_p0 <= 0x03))) {
1209 data++; /* 62h EVEX prefix */
1210 prefix.evex[0] = *data++;
1211 prefix.evex[1] = *data++;
1212 prefix.evex[2] = *data++;
1213
1214 prefix.rex = REX_EV;
1215 prefix.vex_c = RV_EVEX;
1216 prefix.rex |= (~prefix.evex[0] >> 5) & 7; /* REX_RXB */
1217 prefix.rex |= (prefix.evex[1] >> (7-3)) & REX_W;
1218 prefix.vex_m = prefix.evex[0] & EVEX_P0MM;
1219 prefix.vex_v = (~prefix.evex[1] & EVEX_P1VVVV) >> 3;
1220 prefix.vex_lp = ((prefix.evex[2] & EVEX_P2LL) >> (5-2)) |
1221 (prefix.evex[1] & EVEX_P1PP);
1222
1223 ix = itable_vex[prefix.vex_c][prefix.vex_m][prefix.vex_lp & 3];
1224 }
1225 end_prefix = true;
1226 break;
1227 }
1228
1229 case 0x8F:
1230 if ((data[1] & 030) != 0 &&
1231 (segsize == 64 || (data[1] & 0xc0) == 0xc0)) {
1232 prefix.vex[0] = *data++;
1233 prefix.vex[1] = *data++;
1234 prefix.vex[2] = *data++;
1235
1236 prefix.rex = REX_V;
1237 prefix.vex_c = RV_XOP;
1238
1239 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1240 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1241 prefix.vex_m = prefix.vex[1] & 0x1f;
1242 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1243 prefix.vex_lp = prefix.vex[2] & 7;
1244
1245 ix = itable_vex[RV_XOP][prefix.vex_m][prefix.vex_lp & 3];
1246 }
1247 end_prefix = true;
1248 break;
1249
1250 case REX_P + 0x0:
1251 case REX_P + 0x1:
1252 case REX_P + 0x2:
1253 case REX_P + 0x3:
1254 case REX_P + 0x4:
1255 case REX_P + 0x5:
1256 case REX_P + 0x6:
1257 case REX_P + 0x7:
1258 case REX_P + 0x8:
1259 case REX_P + 0x9:
1260 case REX_P + 0xA:
1261 case REX_P + 0xB:
1262 case REX_P + 0xC:
1263 case REX_P + 0xD:
1264 case REX_P + 0xE:
1265 case REX_P + 0xF:
1266 if (segsize == 64) {
1267 prefix.rex = *data++;
1268 if (prefix.rex & REX_W)
1269 prefix.osize = 64;
1270 }
1271 end_prefix = true;
1272 break;
1273
1274 default:
1275 end_prefix = true;
1276 break;
1277 }
1278 }
1279
1280 iflag_set_all(&best); /* Worst possible */
1281 best_p = NULL;
1282 best_pref = INT_MAX;
1283
1284 if (!ix)
1285 return 0; /* No instruction table at all... */
1286
1287 dp = data;
1288 ix += *dp++;
1289 while (ix->n == -1) {
1290 ix = (const struct disasm_index *)ix->p + *dp++;
1291 }
1292
1293 p = (const struct itemplate * const *)ix->p;
1294 for (n = ix->n; n; n--, p++) {
1295 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1296 works = true;
1297 /*
1298 * Final check to make sure the types of r/m match up.
1299 * XXX: Need to make sure this is actually correct.
1300 */
1301 for (i = 0; i < (*p)->operands; i++) {
1302 if (
1303 /* If it's a mem-only EA but we have a
1304 register, die. */
1305 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1306 is_class(MEMORY, (*p)->opd[i])) ||
1307 /* If it's a reg-only EA but we have a memory
1308 ref, die. */
1309 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1310 !(REG_EA & ~(*p)->opd[i]) &&
1311 !((*p)->opd[i] & REG_SMASK)) ||
1312 /* Register type mismatch (eg FS vs REG_DESS):
1313 die. */
1314 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1315 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1316 !whichreg((*p)->opd[i],
1317 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1318 ) {
1319 works = false;
1320 break;
1321 }
1322 }
1323
1324 /*
1325 * Note: we always prefer instructions which incorporate
1326 * prefixes in the instructions themselves. This is to allow
1327 * e.g. PAUSE to be preferred to REP NOP, and deal with
1328 * MMX/SSE instructions where prefixes are used to select
1329 * between MMX and SSE register sets or outright opcode
1330 * selection.
1331 */
1332 if (works) {
1333 int i, nprefix;
1334 goodness = iflag_pfmask(*p);
1335 goodness = iflag_xor(&goodness, prefer);
1336 nprefix = 0;
1337 for (i = 0; i < MAXPREFIX; i++)
1338 if (tmp_ins.prefixes[i])
1339 nprefix++;
1340 if (nprefix < best_pref ||
1341 (nprefix == best_pref &&
1342 iflag_cmp(&goodness, &best) < 0)) {
1343 /* This is the best one found so far */
1344 best = goodness;
1345 best_p = p;
1346 best_pref = nprefix;
1347 best_length = length;
1348 ins = tmp_ins;
1349 }
1350 }
1351 }
1352 }
1353
1354 if (!best_p)
1355 return 0; /* no instruction was matched */
1356
1357 /* Pick the best match */
1358 p = best_p;
1359 length = best_length;
1360
1361 slen = 0;
1362
1363 /* TODO: snprintf returns the value that the string would have if
1364 * the buffer were long enough, and not the actual length of
1365 * the returned string, so each instance of using the return
1366 * value of snprintf should actually be checked to assure that
1367 * the return value is "sane." Maybe a macro wrapper could
1368 * be used for that purpose.
1369 */
1370 for (i = 0; i < MAXPREFIX; i++) {
1371 const char *prefix = prefix_name(ins.prefixes[i]);
1372 if (prefix)
1373 slen += snprintf(output+slen, outbufsize-slen, "%s ", prefix);
1374 }
1375
1376 i = (*p)->opcode;
1377 if (i >= FIRST_COND_OPCODE)
1378 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1379 nasm_insn_names[i], condition_name[ins.condition]);
1380 else
1381 slen += snprintf(output + slen, outbufsize - slen, "%s",
1382 nasm_insn_names[i]);
1383
1384 colon = false;
1385 is_evex = !!(ins.rex & REX_EV);
1386 length += data - origdata; /* fix up for prefixes */
1387 for (i = 0; i < (*p)->operands; i++) {
1388 opflags_t t = (*p)->opd[i];
1389 decoflags_t deco = (*p)->deco[i];
1390 const operand *o = &ins.oprs[i];
1391 int64_t offs;
1392
1393 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1394
1395 offs = o->offset;
1396 if (o->segment & SEG_RELATIVE) {
1397 offs += offset + length;
1398 /*
1399 * sort out wraparound
1400 */
1401 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1402 offs &= 0xffff;
1403 else if (segsize != 64)
1404 offs &= 0xffffffff;
1405
1406 /*
1407 * add sync marker, if autosync is on
1408 */
1409 if (autosync)
1410 add_sync(offs, 0L);
1411 }
1412
1413 if (t & COLON)
1414 colon = true;
1415 else
1416 colon = false;
1417
1418 if ((t & (REGISTER | FPUREG)) ||
1419 (o->segment & SEG_RMREG)) {
1420 enum reg_enum reg;
1421 reg = whichreg(t, o->basereg, ins.rex);
1422 if (t & TO)
1423 slen += snprintf(output + slen, outbufsize - slen, "to ");
1424 slen += snprintf(output + slen, outbufsize - slen, "%s",
1425 nasm_reg_names[reg-EXPR_REG_START]);
1426 if (is_evex && deco)
1427 slen += append_evex_reg_deco(output + slen, outbufsize - slen,
1428 deco, ins.evex_p);
1429 } else if (!(UNITY & ~t)) {
1430 output[slen++] = '1';
1431 } else if (t & IMMEDIATE) {
1432 if (t & BITS8) {
1433 slen +=
1434 snprintf(output + slen, outbufsize - slen, "byte ");
1435 if (o->segment & SEG_SIGNED) {
1436 if (offs < 0) {
1437 offs *= -1;
1438 output[slen++] = '-';
1439 } else
1440 output[slen++] = '+';
1441 }
1442 } else if (t & BITS16) {
1443 slen +=
1444 snprintf(output + slen, outbufsize - slen, "word ");
1445 } else if (t & BITS32) {
1446 slen +=
1447 snprintf(output + slen, outbufsize - slen, "dword ");
1448 } else if (t & BITS64) {
1449 slen +=
1450 snprintf(output + slen, outbufsize - slen, "qword ");
1451 } else if (t & NEAR) {
1452 slen +=
1453 snprintf(output + slen, outbufsize - slen, "near ");
1454 } else if (t & SHORT) {
1455 slen +=
1456 snprintf(output + slen, outbufsize - slen, "short ");
1457 }
1458 slen +=
1459 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1460 offs);
1461 } else if (!(MEM_OFFS & ~t)) {
1462 slen +=
1463 snprintf(output + slen, outbufsize - slen,
1464 "[%s%s%s0x%"PRIx64"]",
1465 (segover ? segover : ""),
1466 (segover ? ":" : ""),
1467 (o->disp_size == 64 ? "qword " :
1468 o->disp_size == 32 ? "dword " :
1469 o->disp_size == 16 ? "word " : ""), offs);
1470 segover = NULL;
1471 } else if (is_class(REGMEM, t)) {
1472 int started = false;
1473 if (t & BITS8)
1474 slen +=
1475 snprintf(output + slen, outbufsize - slen, "byte ");
1476 if (t & BITS16)
1477 slen +=
1478 snprintf(output + slen, outbufsize - slen, "word ");
1479 if (t & BITS32)
1480 slen +=
1481 snprintf(output + slen, outbufsize - slen, "dword ");
1482 if (t & BITS64)
1483 slen +=
1484 snprintf(output + slen, outbufsize - slen, "qword ");
1485 if (t & BITS80)
1486 slen +=
1487 snprintf(output + slen, outbufsize - slen, "tword ");
1488 if ((ins.evex_p[2] & EVEX_P2B) && (deco & BRDCAST_MASK)) {
1489 /* when broadcasting, each element size should be used */
1490 if (deco & BR_BITS32)
1491 slen +=
1492 snprintf(output + slen, outbufsize - slen, "dword ");
1493 else if (deco & BR_BITS64)
1494 slen +=
1495 snprintf(output + slen, outbufsize - slen, "qword ");
1496 } else {
1497 if (t & BITS128)
1498 slen +=
1499 snprintf(output + slen, outbufsize - slen, "oword ");
1500 if (t & BITS256)
1501 slen +=
1502 snprintf(output + slen, outbufsize - slen, "yword ");
1503 if (t & BITS512)
1504 slen +=
1505 snprintf(output + slen, outbufsize - slen, "zword ");
1506 }
1507 if (t & FAR)
1508 slen += snprintf(output + slen, outbufsize - slen, "far ");
1509 if (t & NEAR)
1510 slen +=
1511 snprintf(output + slen, outbufsize - slen, "near ");
1512 output[slen++] = '[';
1513 if (o->disp_size)
1514 slen += snprintf(output + slen, outbufsize - slen, "%s",
1515 (o->disp_size == 64 ? "qword " :
1516 o->disp_size == 32 ? "dword " :
1517 o->disp_size == 16 ? "word " :
1518 ""));
1519 if (o->eaflags & EAF_REL)
1520 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1521 if (segover) {
1522 slen +=
1523 snprintf(output + slen, outbufsize - slen, "%s:",
1524 segover);
1525 segover = NULL;
1526 }
1527 if (o->basereg != -1) {
1528 slen += snprintf(output + slen, outbufsize - slen, "%s",
1529 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1530 started = true;
1531 }
1532 if (o->indexreg != -1 && !itemp_has(*best_p, IF_MIB)) {
1533 if (started)
1534 output[slen++] = '+';
1535 slen += snprintf(output + slen, outbufsize - slen, "%s",
1536 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1537 if (o->scale > 1)
1538 slen +=
1539 snprintf(output + slen, outbufsize - slen, "*%d",
1540 o->scale);
1541 started = true;
1542 }
1543
1544
1545 if (o->segment & SEG_DISP8) {
1546 if (is_evex) {
1547 const char *prefix;
1548 uint32_t offset = offs;
1549 if ((int32_t)offset < 0) {
1550 prefix = "-";
1551 offset = -offset;
1552 } else {
1553 prefix = "+";
1554 }
1555 slen +=
1556 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx32"",
1557 prefix, offset);
1558 } else {
1559 const char *prefix;
1560 uint8_t offset = offs;
1561 if ((int8_t)offset < 0) {
1562 prefix = "-";
1563 offset = -offset;
1564 } else {
1565 prefix = "+";
1566 }
1567 slen +=
1568 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1569 prefix, offset);
1570 }
1571 } else if (o->segment & SEG_DISP16) {
1572 const char *prefix;
1573 uint16_t offset = offs;
1574 if ((int16_t)offset < 0 && started) {
1575 offset = -offset;
1576 prefix = "-";
1577 } else {
1578 prefix = started ? "+" : "";
1579 }
1580 slen +=
1581 snprintf(output + slen, outbufsize - slen,
1582 "%s0x%"PRIx16"", prefix, offset);
1583 } else if (o->segment & SEG_DISP32) {
1584 if (prefix.asize == 64) {
1585 const char *prefix;
1586 uint64_t offset = (int64_t)(int32_t)offs;
1587 if ((int32_t)offs < 0 && started) {
1588 offset = -offset;
1589 prefix = "-";
1590 } else {
1591 prefix = started ? "+" : "";
1592 }
1593 slen +=
1594 snprintf(output + slen, outbufsize - slen,
1595 "%s0x%"PRIx64"", prefix, offset);
1596 } else {
1597 const char *prefix;
1598 uint32_t offset = offs;
1599 if ((int32_t) offset < 0 && started) {
1600 offset = -offset;
1601 prefix = "-";
1602 } else {
1603 prefix = started ? "+" : "";
1604 }
1605 slen +=
1606 snprintf(output + slen, outbufsize - slen,
1607 "%s0x%"PRIx32"", prefix, offset);
1608 }
1609 }
1610
1611 if (o->indexreg != -1 && itemp_has(*best_p, IF_MIB)) {
1612 output[slen++] = ',';
1613 slen += snprintf(output + slen, outbufsize - slen, "%s",
1614 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1615 if (o->scale > 1)
1616 slen +=
1617 snprintf(output + slen, outbufsize - slen, "*%d",
1618 o->scale);
1619 started = true;
1620 }
1621
1622 output[slen++] = ']';
1623
1624 if (is_evex && deco)
1625 slen += append_evex_mem_deco(output + slen, outbufsize - slen,
1626 t, deco, ins.evex_p);
1627 } else {
1628 slen +=
1629 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1630 i);
1631 }
1632 }
1633 output[slen] = '\0';
1634 if (segover) { /* unused segment override */
1635 char *p = output;
1636 int count = slen + 1;
1637 while (count--)
1638 p[count + 3] = p[count];
1639 strncpy(output, segover, 2);
1640 output[2] = ' ';
1641 }
1642 return length;
1643 }
1644
1645 /*
1646 * This is called when we don't have a complete instruction. If it
1647 * is a standalone *single-byte* prefix show it as such, otherwise
1648 * print it as a literal.
1649 */
1650 int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize)
1651 {
1652 uint8_t byte = *data;
1653 const char *str = NULL;
1654
1655 switch (byte) {
1656 case 0xF2:
1657 str = "repne";
1658 break;
1659 case 0xF3:
1660 str = "rep";
1661 break;
1662 case 0x9B:
1663 str = "wait";
1664 break;
1665 case 0xF0:
1666 str = "lock";
1667 break;
1668 case 0x2E:
1669 str = "cs";
1670 break;
1671 case 0x36:
1672 str = "ss";
1673 break;
1674 case 0x3E:
1675 str = "ss";
1676 break;
1677 case 0x26:
1678 str = "es";
1679 break;
1680 case 0x64:
1681 str = "fs";
1682 break;
1683 case 0x65:
1684 str = "gs";
1685 break;
1686 case 0x66:
1687 str = (segsize == 16) ? "o32" : "o16";
1688 break;
1689 case 0x67:
1690 str = (segsize == 32) ? "a16" : "a32";
1691 break;
1692 case REX_P + 0x0:
1693 case REX_P + 0x1:
1694 case REX_P + 0x2:
1695 case REX_P + 0x3:
1696 case REX_P + 0x4:
1697 case REX_P + 0x5:
1698 case REX_P + 0x6:
1699 case REX_P + 0x7:
1700 case REX_P + 0x8:
1701 case REX_P + 0x9:
1702 case REX_P + 0xA:
1703 case REX_P + 0xB:
1704 case REX_P + 0xC:
1705 case REX_P + 0xD:
1706 case REX_P + 0xE:
1707 case REX_P + 0xF:
1708 if (segsize == 64) {
1709 snprintf(output, outbufsize, "rex%s%s%s%s%s",
1710 (byte == REX_P) ? "" : ".",
1711 (byte & REX_W) ? "w" : "",
1712 (byte & REX_R) ? "r" : "",
1713 (byte & REX_X) ? "x" : "",
1714 (byte & REX_B) ? "b" : "");
1715 break;
1716 }
1717 /* else fall through */
1718 default:
1719 snprintf(output, outbufsize, "db 0x%02x", byte);
1720 break;
1721 }
1722
1723 if (str)
1724 snprintf(output, outbufsize, "%s", str);
1725
1726 return 1;
1727 }
The Netwide Assembler