1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2013 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * assemble.c code generation for the Netwide Assembler
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - the position of index register operand in MIB (BND insns)
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \172\ab - the register number from operand a in bits 7..4, with
64 * the 4-bit immediate from operand b in bits 3..0.
65 * \173\xab - the register number from operand a in bits 7..4, with
66 * the value b in bits 3..0.
67 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
68 * an arbitrary value in bits 3..0 (assembled as zero.)
69 * \2ab - a ModRM, calculated on EA in operand a, with the spare
70 * field equal to digit b.
72 * \240..\243 - this instruction uses EVEX rather than REX or VEX/XOP, with the
73 * V field taken from operand 0..3.
74 * \250 - this instruction uses EVEX rather than REX or VEX/XOP, with the
75 * V field set to 1111b.
76 * EVEX prefixes are followed by the sequence:
77 * \cm\wlp\tup where cm is:
79 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
82 * [l0] ll = 0 (.128, .lz)
85 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
87 * [w0] ww = 0 for W = 0
88 * [w1] ww = 1 for W = 1
89 * [wig] ww = 2 for W don't care (always assembled as 0)
90 * [ww] ww = 3 for W used as REX.W
92 * [p0] pp = 0 for no prefix
93 * [60] pp = 1 for legacy prefix 60
97 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
98 * (compressed displacement encoding)
100 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
101 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
102 * V field taken from operand 0..3.
103 * \270 - this instruction uses VEX/XOP rather than REX, with the
104 * V field set to 1111b.
106 * VEX/XOP prefixes are followed by the sequence:
107 * \tmm\wlp where mm is the M field; and wlp is:
109 * [l0] ll = 0 for L = 0 (.128, .lz)
110 * [l1] ll = 1 for L = 1 (.256)
111 * [lig] ll = 2 for L don't care (always assembled as 0)
113 * [w0] ww = 0 for W = 0
114 * [w1 ] ww = 1 for W = 1
115 * [wig] ww = 2 for W don't care (always assembled as 0)
116 * [ww] ww = 3 for W used as REX.W
118 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
120 * \271 - instruction takes XRELEASE (F3) with or without lock
121 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
122 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
123 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
124 * to the operand size (if o16/o32/o64 present) or the bit size
125 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
126 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
127 * \312 - (disassembler only) invalid with non-default address size.
128 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
129 * \314 - (disassembler only) invalid with REX.B
130 * \315 - (disassembler only) invalid with REX.X
131 * \316 - (disassembler only) invalid with REX.R
132 * \317 - (disassembler only) invalid with REX.W
133 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
134 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
135 * \322 - indicates that this instruction is only valid when the
136 * operand size is the default (instruction to disassembler,
137 * generates no code in the assembler)
138 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
139 * \324 - indicates 64-bit operand size requiring REX prefix.
140 * \325 - instruction which always uses spl/bpl/sil/dil
141 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
142 disassembler only; for SSE instructions.
143 * \330 - a literal byte follows in the code stream, to be added
144 * to the condition code value of the instruction.
145 * \331 - instruction not valid with REP prefix. Hint for
146 * disassembler only; for SSE instructions.
147 * \332 - REP prefix (0xF2 byte) used as opcode extension.
148 * \333 - REP prefix (0xF3 byte) used as opcode extension.
149 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
150 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
151 * \336 - force a REP(E) prefix (0xF3) even if not specified.
152 * \337 - force a REPNE prefix (0xF2) even if not specified.
153 * \336-\337 are still listed as prefixes in the disassembler.
154 * \340 - reserve <operand 0> bytes of uninitialized storage.
155 * Operand 0 had better be a segmentless constant.
156 * \341 - this instruction needs a WAIT "prefix"
157 * \360 - no SSE prefix (== \364\331)
158 * \361 - 66 SSE prefix (== \366\331)
159 * \364 - operand-size prefix (0x66) not permitted
160 * \365 - address-size prefix (0x67) not permitted
161 * \366 - operand-size prefix (0x66) used as opcode extension
162 * \367 - address-size prefix (0x67) used as opcode extension
163 * \370,\371 - match only if operand 0 meets byte jump criteria.
164 * 370 is used for Jcc, 371 is used for JMP.
165 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
166 * used for conditional jump over longer jump
167 * \374 - this instruction takes an XMM VSIB memory EA
168 * \375 - this instruction takes an YMM VSIB memory EA
169 * \376 - this instruction takes an ZMM VSIB memory EA
172 #include "compiler.h"
176 #include <inttypes.h>
180 #include "assemble.h"
187 * Matching errors. These should be sorted so that more specific
188 * errors come later in the sequence.
201 * Matching success; the conditional ones first
203 MOK_JUMP
, /* Matching OK but needs jmp_match() */
204 MOK_GOOD
/* Matching unconditionally OK */
208 enum ea_type type
; /* what kind of EA is this? */
209 int sib_present
; /* is a SIB byte necessary? */
210 int bytes
; /* # of bytes of offset needed */
211 int size
; /* lazy - this is sib+bytes+1 */
212 uint8_t modrm
, sib
, rex
, rip
; /* the bytes themselves */
213 int8_t disp8
; /* compressed displacement for EVEX */
216 #define GEN_SIB(scale, index, base) \
217 (((scale) << 6) | ((index) << 3) | ((base)))
219 #define GEN_MODRM(mod, reg, rm) \
220 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
222 static iflag_t cpu
; /* cpu level received from nasm.c */
223 static efunc errfunc
;
224 static struct ofmt
*outfmt
;
225 static ListGen
*list
;
227 static int64_t calcsize(int32_t, int64_t, int, insn
*,
228 const struct itemplate
*);
229 static void gencode(int32_t segment
, int64_t offset
, int bits
,
230 insn
* ins
, const struct itemplate
*temp
,
232 static enum match_result
find_match(const struct itemplate
**tempp
,
234 int32_t segment
, int64_t offset
, int bits
);
235 static enum match_result
matches(const struct itemplate
*, insn
*, int bits
);
236 static opflags_t
regflag(const operand
*);
237 static int32_t regval(const operand
*);
238 static int rexflags(int, opflags_t
, int);
239 static int op_rexflags(const operand
*, int);
240 static int op_evexflags(const operand
*, int, uint8_t);
241 static void add_asp(insn
*, int);
243 static enum ea_type
process_ea(operand
*, ea
*, int, int, opflags_t
, insn
*);
245 static int has_prefix(insn
* ins
, enum prefix_pos pos
, int prefix
)
247 return ins
->prefixes
[pos
] == prefix
;
250 static void assert_no_prefix(insn
* ins
, enum prefix_pos pos
)
252 if (ins
->prefixes
[pos
])
253 errfunc(ERR_NONFATAL
, "invalid %s prefix",
254 prefix_name(ins
->prefixes
[pos
]));
257 static const char *size_name(int size
)
281 static void warn_overflow(int pass
, int size
)
283 errfunc(ERR_WARNING
| pass
| ERR_WARN_NOV
,
284 "%s data exceeds bounds", size_name(size
));
287 static void warn_overflow_const(int64_t data
, int size
)
289 if (overflow_general(data
, size
))
290 warn_overflow(ERR_PASS1
, size
);
293 static void warn_overflow_opd(const struct operand
*o
, int size
)
295 if (o
->wrt
== NO_SEG
&& o
->segment
== NO_SEG
) {
296 if (overflow_general(o
->offset
, size
))
297 warn_overflow(ERR_PASS2
, size
);
302 * This routine wrappers the real output format's output routine,
303 * in order to pass a copy of the data off to the listing file
304 * generator at the same time.
306 static void out(int64_t offset
, int32_t segto
, const void *data
,
307 enum out_type type
, uint64_t size
,
308 int32_t segment
, int32_t wrt
)
310 static int32_t lineno
= 0; /* static!!! */
311 static char *lnfname
= NULL
;
314 if (type
== OUT_ADDRESS
&& segment
== NO_SEG
&& wrt
== NO_SEG
) {
316 * This is a non-relocated address, and we're going to
317 * convert it into RAWDATA format.
322 errfunc(ERR_PANIC
, "OUT_ADDRESS with size > 8");
326 WRITEADDR(q
, *(int64_t *)data
, size
);
331 list
->output(offset
, data
, type
, size
);
334 * this call to src_get determines when we call the
335 * debug-format-specific "linenum" function
336 * it updates lineno and lnfname to the current values
337 * returning 0 if "same as last time", -2 if lnfname
338 * changed, and the amount by which lineno changed,
339 * if it did. thus, these variables must be static
342 if (src_get(&lineno
, &lnfname
))
343 outfmt
->current_dfmt
->linenum(lnfname
, lineno
, segto
);
345 outfmt
->output(segto
, data
, type
, size
, segment
, wrt
);
348 static void out_imm8(int64_t offset
, int32_t segment
, struct operand
*opx
)
350 if (opx
->segment
!= NO_SEG
) {
351 uint64_t data
= opx
->offset
;
352 out(offset
, segment
, &data
, OUT_ADDRESS
, 1, opx
->segment
, opx
->wrt
);
354 uint8_t byte
= opx
->offset
;
355 out(offset
, segment
, &byte
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
359 static bool jmp_match(int32_t segment
, int64_t offset
, int bits
,
360 insn
* ins
, const struct itemplate
*temp
)
363 const uint8_t *code
= temp
->code
;
367 if (((c
& ~1) != 0370) || (ins
->oprs
[0].type
& STRICT
))
371 if (optimizing
< 0 && c
== 0371)
374 isize
= calcsize(segment
, offset
, bits
, ins
, temp
);
376 if (ins
->oprs
[0].opflags
& OPFLAG_UNKNOWN
)
377 /* Be optimistic in pass 1 */
380 if (ins
->oprs
[0].segment
!= segment
)
383 isize
= ins
->oprs
[0].offset
- offset
- isize
; /* isize is delta */
384 is_byte
= (isize
>= -128 && isize
<= 127); /* is it byte size? */
386 if (is_byte
&& c
== 0371 && ins
->prefixes
[PPS_REP
] == P_BND
) {
387 /* jmp short (opcode eb) cannot be used with bnd prefix. */
388 ins
->prefixes
[PPS_REP
] = P_none
;
389 errfunc(ERR_WARNING
| ERR_WARN_BND
| ERR_PASS2
,
390 "jmp short does not init bnd regs - bnd prefix dropped.");
396 int64_t assemble(int32_t segment
, int64_t offset
, int bits
, iflag_t cp
,
397 insn
* instruction
, struct ofmt
*output
, efunc error
,
400 const struct itemplate
*temp
;
405 int64_t start
= offset
;
406 int64_t wsize
; /* size for DB etc. */
408 errfunc
= error
; /* to pass to other functions */
410 outfmt
= output
; /* likewise */
411 list
= listgen
; /* and again */
413 wsize
= idata_bytes(instruction
->opcode
);
419 int32_t t
= instruction
->times
;
422 "instruction->times < 0 (%ld) in assemble()", t
);
424 while (t
--) { /* repeat TIMES times */
425 list_for_each(e
, instruction
->eops
) {
426 if (e
->type
== EOT_DB_NUMBER
) {
428 errfunc(ERR_NONFATAL
,
429 "integer supplied to a DT, DO or DY"
432 out(offset
, segment
, &e
->offset
,
433 OUT_ADDRESS
, wsize
, e
->segment
, e
->wrt
);
436 } else if (e
->type
== EOT_DB_STRING
||
437 e
->type
== EOT_DB_STRING_FREE
) {
440 out(offset
, segment
, e
->stringval
,
441 OUT_RAWDATA
, e
->stringlen
, NO_SEG
, NO_SEG
);
442 align
= e
->stringlen
% wsize
;
445 align
= wsize
- align
;
446 out(offset
, segment
, zero_buffer
,
447 OUT_RAWDATA
, align
, NO_SEG
, NO_SEG
);
449 offset
+= e
->stringlen
+ align
;
452 if (t
> 0 && t
== instruction
->times
- 1) {
454 * Dummy call to list->output to give the offset to the
457 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
458 list
->uplevel(LIST_TIMES
);
461 if (instruction
->times
> 1)
462 list
->downlevel(LIST_TIMES
);
463 return offset
- start
;
466 if (instruction
->opcode
== I_INCBIN
) {
467 const char *fname
= instruction
->eops
->stringval
;
470 fp
= fopen(fname
, "rb");
472 error(ERR_NONFATAL
, "`incbin': unable to open file `%s'",
474 } else if (fseek(fp
, 0L, SEEK_END
) < 0) {
475 error(ERR_NONFATAL
, "`incbin': unable to seek on file `%s'",
479 static char buf
[4096];
480 size_t t
= instruction
->times
;
485 if (instruction
->eops
->next
) {
486 base
= instruction
->eops
->next
->offset
;
488 if (instruction
->eops
->next
->next
&&
489 len
> (size_t)instruction
->eops
->next
->next
->offset
)
490 len
= (size_t)instruction
->eops
->next
->next
->offset
;
493 * Dummy call to list->output to give the offset to the
496 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
497 list
->uplevel(LIST_INCBIN
);
501 fseek(fp
, base
, SEEK_SET
);
505 m
= fread(buf
, 1, l
> sizeof(buf
) ? sizeof(buf
) : l
, fp
);
508 * This shouldn't happen unless the file
509 * actually changes while we are reading
513 "`incbin': unexpected EOF while"
514 " reading file `%s'", fname
);
515 t
= 0; /* Try to exit cleanly */
518 out(offset
, segment
, buf
, OUT_RAWDATA
, m
,
523 list
->downlevel(LIST_INCBIN
);
524 if (instruction
->times
> 1) {
526 * Dummy call to list->output to give the offset to the
529 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
530 list
->uplevel(LIST_TIMES
);
531 list
->downlevel(LIST_TIMES
);
534 return instruction
->times
* len
;
536 return 0; /* if we're here, there's an error */
539 /* Check to see if we need an address-size prefix */
540 add_asp(instruction
, bits
);
542 m
= find_match(&temp
, instruction
, segment
, offset
, bits
);
546 int64_t insn_size
= calcsize(segment
, offset
, bits
, instruction
, temp
);
547 itimes
= instruction
->times
;
548 if (insn_size
< 0) /* shouldn't be, on pass two */
549 error(ERR_PANIC
, "errors made it through from pass one");
552 for (j
= 0; j
< MAXPREFIX
; j
++) {
554 switch (instruction
->prefixes
[j
]) {
575 error(ERR_WARNING
| ERR_PASS2
,
576 "cs segment base generated, but will be ignored in 64-bit mode");
582 error(ERR_WARNING
| ERR_PASS2
,
583 "ds segment base generated, but will be ignored in 64-bit mode");
589 error(ERR_WARNING
| ERR_PASS2
,
590 "es segment base generated, but will be ignored in 64-bit mode");
602 error(ERR_WARNING
| ERR_PASS2
,
603 "ss segment base generated, but will be ignored in 64-bit mode");
610 "segr6 and segr7 cannot be used as prefixes");
615 "16-bit addressing is not supported "
617 } else if (bits
!= 16)
627 "64-bit addressing is only supported "
655 error(ERR_PANIC
, "invalid instruction prefix");
658 out(offset
, segment
, &c
, OUT_RAWDATA
, 1,
663 insn_end
= offset
+ insn_size
;
664 gencode(segment
, offset
, bits
, instruction
,
667 if (itimes
> 0 && itimes
== instruction
->times
- 1) {
669 * Dummy call to list->output to give the offset to the
672 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
673 list
->uplevel(LIST_TIMES
);
676 if (instruction
->times
> 1)
677 list
->downlevel(LIST_TIMES
);
678 return offset
- start
;
682 case MERR_OPSIZEMISSING
:
683 error(ERR_NONFATAL
, "operation size not specified");
685 case MERR_OPSIZEMISMATCH
:
686 error(ERR_NONFATAL
, "mismatch in operand sizes");
688 case MERR_BRNUMMISMATCH
:
690 "mismatch in the number of broadcasting elements");
693 error(ERR_NONFATAL
, "no instruction for this cpu level");
696 error(ERR_NONFATAL
, "instruction not supported in %d-bit mode",
699 case MERR_ENCMISMATCH
:
700 error(ERR_NONFATAL
, "specific encoding scheme not available");
703 error(ERR_NONFATAL
, "bnd prefix is not allowed");
706 error(ERR_NONFATAL
, "%s prefix is not allowed",
707 (has_prefix(instruction
, PPS_REP
, P_REPNE
) ?
712 "invalid combination of opcode and operands");
719 int64_t insn_size(int32_t segment
, int64_t offset
, int bits
, iflag_t cp
,
720 insn
* instruction
, efunc error
)
722 const struct itemplate
*temp
;
725 errfunc
= error
; /* to pass to other functions */
728 if (instruction
->opcode
== I_none
)
731 if (instruction
->opcode
== I_DB
|| instruction
->opcode
== I_DW
||
732 instruction
->opcode
== I_DD
|| instruction
->opcode
== I_DQ
||
733 instruction
->opcode
== I_DT
|| instruction
->opcode
== I_DO
||
734 instruction
->opcode
== I_DY
) {
736 int32_t isize
, osize
, wsize
;
739 wsize
= idata_bytes(instruction
->opcode
);
741 list_for_each(e
, instruction
->eops
) {
745 if (e
->type
== EOT_DB_NUMBER
) {
747 warn_overflow_const(e
->offset
, wsize
);
748 } else if (e
->type
== EOT_DB_STRING
||
749 e
->type
== EOT_DB_STRING_FREE
)
750 osize
= e
->stringlen
;
752 align
= (-osize
) % wsize
;
755 isize
+= osize
+ align
;
757 return isize
* instruction
->times
;
760 if (instruction
->opcode
== I_INCBIN
) {
761 const char *fname
= instruction
->eops
->stringval
;
766 fp
= fopen(fname
, "rb");
768 error(ERR_NONFATAL
, "`incbin': unable to open file `%s'",
770 else if (fseek(fp
, 0L, SEEK_END
) < 0)
771 error(ERR_NONFATAL
, "`incbin': unable to seek on file `%s'",
775 if (instruction
->eops
->next
) {
776 len
-= instruction
->eops
->next
->offset
;
777 if (instruction
->eops
->next
->next
&&
778 len
> (size_t)instruction
->eops
->next
->next
->offset
) {
779 len
= (size_t)instruction
->eops
->next
->next
->offset
;
782 val
= instruction
->times
* len
;
789 /* Check to see if we need an address-size prefix */
790 add_asp(instruction
, bits
);
792 m
= find_match(&temp
, instruction
, segment
, offset
, bits
);
794 /* we've matched an instruction. */
798 isize
= calcsize(segment
, offset
, bits
, instruction
, temp
);
801 for (j
= 0; j
< MAXPREFIX
; j
++) {
802 switch (instruction
->prefixes
[j
]) {
832 return isize
* instruction
->times
;
834 return -1; /* didn't match any instruction */
838 static void bad_hle_warn(const insn
* ins
, uint8_t hleok
)
840 enum prefixes rep_pfx
= ins
->prefixes
[PPS_REP
];
841 enum whatwarn
{ w_none
, w_lock
, w_inval
} ww
;
842 static const enum whatwarn warn
[2][4] =
844 { w_inval
, w_inval
, w_none
, w_lock
}, /* XACQUIRE */
845 { w_inval
, w_none
, w_none
, w_lock
}, /* XRELEASE */
849 n
= (unsigned int)rep_pfx
- P_XACQUIRE
;
851 return; /* Not XACQUIRE/XRELEASE */
854 if (!is_class(MEMORY
, ins
->oprs
[0].type
))
855 ww
= w_inval
; /* HLE requires operand 0 to be memory */
862 if (ins
->prefixes
[PPS_LOCK
] != P_LOCK
) {
863 errfunc(ERR_WARNING
| ERR_WARN_HLE
| ERR_PASS2
,
864 "%s with this instruction requires lock",
865 prefix_name(rep_pfx
));
870 errfunc(ERR_WARNING
| ERR_WARN_HLE
| ERR_PASS2
,
871 "%s invalid with this instruction",
872 prefix_name(rep_pfx
));
877 /* Common construct */
878 #define case3(x) case (x): case (x)+1: case (x)+2
879 #define case4(x) case3(x): case (x)+3
881 static int64_t calcsize(int32_t segment
, int64_t offset
, int bits
,
882 insn
* ins
, const struct itemplate
*temp
)
884 const uint8_t *codes
= temp
->code
;
893 bool lockcheck
= true;
894 enum reg_enum mib_index
= R_none
; /* For a separate index MIB reg form */
896 ins
->rex
= 0; /* Ensure REX is reset */
897 eat
= EA_SCALAR
; /* Expect a scalar EA */
898 memset(ins
->evex_p
, 0, 3); /* Ensure EVEX is reset */
900 if (ins
->prefixes
[PPS_OSIZE
] == P_O64
)
903 (void)segment
; /* Don't warn that this parameter is unused */
904 (void)offset
; /* Don't warn that this parameter is unused */
908 op1
= (c
& 3) + ((opex
& 1) << 2);
909 op2
= ((c
>> 3) & 3) + ((opex
& 2) << 1);
910 opx
= &ins
->oprs
[op1
];
911 opex
= 0; /* For the next iteration */
915 codes
+= c
, length
+= c
;
924 op_rexflags(opx
, REX_B
|REX_H
|REX_P
|REX_W
);
929 /* this is an index reg of MIB operand */
930 mib_index
= opx
->basereg
;
943 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
944 length
+= (opx
->type
& BITS16
) ? 2 : 4;
946 length
+= (bits
== 16) ? 2 : 4;
954 length
+= ins
->addr_size
>> 3;
962 length
+= 8; /* MOV reg64/imm */
970 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
971 length
+= (opx
->type
& BITS16
) ? 2 : 4;
973 length
+= (bits
== 16) ? 2 : 4;
996 ins
->vexreg
= regval(opx
);
997 ins
->evex_p
[2] |= op_evexflags(opx
, EVEX_P2VP
, 2); /* High-16 NDS */
998 ins
->vex_cm
= *codes
++;
999 ins
->vex_wlp
= *codes
++;
1000 ins
->evex_tuple
= (*codes
++ - 0300);
1006 ins
->vex_cm
= *codes
++;
1007 ins
->vex_wlp
= *codes
++;
1008 ins
->evex_tuple
= (*codes
++ - 0300);
1017 ins
->vexreg
= regval(opx
);
1018 ins
->vex_cm
= *codes
++;
1019 ins
->vex_wlp
= *codes
++;
1025 ins
->vex_cm
= *codes
++;
1026 ins
->vex_wlp
= *codes
++;
1043 length
+= (bits
!= 16) && !has_prefix(ins
, PPS_ASIZE
, P_A16
);
1047 length
+= (bits
!= 32) && !has_prefix(ins
, PPS_ASIZE
, P_A32
);
1054 if (bits
!= 64 || has_prefix(ins
, PPS_ASIZE
, P_A16
) ||
1055 has_prefix(ins
, PPS_ASIZE
, P_A32
))
1064 enum prefixes pfx
= ins
->prefixes
[PPS_OSIZE
];
1068 errfunc(ERR_WARNING
| ERR_PASS2
, "invalid operand size prefix");
1070 ins
->prefixes
[PPS_OSIZE
] = P_O16
;
1076 enum prefixes pfx
= ins
->prefixes
[PPS_OSIZE
];
1080 errfunc(ERR_WARNING
| ERR_PASS2
, "invalid operand size prefix");
1082 ins
->prefixes
[PPS_OSIZE
] = P_O32
;
1124 if (!ins
->prefixes
[PPS_REP
])
1125 ins
->prefixes
[PPS_REP
] = P_REP
;
1129 if (!ins
->prefixes
[PPS_REP
])
1130 ins
->prefixes
[PPS_REP
] = P_REPNE
;
1134 if (ins
->oprs
[0].segment
!= NO_SEG
)
1135 errfunc(ERR_NONFATAL
, "attempt to reserve non-constant"
1136 " quantity of BSS space");
1138 length
+= ins
->oprs
[0].offset
;
1142 if (!ins
->prefixes
[PPS_WAIT
])
1143 ins
->prefixes
[PPS_WAIT
] = P_WAIT
;
1198 struct operand
*opy
= &ins
->oprs
[op2
];
1199 struct operand
*op_er_sae
;
1201 ea_data
.rex
= 0; /* Ensure ea.REX is initially 0 */
1204 /* pick rfield from operand b (opx) */
1205 rflags
= regflag(opx
);
1206 rfield
= nasm_regvals
[opx
->basereg
];
1212 /* EVEX.b1 : evex_brerop contains the operand position */
1213 op_er_sae
= (ins
->evex_brerop
>= 0 ?
1214 &ins
->oprs
[ins
->evex_brerop
] : NULL
);
1216 if (op_er_sae
&& (op_er_sae
->decoflags
& (ER
| SAE
))) {
1218 ins
->evex_p
[2] |= EVEX_P2B
;
1219 if (op_er_sae
->decoflags
& ER
) {
1220 /* set EVEX.RC (rounding control) */
1221 ins
->evex_p
[2] |= ((ins
->evex_rm
- BRC_RN
) << 5)
1225 /* set EVEX.L'L (vector length) */
1226 ins
->evex_p
[2] |= ((ins
->vex_wlp
<< (5 - 2)) & EVEX_P2LL
);
1227 ins
->evex_p
[1] |= ((ins
->vex_wlp
<< (7 - 4)) & EVEX_P1W
);
1228 if (opy
->decoflags
& BRDCAST_MASK
) {
1230 ins
->evex_p
[2] |= EVEX_P2B
;
1235 * if a separate form of MIB (ICC style) is used,
1236 * the index reg info is merged into mem operand
1238 if (mib_index
!= R_none
) {
1239 opy
->indexreg
= mib_index
;
1241 opy
->hintbase
= mib_index
;
1242 opy
->hinttype
= EAH_NOTBASE
;
1246 * only for mib operands, make a single reg index [reg*1].
1247 * gas uses this form to explicitly denote index register.
1249 if (itemp_has(temp
, IF_MIB
) &&
1250 (opy
->indexreg
== -1 && opy
->hintbase
== opy
->basereg
&&
1251 opy
->hinttype
== EAH_NOTBASE
)) {
1252 opy
->indexreg
= opy
->basereg
;
1257 if (process_ea(opy
, &ea_data
, bits
,
1258 rfield
, rflags
, ins
) != eat
) {
1259 errfunc(ERR_NONFATAL
, "invalid effective address");
1262 ins
->rex
|= ea_data
.rex
;
1263 length
+= ea_data
.size
;
1269 errfunc(ERR_PANIC
, "internal instruction table corrupt"
1270 ": instruction code \\%o (0x%02X) given", c
, c
);
1275 ins
->rex
&= rex_mask
;
1277 if (ins
->rex
& REX_NH
) {
1278 if (ins
->rex
& REX_H
) {
1279 errfunc(ERR_NONFATAL
, "instruction cannot use high registers");
1282 ins
->rex
&= ~REX_P
; /* Don't force REX prefix due to high reg */
1285 switch (ins
->prefixes
[PPS_VEX
]) {
1287 if (!(ins
->rex
& REX_EV
))
1292 if (!(ins
->rex
& REX_V
))
1299 if (ins
->rex
& (REX_V
| REX_EV
)) {
1300 int bad32
= REX_R
|REX_W
|REX_X
|REX_B
;
1302 if (ins
->rex
& REX_H
) {
1303 errfunc(ERR_NONFATAL
, "cannot use high register in AVX instruction");
1306 switch (ins
->vex_wlp
& 060) {
1320 if (bits
!= 64 && ((ins
->rex
& bad32
) || ins
->vexreg
> 7)) {
1321 errfunc(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1323 } else if (!(ins
->rex
& REX_EV
) &&
1324 ((ins
->vexreg
> 15) || (ins
->evex_p
[0] & 0xf0))) {
1325 errfunc(ERR_NONFATAL
, "invalid high-16 register in non-AVX-512");
1328 if (ins
->rex
& REX_EV
)
1330 else if (ins
->vex_cm
!= 1 || (ins
->rex
& (REX_W
|REX_X
|REX_B
)) ||
1331 ins
->prefixes
[PPS_VEX
] == P_VEX3
)
1335 } else if (ins
->rex
& REX_REAL
) {
1336 if (ins
->rex
& REX_H
) {
1337 errfunc(ERR_NONFATAL
, "cannot use high register in rex instruction");
1339 } else if (bits
== 64) {
1341 } else if ((ins
->rex
& REX_L
) &&
1342 !(ins
->rex
& (REX_P
|REX_W
|REX_X
|REX_B
)) &&
1343 iflag_ffs(&cpu
) >= IF_X86_64
) {
1345 assert_no_prefix(ins
, PPS_LOCK
);
1346 lockcheck
= false; /* Already errored, no need for warning */
1349 errfunc(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1354 if (has_prefix(ins
, PPS_LOCK
, P_LOCK
) && lockcheck
&&
1355 (!itemp_has(temp
,IF_LOCK
) || !is_class(MEMORY
, ins
->oprs
[0].type
))) {
1356 errfunc(ERR_WARNING
| ERR_WARN_LOCK
| ERR_PASS2
,
1357 "instruction is not lockable");
1360 bad_hle_warn(ins
, hleok
);
1363 * when BND prefix is set by DEFAULT directive,
1364 * BND prefix is added to every appropriate instruction line
1365 * unless it is overridden by NOBND prefix.
1368 (itemp_has(temp
, IF_BND
) && !has_prefix(ins
, PPS_REP
, P_NOBND
)))
1369 ins
->prefixes
[PPS_REP
] = P_BND
;
1374 static inline unsigned int emit_rex(insn
*ins
, int32_t segment
, int64_t offset
, int bits
)
1377 if ((ins
->rex
& REX_REAL
) && !(ins
->rex
& (REX_V
| REX_EV
))) {
1378 ins
->rex
= (ins
->rex
& REX_REAL
) | REX_P
;
1379 out(offset
, segment
, &ins
->rex
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1388 static void gencode(int32_t segment
, int64_t offset
, int bits
,
1389 insn
* ins
, const struct itemplate
*temp
,
1397 struct operand
*opx
;
1398 const uint8_t *codes
= temp
->code
;
1400 enum ea_type eat
= EA_SCALAR
;
1404 op1
= (c
& 3) + ((opex
& 1) << 2);
1405 op2
= ((c
>> 3) & 3) + ((opex
& 2) << 1);
1406 opx
= &ins
->oprs
[op1
];
1407 opex
= 0; /* For the next iteration */
1414 offset
+= emit_rex(ins
, segment
, offset
, bits
);
1415 out(offset
, segment
, codes
, OUT_RAWDATA
, c
, NO_SEG
, NO_SEG
);
1427 offset
+= emit_rex(ins
, segment
, offset
, bits
);
1428 bytes
[0] = *codes
++ + (regval(opx
) & 7);
1429 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1437 if (opx
->offset
< -256 || opx
->offset
> 255) {
1438 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1439 "byte value exceeds bounds");
1441 out_imm8(offset
, segment
, opx
);
1446 if (opx
->offset
< 0 || opx
->offset
> 255)
1447 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1448 "unsigned byte value exceeds bounds");
1449 out_imm8(offset
, segment
, opx
);
1454 warn_overflow_opd(opx
, 2);
1456 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1457 opx
->segment
, opx
->wrt
);
1462 if (opx
->type
& (BITS16
| BITS32
))
1463 size
= (opx
->type
& BITS16
) ? 2 : 4;
1465 size
= (bits
== 16) ? 2 : 4;
1466 warn_overflow_opd(opx
, size
);
1468 out(offset
, segment
, &data
, OUT_ADDRESS
, size
,
1469 opx
->segment
, opx
->wrt
);
1474 warn_overflow_opd(opx
, 4);
1476 out(offset
, segment
, &data
, OUT_ADDRESS
, 4,
1477 opx
->segment
, opx
->wrt
);
1483 size
= ins
->addr_size
>> 3;
1484 warn_overflow_opd(opx
, size
);
1485 out(offset
, segment
, &data
, OUT_ADDRESS
, size
,
1486 opx
->segment
, opx
->wrt
);
1491 if (opx
->segment
!= segment
) {
1493 out(offset
, segment
, &data
,
1494 OUT_REL1ADR
, insn_end
- offset
,
1495 opx
->segment
, opx
->wrt
);
1497 data
= opx
->offset
- insn_end
;
1498 if (data
> 127 || data
< -128)
1499 errfunc(ERR_NONFATAL
, "short jump is out of range");
1500 out(offset
, segment
, &data
,
1501 OUT_ADDRESS
, 1, NO_SEG
, NO_SEG
);
1507 data
= (int64_t)opx
->offset
;
1508 out(offset
, segment
, &data
, OUT_ADDRESS
, 8,
1509 opx
->segment
, opx
->wrt
);
1514 if (opx
->segment
!= segment
) {
1516 out(offset
, segment
, &data
,
1517 OUT_REL2ADR
, insn_end
- offset
,
1518 opx
->segment
, opx
->wrt
);
1520 data
= opx
->offset
- insn_end
;
1521 out(offset
, segment
, &data
,
1522 OUT_ADDRESS
, 2, NO_SEG
, NO_SEG
);
1528 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
1529 size
= (opx
->type
& BITS16
) ? 2 : 4;
1531 size
= (bits
== 16) ? 2 : 4;
1532 if (opx
->segment
!= segment
) {
1534 out(offset
, segment
, &data
,
1535 size
== 2 ? OUT_REL2ADR
: OUT_REL4ADR
,
1536 insn_end
- offset
, opx
->segment
, opx
->wrt
);
1538 data
= opx
->offset
- insn_end
;
1539 out(offset
, segment
, &data
,
1540 OUT_ADDRESS
, size
, NO_SEG
, NO_SEG
);
1546 if (opx
->segment
!= segment
) {
1548 out(offset
, segment
, &data
,
1549 OUT_REL4ADR
, insn_end
- offset
,
1550 opx
->segment
, opx
->wrt
);
1552 data
= opx
->offset
- insn_end
;
1553 out(offset
, segment
, &data
,
1554 OUT_ADDRESS
, 4, NO_SEG
, NO_SEG
);
1560 if (opx
->segment
== NO_SEG
)
1561 errfunc(ERR_NONFATAL
, "value referenced by FAR is not"
1564 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1565 outfmt
->segbase(1 + opx
->segment
),
1572 opx
= &ins
->oprs
[c
>> 3];
1573 bytes
[0] = nasm_regvals
[opx
->basereg
] << 4;
1574 opx
= &ins
->oprs
[c
& 7];
1575 if (opx
->segment
!= NO_SEG
|| opx
->wrt
!= NO_SEG
) {
1576 errfunc(ERR_NONFATAL
,
1577 "non-absolute expression not permitted as argument %d",
1580 if (opx
->offset
& ~15) {
1581 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1582 "four-bit argument exceeds bounds");
1584 bytes
[0] |= opx
->offset
& 15;
1586 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1592 opx
= &ins
->oprs
[c
>> 4];
1593 bytes
[0] = nasm_regvals
[opx
->basereg
] << 4;
1595 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1600 bytes
[0] = nasm_regvals
[opx
->basereg
] << 4;
1601 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1607 if (opx
->wrt
== NO_SEG
&& opx
->segment
== NO_SEG
&&
1608 (int32_t)data
!= (int64_t)data
) {
1609 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1610 "signed dword immediate exceeds bounds");
1612 out(offset
, segment
, &data
, OUT_ADDRESS
, 4,
1613 opx
->segment
, opx
->wrt
);
1620 ins
->evex_p
[2] |= op_evexflags(&ins
->oprs
[0],
1621 EVEX_P2Z
| EVEX_P2AAA
, 2);
1622 ins
->evex_p
[2] ^= EVEX_P2VP
; /* 1's complement */
1624 /* EVEX.X can be set by either REX or EVEX for different reasons */
1625 bytes
[1] = ((((ins
->rex
& 7) << 5) |
1626 (ins
->evex_p
[0] & (EVEX_P0X
| EVEX_P0RP
))) ^ 0xf0) |
1628 bytes
[2] = ((ins
->rex
& REX_W
) << (7 - 3)) |
1629 ((~ins
->vexreg
& 15) << 3) |
1630 (1 << 2) | (ins
->vex_wlp
& 3);
1631 bytes
[3] = ins
->evex_p
[2];
1632 out(offset
, segment
, &bytes
, OUT_RAWDATA
, 4, NO_SEG
, NO_SEG
);
1639 if (ins
->vex_cm
!= 1 || (ins
->rex
& (REX_W
|REX_X
|REX_B
)) ||
1640 ins
->prefixes
[PPS_VEX
] == P_VEX3
) {
1641 bytes
[0] = (ins
->vex_cm
>> 6) ? 0x8f : 0xc4;
1642 bytes
[1] = (ins
->vex_cm
& 31) | ((~ins
->rex
& 7) << 5);
1643 bytes
[2] = ((ins
->rex
& REX_W
) << (7-3)) |
1644 ((~ins
->vexreg
& 15)<< 3) | (ins
->vex_wlp
& 07);
1645 out(offset
, segment
, &bytes
, OUT_RAWDATA
, 3, NO_SEG
, NO_SEG
);
1649 bytes
[1] = ((~ins
->rex
& REX_R
) << (7-2)) |
1650 ((~ins
->vexreg
& 15) << 3) | (ins
->vex_wlp
& 07);
1651 out(offset
, segment
, &bytes
, OUT_RAWDATA
, 2, NO_SEG
, NO_SEG
);
1666 if (ins
->rex
& REX_W
)
1668 else if (ins
->prefixes
[PPS_OSIZE
] == P_O16
)
1670 else if (ins
->prefixes
[PPS_OSIZE
] == P_O32
)
1675 um
= (uint64_t)2 << (s
-1);
1678 if (uv
> 127 && uv
< (uint64_t)-128 &&
1679 (uv
< um
-128 || uv
> um
-1)) {
1680 /* If this wasn't explicitly byte-sized, warn as though we
1681 * had fallen through to the imm16/32/64 case.
1683 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1684 "%s value exceeds bounds",
1685 (opx
->type
& BITS8
) ? "signed byte" :
1690 if (opx
->segment
!= NO_SEG
) {
1692 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1693 opx
->segment
, opx
->wrt
);
1696 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1707 if (bits
== 32 && !has_prefix(ins
, PPS_ASIZE
, P_A16
)) {
1709 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1716 if (bits
!= 32 && !has_prefix(ins
, PPS_ASIZE
, P_A32
)) {
1718 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1753 *bytes
= *codes
++ ^ get_cond_opcode(ins
->condition
);
1754 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1763 *bytes
= c
- 0332 + 0xF2;
1764 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1769 if (ins
->rex
& REX_R
) {
1771 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1774 ins
->rex
&= ~(REX_L
|REX_R
);
1785 if (ins
->oprs
[0].segment
!= NO_SEG
)
1786 errfunc(ERR_PANIC
, "non-constant BSS size in pass two");
1788 int64_t size
= ins
->oprs
[0].offset
;
1790 out(offset
, segment
, NULL
,
1791 OUT_RESERVE
, size
, NO_SEG
, NO_SEG
);
1804 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1814 *bytes
= c
- 0366 + 0x66;
1815 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1823 *bytes
= bits
== 16 ? 3 : 5;
1824 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1858 struct operand
*opy
= &ins
->oprs
[op2
];
1861 /* pick rfield from operand b (opx) */
1862 rflags
= regflag(opx
);
1863 rfield
= nasm_regvals
[opx
->basereg
];
1865 /* rfield is constant */
1870 if (process_ea(opy
, &ea_data
, bits
,
1871 rfield
, rflags
, ins
) != eat
)
1872 errfunc(ERR_NONFATAL
, "invalid effective address");
1875 *p
++ = ea_data
.modrm
;
1876 if (ea_data
.sib_present
)
1880 out(offset
, segment
, bytes
, OUT_RAWDATA
, s
, NO_SEG
, NO_SEG
);
1883 * Make sure the address gets the right offset in case
1884 * the line breaks in the .lst file (BR 1197827)
1889 switch (ea_data
.bytes
) {
1896 /* use compressed displacement, if available */
1897 data
= ea_data
.disp8
? ea_data
.disp8
: opy
->offset
;
1900 if (opy
->segment
== segment
) {
1902 if (overflow_signed(data
, ea_data
.bytes
))
1903 warn_overflow(ERR_PASS2
, ea_data
.bytes
);
1904 out(offset
, segment
, &data
, OUT_ADDRESS
,
1905 ea_data
.bytes
, NO_SEG
, NO_SEG
);
1907 /* overflow check in output/linker? */
1908 out(offset
, segment
, &data
, OUT_REL4ADR
,
1909 insn_end
- offset
, opy
->segment
, opy
->wrt
);
1912 if (overflow_general(data
, ins
->addr_size
>> 3) ||
1913 signed_bits(data
, ins
->addr_size
) !=
1914 signed_bits(data
, ea_data
.bytes
* 8))
1915 warn_overflow(ERR_PASS2
, ea_data
.bytes
);
1917 out(offset
, segment
, &data
, OUT_ADDRESS
,
1918 ea_data
.bytes
, opy
->segment
, opy
->wrt
);
1924 "Invalid amount of bytes (%d) for offset?!",
1933 errfunc(ERR_PANIC
, "internal instruction table corrupt"
1934 ": instruction code \\%o (0x%02X) given", c
, c
);
1940 static opflags_t
regflag(const operand
* o
)
1942 if (!is_register(o
->basereg
))
1943 errfunc(ERR_PANIC
, "invalid operand passed to regflag()");
1944 return nasm_reg_flags
[o
->basereg
];
1947 static int32_t regval(const operand
* o
)
1949 if (!is_register(o
->basereg
))
1950 errfunc(ERR_PANIC
, "invalid operand passed to regval()");
1951 return nasm_regvals
[o
->basereg
];
1954 static int op_rexflags(const operand
* o
, int mask
)
1959 if (!is_register(o
->basereg
))
1960 errfunc(ERR_PANIC
, "invalid operand passed to op_rexflags()");
1962 flags
= nasm_reg_flags
[o
->basereg
];
1963 val
= nasm_regvals
[o
->basereg
];
1965 return rexflags(val
, flags
, mask
);
1968 static int rexflags(int val
, opflags_t flags
, int mask
)
1972 if (val
>= 0 && (val
& 8))
1973 rex
|= REX_B
|REX_X
|REX_R
;
1976 if (!(REG_HIGH
& ~flags
)) /* AH, CH, DH, BH */
1978 else if (!(REG8
& ~flags
) && val
>= 4) /* SPL, BPL, SIL, DIL */
1984 static int evexflags(int val
, decoflags_t deco
,
1985 int mask
, uint8_t byte
)
1991 if (val
>= 0 && (val
& 16))
1992 evex
|= (EVEX_P0RP
| EVEX_P0X
);
1995 if (val
>= 0 && (val
& 16))
1999 if (deco
& OPMASK_MASK
)
2000 evex
|= deco
& EVEX_P2AAA
;
2006 static int op_evexflags(const operand
* o
, int mask
, uint8_t byte
)
2010 if (!is_register(o
->basereg
))
2011 errfunc(ERR_PANIC
, "invalid operand passed to op_evexflags()");
2013 val
= nasm_regvals
[o
->basereg
];
2015 return evexflags(val
, o
->decoflags
, mask
, byte
);
2018 static enum match_result
find_match(const struct itemplate
**tempp
,
2020 int32_t segment
, int64_t offset
, int bits
)
2022 const struct itemplate
*temp
;
2023 enum match_result m
, merr
;
2024 opflags_t xsizeflags
[MAX_OPERANDS
];
2025 bool opsizemissing
= false;
2026 int8_t broadcast
= instruction
->evex_brerop
;
2029 /* broadcasting uses a different data element size */
2030 for (i
= 0; i
< instruction
->operands
; i
++)
2032 xsizeflags
[i
] = instruction
->oprs
[i
].decoflags
& BRSIZE_MASK
;
2034 xsizeflags
[i
] = instruction
->oprs
[i
].type
& SIZE_MASK
;
2036 merr
= MERR_INVALOP
;
2038 for (temp
= nasm_instructions
[instruction
->opcode
];
2039 temp
->opcode
!= I_none
; temp
++) {
2040 m
= matches(temp
, instruction
, bits
);
2041 if (m
== MOK_JUMP
) {
2042 if (jmp_match(segment
, offset
, bits
, instruction
, temp
))
2046 } else if (m
== MERR_OPSIZEMISSING
&& !itemp_has(temp
, IF_SX
)) {
2048 * Missing operand size and a candidate for fuzzy matching...
2050 for (i
= 0; i
< temp
->operands
; i
++)
2052 xsizeflags
[i
] |= temp
->deco
[i
] & BRSIZE_MASK
;
2054 xsizeflags
[i
] |= temp
->opd
[i
] & SIZE_MASK
;
2055 opsizemissing
= true;
2059 if (merr
== MOK_GOOD
)
2063 /* No match, but see if we can get a fuzzy operand size match... */
2067 for (i
= 0; i
< instruction
->operands
; i
++) {
2069 * We ignore extrinsic operand sizes on registers, so we should
2070 * never try to fuzzy-match on them. This also resolves the case
2071 * when we have e.g. "xmmrm128" in two different positions.
2073 if (is_class(REGISTER
, instruction
->oprs
[i
].type
))
2076 /* This tests if xsizeflags[i] has more than one bit set */
2077 if ((xsizeflags
[i
] & (xsizeflags
[i
]-1)))
2078 goto done
; /* No luck */
2080 if (i
== broadcast
) {
2081 instruction
->oprs
[i
].decoflags
|= xsizeflags
[i
];
2082 instruction
->oprs
[i
].type
|= (xsizeflags
[i
] == BR_BITS32
?
2085 instruction
->oprs
[i
].type
|= xsizeflags
[i
]; /* Set the size */
2089 /* Try matching again... */
2090 for (temp
= nasm_instructions
[instruction
->opcode
];
2091 temp
->opcode
!= I_none
; temp
++) {
2092 m
= matches(temp
, instruction
, bits
);
2093 if (m
== MOK_JUMP
) {
2094 if (jmp_match(segment
, offset
, bits
, instruction
, temp
))
2101 if (merr
== MOK_GOOD
)
2110 static enum match_result
matches(const struct itemplate
*itemp
,
2111 insn
*instruction
, int bits
)
2113 opflags_t size
[MAX_OPERANDS
], asize
;
2114 bool opsizemissing
= false;
2120 if (itemp
->opcode
!= instruction
->opcode
)
2121 return MERR_INVALOP
;
2124 * Count the operands
2126 if (itemp
->operands
!= instruction
->operands
)
2127 return MERR_INVALOP
;
2132 if (!(optimizing
> 0) && itemp_has(itemp
, IF_OPT
))
2133 return MERR_INVALOP
;
2138 switch (instruction
->prefixes
[PPS_VEX
]) {
2140 if (!itemp_has(itemp
, IF_EVEX
))
2141 return MERR_ENCMISMATCH
;
2145 if (!itemp_has(itemp
, IF_VEX
))
2146 return MERR_ENCMISMATCH
;
2153 * Check that no spurious colons or TOs are present
2155 for (i
= 0; i
< itemp
->operands
; i
++)
2156 if (instruction
->oprs
[i
].type
& ~itemp
->opd
[i
] & (COLON
| TO
))
2157 return MERR_INVALOP
;
2160 * Process size flags
2162 switch (itemp_smask(itemp
)) {
2163 case IF_GENBIT(IF_SB
):
2166 case IF_GENBIT(IF_SW
):
2169 case IF_GENBIT(IF_SD
):
2172 case IF_GENBIT(IF_SQ
):
2175 case IF_GENBIT(IF_SO
):
2178 case IF_GENBIT(IF_SY
):
2181 case IF_GENBIT(IF_SZ
):
2184 case IF_GENBIT(IF_SIZE
):
2205 if (itemp_armask(itemp
)) {
2206 /* S- flags only apply to a specific operand */
2207 i
= itemp_arg(itemp
);
2208 memset(size
, 0, sizeof size
);
2211 /* S- flags apply to all operands */
2212 for (i
= 0; i
< MAX_OPERANDS
; i
++)
2217 * Check that the operand flags all match up,
2218 * it's a bit tricky so lets be verbose:
2220 * 1) Find out the size of operand. If instruction
2221 * doesn't have one specified -- we're trying to
2222 * guess it either from template (IF_S* flag) or
2225 * 2) If template operand do not match the instruction OR
2226 * template has an operand size specified AND this size differ
2227 * from which instruction has (perhaps we got it from code bits)
2229 * a) Check that only size of instruction and operand is differ
2230 * other characteristics do match
2231 * b) Perhaps it's a register specified in instruction so
2232 * for such a case we just mark that operand as "size
2233 * missing" and this will turn on fuzzy operand size
2234 * logic facility (handled by a caller)
2236 for (i
= 0; i
< itemp
->operands
; i
++) {
2237 opflags_t type
= instruction
->oprs
[i
].type
;
2238 decoflags_t deco
= instruction
->oprs
[i
].decoflags
;
2239 bool is_broadcast
= deco
& BRDCAST_MASK
;
2240 uint8_t brcast_num
= 0;
2241 opflags_t template_opsize
, insn_opsize
;
2243 if (!(type
& SIZE_MASK
))
2246 insn_opsize
= type
& SIZE_MASK
;
2247 if (!is_broadcast
) {
2248 template_opsize
= itemp
->opd
[i
] & SIZE_MASK
;
2250 decoflags_t deco_brsize
= itemp
->deco
[i
] & BRSIZE_MASK
;
2252 * when broadcasting, the element size depends on
2253 * the instruction type. decorator flag should match.
2257 template_opsize
= (deco_brsize
== BR_BITS32
? BITS32
: BITS64
);
2258 /* calculate the proper number : {1to<brcast_num>} */
2259 brcast_num
= (itemp
->opd
[i
] & SIZE_MASK
) / BITS128
*
2260 BITS64
/ template_opsize
* 2;
2262 template_opsize
= 0;
2266 if ((itemp
->opd
[i
] & ~type
& ~SIZE_MASK
) ||
2267 (deco
& ~itemp
->deco
[i
] & ~BRNUM_MASK
)) {
2268 return MERR_INVALOP
;
2269 } else if (template_opsize
) {
2270 if (template_opsize
!= insn_opsize
) {
2272 return MERR_INVALOP
;
2273 } else if (!is_class(REGISTER
, type
)) {
2275 * Note: we don't honor extrinsic operand sizes for registers,
2276 * so "missing operand size" for a register should be
2277 * considered a wildcard match rather than an error.
2279 opsizemissing
= true;
2281 } else if (is_broadcast
&&
2283 (8U << ((deco
& BRNUM_MASK
) >> BRNUM_SHIFT
)))) {
2285 * broadcasting opsize matches but the number of repeated memory
2286 * element does not match.
2287 * if 64b double precision float is broadcasted to zmm (512b),
2288 * broadcasting decorator must be {1to8}.
2290 return MERR_BRNUMMISMATCH
;
2296 return MERR_OPSIZEMISSING
;
2299 * Check operand sizes
2301 if (itemp_has(itemp
, IF_SM
) || itemp_has(itemp
, IF_SM2
)) {
2302 oprs
= (itemp_has(itemp
, IF_SM2
) ? 2 : itemp
->operands
);
2303 for (i
= 0; i
< oprs
; i
++) {
2304 asize
= itemp
->opd
[i
] & SIZE_MASK
;
2306 for (i
= 0; i
< oprs
; i
++)
2312 oprs
= itemp
->operands
;
2315 for (i
= 0; i
< itemp
->operands
; i
++) {
2316 if (!(itemp
->opd
[i
] & SIZE_MASK
) &&
2317 (instruction
->oprs
[i
].type
& SIZE_MASK
& ~size
[i
]))
2318 return MERR_OPSIZEMISMATCH
;
2322 * Check template is okay at the set cpu level
2324 if (iflag_cmp_cpu_level(&insns_flags
[itemp
->iflag_idx
], &cpu
) > 0)
2328 * Verify the appropriate long mode flag.
2330 if (itemp_has(itemp
, (bits
== 64 ? IF_NOLONG
: IF_LONG
)))
2331 return MERR_BADMODE
;
2334 * If we have a HLE prefix, look for the NOHLE flag
2336 if (itemp_has(itemp
, IF_NOHLE
) &&
2337 (has_prefix(instruction
, PPS_REP
, P_XACQUIRE
) ||
2338 has_prefix(instruction
, PPS_REP
, P_XRELEASE
)))
2342 * Check if special handling needed for Jumps
2344 if ((itemp
->code
[0] & ~1) == 0370)
2348 * Check if BND prefix is allowed.
2349 * Other 0xF2 (REPNE/REPNZ) prefix is prohibited.
2351 if (!itemp_has(itemp
, IF_BND
) &&
2352 (has_prefix(instruction
, PPS_REP
, P_BND
) ||
2353 has_prefix(instruction
, PPS_REP
, P_NOBND
)))
2355 else if (itemp_has(itemp
, IF_BND
) &&
2356 (has_prefix(instruction
, PPS_REP
, P_REPNE
) ||
2357 has_prefix(instruction
, PPS_REP
, P_REPNZ
)))
2358 return MERR_BADREPNE
;
2364 * Check if ModR/M.mod should/can be 01.
2365 * - EAF_BYTEOFFS is set
2366 * - offset can fit in a byte when EVEX is not used
2367 * - offset can be compressed when EVEX is used
2369 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2370 (o >= -128 && o <= 127 && \
2371 seg == NO_SEG && !forw_ref && \
2372 !(input->eaflags & EAF_WORDOFFS) && \
2373 !(ins->rex & REX_EV)) || \
2374 (ins->rex & REX_EV && \
2375 is_disp8n(input, ins, &output->disp8)))
2377 static enum ea_type
process_ea(operand
*input
, ea
*output
, int bits
,
2378 int rfield
, opflags_t rflags
, insn
*ins
)
2380 bool forw_ref
= !!(input
->opflags
& OPFLAG_UNKNOWN
);
2381 int addrbits
= ins
->addr_size
;
2383 output
->type
= EA_SCALAR
;
2384 output
->rip
= false;
2387 /* REX flags for the rfield operand */
2388 output
->rex
|= rexflags(rfield
, rflags
, REX_R
| REX_P
| REX_W
| REX_H
);
2389 /* EVEX.R' flag for the REG operand */
2390 ins
->evex_p
[0] |= evexflags(rfield
, 0, EVEX_P0RP
, 0);
2392 if (is_class(REGISTER
, input
->type
)) {
2394 * It's a direct register.
2396 if (!is_register(input
->basereg
))
2399 if (!is_reg_class(REG_EA
, input
->basereg
))
2402 /* broadcasting is not available with a direct register operand. */
2403 if (input
->decoflags
& BRDCAST_MASK
) {
2404 nasm_error(ERR_NONFATAL
, "Broadcasting not allowed from a register");
2408 output
->rex
|= op_rexflags(input
, REX_B
| REX_P
| REX_W
| REX_H
);
2409 ins
->evex_p
[0] |= op_evexflags(input
, EVEX_P0X
, 0);
2410 output
->sib_present
= false; /* no SIB necessary */
2411 output
->bytes
= 0; /* no offset necessary either */
2412 output
->modrm
= GEN_MODRM(3, rfield
, nasm_regvals
[input
->basereg
]);
2415 * It's a memory reference.
2418 /* Embedded rounding or SAE is not available with a mem ref operand. */
2419 if (input
->decoflags
& (ER
| SAE
)) {
2420 nasm_error(ERR_NONFATAL
,
2421 "Embedded rounding is available only with reg-reg op.");
2425 if (input
->basereg
== -1 &&
2426 (input
->indexreg
== -1 || input
->scale
== 0)) {
2428 * It's a pure offset.
2430 if (bits
== 64 && ((input
->type
& IP_REL
) == IP_REL
) &&
2431 input
->segment
== NO_SEG
) {
2432 nasm_error(ERR_WARNING
| ERR_PASS1
, "absolute address can not be RIP-relative");
2433 input
->type
&= ~IP_REL
;
2434 input
->type
|= MEMORY
;
2437 if (input
->eaflags
& EAF_BYTEOFFS
||
2438 (input
->eaflags
& EAF_WORDOFFS
&&
2439 input
->disp_size
!= (addrbits
!= 16 ? 32 : 16))) {
2440 nasm_error(ERR_WARNING
| ERR_PASS1
, "displacement size ignored on absolute address");
2443 if (bits
== 64 && (~input
->type
& IP_REL
)) {
2444 output
->sib_present
= true;
2445 output
->sib
= GEN_SIB(0, 4, 5);
2447 output
->modrm
= GEN_MODRM(0, rfield
, 4);
2448 output
->rip
= false;
2450 output
->sib_present
= false;
2451 output
->bytes
= (addrbits
!= 16 ? 4 : 2);
2452 output
->modrm
= GEN_MODRM(0, rfield
, (addrbits
!= 16 ? 5 : 6));
2453 output
->rip
= bits
== 64;
2457 * It's an indirection.
2459 int i
= input
->indexreg
, b
= input
->basereg
, s
= input
->scale
;
2460 int32_t seg
= input
->segment
;
2461 int hb
= input
->hintbase
, ht
= input
->hinttype
;
2462 int t
, it
, bt
; /* register numbers */
2463 opflags_t x
, ix
, bx
; /* register flags */
2466 i
= -1; /* make this easy, at least */
2468 if (is_register(i
)) {
2469 it
= nasm_regvals
[i
];
2470 ix
= nasm_reg_flags
[i
];
2476 if (is_register(b
)) {
2477 bt
= nasm_regvals
[b
];
2478 bx
= nasm_reg_flags
[b
];
2484 /* if either one are a vector register... */
2485 if ((ix
|bx
) & (XMMREG
|YMMREG
|ZMMREG
) & ~REG_EA
) {
2486 opflags_t sok
= BITS32
| BITS64
;
2487 int32_t o
= input
->offset
;
2488 int mod
, scale
, index
, base
;
2491 * For a vector SIB, one has to be a vector and the other,
2492 * if present, a GPR. The vector must be the index operand.
2494 if (it
== -1 || (bx
& (XMMREG
|YMMREG
|ZMMREG
) & ~REG_EA
)) {
2500 t
= bt
, bt
= it
, it
= t
;
2501 x
= bx
, bx
= ix
, ix
= x
;
2507 if (!(REG64
& ~bx
) || !(REG32
& ~bx
))
2514 * While we're here, ensure the user didn't specify
2517 if (input
->disp_size
== 16 || input
->disp_size
== 64)
2520 if (addrbits
== 16 ||
2521 (addrbits
== 32 && !(sok
& BITS32
)) ||
2522 (addrbits
== 64 && !(sok
& BITS64
)))
2525 output
->type
= ((ix
& ZMMREG
& ~REG_EA
) ? EA_ZMMVSIB
2526 : ((ix
& YMMREG
& ~REG_EA
)
2527 ? EA_YMMVSIB
: EA_XMMVSIB
));
2529 output
->rex
|= rexflags(it
, ix
, REX_X
);
2530 output
->rex
|= rexflags(bt
, bx
, REX_B
);
2531 ins
->evex_p
[2] |= evexflags(it
, 0, EVEX_P2VP
, 2);
2533 index
= it
& 7; /* it is known to be != -1 */
2548 default: /* then what the smeg is it? */
2549 goto err
; /* panic */
2557 if (base
!= REG_NUM_EBP
&& o
== 0 &&
2558 seg
== NO_SEG
&& !forw_ref
&&
2559 !(input
->eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2561 else if (IS_MOD_01())
2567 output
->sib_present
= true;
2568 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2569 output
->modrm
= GEN_MODRM(mod
, rfield
, 4);
2570 output
->sib
= GEN_SIB(scale
, index
, base
);
2571 } else if ((ix
|bx
) & (BITS32
|BITS64
)) {
2573 * it must be a 32/64-bit memory reference. Firstly we have
2574 * to check that all registers involved are type E/Rxx.
2576 opflags_t sok
= BITS32
| BITS64
;
2577 int32_t o
= input
->offset
;
2580 if (!(REG64
& ~ix
) || !(REG32
& ~ix
))
2588 goto err
; /* Invalid register */
2589 if (~sok
& bx
& SIZE_MASK
)
2590 goto err
; /* Invalid size */
2595 * While we're here, ensure the user didn't specify
2598 if (input
->disp_size
== 16 || input
->disp_size
== 64)
2601 if (addrbits
== 16 ||
2602 (addrbits
== 32 && !(sok
& BITS32
)) ||
2603 (addrbits
== 64 && !(sok
& BITS64
)))
2606 /* now reorganize base/index */
2607 if (s
== 1 && bt
!= it
&& bt
!= -1 && it
!= -1 &&
2608 ((hb
== b
&& ht
== EAH_NOTBASE
) ||
2609 (hb
== i
&& ht
== EAH_MAKEBASE
))) {
2610 /* swap if hints say so */
2611 t
= bt
, bt
= it
, it
= t
;
2612 x
= bx
, bx
= ix
, ix
= x
;
2614 if (bt
== it
) /* convert EAX+2*EAX to 3*EAX */
2615 bt
= -1, bx
= 0, s
++;
2616 if (bt
== -1 && s
== 1 && !(hb
== i
&& ht
== EAH_NOTBASE
)) {
2617 /* make single reg base, unless hint */
2618 bt
= it
, bx
= ix
, it
= -1, ix
= 0;
2620 if (((s
== 2 && it
!= REG_NUM_ESP
&& !(input
->eaflags
& EAF_TIMESTWO
)) ||
2621 s
== 3 || s
== 5 || s
== 9) && bt
== -1)
2622 bt
= it
, bx
= ix
, s
--; /* convert 3*EAX to EAX+2*EAX */
2623 if (it
== -1 && (bt
& 7) != REG_NUM_ESP
&&
2624 (input
->eaflags
& EAF_TIMESTWO
))
2625 it
= bt
, ix
= bx
, bt
= -1, bx
= 0, s
= 1;
2626 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2627 if (s
== 1 && it
== REG_NUM_ESP
) {
2628 /* swap ESP into base if scale is 1 */
2629 t
= it
, it
= bt
, bt
= t
;
2630 x
= ix
, ix
= bx
, bx
= x
;
2632 if (it
== REG_NUM_ESP
||
2633 (s
!= 1 && s
!= 2 && s
!= 4 && s
!= 8 && it
!= -1))
2634 goto err
; /* wrong, for various reasons */
2636 output
->rex
|= rexflags(it
, ix
, REX_X
);
2637 output
->rex
|= rexflags(bt
, bx
, REX_B
);
2639 if (it
== -1 && (bt
& 7) != REG_NUM_ESP
) {
2648 if (rm
!= REG_NUM_EBP
&& o
== 0 &&
2649 seg
== NO_SEG
&& !forw_ref
&&
2650 !(input
->eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2652 else if (IS_MOD_01())
2658 output
->sib_present
= false;
2659 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2660 output
->modrm
= GEN_MODRM(mod
, rfield
, rm
);
2663 int mod
, scale
, index
, base
;
2683 default: /* then what the smeg is it? */
2684 goto err
; /* panic */
2692 if (base
!= REG_NUM_EBP
&& o
== 0 &&
2693 seg
== NO_SEG
&& !forw_ref
&&
2694 !(input
->eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2696 else if (IS_MOD_01())
2702 output
->sib_present
= true;
2703 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2704 output
->modrm
= GEN_MODRM(mod
, rfield
, 4);
2705 output
->sib
= GEN_SIB(scale
, index
, base
);
2707 } else { /* it's 16-bit */
2709 int16_t o
= input
->offset
;
2711 /* check for 64-bit long mode */
2715 /* check all registers are BX, BP, SI or DI */
2716 if ((b
!= -1 && b
!= R_BP
&& b
!= R_BX
&& b
!= R_SI
&& b
!= R_DI
) ||
2717 (i
!= -1 && i
!= R_BP
&& i
!= R_BX
&& i
!= R_SI
&& i
!= R_DI
))
2720 /* ensure the user didn't specify DWORD/QWORD */
2721 if (input
->disp_size
== 32 || input
->disp_size
== 64)
2724 if (s
!= 1 && i
!= -1)
2725 goto err
; /* no can do, in 16-bit EA */
2726 if (b
== -1 && i
!= -1) {
2731 if ((b
== R_SI
|| b
== R_DI
) && i
!= -1) {
2736 /* have BX/BP as base, SI/DI index */
2738 goto err
; /* shouldn't ever happen, in theory */
2739 if (i
!= -1 && b
!= -1 &&
2740 (i
== R_BP
|| i
== R_BX
|| b
== R_SI
|| b
== R_DI
))
2741 goto err
; /* invalid combinations */
2742 if (b
== -1) /* pure offset: handled above */
2743 goto err
; /* so if it gets to here, panic! */
2747 switch (i
* 256 + b
) {
2748 case R_SI
* 256 + R_BX
:
2751 case R_DI
* 256 + R_BX
:
2754 case R_SI
* 256 + R_BP
:
2757 case R_DI
* 256 + R_BP
:
2775 if (rm
== -1) /* can't happen, in theory */
2776 goto err
; /* so panic if it does */
2778 if (o
== 0 && seg
== NO_SEG
&& !forw_ref
&& rm
!= 6 &&
2779 !(input
->eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2781 else if (IS_MOD_01())
2786 output
->sib_present
= false; /* no SIB - it's 16-bit */
2787 output
->bytes
= mod
; /* bytes of offset needed */
2788 output
->modrm
= GEN_MODRM(mod
, rfield
, rm
);
2793 output
->size
= 1 + output
->sib_present
+ output
->bytes
;
2794 return output
->type
;
2797 return output
->type
= EA_INVALID
;
2800 static void add_asp(insn
*ins
, int addrbits
)
2805 valid
= (addrbits
== 64) ? 64|32 : 32|16;
2807 switch (ins
->prefixes
[PPS_ASIZE
]) {
2818 valid
&= (addrbits
== 32) ? 16 : 32;
2824 for (j
= 0; j
< ins
->operands
; j
++) {
2825 if (is_class(MEMORY
, ins
->oprs
[j
].type
)) {
2828 /* Verify as Register */
2829 if (!is_register(ins
->oprs
[j
].indexreg
))
2832 i
= nasm_reg_flags
[ins
->oprs
[j
].indexreg
];
2834 /* Verify as Register */
2835 if (!is_register(ins
->oprs
[j
].basereg
))
2838 b
= nasm_reg_flags
[ins
->oprs
[j
].basereg
];
2840 if (ins
->oprs
[j
].scale
== 0)
2844 int ds
= ins
->oprs
[j
].disp_size
;
2845 if ((addrbits
!= 64 && ds
> 8) ||
2846 (addrbits
== 64 && ds
== 16))
2866 if (valid
& addrbits
) {
2867 ins
->addr_size
= addrbits
;
2868 } else if (valid
& ((addrbits
== 32) ? 16 : 32)) {
2869 /* Add an address size prefix */
2870 ins
->prefixes
[PPS_ASIZE
] = (addrbits
== 32) ? P_A16
: P_A32
;;
2871 ins
->addr_size
= (addrbits
== 32) ? 16 : 32;
2874 errfunc(ERR_NONFATAL
, "impossible combination of address sizes");
2875 ins
->addr_size
= addrbits
; /* Error recovery */
2878 defdisp
= ins
->addr_size
== 16 ? 16 : 32;
2880 for (j
= 0; j
< ins
->operands
; j
++) {
2881 if (!(MEM_OFFS
& ~ins
->oprs
[j
].type
) &&
2882 (ins
->oprs
[j
].disp_size
? ins
->oprs
[j
].disp_size
: defdisp
) != ins
->addr_size
) {
2884 * mem_offs sizes must match the address size; if not,
2885 * strip the MEM_OFFS bit and match only EA instructions
2887 ins
->oprs
[j
].type
&= ~(MEM_OFFS
& ~MEMORY
);