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assemble.c: do not warn on valid SBYTE optimizations
[nasm.git] / assemble.c
blobbc41e026fd418ac7983905cf1b4fa2c6e9c22367
1 /* assemble.c code generation for the Netwide Assembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
7 *
8 * the actual codes (C syntax, i.e. octal):
9 * \0 - terminates the code. (Unless it's a literal of course.)
10 * \1, \2, \3 - that many literal bytes follow in the code stream
11 * \4, \6 - the POP/PUSH (respectively) codes for CS, DS, ES, SS
12 * (POP is never used for CS) depending on operand 0
13 * \5, \7 - the second byte of POP/PUSH codes for FS, GS, depending
14 * on operand 0
15 * \10..\13 - a literal byte follows in the code stream, to be added
16 * to the register value of operand 0..3
17 * \14..\17 - a signed byte immediate operand, from operand 0..3
18 * \20..\23 - a byte immediate operand, from operand 0..3
19 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
20 * \30..\33 - a word immediate operand, from operand 0..3
21 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
22 * assembly mode or the operand-size override on the operand
23 * \40..\43 - a long immediate operand, from operand 0..3
24 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
25 * depending on the address size of the instruction.
26 * \50..\53 - a byte relative operand, from operand 0..3
27 * \54..\57 - a qword immediate operand, from operand 0..3
28 * \60..\63 - a word relative operand, from operand 0..3
29 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
30 * assembly mode or the operand-size override on the operand
31 * \70..\73 - a long relative operand, from operand 0..3
32 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
33 * \1ab - a ModRM, calculated on EA in operand a, with the spare
34 * field the register value of operand b.
35 * \140..\143 - an immediate word or signed byte for operand 0..3
36 * \144..\147 - or 2 (s-field) into opcode byte if operand 0..3
37 * is a signed byte rather than a word. Opcode byte follows.
38 * \150..\153 - an immediate dword or signed byte for operand 0..3
39 * \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
40 * is a signed byte rather than a dword. Opcode byte follows.
41 * \160..\163 - this instruction uses DREX rather than REX, with the
42 * OC0 field set to 0, and the dest field taken from
43 * operand 0..3.
44 * \164..\167 - this instruction uses DREX rather than REX, with the
45 * OC0 field set to 1, and the dest field taken from
46 * operand 0..3.
47 * \171 - placement of DREX suffix in the absence of an EA
48 * \172\ab - the register number from operand a in bits 7..4, with
49 * the 4-bit immediate from operand b in bits 3..0.
50 * \173\xab - the register number from operand a in bits 7..4, with
51 * the value b in bits 3..0.
52 * \174\a - the register number from operand a in bits 7..4, and
53 * an arbitrary value in bits 3..0 (assembled as zero.)
54 * \2ab - a ModRM, calculated on EA in operand a, with the spare
55 * field equal to digit b.
56 * \250..\253 - same as \150..\153, except warn if the 64-bit operand
57 * is not equal to the truncated and sign-extended 32-bit
58 * operand; used for 32-bit immediates in 64-bit mode.
59 * \260..\263 - this instruction uses VEX rather than REX, with the
60 * V field taken from operand 0..3.
61 * \270 - this instruction uses VEX rather than REX, with the
62 * V field set to 1111b.
63 *
64 * VEX prefixes are followed by the sequence:
65 * \mm\wlp where mm is the M field; and wlp is:
66 * 00 0ww lpp
67 * [w0] ww = 0 for W = 0
68 * [w1] ww = 1 for W = 1
69 * [wx] ww = 2 for W don't care (always assembled as 0)
70 * [ww] ww = 3 for W used as REX.W
71 *
72 *
73 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
74 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
75 * \312 - (disassembler only) marker on LOOP, LOOPxx instructions.
76 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
77 * \314 - (disassembler only) invalid with REX.B
78 * \315 - (disassembler only) invalid with REX.X
79 * \316 - (disassembler only) invalid with REX.R
80 * \317 - (disassembler only) invalid with REX.W
81 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
82 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
83 * \322 - indicates that this instruction is only valid when the
84 * operand size is the default (instruction to disassembler,
85 * generates no code in the assembler)
86 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
87 * \324 - indicates 64-bit operand size requiring REX prefix.
88 * \330 - a literal byte follows in the code stream, to be added
89 * to the condition code value of the instruction.
90 * \331 - instruction not valid with REP prefix. Hint for
91 * disassembler only; for SSE instructions.
92 * \332 - REP prefix (0xF2 byte) used as opcode extension.
93 * \333 - REP prefix (0xF3 byte) used as opcode extension.
94 * \334 - LOCK prefix used instead of REX.R
95 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
96 * \336 - force a REP(E) prefix (0xF2) even if not specified.
97 * \337 - force a REPNE prefix (0xF3) even if not specified.
98 * \336-\337 are still listed as prefixes in the disassembler.
99 * \340 - reserve <operand 0> bytes of uninitialized storage.
100 * Operand 0 had better be a segmentless constant.
101 * \360 - no SSE prefix (== \364\331)
102 * \361 - 66 SSE prefix (== \366\331)
103 * \362 - F2 SSE prefix (== \364\332)
104 * \363 - F3 SSE prefix (== \364\333)
105 * \364 - operand-size prefix (0x66) not permitted
106 * \365 - address-size prefix (0x67) not permitted
107 * \366 - operand-size prefix (0x66) used as opcode extension
108 * \367 - address-size prefix (0x67) used as opcode extension
109 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
110 * 370 is used for Jcc, 371 is used for JMP.
111 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
112 * used for conditional jump over longer jump
113 */
114
115 #include "compiler.h"
116
117 #include <stdio.h>
118 #include <string.h>
119 #include <inttypes.h>
120
121 #include "nasm.h"
122 #include "nasmlib.h"
123 #include "assemble.h"
124 #include "insns.h"
125 #include "tables.h"
126
127 /* Initialized to zero by the C standard */
128 static const uint8_t const_zero_buf[256];
129
130 typedef struct {
131 int sib_present; /* is a SIB byte necessary? */
132 int bytes; /* # of bytes of offset needed */
133 int size; /* lazy - this is sib+bytes+1 */
134 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
135 } ea;
136
137 static uint32_t cpu; /* cpu level received from nasm.c */
138 static efunc errfunc;
139 static struct ofmt *outfmt;
140 static ListGen *list;
141
142 static int64_t calcsize(int32_t, int64_t, int, insn *, const uint8_t *);
143 static void gencode(int32_t, int64_t, int, insn *, const uint8_t *, int64_t);
144 static int matches(const struct itemplate *, insn *, int bits);
145 static int32_t regflag(const operand *);
146 static int32_t regval(const operand *);
147 static int rexflags(int, int32_t, int);
148 static int op_rexflags(const operand *, int);
149 static ea *process_ea(operand *, ea *, int, int, int, int32_t);
150 static void add_asp(insn *, int);
151
152 static int has_prefix(insn * ins, enum prefix_pos pos, enum prefixes prefix)
153 {
154 return ins->prefixes[pos] == prefix;
155 }
156
157 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
158 {
159 if (ins->prefixes[pos])
160 errfunc(ERR_NONFATAL, "invalid %s prefix",
161 prefix_name(ins->prefixes[pos]));
162 }
163
164 static const char *size_name(int size)
165 {
166 switch (size) {
167 case 1:
168 return "byte";
169 case 2:
170 return "word";
171 case 4:
172 return "dword";
173 case 8:
174 return "qword";
175 case 10:
176 return "tword";
177 case 16:
178 return "oword";
179 case 32:
180 return "yword";
181 default:
182 return "???";
183 }
184 }
185
186 static void warn_overflow(int size, int64_t data)
187 {
188 if (size < 8) {
189 int64_t lim = ((int64_t)1 << (size*8))-1;
190
191 if (data < ~lim || data > lim)
192 errfunc(ERR_WARNING | ERR_WARN_NOV,
193 "%s data exceeds bounds", size_name(size));
194 }
195 }
196 /*
197 * This routine wrappers the real output format's output routine,
198 * in order to pass a copy of the data off to the listing file
199 * generator at the same time.
200 */
201 static void out(int64_t offset, int32_t segto, const void *data,
202 enum out_type type, uint64_t size,
203 int32_t segment, int32_t wrt)
204 {
205 static int32_t lineno = 0; /* static!!! */
206 static char *lnfname = NULL;
207 uint8_t p[8];
208
209 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
210 /*
211 * This is a non-relocated address, and we're going to
212 * convert it into RAWDATA format.
213 */
214 uint8_t *q = p;
215
216 if (size > 8) {
217 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
218 return;
219 }
220
221 WRITEADDR(q, *(int64_t *)data, size);
222 data = p;
223 type = OUT_RAWDATA;
224 }
225
226 list->output(offset, data, type, size);
227
228 /*
229 * this call to src_get determines when we call the
230 * debug-format-specific "linenum" function
231 * it updates lineno and lnfname to the current values
232 * returning 0 if "same as last time", -2 if lnfname
233 * changed, and the amount by which lineno changed,
234 * if it did. thus, these variables must be static
235 */
236
237 if (src_get(&lineno, &lnfname)) {
238 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
239 }
240
241 outfmt->output(segto, data, type, size, segment, wrt);
242 }
243
244 static bool jmp_match(int32_t segment, int64_t offset, int bits,
245 insn * ins, const uint8_t *code)
246 {
247 int64_t isize;
248 uint8_t c = code[0];
249
250 if ((c != 0370 && c != 0371) || (ins->oprs[0].type & STRICT))
251 return false;
252 if (!optimizing)
253 return false;
254 if (optimizing < 0 && c == 0371)
255 return false;
256
257 isize = calcsize(segment, offset, bits, ins, code);
258 if (ins->oprs[0].segment != segment)
259 return false;
260
261 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
262 return (isize >= -128 && isize <= 127); /* is it byte size? */
263 }
264
265 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
266 insn * instruction, struct ofmt *output, efunc error,
267 ListGen * listgen)
268 {
269 const struct itemplate *temp;
270 int j;
271 int size_prob;
272 int64_t insn_end;
273 int32_t itimes;
274 int64_t start = offset;
275 int64_t wsize = 0; /* size for DB etc. */
276
277 errfunc = error; /* to pass to other functions */
278 cpu = cp;
279 outfmt = output; /* likewise */
280 list = listgen; /* and again */
281
282 switch (instruction->opcode) {
283 case -1:
284 return 0;
285 case I_DB:
286 wsize = 1;
287 break;
288 case I_DW:
289 wsize = 2;
290 break;
291 case I_DD:
292 wsize = 4;
293 break;
294 case I_DQ:
295 wsize = 8;
296 break;
297 case I_DT:
298 wsize = 10;
299 break;
300 case I_DO:
301 wsize = 16;
302 break;
303 case I_DY:
304 wsize = 32;
305 break;
306 default:
307 break;
308 }
309
310 if (wsize) {
311 extop *e;
312 int32_t t = instruction->times;
313 if (t < 0)
314 errfunc(ERR_PANIC,
315 "instruction->times < 0 (%ld) in assemble()", t);
316
317 while (t--) { /* repeat TIMES times */
318 for (e = instruction->eops; e; e = e->next) {
319 if (e->type == EOT_DB_NUMBER) {
320 if (wsize == 1) {
321 if (e->segment != NO_SEG)
322 errfunc(ERR_NONFATAL,
323 "one-byte relocation attempted");
324 else {
325 uint8_t out_byte = e->offset;
326 out(offset, segment, &out_byte,
327 OUT_RAWDATA, 1, NO_SEG, NO_SEG);
328 }
329 } else if (wsize > 8) {
330 errfunc(ERR_NONFATAL,
331 "integer supplied to a DT, DO or DY"
332 " instruction");
333 } else
334 out(offset, segment, &e->offset,
335 OUT_ADDRESS, wsize, e->segment, e->wrt);
336 offset += wsize;
337 } else if (e->type == EOT_DB_STRING ||
338 e->type == EOT_DB_STRING_FREE) {
339 int align;
340
341 out(offset, segment, e->stringval,
342 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
343 align = e->stringlen % wsize;
344
345 if (align) {
346 align = wsize - align;
347 out(offset, segment, const_zero_buf,
348 OUT_RAWDATA, align, NO_SEG, NO_SEG);
349 }
350 offset += e->stringlen + align;
351 }
352 }
353 if (t > 0 && t == instruction->times - 1) {
354 /*
355 * Dummy call to list->output to give the offset to the
356 * listing module.
357 */
358 list->output(offset, NULL, OUT_RAWDATA, 0);
359 list->uplevel(LIST_TIMES);
360 }
361 }
362 if (instruction->times > 1)
363 list->downlevel(LIST_TIMES);
364 return offset - start;
365 }
366
367 if (instruction->opcode == I_INCBIN) {
368 const char *fname = instruction->eops->stringval;
369 FILE *fp;
370
371 fp = fopen(fname, "rb");
372 if (!fp) {
373 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
374 fname);
375 } else if (fseek(fp, 0L, SEEK_END) < 0) {
376 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
377 fname);
378 } else {
379 static char buf[4096];
380 size_t t = instruction->times;
381 size_t base = 0;
382 size_t len;
383
384 len = ftell(fp);
385 if (instruction->eops->next) {
386 base = instruction->eops->next->offset;
387 len -= base;
388 if (instruction->eops->next->next &&
389 len > (size_t)instruction->eops->next->next->offset)
390 len = (size_t)instruction->eops->next->next->offset;
391 }
392 /*
393 * Dummy call to list->output to give the offset to the
394 * listing module.
395 */
396 list->output(offset, NULL, OUT_RAWDATA, 0);
397 list->uplevel(LIST_INCBIN);
398 while (t--) {
399 size_t l;
400
401 fseek(fp, base, SEEK_SET);
402 l = len;
403 while (l > 0) {
404 int32_t m =
405 fread(buf, 1, (l > (int32_t) sizeof(buf) ? (int32_t) sizeof(buf) : l),
406 fp);
407 if (!m) {
408 /*
409 * This shouldn't happen unless the file
410 * actually changes while we are reading
411 * it.
412 */
413 error(ERR_NONFATAL,
414 "`incbin': unexpected EOF while"
415 " reading file `%s'", fname);
416 t = 0; /* Try to exit cleanly */
417 break;
418 }
419 out(offset, segment, buf, OUT_RAWDATA, m,
420 NO_SEG, NO_SEG);
421 l -= m;
422 }
423 }
424 list->downlevel(LIST_INCBIN);
425 if (instruction->times > 1) {
426 /*
427 * Dummy call to list->output to give the offset to the
428 * listing module.
429 */
430 list->output(offset, NULL, OUT_RAWDATA, 0);
431 list->uplevel(LIST_TIMES);
432 list->downlevel(LIST_TIMES);
433 }
434 fclose(fp);
435 return instruction->times * len;
436 }
437 return 0; /* if we're here, there's an error */
438 }
439
440 /* Check to see if we need an address-size prefix */
441 add_asp(instruction, bits);
442
443 size_prob = false;
444
445 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++){
446 int m = matches(temp, instruction, bits);
447 if (m == 100 ||
448 (m == 99 && jmp_match(segment, offset, bits,
449 instruction, temp->code))) {
450 /* Matches! */
451 const uint8_t *codes = temp->code;
452 int64_t insn_size = calcsize(segment, offset, bits,
453 instruction, codes);
454 itimes = instruction->times;
455 if (insn_size < 0) /* shouldn't be, on pass two */
456 error(ERR_PANIC, "errors made it through from pass one");
457 else
458 while (itimes--) {
459 for (j = 0; j < MAXPREFIX; j++) {
460 uint8_t c = 0;
461 switch (instruction->prefixes[j]) {
462 case P_LOCK:
463 c = 0xF0;
464 break;
465 case P_REPNE:
466 case P_REPNZ:
467 c = 0xF2;
468 break;
469 case P_REPE:
470 case P_REPZ:
471 case P_REP:
472 c = 0xF3;
473 break;
474 case R_CS:
475 if (bits == 64) {
476 error(ERR_WARNING,
477 "cs segment base generated, but will be ignored in 64-bit mode");
478 }
479 c = 0x2E;
480 break;
481 case R_DS:
482 if (bits == 64) {
483 error(ERR_WARNING,
484 "ds segment base generated, but will be ignored in 64-bit mode");
485 }
486 c = 0x3E;
487 break;
488 case R_ES:
489 if (bits == 64) {
490 error(ERR_WARNING,
491 "es segment base generated, but will be ignored in 64-bit mode");
492 }
493 c = 0x26;
494 break;
495 case R_FS:
496 c = 0x64;
497 break;
498 case R_GS:
499 c = 0x65;
500 break;
501 case R_SS:
502 if (bits == 64) {
503 error(ERR_WARNING,
504 "ss segment base generated, but will be ignored in 64-bit mode");
505 }
506 c = 0x36;
507 break;
508 case R_SEGR6:
509 case R_SEGR7:
510 error(ERR_NONFATAL,
511 "segr6 and segr7 cannot be used as prefixes");
512 break;
513 case P_A16:
514 if (bits == 64) {
515 error(ERR_NONFATAL,
516 "16-bit addressing is not supported "
517 "in 64-bit mode");
518 } else if (bits != 16)
519 c = 0x67;
520 break;
521 case P_A32:
522 if (bits != 32)
523 c = 0x67;
524 break;
525 case P_A64:
526 if (bits != 64) {
527 error(ERR_NONFATAL,
528 "64-bit addressing is only supported "
529 "in 64-bit mode");
530 }
531 break;
532 case P_ASP:
533 c = 0x67;
534 break;
535 case P_O16:
536 if (bits != 16)
537 c = 0x66;
538 break;
539 case P_O32:
540 if (bits == 16)
541 c = 0x66;
542 break;
543 case P_O64:
544 /* REX.W */
545 break;
546 case P_OSP:
547 c = 0x66;
548 break;
549 case P_none:
550 break;
551 default:
552 error(ERR_PANIC, "invalid instruction prefix");
553 }
554 if (c != 0) {
555 out(offset, segment, &c, OUT_RAWDATA, 1,
556 NO_SEG, NO_SEG);
557 offset++;
558 }
559 }
560 insn_end = offset + insn_size;
561 gencode(segment, offset, bits, instruction, codes,
562 insn_end);
563 offset += insn_size;
564 if (itimes > 0 && itimes == instruction->times - 1) {
565 /*
566 * Dummy call to list->output to give the offset to the
567 * listing module.
568 */
569 list->output(offset, NULL, OUT_RAWDATA, 0);
570 list->uplevel(LIST_TIMES);
571 }
572 }
573 if (instruction->times > 1)
574 list->downlevel(LIST_TIMES);
575 return offset - start;
576 } else if (m > 0 && m > size_prob) {
577 size_prob = m;
578 }
579 }
580
581 if (temp->opcode == -1) { /* didn't match any instruction */
582 switch (size_prob) {
583 case 1:
584 error(ERR_NONFATAL, "operation size not specified");
585 break;
586 case 2:
587 error(ERR_NONFATAL, "mismatch in operand sizes");
588 break;
589 case 3:
590 error(ERR_NONFATAL, "no instruction for this cpu level");
591 break;
592 case 4:
593 error(ERR_NONFATAL, "instruction not supported in 64-bit mode");
594 break;
595 default:
596 error(ERR_NONFATAL,
597 "invalid combination of opcode and operands");
598 break;
599 }
600 }
601 return 0;
602 }
603
604 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
605 insn * instruction, efunc error)
606 {
607 const struct itemplate *temp;
608
609 errfunc = error; /* to pass to other functions */
610 cpu = cp;
611
612 if (instruction->opcode == -1)
613 return 0;
614
615 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
616 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
617 instruction->opcode == I_DT || instruction->opcode == I_DO ||
618 instruction->opcode == I_DY) {
619 extop *e;
620 int32_t isize, osize, wsize = 0; /* placate gcc */
621
622 isize = 0;
623 switch (instruction->opcode) {
624 case I_DB:
625 wsize = 1;
626 break;
627 case I_DW:
628 wsize = 2;
629 break;
630 case I_DD:
631 wsize = 4;
632 break;
633 case I_DQ:
634 wsize = 8;
635 break;
636 case I_DT:
637 wsize = 10;
638 break;
639 case I_DO:
640 wsize = 16;
641 break;
642 case I_DY:
643 wsize = 32;
644 break;
645 default:
646 break;
647 }
648
649 for (e = instruction->eops; e; e = e->next) {
650 int32_t align;
651
652 osize = 0;
653 if (e->type == EOT_DB_NUMBER)
654 osize = 1;
655 else if (e->type == EOT_DB_STRING ||
656 e->type == EOT_DB_STRING_FREE)
657 osize = e->stringlen;
658
659 align = (-osize) % wsize;
660 if (align < 0)
661 align += wsize;
662 isize += osize + align;
663 }
664 return isize * instruction->times;
665 }
666
667 if (instruction->opcode == I_INCBIN) {
668 const char *fname = instruction->eops->stringval;
669 FILE *fp;
670 size_t len;
671
672 fp = fopen(fname, "rb");
673 if (!fp)
674 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
675 fname);
676 else if (fseek(fp, 0L, SEEK_END) < 0)
677 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
678 fname);
679 else {
680 len = ftell(fp);
681 fclose(fp);
682 if (instruction->eops->next) {
683 len -= instruction->eops->next->offset;
684 if (instruction->eops->next->next &&
685 len > (size_t)instruction->eops->next->next->offset) {
686 len = (size_t)instruction->eops->next->next->offset;
687 }
688 }
689 return instruction->times * len;
690 }
691 return 0; /* if we're here, there's an error */
692 }
693
694 /* Check to see if we need an address-size prefix */
695 add_asp(instruction, bits);
696
697 for (temp = nasm_instructions[instruction->opcode]; temp->opcode != -1; temp++) {
698 int m = matches(temp, instruction, bits);
699 if (m == 100 ||
700 (m == 99 && jmp_match(segment, offset, bits,
701 instruction, temp->code))) {
702 /* we've matched an instruction. */
703 int64_t isize;
704 const uint8_t *codes = temp->code;
705 int j;
706
707 isize = calcsize(segment, offset, bits, instruction, codes);
708 if (isize < 0)
709 return -1;
710 for (j = 0; j < MAXPREFIX; j++) {
711 switch (instruction->prefixes[j]) {
712 case P_A16:
713 if (bits != 16)
714 isize++;
715 break;
716 case P_A32:
717 if (bits != 32)
718 isize++;
719 break;
720 case P_O16:
721 if (bits != 16)
722 isize++;
723 break;
724 case P_O32:
725 if (bits == 16)
726 isize++;
727 break;
728 case P_A64:
729 case P_O64:
730 case P_none:
731 break;
732 default:
733 isize++;
734 break;
735 }
736 }
737 return isize * instruction->times;
738 }
739 }
740 return -1; /* didn't match any instruction */
741 }
742
743 static bool possible_sbyte(operand *o)
744 {
745 return !(o->opflags & OPFLAG_FORWARD) &&
746 optimizing >= 0 && !(o->type & STRICT) &&
747 o->wrt == NO_SEG && o->segment == NO_SEG;
748 }
749
750 /* check that opn[op] is a signed byte of size 16 or 32 */
751 static bool is_sbyte16(operand *o)
752 {
753 int16_t v;
754
755 if (!possible_sbyte(o))
756 return false;
757
758 v = o->offset;
759 return v >= -128 && v <= 127;
760 }
761
762 static bool is_sbyte32(operand *o)
763 {
764 int32_t v;
765
766 if (!possible_sbyte(o))
767 return false;
768
769 v = o->offset;
770 return v >= -128 && v <= 127;
771 }
772
773 /* check that opn[op] is a signed byte of size 32; warn if this is not
774 the original value when extended to 64 bits */
775 static bool is_sbyte64(operand *o)
776 {
777 int64_t v64;
778 int32_t v32;
779
780 /* dead in the water on forward reference or External */
781 if (!possible_sbyte(o))
782 return false;
783
784 v64 = o->offset;
785 v32 = (int32_t)v64;
786
787 warn_overflow(32, v64);
788
789 return v32 >= -128 && v32 <= 127;
790 }
791 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
792 insn * ins, const uint8_t *codes)
793 {
794 int64_t length = 0;
795 uint8_t c;
796 int rex_mask = ~0;
797 struct operand *opx;
798
799 ins->rex = 0; /* Ensure REX is reset */
800
801 if (ins->prefixes[PPS_OSIZE] == P_O64)
802 ins->rex |= REX_W;
803
804 (void)segment; /* Don't warn that this parameter is unused */
805 (void)offset; /* Don't warn that this parameter is unused */
806
807 while (*codes) {
808 c = *codes++;
809 opx = &ins->oprs[c & 3];
810 switch (c) {
811 case 01:
812 case 02:
813 case 03:
814 codes += c, length += c;
815 break;
816 case 04:
817 case 05:
818 case 06:
819 case 07:
820 length++;
821 break;
822 case 010:
823 case 011:
824 case 012:
825 case 013:
826 ins->rex |=
827 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
828 codes++, length++;
829 break;
830 case 014:
831 case 015:
832 case 016:
833 case 017:
834 length++;
835 break;
836 case 020:
837 case 021:
838 case 022:
839 case 023:
840 length++;
841 break;
842 case 024:
843 case 025:
844 case 026:
845 case 027:
846 length++;
847 break;
848 case 030:
849 case 031:
850 case 032:
851 case 033:
852 length += 2;
853 break;
854 case 034:
855 case 035:
856 case 036:
857 case 037:
858 if (opx->type & (BITS16 | BITS32 | BITS64))
859 length += (opx->type & BITS16) ? 2 : 4;
860 else
861 length += (bits == 16) ? 2 : 4;
862 break;
863 case 040:
864 case 041:
865 case 042:
866 case 043:
867 length += 4;
868 break;
869 case 044:
870 case 045:
871 case 046:
872 case 047:
873 length += ins->addr_size >> 3;
874 break;
875 case 050:
876 case 051:
877 case 052:
878 case 053:
879 length++;
880 break;
881 case 054:
882 case 055:
883 case 056:
884 case 057:
885 length += 8; /* MOV reg64/imm */
886 break;
887 case 060:
888 case 061:
889 case 062:
890 case 063:
891 length += 2;
892 break;
893 case 064:
894 case 065:
895 case 066:
896 case 067:
897 if (opx->type & (BITS16 | BITS32 | BITS64))
898 length += (opx->type & BITS16) ? 2 : 4;
899 else
900 length += (bits == 16) ? 2 : 4;
901 break;
902 case 070:
903 case 071:
904 case 072:
905 case 073:
906 length += 4;
907 break;
908 case 074:
909 case 075:
910 case 076:
911 case 077:
912 length += 2;
913 break;
914 case 0140:
915 case 0141:
916 case 0142:
917 case 0143:
918 length += is_sbyte16(opx) ? 1 : 2;
919 break;
920 case 0144:
921 case 0145:
922 case 0146:
923 case 0147:
924 codes++;
925 length++;
926 break;
927 case 0150:
928 case 0151:
929 case 0152:
930 case 0153:
931 length += is_sbyte32(opx) ? 1 : 4;
932 break;
933 case 0154:
934 case 0155:
935 case 0156:
936 case 0157:
937 codes++;
938 length++;
939 break;
940 case 0160:
941 case 0161:
942 case 0162:
943 case 0163:
944 length++;
945 ins->rex |= REX_D;
946 ins->drexdst = regval(opx);
947 break;
948 case 0164:
949 case 0165:
950 case 0166:
951 case 0167:
952 length++;
953 ins->rex |= REX_D|REX_OC;
954 ins->drexdst = regval(opx);
955 break;
956 case 0171:
957 break;
958 case 0172:
959 case 0173:
960 case 0174:
961 codes++;
962 length++;
963 break;
964 case 0250:
965 case 0251:
966 case 0252:
967 case 0253:
968 length += is_sbyte64(opx) ? 1 : 4;
969 break;
970 case 0260:
971 case 0261:
972 case 0262:
973 case 0263:
974 ins->rex |= REX_V;
975 ins->drexdst = regval(opx);
976 ins->vex_m = *codes++;
977 ins->vex_wlp = *codes++;
978 break;
979 case 0270:
980 ins->rex |= REX_V;
981 ins->drexdst = 0;
982 ins->vex_m = *codes++;
983 ins->vex_wlp = *codes++;
984 break;
985 case 0300:
986 case 0301:
987 case 0302:
988 case 0303:
989 break;
990 case 0310:
991 if (bits == 64)
992 return -1;
993 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
994 break;
995 case 0311:
996 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
997 break;
998 case 0312:
999 break;
1000 case 0313:
1001 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1002 has_prefix(ins, PPS_ASIZE, P_A32))
1003 return -1;
1004 break;
1005 case 0314:
1006 case 0315:
1007 case 0316:
1008 case 0317:
1009 break;
1010 case 0320:
1011 length += (bits != 16);
1012 break;
1013 case 0321:
1014 length += (bits == 16);
1015 break;
1016 case 0322:
1017 break;
1018 case 0323:
1019 rex_mask &= ~REX_W;
1020 break;
1021 case 0324:
1022 ins->rex |= REX_W;
1023 break;
1024 case 0330:
1025 codes++, length++;
1026 break;
1027 case 0331:
1028 break;
1029 case 0332:
1030 case 0333:
1031 length++;
1032 break;
1033 case 0334:
1034 ins->rex |= REX_L;
1035 break;
1036 case 0335:
1037 break;
1038 case 0336:
1039 if (!ins->prefixes[PPS_LREP])
1040 ins->prefixes[PPS_LREP] = P_REP;
1041 break;
1042 case 0337:
1043 if (!ins->prefixes[PPS_LREP])
1044 ins->prefixes[PPS_LREP] = P_REPNE;
1045 break;
1046 case 0340:
1047 if (ins->oprs[0].segment != NO_SEG)
1048 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1049 " quantity of BSS space");
1050 else
1051 length += ins->oprs[0].offset;
1052 break;
1053 case 0360:
1054 break;
1055 case 0361:
1056 case 0362:
1057 case 0363:
1058 length++;
1059 break;
1060 case 0364:
1061 case 0365:
1062 break;
1063 case 0366:
1064 case 0367:
1065 length++;
1066 break;
1067 case 0370:
1068 case 0371:
1069 case 0372:
1070 break;
1071 case 0373:
1072 length++;
1073 break;
1074 default: /* can't do it by 'case' statements */
1075 if (c >= 0100 && c <= 0277) { /* it's an EA */
1076 ea ea_data;
1077 int rfield;
1078 int32_t rflags;
1079 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1080
1081 if (c <= 0177) {
1082 /* pick rfield from operand b */
1083 rflags = regflag(&ins->oprs[c & 7]);
1084 rfield = nasm_regvals[ins->oprs[c & 7].basereg];
1085 } else {
1086 rflags = 0;
1087 rfield = c & 7;
1088 }
1089
1090 if (!process_ea
1091 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1092 ins->addr_size, rfield, rflags)) {
1093 errfunc(ERR_NONFATAL, "invalid effective address");
1094 return -1;
1095 } else {
1096 ins->rex |= ea_data.rex;
1097 length += ea_data.size;
1098 }
1099 } else {
1100 errfunc(ERR_PANIC, "internal instruction table corrupt"
1101 ": instruction code 0x%02X given", c);
1102 }
1103 }
1104 }
1105
1106 ins->rex &= rex_mask;
1107
1108 if (ins->rex & REX_V) {
1109 int bad32 = REX_R|REX_W|REX_X|REX_B;
1110
1111 if (ins->rex & REX_H) {
1112 errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
1113 return -1;
1114 }
1115 switch (ins->vex_wlp & 030) {
1116 case 000:
1117 case 020:
1118 ins->rex &= ~REX_W;
1119 break;
1120 case 010:
1121 ins->rex |= REX_W;
1122 bad32 &= ~REX_W;
1123 break;
1124 case 030:
1125 /* Follow REX_W */
1126 break;
1127 }
1128
1129 if (bits != 64 && ((ins->rex & bad32) || ins->drexdst > 7)) {
1130 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1131 return -1;
1132 }
1133 if (ins->vex_m != 1 || (ins->rex & (REX_W|REX_R|REX_B)))
1134 length += 3;
1135 else
1136 length += 2;
1137 } else if (ins->rex & REX_D) {
1138 if (ins->rex & REX_H) {
1139 errfunc(ERR_NONFATAL, "cannot use high register in drex instruction");
1140 return -1;
1141 }
1142 if (bits != 64 && ((ins->rex & (REX_R|REX_W|REX_X|REX_B)) ||
1143 ins->drexdst > 7)) {
1144 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1145 return -1;
1146 }
1147 length++;
1148 } else if (ins->rex & REX_REAL) {
1149 if (ins->rex & REX_H) {
1150 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1151 return -1;
1152 } else if (bits == 64) {
1153 length++;
1154 } else if ((ins->rex & REX_L) &&
1155 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1156 cpu >= IF_X86_64) {
1157 /* LOCK-as-REX.R */
1158 assert_no_prefix(ins, PPS_LREP);
1159 length++;
1160 } else {
1161 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1162 return -1;
1163 }
1164 }
1165
1166 return length;
1167 }
1168
1169 #define EMIT_REX() \
1170 if (!(ins->rex & (REX_D|REX_V)) && (ins->rex & REX_REAL) && (bits == 64)) { \
1171 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1172 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1173 ins->rex = 0; \
1174 offset += 1; \
1175 }
1176
1177 static void gencode(int32_t segment, int64_t offset, int bits,
1178 insn * ins, const uint8_t *codes, int64_t insn_end)
1179 {
1180 static char condval[] = { /* conditional opcodes */
1181 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1182 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1183 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1184 };
1185 uint8_t c;
1186 uint8_t bytes[4];
1187 int64_t size;
1188 int64_t data;
1189 struct operand *opx;
1190
1191 while (*codes) {
1192 c = *codes++;
1193 opx = &ins->oprs[c & 3];
1194 switch (c) {
1195 case 01:
1196 case 02:
1197 case 03:
1198 EMIT_REX();
1199 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1200 codes += c;
1201 offset += c;
1202 break;
1203
1204 case 04:
1205 case 06:
1206 switch (ins->oprs[0].basereg) {
1207 case R_CS:
1208 bytes[0] = 0x0E + (c == 0x04 ? 1 : 0);
1209 break;
1210 case R_DS:
1211 bytes[0] = 0x1E + (c == 0x04 ? 1 : 0);
1212 break;
1213 case R_ES:
1214 bytes[0] = 0x06 + (c == 0x04 ? 1 : 0);
1215 break;
1216 case R_SS:
1217 bytes[0] = 0x16 + (c == 0x04 ? 1 : 0);
1218 break;
1219 default:
1220 errfunc(ERR_PANIC,
1221 "bizarre 8086 segment register received");
1222 }
1223 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1224 offset++;
1225 break;
1226
1227 case 05:
1228 case 07:
1229 switch (ins->oprs[0].basereg) {
1230 case R_FS:
1231 bytes[0] = 0xA0 + (c == 0x05 ? 1 : 0);
1232 break;
1233 case R_GS:
1234 bytes[0] = 0xA8 + (c == 0x05 ? 1 : 0);
1235 break;
1236 default:
1237 errfunc(ERR_PANIC,
1238 "bizarre 386 segment register received");
1239 }
1240 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1241 offset++;
1242 break;
1243
1244 case 010:
1245 case 011:
1246 case 012:
1247 case 013:
1248 EMIT_REX();
1249 bytes[0] = *codes++ + ((regval(opx)) & 7);
1250 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1251 offset += 1;
1252 break;
1253
1254 case 014:
1255 case 015:
1256 case 016:
1257 case 017:
1258 /* The test for BITS8 and SBYTE here is intended to avoid
1259 warning on optimizer actions due to SBYTE, while still
1260 warn on explicit BYTE directives. Also warn, obviously,
1261 if the optimizer isn't enabled. */
1262 if (((opx->type & BITS8) ||
1263 !(opx->type & (SBYTE16|SBYTE32|SBYTE64))) &&
1264 (opx->offset < -128 || opx->offset > 127)) {
1265 errfunc(ERR_WARNING | ERR_WARN_NOV,
1266 "signed byte value exceeds bounds");
1267 }
1268 if (opx->segment != NO_SEG) {
1269 data = opx->offset;
1270 out(offset, segment, &data, OUT_ADDRESS, 1,
1271 opx->segment, opx->wrt);
1272 } else {
1273 bytes[0] = opx->offset;
1274 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1275 NO_SEG);
1276 }
1277 offset += 1;
1278 break;
1279
1280 case 020:
1281 case 021:
1282 case 022:
1283 case 023:
1284 if (opx->offset < -256 || opx->offset > 255) {
1285 errfunc(ERR_WARNING | ERR_WARN_NOV,
1286 "byte value exceeds bounds");
1287 }
1288 if (opx->segment != NO_SEG) {
1289 data = opx->offset;
1290 out(offset, segment, &data, OUT_ADDRESS, 1,
1291 opx->segment, opx->wrt);
1292 } else {
1293 bytes[0] = opx->offset;
1294 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1295 NO_SEG);
1296 }
1297 offset += 1;
1298 break;
1299
1300 case 024:
1301 case 025:
1302 case 026:
1303 case 027:
1304 if (opx->offset < 0 || opx->offset > 255)
1305 errfunc(ERR_WARNING | ERR_WARN_NOV,
1306 "unsigned byte value exceeds bounds");
1307 if (opx->segment != NO_SEG) {
1308 data = opx->offset;
1309 out(offset, segment, &data, OUT_ADDRESS, 1,
1310 opx->segment, opx->wrt);
1311 } else {
1312 bytes[0] = opx->offset;
1313 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1314 NO_SEG);
1315 }
1316 offset += 1;
1317 break;
1318
1319 case 030:
1320 case 031:
1321 case 032:
1322 case 033:
1323 data = opx->offset;
1324 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1325 warn_overflow(2, data);
1326 out(offset, segment, &data, OUT_ADDRESS, 2,
1327 opx->segment, opx->wrt);
1328 offset += 2;
1329 break;
1330
1331 case 034:
1332 case 035:
1333 case 036:
1334 case 037:
1335 if (opx->type & (BITS16 | BITS32))
1336 size = (opx->type & BITS16) ? 2 : 4;
1337 else
1338 size = (bits == 16) ? 2 : 4;
1339 data = opx->offset;
1340 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1341 warn_overflow(size, data);
1342 out(offset, segment, &data, OUT_ADDRESS, size,
1343 opx->segment, opx->wrt);
1344 offset += size;
1345 break;
1346
1347 case 040:
1348 case 041:
1349 case 042:
1350 case 043:
1351 data = opx->offset;
1352 if (opx->segment == NO_SEG && opx->wrt == NO_SEG)
1353 warn_overflow(4, data);
1354 out(offset, segment, &data, OUT_ADDRESS, 4,
1355 opx->segment, opx->wrt);
1356 offset += 4;
1357 break;
1358
1359 case 044:
1360 case 045:
1361 case 046:
1362 case 047:
1363 data = opx->offset;
1364 size = ins->addr_size >> 3;
1365 if (opx->segment == NO_SEG &&
1366 opx->wrt == NO_SEG)
1367 warn_overflow(size, data);
1368 out(offset, segment, &data, OUT_ADDRESS, size,
1369 opx->segment, opx->wrt);
1370 offset += size;
1371 break;
1372
1373 case 050:
1374 case 051:
1375 case 052:
1376 case 053:
1377 if (opx->segment != segment)
1378 errfunc(ERR_NONFATAL,
1379 "short relative jump outside segment");
1380 data = opx->offset - insn_end;
1381 if (data > 127 || data < -128)
1382 errfunc(ERR_NONFATAL, "short jump is out of range");
1383 bytes[0] = data;
1384 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1385 offset += 1;
1386 break;
1387
1388 case 054:
1389 case 055:
1390 case 056:
1391 case 057:
1392 data = (int64_t)opx->offset;
1393 out(offset, segment, &data, OUT_ADDRESS, 8,
1394 opx->segment, opx->wrt);
1395 offset += 8;
1396 break;
1397
1398 case 060:
1399 case 061:
1400 case 062:
1401 case 063:
1402 if (opx->segment != segment) {
1403 data = opx->offset;
1404 out(offset, segment, &data,
1405 OUT_REL2ADR, insn_end - offset,
1406 opx->segment, opx->wrt);
1407 } else {
1408 data = opx->offset - insn_end;
1409 out(offset, segment, &data,
1410 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1411 }
1412 offset += 2;
1413 break;
1414
1415 case 064:
1416 case 065:
1417 case 066:
1418 case 067:
1419 if (opx->type & (BITS16 | BITS32 | BITS64))
1420 size = (opx->type & BITS16) ? 2 : 4;
1421 else
1422 size = (bits == 16) ? 2 : 4;
1423 if (opx->segment != segment) {
1424 data = opx->offset;
1425 out(offset, segment, &data,
1426 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1427 insn_end - offset, opx->segment, opx->wrt);
1428 } else {
1429 data = opx->offset - insn_end;
1430 out(offset, segment, &data,
1431 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1432 }
1433 offset += size;
1434 break;
1435
1436 case 070:
1437 case 071:
1438 case 072:
1439 case 073:
1440 if (opx->segment != segment) {
1441 data = opx->offset;
1442 out(offset, segment, &data,
1443 OUT_REL4ADR, insn_end - offset,
1444 opx->segment, opx->wrt);
1445 } else {
1446 data = opx->offset - insn_end;
1447 out(offset, segment, &data,
1448 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1449 }
1450 offset += 4;
1451 break;
1452
1453 case 074:
1454 case 075:
1455 case 076:
1456 case 077:
1457 if (opx->segment == NO_SEG)
1458 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1459 " relocatable");
1460 data = 0;
1461 out(offset, segment, &data, OUT_ADDRESS, 2,
1462 outfmt->segbase(1 + opx->segment),
1463 opx->wrt);
1464 offset += 2;
1465 break;
1466
1467 case 0140:
1468 case 0141:
1469 case 0142:
1470 case 0143:
1471 data = opx->offset;
1472 if (is_sbyte16(opx)) {
1473 bytes[0] = data;
1474 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1475 NO_SEG);
1476 offset++;
1477 } else {
1478 if (opx->segment == NO_SEG &&
1479 opx->wrt == NO_SEG)
1480 warn_overflow(2, data);
1481 out(offset, segment, &data, OUT_ADDRESS, 2,
1482 opx->segment, opx->wrt);
1483 offset += 2;
1484 }
1485 break;
1486
1487 case 0144:
1488 case 0145:
1489 case 0146:
1490 case 0147:
1491 EMIT_REX();
1492 bytes[0] = *codes++;
1493 if (is_sbyte16(opx))
1494 bytes[0] |= 2; /* s-bit */
1495 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1496 offset++;
1497 break;
1498
1499 case 0150:
1500 case 0151:
1501 case 0152:
1502 case 0153:
1503 data = opx->offset;
1504 if (is_sbyte32(opx)) {
1505 bytes[0] = data;
1506 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1507 NO_SEG);
1508 offset++;
1509 } else {
1510 out(offset, segment, &data, OUT_ADDRESS, 4,
1511 opx->segment, opx->wrt);
1512 offset += 4;
1513 }
1514 break;
1515
1516 case 0154:
1517 case 0155:
1518 case 0156:
1519 case 0157:
1520 EMIT_REX();
1521 bytes[0] = *codes++;
1522 if (is_sbyte32(opx))
1523 bytes[0] |= 2; /* s-bit */
1524 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1525 offset++;
1526 break;
1527
1528 case 0160:
1529 case 0161:
1530 case 0162:
1531 case 0163:
1532 case 0164:
1533 case 0165:
1534 case 0166:
1535 case 0167:
1536 break;
1537
1538 case 0171:
1539 bytes[0] =
1540 (ins->drexdst << 4) |
1541 (ins->rex & REX_OC ? 0x08 : 0) |
1542 (ins->rex & (REX_R|REX_X|REX_B));
1543 ins->rex = 0;
1544 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1545 offset++;
1546 break;
1547
1548 case 0172:
1549 c = *codes++;
1550 opx = &ins->oprs[c >> 3];
1551 bytes[0] = nasm_regvals[opx->basereg] << 4;
1552 opx = &ins->oprs[c & 7];
1553 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1554 errfunc(ERR_NONFATAL,
1555 "non-absolute expression not permitted as argument %d",
1556 c & 7);
1557 } else {
1558 if (opx->offset & ~15) {
1559 errfunc(ERR_WARNING | ERR_WARN_NOV,
1560 "four-bit argument exceeds bounds");
1561 }
1562 bytes[0] |= opx->offset & 15;
1563 }
1564 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1565 offset++;
1566 break;
1567
1568 case 0173:
1569 c = *codes++;
1570 opx = &ins->oprs[c >> 4];
1571 bytes[0] = nasm_regvals[opx->basereg] << 4;
1572 bytes[0] |= c & 15;
1573 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1574 offset++;
1575 break;
1576
1577 case 0174:
1578 c = *codes++;
1579 opx = &ins->oprs[c];
1580 bytes[0] = nasm_regvals[opx->basereg] << 4;
1581 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1582 offset++;
1583 break;
1584
1585 case 0250:
1586 case 0251:
1587 case 0252:
1588 case 0253:
1589 data = opx->offset;
1590 /* is_sbyte32() is right here, we have already warned */
1591 if (is_sbyte32(opx)) {
1592 bytes[0] = data;
1593 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1594 NO_SEG);
1595 offset++;
1596 } else {
1597 out(offset, segment, &data, OUT_ADDRESS, 4,
1598 opx->segment, opx->wrt);
1599 offset += 4;
1600 }
1601 break;
1602
1603 case 0260:
1604 case 0261:
1605 case 0262:
1606 case 0263:
1607 case 0270:
1608 codes += 2;
1609 if (ins->vex_m != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1610 bytes[0] = 0xc4;
1611 bytes[1] = ins->vex_m | ((~ins->rex & 7) << 5);
1612 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1613 ((~ins->drexdst & 15)<< 3) | (ins->vex_wlp & 07);
1614 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1615 offset += 3;
1616 } else {
1617 bytes[0] = 0xc5;
1618 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1619 ((~ins->drexdst & 15) << 3) | (ins->vex_wlp & 07);
1620 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1621 offset += 2;
1622 }
1623 break;
1624
1625 case 0300:
1626 case 0301:
1627 case 0302:
1628 case 0303:
1629 break;
1630
1631 case 0310:
1632 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1633 *bytes = 0x67;
1634 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1635 offset += 1;
1636 } else
1637 offset += 0;
1638 break;
1639
1640 case 0311:
1641 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1642 *bytes = 0x67;
1643 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1644 offset += 1;
1645 } else
1646 offset += 0;
1647 break;
1648
1649 case 0312:
1650 break;
1651
1652 case 0313:
1653 ins->rex = 0;
1654 break;
1655
1656 case 0314:
1657 case 0315:
1658 case 0316:
1659 case 0317:
1660 break;
1661
1662 case 0320:
1663 if (bits != 16) {
1664 *bytes = 0x66;
1665 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1666 offset += 1;
1667 } else
1668 offset += 0;
1669 break;
1670
1671 case 0321:
1672 if (bits == 16) {
1673 *bytes = 0x66;
1674 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1675 offset += 1;
1676 } else
1677 offset += 0;
1678 break;
1679
1680 case 0322:
1681 case 0323:
1682 break;
1683
1684 case 0324:
1685 ins->rex |= REX_W;
1686 break;
1687
1688 case 0330:
1689 *bytes = *codes++ ^ condval[ins->condition];
1690 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1691 offset += 1;
1692 break;
1693
1694 case 0331:
1695 break;
1696
1697 case 0332:
1698 case 0333:
1699 *bytes = c - 0332 + 0xF2;
1700 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1701 offset += 1;
1702 break;
1703
1704 case 0334:
1705 if (ins->rex & REX_R) {
1706 *bytes = 0xF0;
1707 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1708 offset += 1;
1709 }
1710 ins->rex &= ~(REX_L|REX_R);
1711 break;
1712
1713 case 0335:
1714 break;
1715
1716 case 0336:
1717 case 0337:
1718 break;
1719
1720 case 0340:
1721 if (ins->oprs[0].segment != NO_SEG)
1722 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1723 else {
1724 int64_t size = ins->oprs[0].offset;
1725 if (size > 0)
1726 out(offset, segment, NULL,
1727 OUT_RESERVE, size, NO_SEG, NO_SEG);
1728 offset += size;
1729 }
1730 break;
1731
1732 case 0360:
1733 break;
1734
1735 case 0361:
1736 bytes[0] = 0x66;
1737 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1738 offset += 1;
1739 break;
1740
1741 case 0362:
1742 case 0363:
1743 bytes[0] = c - 0362 + 0xf2;
1744 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1745 offset += 1;
1746 break;
1747
1748 case 0364:
1749 case 0365:
1750 break;
1751
1752 case 0366:
1753 case 0367:
1754 *bytes = c - 0366 + 0x66;
1755 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1756 offset += 1;
1757 break;
1758
1759 case 0370:
1760 case 0371:
1761 case 0372:
1762 break;
1763
1764 case 0373:
1765 *bytes = bits == 16 ? 3 : 5;
1766 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1767 offset += 1;
1768 break;
1769
1770 default: /* can't do it by 'case' statements */
1771 if (c >= 0100 && c <= 0277) { /* it's an EA */
1772 ea ea_data;
1773 int rfield;
1774 int32_t rflags;
1775 uint8_t *p;
1776 int32_t s;
1777
1778 if (c <= 0177) {
1779 /* pick rfield from operand b */
1780 rflags = regflag(&ins->oprs[c & 7]);
1781 rfield = nasm_regvals[ins->oprs[c & 7].basereg];
1782 } else {
1783 /* rfield is constant */
1784 rflags = 0;
1785 rfield = c & 7;
1786 }
1787
1788 if (!process_ea
1789 (&ins->oprs[(c >> 3) & 7], &ea_data, bits,
1790 ins->addr_size, rfield, rflags)) {
1791 errfunc(ERR_NONFATAL, "invalid effective address");
1792 }
1793
1794
1795 p = bytes;
1796 *p++ = ea_data.modrm;
1797 if (ea_data.sib_present)
1798 *p++ = ea_data.sib;
1799
1800 /* DREX suffixes come between the SIB and the displacement */
1801 if (ins->rex & REX_D) {
1802 *p++ =
1803 (ins->drexdst << 4) |
1804 (ins->rex & REX_OC ? 0x08 : 0) |
1805 (ins->rex & (REX_R|REX_X|REX_B));
1806 ins->rex = 0;
1807 }
1808
1809 s = p - bytes;
1810 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1811
1812 /*
1813 * Make sure the address gets the right offset in case
1814 * the line breaks in the .lst file (BR 1197827)
1815 */
1816 offset += s;
1817 s = 0;
1818
1819 switch (ea_data.bytes) {
1820 case 0:
1821 break;
1822 case 1:
1823 if (ins->oprs[(c >> 3) & 7].segment != NO_SEG) {
1824 data = ins->oprs[(c >> 3) & 7].offset;
1825 out(offset, segment, &data, OUT_ADDRESS, 1,
1826 ins->oprs[(c >> 3) & 7].segment,
1827 ins->oprs[(c >> 3) & 7].wrt);
1828 } else {
1829 *bytes = ins->oprs[(c >> 3) & 7].offset;
1830 out(offset, segment, bytes, OUT_RAWDATA, 1,
1831 NO_SEG, NO_SEG);
1832 }
1833 s++;
1834 break;
1835 case 8:
1836 case 2:
1837 case 4:
1838 data = ins->oprs[(c >> 3) & 7].offset;
1839 warn_overflow(ea_data.bytes, data);
1840 out(offset, segment, &data,
1841 ea_data.rip ? OUT_REL4ADR : OUT_ADDRESS,
1842 ea_data.bytes,
1843 ins->oprs[(c >> 3) & 7].segment,
1844 ins->oprs[(c >> 3) & 7].wrt);
1845 s += ea_data.bytes;
1846 break;
1847 }
1848 offset += s;
1849 } else {
1850 errfunc(ERR_PANIC, "internal instruction table corrupt"
1851 ": instruction code 0x%02X given", c);
1852 }
1853 }
1854 }
1855 }
1856
1857 static int32_t regflag(const operand * o)
1858 {
1859 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1860 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1861 }
1862 return nasm_reg_flags[o->basereg];
1863 }
1864
1865 static int32_t regval(const operand * o)
1866 {
1867 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1868 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1869 }
1870 return nasm_regvals[o->basereg];
1871 }
1872
1873 static int op_rexflags(const operand * o, int mask)
1874 {
1875 int32_t flags;
1876 int val;
1877
1878 if (o->basereg < EXPR_REG_START || o->basereg >= REG_ENUM_LIMIT) {
1879 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1880 }
1881
1882 flags = nasm_reg_flags[o->basereg];
1883 val = nasm_regvals[o->basereg];
1884
1885 return rexflags(val, flags, mask);
1886 }
1887
1888 static int rexflags(int val, int32_t flags, int mask)
1889 {
1890 int rex = 0;
1891
1892 if (val >= 8)
1893 rex |= REX_B|REX_X|REX_R;
1894 if (flags & BITS64)
1895 rex |= REX_W;
1896 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1897 rex |= REX_H;
1898 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1899 rex |= REX_P;
1900
1901 return rex & mask;
1902 }
1903
1904 static int matches(const struct itemplate *itemp, insn * instruction, int bits)
1905 {
1906 int i, size[MAX_OPERANDS], asize, oprs, ret;
1907
1908 ret = 100;
1909
1910 /*
1911 * Check the opcode
1912 */
1913 if (itemp->opcode != instruction->opcode)
1914 return 0;
1915
1916 /*
1917 * Count the operands
1918 */
1919 if (itemp->operands != instruction->operands)
1920 return 0;
1921
1922 /*
1923 * Check that no spurious colons or TOs are present
1924 */
1925 for (i = 0; i < itemp->operands; i++)
1926 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1927 return 0;
1928
1929 /*
1930 * Process size flags
1931 */
1932 if (itemp->flags & IF_ARMASK) {
1933 memset(size, 0, sizeof size);
1934
1935 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
1936
1937 switch (itemp->flags & IF_SMASK) {
1938 case IF_SB:
1939 size[i] = BITS8;
1940 break;
1941 case IF_SW:
1942 size[i] = BITS16;
1943 break;
1944 case IF_SD:
1945 size[i] = BITS32;
1946 break;
1947 case IF_SQ:
1948 size[i] = BITS64;
1949 break;
1950 case IF_SO:
1951 size[i] = BITS128;
1952 break;
1953 case IF_SY:
1954 size[i] = BITS256;
1955 break;
1956 case IF_SZ:
1957 switch (bits) {
1958 case 16:
1959 size[i] = BITS16;
1960 break;
1961 case 32:
1962 size[i] = BITS32;
1963 break;
1964 case 64:
1965 size[i] = BITS64;
1966 break;
1967 }
1968 break;
1969 default:
1970 break;
1971 }
1972 } else {
1973 asize = 0;
1974 switch (itemp->flags & IF_SMASK) {
1975 case IF_SB:
1976 asize = BITS8;
1977 break;
1978 case IF_SW:
1979 asize = BITS16;
1980 break;
1981 case IF_SD:
1982 asize = BITS32;
1983 break;
1984 case IF_SQ:
1985 asize = BITS64;
1986 break;
1987 case IF_SO:
1988 asize = BITS128;
1989 break;
1990 case IF_SY:
1991 asize = BITS256;
1992 break;
1993 case IF_SZ:
1994 switch (bits) {
1995 case 16:
1996 asize = BITS16;
1997 break;
1998 case 32:
1999 asize = BITS32;
2000 break;
2001 case 64:
2002 asize = BITS64;
2003 break;
2004 }
2005 break;
2006 default:
2007 break;
2008 }
2009 for (i = 0; i < MAX_OPERANDS; i++)
2010 size[i] = asize;
2011 }
2012
2013 /*
2014 * Check that the operand flags all match up
2015 */
2016 for (i = 0; i < itemp->operands; i++) {
2017 int32_t type = instruction->oprs[i].type;
2018 if (!(type & SIZE_MASK))
2019 type |= size[i];
2020
2021 if (itemp->opd[i] & SAME_AS) {
2022 int j = itemp->opd[i] & ~SAME_AS;
2023 if (type != instruction->oprs[j].type ||
2024 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
2025 return 0;
2026 } else if (itemp->opd[i] & ~type ||
2027 ((itemp->opd[i] & SIZE_MASK) &&
2028 ((itemp->opd[i] ^ type) & SIZE_MASK))) {
2029 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2030 (type & SIZE_MASK))
2031 return 0;
2032 else
2033 return 1;
2034 }
2035 }
2036
2037 /*
2038 * Check operand sizes
2039 */
2040 if (itemp->flags & (IF_SM | IF_SM2)) {
2041 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2042 asize = 0;
2043 for (i = 0; i < oprs; i++) {
2044 if ((asize = itemp->opd[i] & SIZE_MASK) != 0) {
2045 int j;
2046 for (j = 0; j < oprs; j++)
2047 size[j] = asize;
2048 break;
2049 }
2050 }
2051 } else {
2052 oprs = itemp->operands;
2053 }
2054
2055 for (i = 0; i < itemp->operands; i++) {
2056 if (!(itemp->opd[i] & SIZE_MASK) &&
2057 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2058 return 2;
2059 }
2060
2061 /*
2062 * Check template is okay at the set cpu level
2063 */
2064 if (((itemp->flags & IF_PLEVEL) > cpu))
2065 return 3;
2066
2067 /*
2068 * Check if instruction is available in long mode
2069 */
2070 if ((itemp->flags & IF_NOLONG) && (bits == 64))
2071 return 4;
2072
2073 /*
2074 * Check if special handling needed for Jumps
2075 */
2076 if ((uint8_t)(itemp->code[0]) >= 0370)
2077 return 99;
2078
2079 return ret;
2080 }
2081
2082 static ea *process_ea(operand * input, ea * output, int bits,
2083 int addrbits, int rfield, int32_t rflags)
2084 {
2085 bool forw_ref = !!(input->opflags & OPFLAG_FORWARD);
2086
2087 output->rip = false;
2088
2089 /* REX flags for the rfield operand */
2090 output->rex |= rexflags(rfield, rflags, REX_R|REX_P|REX_W|REX_H);
2091
2092 if (!(REGISTER & ~input->type)) { /* register direct */
2093 int i;
2094 int32_t f;
2095
2096 if (input->basereg < EXPR_REG_START /* Verify as Register */
2097 || input->basereg >= REG_ENUM_LIMIT)
2098 return NULL;
2099 f = regflag(input);
2100 i = nasm_regvals[input->basereg];
2101
2102 if (REG_EA & ~f)
2103 return NULL; /* Invalid EA register */
2104
2105 output->rex |= op_rexflags(input, REX_B|REX_P|REX_W|REX_H);
2106
2107 output->sib_present = false; /* no SIB necessary */
2108 output->bytes = 0; /* no offset necessary either */
2109 output->modrm = 0xC0 | ((rfield & 7) << 3) | (i & 7);
2110 } else { /* it's a memory reference */
2111 if (input->basereg == -1
2112 && (input->indexreg == -1 || input->scale == 0)) {
2113 /* it's a pure offset */
2114 if (bits == 64 && (~input->type & IP_REL)) {
2115 int scale, index, base;
2116 output->sib_present = true;
2117 scale = 0;
2118 index = 4;
2119 base = 5;
2120 output->sib = (scale << 6) | (index << 3) | base;
2121 output->bytes = 4;
2122 output->modrm = 4 | ((rfield & 7) << 3);
2123 output->rip = false;
2124 } else {
2125 output->sib_present = false;
2126 output->bytes = (addrbits != 16 ? 4 : 2);
2127 output->modrm = (addrbits != 16 ? 5 : 6) | ((rfield & 7) << 3);
2128 output->rip = bits == 64;
2129 }
2130 } else { /* it's an indirection */
2131 int i = input->indexreg, b = input->basereg, s = input->scale;
2132 int32_t o = input->offset, seg = input->segment;
2133 int hb = input->hintbase, ht = input->hinttype;
2134 int t;
2135 int it, bt;
2136 int32_t ix, bx; /* register flags */
2137
2138 if (s == 0)
2139 i = -1; /* make this easy, at least */
2140
2141 if (i >= EXPR_REG_START && i < REG_ENUM_LIMIT) {
2142 it = nasm_regvals[i];
2143 ix = nasm_reg_flags[i];
2144 } else {
2145 it = -1;
2146 ix = 0;
2147 }
2148
2149 if (b >= EXPR_REG_START && b < REG_ENUM_LIMIT) {
2150 bt = nasm_regvals[b];
2151 bx = nasm_reg_flags[b];
2152 } else {
2153 bt = -1;
2154 bx = 0;
2155 }
2156
2157 /* check for a 32/64-bit memory reference... */
2158 if ((ix|bx) & (BITS32|BITS64)) {
2159 /* it must be a 32/64-bit memory reference. Firstly we have
2160 * to check that all registers involved are type E/Rxx. */
2161 int32_t sok = BITS32|BITS64;
2162
2163 if (it != -1) {
2164 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2165 sok &= ix;
2166 else
2167 return NULL;
2168 }
2169
2170 if (bt != -1) {
2171 if (REG_GPR & ~bx)
2172 return NULL; /* Invalid register */
2173 if (~sok & bx & SIZE_MASK)
2174 return NULL; /* Invalid size */
2175 sok &= bx;
2176 }
2177
2178 /* While we're here, ensure the user didn't specify
2179 WORD or QWORD. */
2180 if (input->disp_size == 16 || input->disp_size == 64)
2181 return NULL;
2182
2183 if (addrbits == 16 ||
2184 (addrbits == 32 && !(sok & BITS32)) ||
2185 (addrbits == 64 && !(sok & BITS64)))
2186 return NULL;
2187
2188 /* now reorganize base/index */
2189 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2190 ((hb == b && ht == EAH_NOTBASE)
2191 || (hb == i && ht == EAH_MAKEBASE))) {
2192 /* swap if hints say so */
2193 t = bt, bt = it, it = t;
2194 t = bx, bx = ix, ix = t;
2195 }
2196 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2197 bt = -1, bx = 0, s++;
2198 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2199 /* make single reg base, unless hint */
2200 bt = it, bx = ix, it = -1, ix = 0;
2201 }
2202 if (((s == 2 && it != REG_NUM_ESP
2203 && !(input->eaflags & EAF_TIMESTWO)) || s == 3
2204 || s == 5 || s == 9) && bt == -1)
2205 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2206 if (it == -1 && (bt & 7) != REG_NUM_ESP
2207 && (input->eaflags & EAF_TIMESTWO))
2208 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2209 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2210 if (s == 1 && it == REG_NUM_ESP) {
2211 /* swap ESP into base if scale is 1 */
2212 t = it, it = bt, bt = t;
2213 t = ix, ix = bx, bx = t;
2214 }
2215 if (it == REG_NUM_ESP
2216 || (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2217 return NULL; /* wrong, for various reasons */
2218
2219 output->rex |= rexflags(it, ix, REX_X);
2220 output->rex |= rexflags(bt, bx, REX_B);
2221
2222 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2223 /* no SIB needed */
2224 int mod, rm;
2225
2226 if (bt == -1) {
2227 rm = 5;
2228 mod = 0;
2229 } else {
2230 rm = (bt & 7);
2231 if (rm != REG_NUM_EBP && o == 0 &&
2232 seg == NO_SEG && !forw_ref &&
2233 !(input->eaflags &
2234 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2235 mod = 0;
2236 else if (input->eaflags & EAF_BYTEOFFS ||
2237 (o >= -128 && o <= 127 && seg == NO_SEG
2238 && !forw_ref
2239 && !(input->eaflags & EAF_WORDOFFS)))
2240 mod = 1;
2241 else
2242 mod = 2;
2243 }
2244
2245 output->sib_present = false;
2246 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2247 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2248 } else {
2249 /* we need a SIB */
2250 int mod, scale, index, base;
2251
2252 if (it == -1)
2253 index = 4, s = 1;
2254 else
2255 index = (it & 7);
2256
2257 switch (s) {
2258 case 1:
2259 scale = 0;
2260 break;
2261 case 2:
2262 scale = 1;
2263 break;
2264 case 4:
2265 scale = 2;
2266 break;
2267 case 8:
2268 scale = 3;
2269 break;
2270 default: /* then what the smeg is it? */
2271 return NULL; /* panic */
2272 }
2273
2274 if (bt == -1) {
2275 base = 5;
2276 mod = 0;
2277 } else {
2278 base = (bt & 7);
2279 if (base != REG_NUM_EBP && o == 0 &&
2280 seg == NO_SEG && !forw_ref &&
2281 !(input->eaflags &
2282 (EAF_BYTEOFFS | EAF_WORDOFFS)))
2283 mod = 0;
2284 else if (input->eaflags & EAF_BYTEOFFS ||
2285 (o >= -128 && o <= 127 && seg == NO_SEG
2286 && !forw_ref
2287 && !(input->eaflags & EAF_WORDOFFS)))
2288 mod = 1;
2289 else
2290 mod = 2;
2291 }
2292
2293 output->sib_present = true;
2294 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2295 output->modrm = (mod << 6) | ((rfield & 7) << 3) | 4;
2296 output->sib = (scale << 6) | (index << 3) | base;
2297 }
2298 } else { /* it's 16-bit */
2299 int mod, rm;
2300
2301 /* check for 64-bit long mode */
2302 if (addrbits == 64)
2303 return NULL;
2304
2305 /* check all registers are BX, BP, SI or DI */
2306 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI
2307 && b != R_DI) || (i != -1 && i != R_BP && i != R_BX
2308 && i != R_SI && i != R_DI))
2309 return NULL;
2310
2311 /* ensure the user didn't specify DWORD/QWORD */
2312 if (input->disp_size == 32 || input->disp_size == 64)
2313 return NULL;
2314
2315 if (s != 1 && i != -1)
2316 return NULL; /* no can do, in 16-bit EA */
2317 if (b == -1 && i != -1) {
2318 int tmp = b;
2319 b = i;
2320 i = tmp;
2321 } /* swap */
2322 if ((b == R_SI || b == R_DI) && i != -1) {
2323 int tmp = b;
2324 b = i;
2325 i = tmp;
2326 }
2327 /* have BX/BP as base, SI/DI index */
2328 if (b == i)
2329 return NULL; /* shouldn't ever happen, in theory */
2330 if (i != -1 && b != -1 &&
2331 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2332 return NULL; /* invalid combinations */
2333 if (b == -1) /* pure offset: handled above */
2334 return NULL; /* so if it gets to here, panic! */
2335
2336 rm = -1;
2337 if (i != -1)
2338 switch (i * 256 + b) {
2339 case R_SI * 256 + R_BX:
2340 rm = 0;
2341 break;
2342 case R_DI * 256 + R_BX:
2343 rm = 1;
2344 break;
2345 case R_SI * 256 + R_BP:
2346 rm = 2;
2347 break;
2348 case R_DI * 256 + R_BP:
2349 rm = 3;
2350 break;
2351 } else
2352 switch (b) {
2353 case R_SI:
2354 rm = 4;
2355 break;
2356 case R_DI:
2357 rm = 5;
2358 break;
2359 case R_BP:
2360 rm = 6;
2361 break;
2362 case R_BX:
2363 rm = 7;
2364 break;
2365 }
2366 if (rm == -1) /* can't happen, in theory */
2367 return NULL; /* so panic if it does */
2368
2369 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2370 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2371 mod = 0;
2372 else if (input->eaflags & EAF_BYTEOFFS ||
2373 (o >= -128 && o <= 127 && seg == NO_SEG
2374 && !forw_ref
2375 && !(input->eaflags & EAF_WORDOFFS)))
2376 mod = 1;
2377 else
2378 mod = 2;
2379
2380 output->sib_present = false; /* no SIB - it's 16-bit */
2381 output->bytes = mod; /* bytes of offset needed */
2382 output->modrm = (mod << 6) | ((rfield & 7) << 3) | rm;
2383 }
2384 }
2385 }
2386
2387 output->size = 1 + output->sib_present + output->bytes;
2388 return output;
2389 }
2390
2391 static void add_asp(insn *ins, int addrbits)
2392 {
2393 int j, valid;
2394 int defdisp;
2395
2396 valid = (addrbits == 64) ? 64|32 : 32|16;
2397
2398 switch (ins->prefixes[PPS_ASIZE]) {
2399 case P_A16:
2400 valid &= 16;
2401 break;
2402 case P_A32:
2403 valid &= 32;
2404 break;
2405 case P_A64:
2406 valid &= 64;
2407 break;
2408 case P_ASP:
2409 valid &= (addrbits == 32) ? 16 : 32;
2410 break;
2411 default:
2412 break;
2413 }
2414
2415 for (j = 0; j < ins->operands; j++) {
2416 if (!(MEMORY & ~ins->oprs[j].type)) {
2417 int32_t i, b;
2418
2419 /* Verify as Register */
2420 if (ins->oprs[j].indexreg < EXPR_REG_START
2421 || ins->oprs[j].indexreg >= REG_ENUM_LIMIT)
2422 i = 0;
2423 else
2424 i = nasm_reg_flags[ins->oprs[j].indexreg];
2425
2426 /* Verify as Register */
2427 if (ins->oprs[j].basereg < EXPR_REG_START
2428 || ins->oprs[j].basereg >= REG_ENUM_LIMIT)
2429 b = 0;
2430 else
2431 b = nasm_reg_flags[ins->oprs[j].basereg];
2432
2433 if (ins->oprs[j].scale == 0)
2434 i = 0;
2435
2436 if (!i && !b) {
2437 int ds = ins->oprs[j].disp_size;
2438 if ((addrbits != 64 && ds > 8) ||
2439 (addrbits == 64 && ds == 16))
2440 valid &= ds;
2441 } else {
2442 if (!(REG16 & ~b))
2443 valid &= 16;
2444 if (!(REG32 & ~b))
2445 valid &= 32;
2446 if (!(REG64 & ~b))
2447 valid &= 64;
2448
2449 if (!(REG16 & ~i))
2450 valid &= 16;
2451 if (!(REG32 & ~i))
2452 valid &= 32;
2453 if (!(REG64 & ~i))
2454 valid &= 64;
2455 }
2456 }
2457 }
2458
2459 if (valid & addrbits) {
2460 ins->addr_size = addrbits;
2461 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2462 /* Add an address size prefix */
2463 enum prefixes pref = (addrbits == 32) ? P_A16 : P_A32;
2464 ins->prefixes[PPS_ASIZE] = pref;
2465 ins->addr_size = (addrbits == 32) ? 16 : 32;
2466 } else {
2467 /* Impossible... */
2468 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2469 ins->addr_size = addrbits; /* Error recovery */
2470 }
2471
2472 defdisp = ins->addr_size == 16 ? 16 : 32;
2473
2474 for (j = 0; j < ins->operands; j++) {
2475 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2476 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp)
2477 != ins->addr_size) {
2478 /* mem_offs sizes must match the address size; if not,
2479 strip the MEM_OFFS bit and match only EA instructions */
2480 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2481 }
2482 }
2483 }
The Netwide Assembler