insns.h

   1 /* insns.h   header file for insns.c
   2  * $Id$
   3  *
   4  * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
   5  * Julian Hall. All rights reserved. The software is
   6  * redistributable under the licence given in the file "Licence"
   7  * distributed in the NASM archive.
   8  */
   9
  10 #ifndef NASM_INSNS_H
  11 #define NASM_INSNS_H
  12
  13 #include "insnsi.h"                    /* instruction opcode enum */
  14
  15 /* max length of any instruction, register name etc. */
  16 #if MAX_INSLEN > 9              /* MAX_INSLEN defined in insnsi.h */
  17 #define MAX_KEYWORD MAX_INSLEN
  18 #else
  19 #define MAX_KEYWORD 9
  20 #endif
  21
  22 struct itemplate {
  23     int opcode;                        /* the token, passed from "parser.c" */
  24     int operands;                      /* number of operands */
  25     long opd[3];                       /* bit flags for operand types */
  26     const char *code;              /* the code it assembles to */
  27     unsigned long flags;               /* some flags */
  28 };
  29
  30 /*
  31  * this define is used to signify the end of an itemplate
  32  */
  33 #define ITEMPLATE_END {-1,-1,{-1,-1,-1},NULL,0}
  34
  35 /*
  36  * Instruction template flags. These specify which processor
  37  * targets the instruction is eligible for, whether it is
  38  * privileged or undocumented, and also specify extra error
  39  * checking on the matching of the instruction.
  40  *
  41  * IF_SM stands for Size Match: any operand whose size is not
  42  * explicitly specified by the template is `really' intended to be
  43  * the same size as the first size-specified operand.
  44  * Non-specification is tolerated in the input instruction, but
  45  * _wrong_ specification is not.
  46  *
  47  * IF_SM2 invokes Size Match on only the first _two_ operands, for
  48  * three-operand instructions such as SHLD: it implies that the
  49  * first two operands must match in size, but that the third is
  50  * required to be _unspecified_.
  51  *
  52  * IF_SB invokes Size Byte: operands with unspecified size in the
  53  * template are really bytes, and so no non-byte specification in
  54  * the input instruction will be tolerated. IF_SW similarly invokes
  55  * Size Word, and IF_SD invokes Size Doubleword.
  56  *
  57  * (The default state if neither IF_SM nor IF_SM2 is specified is
  58  * that any operand with unspecified size in the template is
  59  * required to have unspecified size in the instruction too...)
  60  */
  61
  62 #define IF_SM     0x00000001UL         /* size match */
  63 #define IF_SM2    0x00000002UL         /* size match first two operands */
  64 #define IF_SB     0x00000004UL         /* unsized operands can't be non-byte */
  65 #define IF_SW     0x00000008UL         /* unsized operands can't be non-word */
  66 #define IF_SD     0x00000010UL         /* unsized operands can't be nondword */
  67 #define IF_AR0    0x00000020UL         /* SB, SW, SD applies to argument 0 */
  68 #define IF_AR1    0x00000040UL         /* SB, SW, SD applies to argument 1 */
  69 #define IF_AR2    0x00000060UL         /* SB, SW, SD applies to argument 2 */
  70 #define IF_ARMASK 0x00000060UL         /* mask for unsized argument spec */
  71 #define IF_PRIV   0x00000100UL         /* it's a privileged instruction */
  72 #define IF_SMM    0x00000200UL         /* it's only valid in SMM */
  73 #define IF_PROT   0x00000400UL         /* it's protected mode only */
  74 #define IF_UNDOC  0x00001000UL         /* it's an undocumented instruction */
  75 #define IF_FPU    0x00002000UL         /* it's an FPU instruction */
  76 #define IF_MMX    0x00004000UL         /* it's an MMX instruction */
  77 #define IF_3DNOW  0x00008000UL         /* it's a 3DNow! instruction */
  78 #define IF_SSE    0x00010000UL         /* it's a SSE (KNI, MMX2) instruction */
  79 #define IF_SSE2   0x00020000UL         /* it's a SSE2 instruction */
  80 #define IF_PMASK  0xFF000000UL         /* the mask for processor types */
  81 #define IF_PLEVEL 0x0F000000UL         /* the mask for processor instr. level */
  82                                         /* also the highest possible processor */
  83 #define IF_PFMASK 0xF001FF00UL         /* the mask for disassembly "prefer" */
  84 #define IF_8086   0x00000000UL         /* 8086 instruction */
  85 #define IF_186    0x01000000UL         /* 186+ instruction */
  86 #define IF_286    0x02000000UL         /* 286+ instruction */
  87 #define IF_386    0x03000000UL         /* 386+ instruction */
  88 #define IF_486    0x04000000UL         /* 486+ instruction */
  89 #define IF_PENT   0x05000000UL         /* Pentium instruction */
  90 #define IF_P6     0x06000000UL         /* P6 instruction */
  91 #define IF_KATMAI 0x07000000UL         /* Katmai instructions */
  92 #define IF_WILLAMETTE 0x08000000UL         /* Willamette instructions */
  93 #define IF_IA64   0x0F000000UL         /* IA64 instructions */
  94 #define IF_CYRIX  0x10000000UL         /* Cyrix-specific instruction */
  95 #define IF_AMD    0x20000000UL         /* AMD-specific instruction */
  96
  97 #endif