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insns.pl: better error messages, handle no-operand instructions better
[nasm.git] / disasm.c
blob77b87b03743ca596d31d0ad2d4714a6eda66cf4b
1 /* disasm.c where all the _work_ gets done in the Netwide Disassembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
7 *
8 * initial version 27/iii/95 by Simon Tatham
9 */
10
11 #include "compiler.h"
12
13 #include <stdio.h>
14 #include <string.h>
15 #include <limits.h>
16 #include <inttypes.h>
17
18 #include "nasm.h"
19 #include "disasm.h"
20 #include "sync.h"
21 #include "insns.h"
22 #include "tables.h"
23 #include "regdis.h"
24
25 /*
26 * Flags that go into the `segment' field of `insn' structures
27 * during disassembly.
28 */
29 #define SEG_RELATIVE 1
30 #define SEG_32BIT 2
31 #define SEG_RMREG 4
32 #define SEG_DISP8 8
33 #define SEG_DISP16 16
34 #define SEG_DISP32 32
35 #define SEG_NODISP 64
36 #define SEG_SIGNED 128
37 #define SEG_64BIT 256
38
39 /*
40 * Prefix information
41 */
42 struct prefix_info {
43 uint8_t osize; /* Operand size */
44 uint8_t asize; /* Address size */
45 uint8_t osp; /* Operand size prefix present */
46 uint8_t asp; /* Address size prefix present */
47 uint8_t rep; /* Rep prefix present */
48 uint8_t seg; /* Segment override prefix present */
49 uint8_t lock; /* Lock prefix present */
50 uint8_t vex[3]; /* VEX prefix present */
51 uint8_t vex_m; /* VEX.M field */
52 uint8_t vex_v;
53 uint8_t vex_lp; /* VEX.LP fields */
54 uint32_t rex; /* REX prefix present */
55 };
56
57 #define getu8(x) (*(uint8_t *)(x))
58 #if X86_MEMORY
59 /* Littleendian CPU which can handle unaligned references */
60 #define getu16(x) (*(uint16_t *)(x))
61 #define getu32(x) (*(uint32_t *)(x))
62 #define getu64(x) (*(uint64_t *)(x))
63 #else
64 static uint16_t getu16(uint8_t *data)
65 {
66 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
67 }
68 static uint32_t getu32(uint8_t *data)
69 {
70 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
71 }
72 static uint64_t getu64(uint8_t *data)
73 {
74 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
75 }
76 #endif
77
78 #define gets8(x) ((int8_t)getu8(x))
79 #define gets16(x) ((int16_t)getu16(x))
80 #define gets32(x) ((int32_t)getu32(x))
81 #define gets64(x) ((int64_t)getu64(x))
82
83 /* Important: regval must already have been adjusted for rex extensions */
84 static enum reg_enum whichreg(int32_t regflags, int regval, int rex)
85 {
86 if (!(regflags & (REGISTER|REGMEM)))
87 return 0; /* Registers not permissible?! */
88
89 regflags |= REGISTER;
90
91 if (!(REG_AL & ~regflags))
92 return R_AL;
93 if (!(REG_AX & ~regflags))
94 return R_AX;
95 if (!(REG_EAX & ~regflags))
96 return R_EAX;
97 if (!(REG_RAX & ~regflags))
98 return R_RAX;
99 if (!(REG_DL & ~regflags))
100 return R_DL;
101 if (!(REG_DX & ~regflags))
102 return R_DX;
103 if (!(REG_EDX & ~regflags))
104 return R_EDX;
105 if (!(REG_RDX & ~regflags))
106 return R_RDX;
107 if (!(REG_CL & ~regflags))
108 return R_CL;
109 if (!(REG_CX & ~regflags))
110 return R_CX;
111 if (!(REG_ECX & ~regflags))
112 return R_ECX;
113 if (!(REG_RCX & ~regflags))
114 return R_RCX;
115 if (!(FPU0 & ~regflags))
116 return R_ST0;
117 if (!(XMM0 & ~regflags))
118 return R_XMM0;
119 if (!(YMM0 & ~regflags))
120 return R_YMM0;
121 if (!(REG_CS & ~regflags))
122 return (regval == 1) ? R_CS : 0;
123 if (!(REG_DESS & ~regflags))
124 return (regval == 0 || regval == 2
125 || regval == 3 ? nasm_rd_sreg[regval] : 0);
126 if (!(REG_FSGS & ~regflags))
127 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
128 if (!(REG_SEG67 & ~regflags))
129 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
130
131 /* All the entries below look up regval in an 16-entry array */
132 if (regval < 0 || regval > 15)
133 return 0;
134
135 if (!(REG8 & ~regflags)) {
136 if (rex & REX_P)
137 return nasm_rd_reg8_rex[regval];
138 else
139 return nasm_rd_reg8[regval];
140 }
141 if (!(REG16 & ~regflags))
142 return nasm_rd_reg16[regval];
143 if (!(REG32 & ~regflags))
144 return nasm_rd_reg32[regval];
145 if (!(REG64 & ~regflags))
146 return nasm_rd_reg64[regval];
147 if (!(REG_SREG & ~regflags))
148 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
149 if (!(REG_CREG & ~regflags))
150 return nasm_rd_creg[regval];
151 if (!(REG_DREG & ~regflags))
152 return nasm_rd_dreg[regval];
153 if (!(REG_TREG & ~regflags)) {
154 if (rex & REX_P)
155 return 0; /* TR registers are ill-defined with rex */
156 return nasm_rd_treg[regval];
157 }
158 if (!(FPUREG & ~regflags))
159 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
160 if (!(MMXREG & ~regflags))
161 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
162 if (!(XMMREG & ~regflags))
163 return nasm_rd_xmmreg[regval];
164 if (!(YMMREG & ~regflags))
165 return nasm_rd_ymmreg[regval];
166
167 return 0;
168 }
169
170 /*
171 * Process a DREX suffix
172 */
173 static uint8_t *do_drex(uint8_t *data, insn *ins)
174 {
175 uint8_t drex = *data++;
176 operand *dst = &ins->oprs[ins->drexdst];
177
178 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
179 return NULL; /* OC0 mismatch */
180 ins->rex = (ins->rex & ~7) | (drex & 7);
181
182 dst->segment = SEG_RMREG;
183 dst->basereg = drex >> 4;
184 return data;
185 }
186
187
188 /*
189 * Process an effective address (ModRM) specification.
190 */
191 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
192 int segsize, operand * op, insn *ins)
193 {
194 int mod, rm, scale, index, base;
195 int rex;
196 uint8_t sib = 0;
197
198 mod = (modrm >> 6) & 03;
199 rm = modrm & 07;
200
201 if (mod != 3 && rm == 4 && asize != 16)
202 sib = *data++;
203
204 if (ins->rex & REX_D) {
205 data = do_drex(data, ins);
206 if (!data)
207 return NULL;
208 }
209 rex = ins->rex;
210
211 if (mod == 3) { /* pure register version */
212 op->basereg = rm+(rex & REX_B ? 8 : 0);
213 op->segment |= SEG_RMREG;
214 return data;
215 }
216
217 op->disp_size = 0;
218 op->eaflags = 0;
219
220 if (asize == 16) {
221 /*
222 * <mod> specifies the displacement size (none, byte or
223 * word), and <rm> specifies the register combination.
224 * Exception: mod=0,rm=6 does not specify [BP] as one might
225 * expect, but instead specifies [disp16].
226 */
227 op->indexreg = op->basereg = -1;
228 op->scale = 1; /* always, in 16 bits */
229 switch (rm) {
230 case 0:
231 op->basereg = R_BX;
232 op->indexreg = R_SI;
233 break;
234 case 1:
235 op->basereg = R_BX;
236 op->indexreg = R_DI;
237 break;
238 case 2:
239 op->basereg = R_BP;
240 op->indexreg = R_SI;
241 break;
242 case 3:
243 op->basereg = R_BP;
244 op->indexreg = R_DI;
245 break;
246 case 4:
247 op->basereg = R_SI;
248 break;
249 case 5:
250 op->basereg = R_DI;
251 break;
252 case 6:
253 op->basereg = R_BP;
254 break;
255 case 7:
256 op->basereg = R_BX;
257 break;
258 }
259 if (rm == 6 && mod == 0) { /* special case */
260 op->basereg = -1;
261 if (segsize != 16)
262 op->disp_size = 16;
263 mod = 2; /* fake disp16 */
264 }
265 switch (mod) {
266 case 0:
267 op->segment |= SEG_NODISP;
268 break;
269 case 1:
270 op->segment |= SEG_DISP8;
271 op->offset = (int8_t)*data++;
272 break;
273 case 2:
274 op->segment |= SEG_DISP16;
275 op->offset = *data++;
276 op->offset |= ((unsigned)*data++) << 8;
277 break;
278 }
279 return data;
280 } else {
281 /*
282 * Once again, <mod> specifies displacement size (this time
283 * none, byte or *dword*), while <rm> specifies the base
284 * register. Again, [EBP] is missing, replaced by a pure
285 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
286 * and RIP-relative addressing in 64-bit mode.
287 *
288 * However, rm=4
289 * indicates not a single base register, but instead the
290 * presence of a SIB byte...
291 */
292 int a64 = asize == 64;
293
294 op->indexreg = -1;
295
296 if (a64)
297 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
298 else
299 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
300
301 if (rm == 5 && mod == 0) {
302 if (segsize == 64) {
303 op->eaflags |= EAF_REL;
304 op->segment |= SEG_RELATIVE;
305 mod = 2; /* fake disp32 */
306 }
307
308 if (asize != 64)
309 op->disp_size = asize;
310
311 op->basereg = -1;
312 mod = 2; /* fake disp32 */
313 }
314
315 if (rm == 4) { /* process SIB */
316 scale = (sib >> 6) & 03;
317 index = (sib >> 3) & 07;
318 base = sib & 07;
319
320 op->scale = 1 << scale;
321
322 if (index == 4)
323 op->indexreg = -1; /* ESP/RSP/R12 cannot be an index */
324 else if (a64)
325 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
326 else
327 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
328
329 if (base == 5 && mod == 0) {
330 op->basereg = -1;
331 mod = 2; /* Fake disp32 */
332 } else if (a64)
333 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
334 else
335 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
336
337 if (segsize == 16)
338 op->disp_size = 32;
339 }
340
341 switch (mod) {
342 case 0:
343 op->segment |= SEG_NODISP;
344 break;
345 case 1:
346 op->segment |= SEG_DISP8;
347 op->offset = gets8(data);
348 data++;
349 break;
350 case 2:
351 op->segment |= SEG_DISP32;
352 op->offset = gets32(data);
353 data += 4;
354 break;
355 }
356 return data;
357 }
358 }
359
360 /*
361 * Determine whether the instruction template in t corresponds to the data
362 * stream in data. Return the number of bytes matched if so.
363 */
364 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
365
366 static int matches(const struct itemplate *t, uint8_t *data,
367 const struct prefix_info *prefix, int segsize, insn *ins)
368 {
369 uint8_t *r = (uint8_t *)(t->code);
370 uint8_t *origdata = data;
371 bool a_used = false, o_used = false;
372 enum prefixes drep = 0;
373 uint8_t lock = prefix->lock;
374 int osize = prefix->osize;
375 int asize = prefix->asize;
376 int i, c;
377 struct operand *opx;
378 int s_field_for = -1; /* No 144/154 series code encountered */
379 bool vex_ok = false;
380
381 for (i = 0; i < MAX_OPERANDS; i++) {
382 ins->oprs[i].segment = ins->oprs[i].disp_size =
383 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
384 }
385 ins->condition = -1;
386 ins->rex = prefix->rex;
387 memset(ins->prefixes, 0, sizeof ins->prefixes);
388
389 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
390 return false;
391
392 if (prefix->rep == 0xF2)
393 drep = P_REPNE;
394 else if (prefix->rep == 0xF3)
395 drep = P_REP;
396
397 while ((c = *r++) != 0) {
398 opx = &ins->oprs[c & 3];
399
400 switch (c) {
401 case 01:
402 case 02:
403 case 03:
404 while (c--)
405 if (*r++ != *data++)
406 return false;
407 break;
408
409 case 04:
410 switch (*data++) {
411 case 0x07:
412 ins->oprs[0].basereg = 0;
413 break;
414 case 0x17:
415 ins->oprs[0].basereg = 2;
416 break;
417 case 0x1F:
418 ins->oprs[0].basereg = 3;
419 break;
420 default:
421 return false;
422 }
423 break;
424
425 case 05:
426 switch (*data++) {
427 case 0xA1:
428 ins->oprs[0].basereg = 4;
429 break;
430 case 0xA9:
431 ins->oprs[0].basereg = 5;
432 break;
433 default:
434 return false;
435 }
436 break;
437
438 case 06:
439 switch (*data++) {
440 case 0x06:
441 ins->oprs[0].basereg = 0;
442 break;
443 case 0x0E:
444 ins->oprs[0].basereg = 1;
445 break;
446 case 0x16:
447 ins->oprs[0].basereg = 2;
448 break;
449 case 0x1E:
450 ins->oprs[0].basereg = 3;
451 break;
452 default:
453 return false;
454 }
455 break;
456
457 case 07:
458 switch (*data++) {
459 case 0xA0:
460 ins->oprs[0].basereg = 4;
461 break;
462 case 0xA8:
463 ins->oprs[0].basereg = 5;
464 break;
465 default:
466 return false;
467 }
468 break;
469
470 case4(010):
471 {
472 int t = *r++, d = *data++;
473 if (d < t || d > t + 7)
474 return false;
475 else {
476 opx->basereg = (d-t)+
477 (ins->rex & REX_B ? 8 : 0);
478 opx->segment |= SEG_RMREG;
479 }
480 break;
481 }
482
483 case4(014):
484 opx->offset = (int8_t)*data++;
485 opx->segment |= SEG_SIGNED;
486 break;
487
488 case4(020):
489 opx->offset = *data++;
490 break;
491
492 case4(024):
493 opx->offset = *data++;
494 break;
495
496 case4(030):
497 opx->offset = getu16(data);
498 data += 2;
499 break;
500
501 case4(034):
502 if (osize == 32) {
503 opx->offset = getu32(data);
504 data += 4;
505 } else {
506 opx->offset = getu16(data);
507 data += 2;
508 }
509 if (segsize != asize)
510 opx->disp_size = asize;
511 break;
512
513 case4(040):
514 opx->offset = getu32(data);
515 data += 4;
516 break;
517
518 case4(044):
519 switch (asize) {
520 case 16:
521 opx->offset = getu16(data);
522 data += 2;
523 if (segsize != 16)
524 opx->disp_size = 16;
525 break;
526 case 32:
527 opx->offset = getu32(data);
528 data += 4;
529 if (segsize == 16)
530 opx->disp_size = 32;
531 break;
532 case 64:
533 opx->offset = getu64(data);
534 opx->disp_size = 64;
535 data += 8;
536 break;
537 }
538 break;
539
540 case4(050):
541 opx->offset = gets8(data++);
542 opx->segment |= SEG_RELATIVE;
543 break;
544
545 case4(054):
546 opx->offset = getu64(data);
547 data += 8;
548 break;
549
550 case4(060):
551 opx->offset = gets16(data);
552 data += 2;
553 opx->segment |= SEG_RELATIVE;
554 opx->segment &= ~SEG_32BIT;
555 break;
556
557 case4(064):
558 opx->segment |= SEG_RELATIVE;
559 if (osize == 16) {
560 opx->offset = gets16(data);
561 data += 2;
562 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
563 } else if (osize == 32) {
564 opx->offset = gets32(data);
565 data += 4;
566 opx->segment &= ~SEG_64BIT;
567 opx->segment |= SEG_32BIT;
568 }
569 if (segsize != osize) {
570 opx->type =
571 (opx->type & ~SIZE_MASK)
572 | ((osize == 16) ? BITS16 : BITS32);
573 }
574 break;
575
576 case4(070):
577 opx->offset = gets32(data);
578 data += 4;
579 opx->segment |= SEG_32BIT | SEG_RELATIVE;
580 break;
581
582 case4(0100):
583 case4(0110):
584 case4(0120):
585 case4(0130):
586 {
587 int modrm = *data++;
588 opx->segment |= SEG_RMREG;
589 data = do_ea(data, modrm, asize, segsize,
590 &ins->oprs[(c >> 3) & 3], ins);
591 if (!data)
592 return false;
593 opx->basereg = ((modrm >> 3)&7)+
594 (ins->rex & REX_R ? 8 : 0);
595 break;
596 }
597
598 case4(0140):
599 if (s_field_for == (c & 3)) {
600 opx->offset = gets8(data);
601 data++;
602 } else {
603 opx->offset = getu16(data);
604 data += 2;
605 }
606 break;
607
608 case4(0144):
609 case4(0154):
610 s_field_for = (*data & 0x02) ? c & 3 : -1;
611 if ((*data++ & ~0x02) != *r++)
612 return false;
613 break;
614
615 case4(0150):
616 if (s_field_for == (c & 3)) {
617 opx->offset = gets8(data);
618 data++;
619 } else {
620 opx->offset = getu32(data);
621 data += 4;
622 }
623 break;
624
625 case4(0160):
626 ins->rex |= REX_D;
627 ins->drexdst = c & 3;
628 break;
629
630 case4(0164):
631 ins->rex |= REX_D|REX_OC;
632 ins->drexdst = c & 3;
633 break;
634
635 case 0171:
636 data = do_drex(data, ins);
637 if (!data)
638 return false;
639 break;
640
641 case 0172:
642 {
643 uint8_t ximm = *data++;
644 c = *r++;
645 ins->oprs[c >> 3].basereg = ximm >> 4;
646 ins->oprs[c >> 3].segment |= SEG_RMREG;
647 ins->oprs[c & 7].offset = ximm & 15;
648 }
649 break;
650
651 case 0173:
652 {
653 uint8_t ximm = *data++;
654 c = *r++;
655
656 if ((c ^ ximm) & 15)
657 return false;
658
659 ins->oprs[c >> 4].basereg = ximm >> 4;
660 ins->oprs[c >> 4].segment |= SEG_RMREG;
661 }
662 break;
663
664 case 0174:
665 {
666 uint8_t ximm = *data++;
667 c = *r++;
668
669 ins->oprs[c].basereg = ximm >> 4;
670 ins->oprs[c].segment |= SEG_RMREG;
671 }
672 break;
673
674 case4(0200):
675 case4(0204):
676 case4(0210):
677 case4(0214):
678 case4(0220):
679 case4(0224):
680 case4(0230):
681 case4(0234):
682 {
683 int modrm = *data++;
684 if (((modrm >> 3) & 07) != (c & 07))
685 return false; /* spare field doesn't match up */
686 data = do_ea(data, modrm, asize, segsize,
687 &ins->oprs[(c >> 3) & 07], ins);
688 if (!data)
689 return false;
690 break;
691 }
692
693 case4(0260):
694 {
695 int vexm = *r++;
696 int vexwlp = *r++;
697 ins->rex |= REX_V;
698 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
699 return false;
700
701 if ((vexm & 0x1f) != prefix->vex_m)
702 return false;
703
704 switch (vexwlp & 030) {
705 case 000:
706 if (prefix->rex & REX_W)
707 return false;
708 break;
709 case 010:
710 if (!(prefix->rex & REX_W))
711 return false;
712 ins->rex &= ~REX_W;
713 break;
714 case 020: /* VEX.W is a don't care */
715 ins->rex &= ~REX_W;
716 break;
717 case 030:
718 break;
719 }
720
721 if ((vexwlp & 007) != prefix->vex_lp)
722 return false;
723
724 opx->segment |= SEG_RMREG;
725 opx->basereg = prefix->vex_v;
726 vex_ok = true;
727 break;
728 }
729
730 case 0270:
731 {
732 int vexm = *r++;
733 int vexwlp = *r++;
734 ins->rex |= REX_V;
735 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
736 return false;
737
738 if ((vexm & 0x1f) != prefix->vex_m)
739 return false;
740
741 switch (vexwlp & 030) {
742 case 000:
743 if (ins->rex & REX_W)
744 return false;
745 break;
746 case 010:
747 if (!(ins->rex & REX_W))
748 return false;
749 break;
750 default:
751 break; /* Need to do anything special here? */
752 }
753
754 if ((vexwlp & 007) != prefix->vex_lp)
755 return false;
756
757 if (prefix->vex_v != 0)
758 return false;
759
760 vex_ok = true;
761 break;
762 }
763
764 case 0310:
765 if (asize != 16)
766 return false;
767 else
768 a_used = true;
769 break;
770
771 case 0311:
772 if (asize == 16)
773 return false;
774 else
775 a_used = true;
776 break;
777
778 case 0312:
779 if (asize != segsize)
780 return false;
781 else
782 a_used = true;
783 break;
784
785 case 0313:
786 if (asize != 64)
787 return false;
788 else
789 a_used = true;
790 break;
791
792 case 0314:
793 if (prefix->rex & REX_B)
794 return false;
795 break;
796
797 case 0315:
798 if (prefix->rex & REX_X)
799 return false;
800 break;
801
802 case 0316:
803 if (prefix->rex & REX_R)
804 return false;
805 break;
806
807 case 0317:
808 if (prefix->rex & REX_W)
809 return false;
810 break;
811
812 case 0320:
813 if (osize != 16)
814 return false;
815 else
816 o_used = true;
817 break;
818
819 case 0321:
820 if (osize != 32)
821 return false;
822 else
823 o_used = true;
824 break;
825
826 case 0322:
827 if (osize != (segsize == 16) ? 16 : 32)
828 return false;
829 else
830 o_used = true;
831 break;
832
833 case 0323:
834 ins->rex |= REX_W; /* 64-bit only instruction */
835 osize = 64;
836 o_used = true;
837 break;
838
839 case 0324:
840 if (!(ins->rex & (REX_P|REX_W)) || osize != 64)
841 return false;
842 o_used = true;
843 break;
844
845 case 0330:
846 {
847 int t = *r++, d = *data++;
848 if (d < t || d > t + 15)
849 return false;
850 else
851 ins->condition = d - t;
852 break;
853 }
854
855 case 0331:
856 if (prefix->rep)
857 return false;
858 break;
859
860 case 0332:
861 if (prefix->rep != 0xF2)
862 return false;
863 drep = 0;
864 break;
865
866 case 0333:
867 if (prefix->rep != 0xF3)
868 return false;
869 drep = 0;
870 break;
871
872 case 0334:
873 if (lock) {
874 ins->rex |= REX_R;
875 lock = 0;
876 }
877 break;
878
879 case 0335:
880 if (drep == P_REP)
881 drep = P_REPE;
882 break;
883
884 case 0340:
885 return false;
886
887 case 0360:
888 if (prefix->osp || prefix->rep)
889 return false;
890 break;
891
892 case 0361:
893 if (!prefix->osp || prefix->rep)
894 return false;
895 o_used = true;
896 break;
897
898 case 0362:
899 if (prefix->osp || prefix->rep != 0xf2)
900 return false;
901 drep = 0;
902 break;
903
904 case 0363:
905 if (prefix->osp || prefix->rep != 0xf3)
906 return false;
907 drep = 0;
908 break;
909
910 case 0364:
911 if (prefix->osp)
912 return false;
913 break;
914
915 case 0365:
916 if (prefix->asp)
917 return false;
918 break;
919
920 case 0366:
921 if (!prefix->osp)
922 return false;
923 o_used = true;
924 break;
925
926 case 0367:
927 if (!prefix->asp)
928 return false;
929 a_used = true;
930 break;
931
932 default:
933 return false; /* Unknown code */
934 }
935 }
936
937 if (!vex_ok && (ins->rex & REX_V))
938 return false;
939
940 /* REX cannot be combined with DREX or VEX */
941 if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
942 return false;
943
944 /*
945 * Check for unused rep or a/o prefixes.
946 */
947 for (i = 0; i < t->operands; i++) {
948 if (ins->oprs[i].segment != SEG_RMREG)
949 a_used = true;
950 }
951
952 if (lock) {
953 if (ins->prefixes[PPS_LREP])
954 return false;
955 ins->prefixes[PPS_LREP] = P_LOCK;
956 }
957 if (drep) {
958 if (ins->prefixes[PPS_LREP])
959 return false;
960 ins->prefixes[PPS_LREP] = drep;
961 }
962 if (!o_used) {
963 if (osize != ((segsize == 16) ? 16 : 32)) {
964 enum prefixes pfx = 0;
965
966 switch (osize) {
967 case 16:
968 pfx = P_O16;
969 break;
970 case 32:
971 pfx = P_O32;
972 break;
973 case 64:
974 pfx = P_O64;
975 break;
976 }
977
978 if (ins->prefixes[PPS_OSIZE])
979 return false;
980 ins->prefixes[PPS_OSIZE] = pfx;
981 }
982 }
983 if (!a_used && asize != segsize) {
984 if (ins->prefixes[PPS_ASIZE])
985 return false;
986 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
987 }
988
989 /* Fix: check for redundant REX prefixes */
990
991 return data - origdata;
992 }
993
994 /* Condition names for disassembly, sorted by x86 code */
995 static const char * const condition_name[16] = {
996 "o", "no", "c", "nc", "z", "nz", "na", "a",
997 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
998 };
999
1000 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
1001 int32_t offset, int autosync, uint32_t prefer)
1002 {
1003 const struct itemplate * const *p, * const *best_p;
1004 const struct disasm_index *ix;
1005 uint8_t *dp;
1006 int length, best_length = 0;
1007 char *segover;
1008 int i, slen, colon, n;
1009 uint8_t *origdata;
1010 int works;
1011 insn tmp_ins, ins;
1012 uint32_t goodness, best;
1013 int best_pref;
1014 struct prefix_info prefix;
1015 bool end_prefix;
1016
1017 memset(&ins, 0, sizeof ins);
1018
1019 /*
1020 * Scan for prefixes.
1021 */
1022 memset(&prefix, 0, sizeof prefix);
1023 prefix.asize = segsize;
1024 prefix.osize = (segsize == 64) ? 32 : segsize;
1025 segover = NULL;
1026 origdata = data;
1027
1028 ix = itable;
1029
1030 end_prefix = false;
1031 while (!end_prefix) {
1032 switch (*data) {
1033 case 0xF2:
1034 case 0xF3:
1035 prefix.rep = *data++;
1036 break;
1037
1038 case 0xF0:
1039 prefix.lock = *data++;
1040 break;
1041
1042 case 0x2E:
1043 segover = "cs", prefix.seg = *data++;
1044 break;
1045 case 0x36:
1046 segover = "ss", prefix.seg = *data++;
1047 break;
1048 case 0x3E:
1049 segover = "ds", prefix.seg = *data++;
1050 break;
1051 case 0x26:
1052 segover = "es", prefix.seg = *data++;
1053 break;
1054 case 0x64:
1055 segover = "fs", prefix.seg = *data++;
1056 break;
1057 case 0x65:
1058 segover = "gs", prefix.seg = *data++;
1059 break;
1060
1061 case 0x66:
1062 prefix.osize = (segsize == 16) ? 32 : 16;
1063 prefix.osp = *data++;
1064 break;
1065 case 0x67:
1066 prefix.asize = (segsize == 32) ? 16 : 32;
1067 prefix.asp = *data++;
1068 break;
1069
1070 case 0xC4:
1071 case 0xC5:
1072 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1073 prefix.vex[0] = *data++;
1074 prefix.vex[1] = *data++;
1075 if (prefix.vex[0] == 0xc4)
1076 prefix.vex[2] = *data++;
1077 }
1078 prefix.rex = REX_V;
1079 if (prefix.vex[0] == 0xc4) {
1080 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1081 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1082 prefix.vex_m = prefix.vex[1] & 0x1f;
1083 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1084 prefix.vex_lp = prefix.vex[2] & 7;
1085 } else {
1086 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1087 prefix.vex_m = 1;
1088 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1089 prefix.vex_lp = prefix.vex[1] & 7;
1090 }
1091
1092 ix = itable_VEX[prefix.vex_m][prefix.vex_lp];
1093 end_prefix = true;
1094 break;
1095
1096 case REX_P + 0x0:
1097 case REX_P + 0x1:
1098 case REX_P + 0x2:
1099 case REX_P + 0x3:
1100 case REX_P + 0x4:
1101 case REX_P + 0x5:
1102 case REX_P + 0x6:
1103 case REX_P + 0x7:
1104 case REX_P + 0x8:
1105 case REX_P + 0x9:
1106 case REX_P + 0xA:
1107 case REX_P + 0xB:
1108 case REX_P + 0xC:
1109 case REX_P + 0xD:
1110 case REX_P + 0xE:
1111 case REX_P + 0xF:
1112 if (segsize == 64) {
1113 prefix.rex = *data++;
1114 if (prefix.rex & REX_W)
1115 prefix.osize = 64;
1116 }
1117 end_prefix = true;
1118 break;
1119
1120 default:
1121 end_prefix = true;
1122 break;
1123 }
1124 }
1125
1126 best = -1; /* Worst possible */
1127 best_p = NULL;
1128 best_pref = INT_MAX;
1129
1130 if (!ix)
1131 return 0; /* No instruction table at all... */
1132
1133 dp = data;
1134 ix += *dp++;
1135 while (ix->n == -1) {
1136 ix = (const struct disasm_index *)ix->p + *dp++;
1137 }
1138
1139 p = (const struct itemplate * const *)ix->p;
1140 for (n = ix->n; n; n--, p++) {
1141 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1142 works = true;
1143 /*
1144 * Final check to make sure the types of r/m match up.
1145 * XXX: Need to make sure this is actually correct.
1146 */
1147 for (i = 0; i < (*p)->operands; i++) {
1148 if (!((*p)->opd[i] & SAME_AS) &&
1149 (
1150 /* If it's a mem-only EA but we have a
1151 register, die. */
1152 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1153 !(MEMORY & ~(*p)->opd[i])) ||
1154 /* If it's a reg-only EA but we have a memory
1155 ref, die. */
1156 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1157 !(REG_EA & ~(*p)->opd[i]) &&
1158 !((*p)->opd[i] & REG_SMASK)) ||
1159 /* Register type mismatch (eg FS vs REG_DESS):
1160 die. */
1161 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1162 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1163 !whichreg((*p)->opd[i],
1164 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1165 )) {
1166 works = false;
1167 break;
1168 }
1169 }
1170
1171 /*
1172 * Note: we always prefer instructions which incorporate
1173 * prefixes in the instructions themselves. This is to allow
1174 * e.g. PAUSE to be preferred to REP NOP, and deal with
1175 * MMX/SSE instructions where prefixes are used to select
1176 * between MMX and SSE register sets or outright opcode
1177 * selection.
1178 */
1179 if (works) {
1180 int i, nprefix;
1181 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1182 nprefix = 0;
1183 for (i = 0; i < MAXPREFIX; i++)
1184 if (tmp_ins.prefixes[i])
1185 nprefix++;
1186 if (nprefix < best_pref ||
1187 (nprefix == best_pref && goodness < best)) {
1188 /* This is the best one found so far */
1189 best = goodness;
1190 best_p = p;
1191 best_pref = nprefix;
1192 best_length = length;
1193 ins = tmp_ins;
1194 }
1195 }
1196 }
1197 }
1198
1199 if (!best_p)
1200 return 0; /* no instruction was matched */
1201
1202 /* Pick the best match */
1203 p = best_p;
1204 length = best_length;
1205
1206 slen = 0;
1207
1208 /* TODO: snprintf returns the value that the string would have if
1209 * the buffer were long enough, and not the actual length of
1210 * the returned string, so each instance of using the return
1211 * value of snprintf should actually be checked to assure that
1212 * the return value is "sane." Maybe a macro wrapper could
1213 * be used for that purpose.
1214 */
1215 for (i = 0; i < MAXPREFIX; i++)
1216 switch (ins.prefixes[i]) {
1217 case P_LOCK:
1218 slen += snprintf(output + slen, outbufsize - slen, "lock ");
1219 break;
1220 case P_REP:
1221 slen += snprintf(output + slen, outbufsize - slen, "rep ");
1222 break;
1223 case P_REPE:
1224 slen += snprintf(output + slen, outbufsize - slen, "repe ");
1225 break;
1226 case P_REPNE:
1227 slen += snprintf(output + slen, outbufsize - slen, "repne ");
1228 break;
1229 case P_A16:
1230 slen += snprintf(output + slen, outbufsize - slen, "a16 ");
1231 break;
1232 case P_A32:
1233 slen += snprintf(output + slen, outbufsize - slen, "a32 ");
1234 break;
1235 case P_A64:
1236 slen += snprintf(output + slen, outbufsize - slen, "a64 ");
1237 break;
1238 case P_O16:
1239 slen += snprintf(output + slen, outbufsize - slen, "o16 ");
1240 break;
1241 case P_O32:
1242 slen += snprintf(output + slen, outbufsize - slen, "o32 ");
1243 break;
1244 case P_O64:
1245 slen += snprintf(output + slen, outbufsize - slen, "o64 ");
1246 break;
1247 default:
1248 break;
1249 }
1250
1251 i = (*p)->opcode;
1252 if (i >= FIRST_COND_OPCODE)
1253 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1254 nasm_insn_names[i], condition_name[ins.condition]);
1255 else
1256 slen += snprintf(output + slen, outbufsize - slen, "%s",
1257 nasm_insn_names[i]);
1258
1259 colon = false;
1260 length += data - origdata; /* fix up for prefixes */
1261 for (i = 0; i < (*p)->operands; i++) {
1262 opflags_t t = (*p)->opd[i];
1263 const operand *o = &ins.oprs[i];
1264 int64_t offs;
1265
1266 if (t & SAME_AS) {
1267 o = &ins.oprs[t & ~SAME_AS];
1268 t = (*p)->opd[t & ~SAME_AS];
1269 }
1270
1271 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1272
1273 offs = o->offset;
1274 if (o->segment & SEG_RELATIVE) {
1275 offs += offset + length;
1276 /*
1277 * sort out wraparound
1278 */
1279 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1280 offs &= 0xffff;
1281 else if (segsize != 64)
1282 offs &= 0xffffffff;
1283
1284 /*
1285 * add sync marker, if autosync is on
1286 */
1287 if (autosync)
1288 add_sync(offs, 0L);
1289 }
1290
1291 if (t & COLON)
1292 colon = true;
1293 else
1294 colon = false;
1295
1296 if ((t & (REGISTER | FPUREG)) ||
1297 (o->segment & SEG_RMREG)) {
1298 enum reg_enum reg;
1299 reg = whichreg(t, o->basereg, ins.rex);
1300 if (t & TO)
1301 slen += snprintf(output + slen, outbufsize - slen, "to ");
1302 slen += snprintf(output + slen, outbufsize - slen, "%s",
1303 nasm_reg_names[reg-EXPR_REG_START]);
1304 } else if (!(UNITY & ~t)) {
1305 output[slen++] = '1';
1306 } else if (t & IMMEDIATE) {
1307 if (t & BITS8) {
1308 slen +=
1309 snprintf(output + slen, outbufsize - slen, "byte ");
1310 if (o->segment & SEG_SIGNED) {
1311 if (offs < 0) {
1312 offs *= -1;
1313 output[slen++] = '-';
1314 } else
1315 output[slen++] = '+';
1316 }
1317 } else if (t & BITS16) {
1318 slen +=
1319 snprintf(output + slen, outbufsize - slen, "word ");
1320 } else if (t & BITS32) {
1321 slen +=
1322 snprintf(output + slen, outbufsize - slen, "dword ");
1323 } else if (t & BITS64) {
1324 slen +=
1325 snprintf(output + slen, outbufsize - slen, "qword ");
1326 } else if (t & NEAR) {
1327 slen +=
1328 snprintf(output + slen, outbufsize - slen, "near ");
1329 } else if (t & SHORT) {
1330 slen +=
1331 snprintf(output + slen, outbufsize - slen, "short ");
1332 }
1333 slen +=
1334 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1335 offs);
1336 } else if (!(MEM_OFFS & ~t)) {
1337 slen +=
1338 snprintf(output + slen, outbufsize - slen,
1339 "[%s%s%s0x%"PRIx64"]",
1340 (segover ? segover : ""),
1341 (segover ? ":" : ""),
1342 (o->disp_size == 64 ? "qword " :
1343 o->disp_size == 32 ? "dword " :
1344 o->disp_size == 16 ? "word " : ""), offs);
1345 segover = NULL;
1346 } else if (!(REGMEM & ~t)) {
1347 int started = false;
1348 if (t & BITS8)
1349 slen +=
1350 snprintf(output + slen, outbufsize - slen, "byte ");
1351 if (t & BITS16)
1352 slen +=
1353 snprintf(output + slen, outbufsize - slen, "word ");
1354 if (t & BITS32)
1355 slen +=
1356 snprintf(output + slen, outbufsize - slen, "dword ");
1357 if (t & BITS64)
1358 slen +=
1359 snprintf(output + slen, outbufsize - slen, "qword ");
1360 if (t & BITS80)
1361 slen +=
1362 snprintf(output + slen, outbufsize - slen, "tword ");
1363 if (t & BITS128)
1364 slen +=
1365 snprintf(output + slen, outbufsize - slen, "oword ");
1366 if (t & BITS256)
1367 slen +=
1368 snprintf(output + slen, outbufsize - slen, "yword ");
1369 if (t & FAR)
1370 slen += snprintf(output + slen, outbufsize - slen, "far ");
1371 if (t & NEAR)
1372 slen +=
1373 snprintf(output + slen, outbufsize - slen, "near ");
1374 output[slen++] = '[';
1375 if (o->disp_size)
1376 slen += snprintf(output + slen, outbufsize - slen, "%s",
1377 (o->disp_size == 64 ? "qword " :
1378 o->disp_size == 32 ? "dword " :
1379 o->disp_size == 16 ? "word " :
1380 ""));
1381 if (o->eaflags & EAF_REL)
1382 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1383 if (segover) {
1384 slen +=
1385 snprintf(output + slen, outbufsize - slen, "%s:",
1386 segover);
1387 segover = NULL;
1388 }
1389 if (o->basereg != -1) {
1390 slen += snprintf(output + slen, outbufsize - slen, "%s",
1391 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1392 started = true;
1393 }
1394 if (o->indexreg != -1) {
1395 if (started)
1396 output[slen++] = '+';
1397 slen += snprintf(output + slen, outbufsize - slen, "%s",
1398 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1399 if (o->scale > 1)
1400 slen +=
1401 snprintf(output + slen, outbufsize - slen, "*%d",
1402 o->scale);
1403 started = true;
1404 }
1405
1406
1407 if (o->segment & SEG_DISP8) {
1408 const char *prefix;
1409 uint8_t offset = offs;
1410 if ((int8_t)offset < 0) {
1411 prefix = "-";
1412 offset = -offset;
1413 } else {
1414 prefix = "+";
1415 }
1416 slen +=
1417 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1418 prefix, offset);
1419 } else if (o->segment & SEG_DISP16) {
1420 const char *prefix;
1421 uint16_t offset = offs;
1422 if ((int16_t)offset < 0 && started) {
1423 offset = -offset;
1424 prefix = "-";
1425 } else {
1426 prefix = started ? "+" : "";
1427 }
1428 slen +=
1429 snprintf(output + slen, outbufsize - slen,
1430 "%s0x%"PRIx16"", prefix, offset);
1431 } else if (o->segment & SEG_DISP32) {
1432 if (prefix.asize == 64) {
1433 const char *prefix;
1434 uint64_t offset = (int64_t)(int32_t)offs;
1435 if ((int32_t)offs < 0 && started) {
1436 offset = -offset;
1437 prefix = "-";
1438 } else {
1439 prefix = started ? "+" : "";
1440 }
1441 slen +=
1442 snprintf(output + slen, outbufsize - slen,
1443 "%s0x%"PRIx64"", prefix, offset);
1444 } else {
1445 const char *prefix;
1446 uint32_t offset = offs;
1447 if ((int32_t) offset < 0 && started) {
1448 offset = -offset;
1449 prefix = "-";
1450 } else {
1451 prefix = started ? "+" : "";
1452 }
1453 slen +=
1454 snprintf(output + slen, outbufsize - slen,
1455 "%s0x%"PRIx32"", prefix, offset);
1456 }
1457 }
1458 output[slen++] = ']';
1459 } else {
1460 slen +=
1461 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1462 i);
1463 }
1464 }
1465 output[slen] = '\0';
1466 if (segover) { /* unused segment override */
1467 char *p = output;
1468 int count = slen + 1;
1469 while (count--)
1470 p[count + 3] = p[count];
1471 strncpy(output, segover, 2);
1472 output[2] = ' ';
1473 }
1474 return length;
1475 }
1476
1477 int32_t eatbyte(uint8_t *data, char *output, int outbufsize)
1478 {
1479 snprintf(output, outbufsize, "db 0x%02X", *data);
1480 return 1;
1481 }
The Netwide Assembler