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Add {vex3} and {vex2} prefixes by analogy with {evex}
[nasm.git] / assemble.c
blobbf1490d0063d117c1bc032642afc2de76b88517f
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2013 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - the position of index register operand in MIB (BND insns)
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \172\ab - the register number from operand a in bits 7..4, with
64 * the 4-bit immediate from operand b in bits 3..0.
65 * \173\xab - the register number from operand a in bits 7..4, with
66 * the value b in bits 3..0.
67 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
68 * an arbitrary value in bits 3..0 (assembled as zero.)
69 * \2ab - a ModRM, calculated on EA in operand a, with the spare
70 * field equal to digit b.
71 *
72 * \240..\243 - this instruction uses EVEX rather than REX or VEX/XOP, with the
73 * V field taken from operand 0..3.
74 * \250 - this instruction uses EVEX rather than REX or VEX/XOP, with the
75 * V field set to 1111b.
76 * EVEX prefixes are followed by the sequence:
77 * \cm\wlp\tup where cm is:
78 * cc 000 0mm
79 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
80 * and wlp is:
81 * 00 wwl lpp
82 * [l0] ll = 0 (.128, .lz)
83 * [l1] ll = 1 (.256)
84 * [l2] ll = 2 (.512)
85 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
86 *
87 * [w0] ww = 0 for W = 0
88 * [w1] ww = 1 for W = 1
89 * [wig] ww = 2 for W don't care (always assembled as 0)
90 * [ww] ww = 3 for W used as REX.W
91 *
92 * [p0] pp = 0 for no prefix
93 * [60] pp = 1 for legacy prefix 60
94 * [f3] pp = 2
95 * [f2] pp = 3
96 *
97 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
98 * (compressed displacement encoding)
99 *
100 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
101 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
102 * V field taken from operand 0..3.
103 * \270 - this instruction uses VEX/XOP rather than REX, with the
104 * V field set to 1111b.
105 *
106 * VEX/XOP prefixes are followed by the sequence:
107 * \tmm\wlp where mm is the M field; and wlp is:
108 * 00 wwl lpp
109 * [l0] ll = 0 for L = 0 (.128, .lz)
110 * [l1] ll = 1 for L = 1 (.256)
111 * [lig] ll = 2 for L don't care (always assembled as 0)
112 *
113 * [w0] ww = 0 for W = 0
114 * [w1 ] ww = 1 for W = 1
115 * [wig] ww = 2 for W don't care (always assembled as 0)
116 * [ww] ww = 3 for W used as REX.W
117 *
118 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
119 *
120 * \271 - instruction takes XRELEASE (F3) with or without lock
121 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
122 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
123 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
124 * to the operand size (if o16/o32/o64 present) or the bit size
125 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
126 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
127 * \312 - (disassembler only) invalid with non-default address size.
128 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
129 * \314 - (disassembler only) invalid with REX.B
130 * \315 - (disassembler only) invalid with REX.X
131 * \316 - (disassembler only) invalid with REX.R
132 * \317 - (disassembler only) invalid with REX.W
133 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
134 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
135 * \322 - indicates that this instruction is only valid when the
136 * operand size is the default (instruction to disassembler,
137 * generates no code in the assembler)
138 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
139 * \324 - indicates 64-bit operand size requiring REX prefix.
140 * \325 - instruction which always uses spl/bpl/sil/dil
141 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
142 disassembler only; for SSE instructions.
143 * \330 - a literal byte follows in the code stream, to be added
144 * to the condition code value of the instruction.
145 * \331 - instruction not valid with REP prefix. Hint for
146 * disassembler only; for SSE instructions.
147 * \332 - REP prefix (0xF2 byte) used as opcode extension.
148 * \333 - REP prefix (0xF3 byte) used as opcode extension.
149 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
150 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
151 * \336 - force a REP(E) prefix (0xF3) even if not specified.
152 * \337 - force a REPNE prefix (0xF2) even if not specified.
153 * \336-\337 are still listed as prefixes in the disassembler.
154 * \340 - reserve <operand 0> bytes of uninitialized storage.
155 * Operand 0 had better be a segmentless constant.
156 * \341 - this instruction needs a WAIT "prefix"
157 * \360 - no SSE prefix (== \364\331)
158 * \361 - 66 SSE prefix (== \366\331)
159 * \364 - operand-size prefix (0x66) not permitted
160 * \365 - address-size prefix (0x67) not permitted
161 * \366 - operand-size prefix (0x66) used as opcode extension
162 * \367 - address-size prefix (0x67) used as opcode extension
163 * \370,\371 - match only if operand 0 meets byte jump criteria.
164 * 370 is used for Jcc, 371 is used for JMP.
165 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
166 * used for conditional jump over longer jump
167 * \374 - this instruction takes an XMM VSIB memory EA
168 * \375 - this instruction takes an YMM VSIB memory EA
169 * \376 - this instruction takes an ZMM VSIB memory EA
170 */
171
172 #include "compiler.h"
173
174 #include <stdio.h>
175 #include <string.h>
176 #include <inttypes.h>
177
178 #include "nasm.h"
179 #include "nasmlib.h"
180 #include "assemble.h"
181 #include "insns.h"
182 #include "tables.h"
183 #include "disp8.h"
184
185 enum match_result {
186 /*
187 * Matching errors. These should be sorted so that more specific
188 * errors come later in the sequence.
189 */
190 MERR_INVALOP,
191 MERR_OPSIZEMISSING,
192 MERR_OPSIZEMISMATCH,
193 MERR_BRNUMMISMATCH,
194 MERR_BADCPU,
195 MERR_BADMODE,
196 MERR_BADHLE,
197 MERR_ENCMISMATCH,
198 MERR_BADBND,
199 /*
200 * Matching success; the conditional ones first
201 */
202 MOK_JUMP, /* Matching OK but needs jmp_match() */
203 MOK_GOOD /* Matching unconditionally OK */
204 };
205
206 typedef struct {
207 enum ea_type type; /* what kind of EA is this? */
208 int sib_present; /* is a SIB byte necessary? */
209 int bytes; /* # of bytes of offset needed */
210 int size; /* lazy - this is sib+bytes+1 */
211 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
212 int8_t disp8; /* compressed displacement for EVEX */
213 } ea;
214
215 #define GEN_SIB(scale, index, base) \
216 (((scale) << 6) | ((index) << 3) | ((base)))
217
218 #define GEN_MODRM(mod, reg, rm) \
219 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
220
221 static iflag_t cpu; /* cpu level received from nasm.c */
222 static efunc errfunc;
223 static struct ofmt *outfmt;
224 static ListGen *list;
225
226 static int64_t calcsize(int32_t, int64_t, int, insn *,
227 const struct itemplate *);
228 static void gencode(int32_t segment, int64_t offset, int bits,
229 insn * ins, const struct itemplate *temp,
230 int64_t insn_end);
231 static enum match_result find_match(const struct itemplate **tempp,
232 insn *instruction,
233 int32_t segment, int64_t offset, int bits);
234 static enum match_result matches(const struct itemplate *, insn *, int bits);
235 static opflags_t regflag(const operand *);
236 static int32_t regval(const operand *);
237 static int rexflags(int, opflags_t, int);
238 static int op_rexflags(const operand *, int);
239 static int op_evexflags(const operand *, int, uint8_t);
240 static void add_asp(insn *, int);
241
242 static enum ea_type process_ea(operand *, ea *, int, int, opflags_t, insn *);
243
244 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
245 {
246 return ins->prefixes[pos] == prefix;
247 }
248
249 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
250 {
251 if (ins->prefixes[pos])
252 errfunc(ERR_NONFATAL, "invalid %s prefix",
253 prefix_name(ins->prefixes[pos]));
254 }
255
256 static const char *size_name(int size)
257 {
258 switch (size) {
259 case 1:
260 return "byte";
261 case 2:
262 return "word";
263 case 4:
264 return "dword";
265 case 8:
266 return "qword";
267 case 10:
268 return "tword";
269 case 16:
270 return "oword";
271 case 32:
272 return "yword";
273 case 64:
274 return "zword";
275 default:
276 return "???";
277 }
278 }
279
280 static void warn_overflow(int pass, int size)
281 {
282 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
283 "%s data exceeds bounds", size_name(size));
284 }
285
286 static void warn_overflow_const(int64_t data, int size)
287 {
288 if (overflow_general(data, size))
289 warn_overflow(ERR_PASS1, size);
290 }
291
292 static void warn_overflow_opd(const struct operand *o, int size)
293 {
294 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
295 if (overflow_general(o->offset, size))
296 warn_overflow(ERR_PASS2, size);
297 }
298 }
299
300 /*
301 * This routine wrappers the real output format's output routine,
302 * in order to pass a copy of the data off to the listing file
303 * generator at the same time.
304 */
305 static void out(int64_t offset, int32_t segto, const void *data,
306 enum out_type type, uint64_t size,
307 int32_t segment, int32_t wrt)
308 {
309 static int32_t lineno = 0; /* static!!! */
310 static char *lnfname = NULL;
311 uint8_t p[8];
312
313 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
314 /*
315 * This is a non-relocated address, and we're going to
316 * convert it into RAWDATA format.
317 */
318 uint8_t *q = p;
319
320 if (size > 8) {
321 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
322 return;
323 }
324
325 WRITEADDR(q, *(int64_t *)data, size);
326 data = p;
327 type = OUT_RAWDATA;
328 }
329
330 list->output(offset, data, type, size);
331
332 /*
333 * this call to src_get determines when we call the
334 * debug-format-specific "linenum" function
335 * it updates lineno and lnfname to the current values
336 * returning 0 if "same as last time", -2 if lnfname
337 * changed, and the amount by which lineno changed,
338 * if it did. thus, these variables must be static
339 */
340
341 if (src_get(&lineno, &lnfname))
342 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
343
344 outfmt->output(segto, data, type, size, segment, wrt);
345 }
346
347 static void out_imm8(int64_t offset, int32_t segment, struct operand *opx)
348 {
349 if (opx->segment != NO_SEG) {
350 uint64_t data = opx->offset;
351 out(offset, segment, &data, OUT_ADDRESS, 1, opx->segment, opx->wrt);
352 } else {
353 uint8_t byte = opx->offset;
354 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
355 }
356 }
357
358 static bool jmp_match(int32_t segment, int64_t offset, int bits,
359 insn * ins, const struct itemplate *temp)
360 {
361 int64_t isize;
362 const uint8_t *code = temp->code;
363 uint8_t c = code[0];
364 bool is_byte;
365
366 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
367 return false;
368 if (!optimizing)
369 return false;
370 if (optimizing < 0 && c == 0371)
371 return false;
372
373 isize = calcsize(segment, offset, bits, ins, temp);
374
375 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
376 /* Be optimistic in pass 1 */
377 return true;
378
379 if (ins->oprs[0].segment != segment)
380 return false;
381
382 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
383 is_byte = (isize >= -128 && isize <= 127); /* is it byte size? */
384
385 if (is_byte && c == 0371 && ins->prefixes[PPS_REP] == P_BND) {
386 /* jmp short (opcode eb) cannot be used with bnd prefix. */
387 ins->prefixes[PPS_REP] = P_none;
388 }
389
390 return is_byte;
391 }
392
393 int64_t assemble(int32_t segment, int64_t offset, int bits, iflag_t cp,
394 insn * instruction, struct ofmt *output, efunc error,
395 ListGen * listgen)
396 {
397 const struct itemplate *temp;
398 int j;
399 enum match_result m;
400 int64_t insn_end;
401 int32_t itimes;
402 int64_t start = offset;
403 int64_t wsize; /* size for DB etc. */
404
405 errfunc = error; /* to pass to other functions */
406 cpu = cp;
407 outfmt = output; /* likewise */
408 list = listgen; /* and again */
409
410 wsize = idata_bytes(instruction->opcode);
411 if (wsize == -1)
412 return 0;
413
414 if (wsize) {
415 extop *e;
416 int32_t t = instruction->times;
417 if (t < 0)
418 errfunc(ERR_PANIC,
419 "instruction->times < 0 (%ld) in assemble()", t);
420
421 while (t--) { /* repeat TIMES times */
422 list_for_each(e, instruction->eops) {
423 if (e->type == EOT_DB_NUMBER) {
424 if (wsize > 8) {
425 errfunc(ERR_NONFATAL,
426 "integer supplied to a DT, DO or DY"
427 " instruction");
428 } else {
429 out(offset, segment, &e->offset,
430 OUT_ADDRESS, wsize, e->segment, e->wrt);
431 offset += wsize;
432 }
433 } else if (e->type == EOT_DB_STRING ||
434 e->type == EOT_DB_STRING_FREE) {
435 int align;
436
437 out(offset, segment, e->stringval,
438 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
439 align = e->stringlen % wsize;
440
441 if (align) {
442 align = wsize - align;
443 out(offset, segment, zero_buffer,
444 OUT_RAWDATA, align, NO_SEG, NO_SEG);
445 }
446 offset += e->stringlen + align;
447 }
448 }
449 if (t > 0 && t == instruction->times - 1) {
450 /*
451 * Dummy call to list->output to give the offset to the
452 * listing module.
453 */
454 list->output(offset, NULL, OUT_RAWDATA, 0);
455 list->uplevel(LIST_TIMES);
456 }
457 }
458 if (instruction->times > 1)
459 list->downlevel(LIST_TIMES);
460 return offset - start;
461 }
462
463 if (instruction->opcode == I_INCBIN) {
464 const char *fname = instruction->eops->stringval;
465 FILE *fp;
466
467 fp = fopen(fname, "rb");
468 if (!fp) {
469 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
470 fname);
471 } else if (fseek(fp, 0L, SEEK_END) < 0) {
472 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
473 fname);
474 fclose(fp);
475 } else {
476 static char buf[4096];
477 size_t t = instruction->times;
478 size_t base = 0;
479 size_t len;
480
481 len = ftell(fp);
482 if (instruction->eops->next) {
483 base = instruction->eops->next->offset;
484 len -= base;
485 if (instruction->eops->next->next &&
486 len > (size_t)instruction->eops->next->next->offset)
487 len = (size_t)instruction->eops->next->next->offset;
488 }
489 /*
490 * Dummy call to list->output to give the offset to the
491 * listing module.
492 */
493 list->output(offset, NULL, OUT_RAWDATA, 0);
494 list->uplevel(LIST_INCBIN);
495 while (t--) {
496 size_t l;
497
498 fseek(fp, base, SEEK_SET);
499 l = len;
500 while (l > 0) {
501 int32_t m;
502 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
503 if (!m) {
504 /*
505 * This shouldn't happen unless the file
506 * actually changes while we are reading
507 * it.
508 */
509 error(ERR_NONFATAL,
510 "`incbin': unexpected EOF while"
511 " reading file `%s'", fname);
512 t = 0; /* Try to exit cleanly */
513 break;
514 }
515 out(offset, segment, buf, OUT_RAWDATA, m,
516 NO_SEG, NO_SEG);
517 l -= m;
518 }
519 }
520 list->downlevel(LIST_INCBIN);
521 if (instruction->times > 1) {
522 /*
523 * Dummy call to list->output to give the offset to the
524 * listing module.
525 */
526 list->output(offset, NULL, OUT_RAWDATA, 0);
527 list->uplevel(LIST_TIMES);
528 list->downlevel(LIST_TIMES);
529 }
530 fclose(fp);
531 return instruction->times * len;
532 }
533 return 0; /* if we're here, there's an error */
534 }
535
536 /* Check to see if we need an address-size prefix */
537 add_asp(instruction, bits);
538
539 m = find_match(&temp, instruction, segment, offset, bits);
540
541 if (m == MOK_GOOD) {
542 /* Matches! */
543 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
544 itimes = instruction->times;
545 if (insn_size < 0) /* shouldn't be, on pass two */
546 error(ERR_PANIC, "errors made it through from pass one");
547 else
548 while (itimes--) {
549 for (j = 0; j < MAXPREFIX; j++) {
550 uint8_t c = 0;
551 switch (instruction->prefixes[j]) {
552 case P_WAIT:
553 c = 0x9B;
554 break;
555 case P_LOCK:
556 c = 0xF0;
557 break;
558 case P_REPNE:
559 case P_REPNZ:
560 case P_XACQUIRE:
561 case P_BND:
562 c = 0xF2;
563 break;
564 case P_REPE:
565 case P_REPZ:
566 case P_REP:
567 case P_XRELEASE:
568 c = 0xF3;
569 break;
570 case R_CS:
571 if (bits == 64) {
572 error(ERR_WARNING | ERR_PASS2,
573 "cs segment base generated, but will be ignored in 64-bit mode");
574 }
575 c = 0x2E;
576 break;
577 case R_DS:
578 if (bits == 64) {
579 error(ERR_WARNING | ERR_PASS2,
580 "ds segment base generated, but will be ignored in 64-bit mode");
581 }
582 c = 0x3E;
583 break;
584 case R_ES:
585 if (bits == 64) {
586 error(ERR_WARNING | ERR_PASS2,
587 "es segment base generated, but will be ignored in 64-bit mode");
588 }
589 c = 0x26;
590 break;
591 case R_FS:
592 c = 0x64;
593 break;
594 case R_GS:
595 c = 0x65;
596 break;
597 case R_SS:
598 if (bits == 64) {
599 error(ERR_WARNING | ERR_PASS2,
600 "ss segment base generated, but will be ignored in 64-bit mode");
601 }
602 c = 0x36;
603 break;
604 case R_SEGR6:
605 case R_SEGR7:
606 error(ERR_NONFATAL,
607 "segr6 and segr7 cannot be used as prefixes");
608 break;
609 case P_A16:
610 if (bits == 64) {
611 error(ERR_NONFATAL,
612 "16-bit addressing is not supported "
613 "in 64-bit mode");
614 } else if (bits != 16)
615 c = 0x67;
616 break;
617 case P_A32:
618 if (bits != 32)
619 c = 0x67;
620 break;
621 case P_A64:
622 if (bits != 64) {
623 error(ERR_NONFATAL,
624 "64-bit addressing is only supported "
625 "in 64-bit mode");
626 }
627 break;
628 case P_ASP:
629 c = 0x67;
630 break;
631 case P_O16:
632 if (bits != 16)
633 c = 0x66;
634 break;
635 case P_O32:
636 if (bits == 16)
637 c = 0x66;
638 break;
639 case P_O64:
640 /* REX.W */
641 break;
642 case P_OSP:
643 c = 0x66;
644 break;
645 case P_EVEX:
646 case P_VEX3:
647 case P_VEX2:
648 case P_none:
649 break;
650 default:
651 error(ERR_PANIC, "invalid instruction prefix");
652 }
653 if (c != 0) {
654 out(offset, segment, &c, OUT_RAWDATA, 1,
655 NO_SEG, NO_SEG);
656 offset++;
657 }
658 }
659 insn_end = offset + insn_size;
660 gencode(segment, offset, bits, instruction,
661 temp, insn_end);
662 offset += insn_size;
663 if (itimes > 0 && itimes == instruction->times - 1) {
664 /*
665 * Dummy call to list->output to give the offset to the
666 * listing module.
667 */
668 list->output(offset, NULL, OUT_RAWDATA, 0);
669 list->uplevel(LIST_TIMES);
670 }
671 }
672 if (instruction->times > 1)
673 list->downlevel(LIST_TIMES);
674 return offset - start;
675 } else {
676 /* No match */
677 switch (m) {
678 case MERR_OPSIZEMISSING:
679 error(ERR_NONFATAL, "operation size not specified");
680 break;
681 case MERR_OPSIZEMISMATCH:
682 error(ERR_NONFATAL, "mismatch in operand sizes");
683 break;
684 case MERR_BRNUMMISMATCH:
685 error(ERR_NONFATAL,
686 "mismatch in the number of broadcasting elements");
687 break;
688 case MERR_BADCPU:
689 error(ERR_NONFATAL, "no instruction for this cpu level");
690 break;
691 case MERR_BADMODE:
692 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
693 bits);
694 break;
695 case MERR_ENCMISMATCH:
696 error(ERR_NONFATAL, "specific encoding scheme not available");
697 break;
698 case MERR_BADBND:
699 error(ERR_NONFATAL, "bnd prefix is not allowed");
700 break;
701 default:
702 error(ERR_NONFATAL,
703 "invalid combination of opcode and operands");
704 break;
705 }
706 }
707 return 0;
708 }
709
710 int64_t insn_size(int32_t segment, int64_t offset, int bits, iflag_t cp,
711 insn * instruction, efunc error)
712 {
713 const struct itemplate *temp;
714 enum match_result m;
715
716 errfunc = error; /* to pass to other functions */
717 cpu = cp;
718
719 if (instruction->opcode == I_none)
720 return 0;
721
722 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
723 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
724 instruction->opcode == I_DT || instruction->opcode == I_DO ||
725 instruction->opcode == I_DY) {
726 extop *e;
727 int32_t isize, osize, wsize;
728
729 isize = 0;
730 wsize = idata_bytes(instruction->opcode);
731
732 list_for_each(e, instruction->eops) {
733 int32_t align;
734
735 osize = 0;
736 if (e->type == EOT_DB_NUMBER) {
737 osize = 1;
738 warn_overflow_const(e->offset, wsize);
739 } else if (e->type == EOT_DB_STRING ||
740 e->type == EOT_DB_STRING_FREE)
741 osize = e->stringlen;
742
743 align = (-osize) % wsize;
744 if (align < 0)
745 align += wsize;
746 isize += osize + align;
747 }
748 return isize * instruction->times;
749 }
750
751 if (instruction->opcode == I_INCBIN) {
752 const char *fname = instruction->eops->stringval;
753 FILE *fp;
754 int64_t val = 0;
755 size_t len;
756
757 fp = fopen(fname, "rb");
758 if (!fp)
759 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
760 fname);
761 else if (fseek(fp, 0L, SEEK_END) < 0)
762 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
763 fname);
764 else {
765 len = ftell(fp);
766 if (instruction->eops->next) {
767 len -= instruction->eops->next->offset;
768 if (instruction->eops->next->next &&
769 len > (size_t)instruction->eops->next->next->offset) {
770 len = (size_t)instruction->eops->next->next->offset;
771 }
772 }
773 val = instruction->times * len;
774 }
775 if (fp)
776 fclose(fp);
777 return val;
778 }
779
780 /* Check to see if we need an address-size prefix */
781 add_asp(instruction, bits);
782
783 m = find_match(&temp, instruction, segment, offset, bits);
784 if (m == MOK_GOOD) {
785 /* we've matched an instruction. */
786 int64_t isize;
787 int j;
788
789 isize = calcsize(segment, offset, bits, instruction, temp);
790 if (isize < 0)
791 return -1;
792 for (j = 0; j < MAXPREFIX; j++) {
793 switch (instruction->prefixes[j]) {
794 case P_A16:
795 if (bits != 16)
796 isize++;
797 break;
798 case P_A32:
799 if (bits != 32)
800 isize++;
801 break;
802 case P_O16:
803 if (bits != 16)
804 isize++;
805 break;
806 case P_O32:
807 if (bits == 16)
808 isize++;
809 break;
810 case P_A64:
811 case P_O64:
812 case P_EVEX:
813 case P_VEX3:
814 case P_VEX2:
815 case P_none:
816 break;
817 default:
818 isize++;
819 break;
820 }
821 }
822 return isize * instruction->times;
823 } else {
824 return -1; /* didn't match any instruction */
825 }
826 }
827
828 static void bad_hle_warn(const insn * ins, uint8_t hleok)
829 {
830 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
831 enum whatwarn { w_none, w_lock, w_inval } ww;
832 static const enum whatwarn warn[2][4] =
833 {
834 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
835 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
836 };
837 unsigned int n;
838
839 n = (unsigned int)rep_pfx - P_XACQUIRE;
840 if (n > 1)
841 return; /* Not XACQUIRE/XRELEASE */
842
843 ww = warn[n][hleok];
844 if (!is_class(MEMORY, ins->oprs[0].type))
845 ww = w_inval; /* HLE requires operand 0 to be memory */
846
847 switch (ww) {
848 case w_none:
849 break;
850
851 case w_lock:
852 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
853 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
854 "%s with this instruction requires lock",
855 prefix_name(rep_pfx));
856 }
857 break;
858
859 case w_inval:
860 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
861 "%s invalid with this instruction",
862 prefix_name(rep_pfx));
863 break;
864 }
865 }
866
867 /* Common construct */
868 #define case3(x) case (x): case (x)+1: case (x)+2
869 #define case4(x) case3(x): case (x)+3
870
871 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
872 insn * ins, const struct itemplate *temp)
873 {
874 const uint8_t *codes = temp->code;
875 int64_t length = 0;
876 uint8_t c;
877 int rex_mask = ~0;
878 int op1, op2;
879 struct operand *opx;
880 uint8_t opex = 0;
881 enum ea_type eat;
882 uint8_t hleok = 0;
883 bool lockcheck = true;
884 enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
885
886 ins->rex = 0; /* Ensure REX is reset */
887 eat = EA_SCALAR; /* Expect a scalar EA */
888 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
889
890 if (ins->prefixes[PPS_OSIZE] == P_O64)
891 ins->rex |= REX_W;
892
893 (void)segment; /* Don't warn that this parameter is unused */
894 (void)offset; /* Don't warn that this parameter is unused */
895
896 while (*codes) {
897 c = *codes++;
898 op1 = (c & 3) + ((opex & 1) << 2);
899 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
900 opx = &ins->oprs[op1];
901 opex = 0; /* For the next iteration */
902
903 switch (c) {
904 case4(01):
905 codes += c, length += c;
906 break;
907
908 case3(05):
909 opex = c;
910 break;
911
912 case4(010):
913 ins->rex |=
914 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
915 codes++, length++;
916 break;
917
918 case4(014):
919 /* this is an index reg of MIB operand */
920 mib_index = opx->basereg;
921 break;
922
923 case4(020):
924 case4(024):
925 length++;
926 break;
927
928 case4(030):
929 length += 2;
930 break;
931
932 case4(034):
933 if (opx->type & (BITS16 | BITS32 | BITS64))
934 length += (opx->type & BITS16) ? 2 : 4;
935 else
936 length += (bits == 16) ? 2 : 4;
937 break;
938
939 case4(040):
940 length += 4;
941 break;
942
943 case4(044):
944 length += ins->addr_size >> 3;
945 break;
946
947 case4(050):
948 length++;
949 break;
950
951 case4(054):
952 length += 8; /* MOV reg64/imm */
953 break;
954
955 case4(060):
956 length += 2;
957 break;
958
959 case4(064):
960 if (opx->type & (BITS16 | BITS32 | BITS64))
961 length += (opx->type & BITS16) ? 2 : 4;
962 else
963 length += (bits == 16) ? 2 : 4;
964 break;
965
966 case4(070):
967 length += 4;
968 break;
969
970 case4(074):
971 length += 2;
972 break;
973
974 case 0172:
975 case 0173:
976 codes++;
977 length++;
978 break;
979
980 case4(0174):
981 length++;
982 break;
983
984 case4(0240):
985 ins->rex |= REX_EV;
986 ins->vexreg = regval(opx);
987 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
988 ins->vex_cm = *codes++;
989 ins->vex_wlp = *codes++;
990 ins->evex_tuple = (*codes++ - 0300);
991 break;
992
993 case 0250:
994 ins->rex |= REX_EV;
995 ins->vexreg = 0;
996 ins->vex_cm = *codes++;
997 ins->vex_wlp = *codes++;
998 ins->evex_tuple = (*codes++ - 0300);
999 break;
1000
1001 case4(0254):
1002 length += 4;
1003 break;
1004
1005 case4(0260):
1006 ins->rex |= REX_V;
1007 ins->vexreg = regval(opx);
1008 ins->vex_cm = *codes++;
1009 ins->vex_wlp = *codes++;
1010 break;
1011
1012 case 0270:
1013 ins->rex |= REX_V;
1014 ins->vexreg = 0;
1015 ins->vex_cm = *codes++;
1016 ins->vex_wlp = *codes++;
1017 break;
1018
1019 case3(0271):
1020 hleok = c & 3;
1021 break;
1022
1023 case4(0274):
1024 length++;
1025 break;
1026
1027 case4(0300):
1028 break;
1029
1030 case 0310:
1031 if (bits == 64)
1032 return -1;
1033 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1034 break;
1035
1036 case 0311:
1037 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1038 break;
1039
1040 case 0312:
1041 break;
1042
1043 case 0313:
1044 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1045 has_prefix(ins, PPS_ASIZE, P_A32))
1046 return -1;
1047 break;
1048
1049 case4(0314):
1050 break;
1051
1052 case 0320:
1053 {
1054 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1055 if (pfx == P_O16)
1056 break;
1057 if (pfx != P_none)
1058 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1059 else
1060 ins->prefixes[PPS_OSIZE] = P_O16;
1061 break;
1062 }
1063
1064 case 0321:
1065 {
1066 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1067 if (pfx == P_O32)
1068 break;
1069 if (pfx != P_none)
1070 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1071 else
1072 ins->prefixes[PPS_OSIZE] = P_O32;
1073 break;
1074 }
1075
1076 case 0322:
1077 break;
1078
1079 case 0323:
1080 rex_mask &= ~REX_W;
1081 break;
1082
1083 case 0324:
1084 ins->rex |= REX_W;
1085 break;
1086
1087 case 0325:
1088 ins->rex |= REX_NH;
1089 break;
1090
1091 case 0326:
1092 break;
1093
1094 case 0330:
1095 codes++, length++;
1096 break;
1097
1098 case 0331:
1099 break;
1100
1101 case 0332:
1102 case 0333:
1103 length++;
1104 break;
1105
1106 case 0334:
1107 ins->rex |= REX_L;
1108 break;
1109
1110 case 0335:
1111 break;
1112
1113 case 0336:
1114 if (!ins->prefixes[PPS_REP])
1115 ins->prefixes[PPS_REP] = P_REP;
1116 break;
1117
1118 case 0337:
1119 if (!ins->prefixes[PPS_REP])
1120 ins->prefixes[PPS_REP] = P_REPNE;
1121 break;
1122
1123 case 0340:
1124 if (ins->oprs[0].segment != NO_SEG)
1125 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1126 " quantity of BSS space");
1127 else
1128 length += ins->oprs[0].offset;
1129 break;
1130
1131 case 0341:
1132 if (!ins->prefixes[PPS_WAIT])
1133 ins->prefixes[PPS_WAIT] = P_WAIT;
1134 break;
1135
1136 case 0360:
1137 break;
1138
1139 case 0361:
1140 length++;
1141 break;
1142
1143 case 0364:
1144 case 0365:
1145 break;
1146
1147 case 0366:
1148 case 0367:
1149 length++;
1150 break;
1151
1152 case 0370:
1153 case 0371:
1154 break;
1155
1156 case 0373:
1157 length++;
1158 break;
1159
1160 case 0374:
1161 eat = EA_XMMVSIB;
1162 break;
1163
1164 case 0375:
1165 eat = EA_YMMVSIB;
1166 break;
1167
1168 case 0376:
1169 eat = EA_ZMMVSIB;
1170 break;
1171
1172 case4(0100):
1173 case4(0110):
1174 case4(0120):
1175 case4(0130):
1176 case4(0200):
1177 case4(0204):
1178 case4(0210):
1179 case4(0214):
1180 case4(0220):
1181 case4(0224):
1182 case4(0230):
1183 case4(0234):
1184 {
1185 ea ea_data;
1186 int rfield;
1187 opflags_t rflags;
1188 struct operand *opy = &ins->oprs[op2];
1189 struct operand *op_er_sae;
1190
1191 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1192
1193 if (c <= 0177) {
1194 /* pick rfield from operand b (opx) */
1195 rflags = regflag(opx);
1196 rfield = nasm_regvals[opx->basereg];
1197 } else {
1198 rflags = 0;
1199 rfield = c & 7;
1200 }
1201
1202 /* EVEX.b1 : evex_brerop contains the operand position */
1203 op_er_sae = (ins->evex_brerop >= 0 ?
1204 &ins->oprs[ins->evex_brerop] : NULL);
1205
1206 if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
1207 /* set EVEX.b */
1208 ins->evex_p[2] |= EVEX_P2B;
1209 if (op_er_sae->decoflags & ER) {
1210 /* set EVEX.RC (rounding control) */
1211 ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
1212 & EVEX_P2RC;
1213 }
1214 } else {
1215 /* set EVEX.L'L (vector length) */
1216 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1217 ins->evex_p[1] |= ((ins->vex_wlp << (7 - 4)) & EVEX_P1W);
1218 if (opy->decoflags & BRDCAST_MASK) {
1219 /* set EVEX.b */
1220 ins->evex_p[2] |= EVEX_P2B;
1221 }
1222 }
1223
1224 /*
1225 * if a separate form of MIB (ICC style) is used,
1226 * the index reg info is merged into mem operand
1227 */
1228 if (mib_index != R_none) {
1229 opy->indexreg = mib_index;
1230 opy->scale = 1;
1231 opy->hintbase = mib_index;
1232 opy->hinttype = EAH_NOTBASE;
1233 }
1234
1235 /*
1236 * only for mib operands, make a single reg index [reg*1].
1237 * gas uses this form to explicitly denote index register.
1238 */
1239 if (itemp_has(temp, IF_MIB) &&
1240 (opy->indexreg == -1 && opy->hintbase == opy->basereg &&
1241 opy->hinttype == EAH_NOTBASE)) {
1242 opy->indexreg = opy->basereg;
1243 opy->basereg = -1;
1244 opy->scale = 1;
1245 }
1246
1247 if (process_ea(opy, &ea_data, bits,
1248 rfield, rflags, ins) != eat) {
1249 errfunc(ERR_NONFATAL, "invalid effective address");
1250 return -1;
1251 } else {
1252 ins->rex |= ea_data.rex;
1253 length += ea_data.size;
1254 }
1255 }
1256 break;
1257
1258 default:
1259 errfunc(ERR_PANIC, "internal instruction table corrupt"
1260 ": instruction code \\%o (0x%02X) given", c, c);
1261 break;
1262 }
1263 }
1264
1265 ins->rex &= rex_mask;
1266
1267 if (ins->rex & REX_NH) {
1268 if (ins->rex & REX_H) {
1269 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1270 return -1;
1271 }
1272 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1273 }
1274
1275 switch (ins->prefixes[PPS_VEX]) {
1276 case P_EVEX:
1277 if (!(ins->rex & REX_EV))
1278 return -1;
1279 break;
1280 case P_VEX3:
1281 case P_VEX2:
1282 if (!(ins->rex & REX_V))
1283 return -1;
1284 break;
1285 default:
1286 break;
1287 }
1288
1289 if (ins->rex & (REX_V | REX_EV)) {
1290 int bad32 = REX_R|REX_W|REX_X|REX_B;
1291
1292 if (ins->rex & REX_H) {
1293 errfunc(ERR_NONFATAL, "cannot use high register in AVX instruction");
1294 return -1;
1295 }
1296 switch (ins->vex_wlp & 060) {
1297 case 000:
1298 case 040:
1299 ins->rex &= ~REX_W;
1300 break;
1301 case 020:
1302 ins->rex |= REX_W;
1303 bad32 &= ~REX_W;
1304 break;
1305 case 060:
1306 /* Follow REX_W */
1307 break;
1308 }
1309
1310 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1311 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1312 return -1;
1313 } else if (!(ins->rex & REX_EV) &&
1314 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1315 errfunc(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1316 return -1;
1317 }
1318 if (ins->rex & REX_EV)
1319 length += 4;
1320 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1321 ins->prefixes[PPS_VEX] == P_VEX3)
1322 length += 3;
1323 else
1324 length += 2;
1325 } else if (ins->rex & REX_REAL) {
1326 if (ins->rex & REX_H) {
1327 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1328 return -1;
1329 } else if (bits == 64) {
1330 length++;
1331 } else if ((ins->rex & REX_L) &&
1332 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1333 iflag_ffs(&cpu) >= IF_X86_64) {
1334 /* LOCK-as-REX.R */
1335 assert_no_prefix(ins, PPS_LOCK);
1336 lockcheck = false; /* Already errored, no need for warning */
1337 length++;
1338 } else {
1339 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1340 return -1;
1341 }
1342 }
1343
1344 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1345 (!itemp_has(temp,IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1346 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1347 "instruction is not lockable");
1348 }
1349
1350 bad_hle_warn(ins, hleok);
1351
1352 return length;
1353 }
1354
1355 static inline unsigned int emit_rex(insn *ins, int32_t segment, int64_t offset, int bits)
1356 {
1357 if (bits == 64) {
1358 if ((ins->rex & REX_REAL) && !(ins->rex & (REX_V | REX_EV))) {
1359 ins->rex = (ins->rex & REX_REAL) | REX_P;
1360 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1361 ins->rex = 0;
1362 return 1;
1363 }
1364 }
1365
1366 return 0;
1367 }
1368
1369 static void gencode(int32_t segment, int64_t offset, int bits,
1370 insn * ins, const struct itemplate *temp,
1371 int64_t insn_end)
1372 {
1373 uint8_t c;
1374 uint8_t bytes[4];
1375 int64_t size;
1376 int64_t data;
1377 int op1, op2;
1378 struct operand *opx;
1379 const uint8_t *codes = temp->code;
1380 uint8_t opex = 0;
1381 enum ea_type eat = EA_SCALAR;
1382
1383 while (*codes) {
1384 c = *codes++;
1385 op1 = (c & 3) + ((opex & 1) << 2);
1386 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1387 opx = &ins->oprs[op1];
1388 opex = 0; /* For the next iteration */
1389
1390 switch (c) {
1391 case 01:
1392 case 02:
1393 case 03:
1394 case 04:
1395 offset += emit_rex(ins, segment, offset, bits);
1396 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1397 codes += c;
1398 offset += c;
1399 break;
1400
1401 case 05:
1402 case 06:
1403 case 07:
1404 opex = c;
1405 break;
1406
1407 case4(010):
1408 offset += emit_rex(ins, segment, offset, bits);
1409 bytes[0] = *codes++ + (regval(opx) & 7);
1410 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1411 offset += 1;
1412 break;
1413
1414 case4(014):
1415 break;
1416
1417 case4(020):
1418 if (opx->offset < -256 || opx->offset > 255) {
1419 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1420 "byte value exceeds bounds");
1421 }
1422 out_imm8(offset, segment, opx);
1423 offset += 1;
1424 break;
1425
1426 case4(024):
1427 if (opx->offset < 0 || opx->offset > 255)
1428 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1429 "unsigned byte value exceeds bounds");
1430 out_imm8(offset, segment, opx);
1431 offset += 1;
1432 break;
1433
1434 case4(030):
1435 warn_overflow_opd(opx, 2);
1436 data = opx->offset;
1437 out(offset, segment, &data, OUT_ADDRESS, 2,
1438 opx->segment, opx->wrt);
1439 offset += 2;
1440 break;
1441
1442 case4(034):
1443 if (opx->type & (BITS16 | BITS32))
1444 size = (opx->type & BITS16) ? 2 : 4;
1445 else
1446 size = (bits == 16) ? 2 : 4;
1447 warn_overflow_opd(opx, size);
1448 data = opx->offset;
1449 out(offset, segment, &data, OUT_ADDRESS, size,
1450 opx->segment, opx->wrt);
1451 offset += size;
1452 break;
1453
1454 case4(040):
1455 warn_overflow_opd(opx, 4);
1456 data = opx->offset;
1457 out(offset, segment, &data, OUT_ADDRESS, 4,
1458 opx->segment, opx->wrt);
1459 offset += 4;
1460 break;
1461
1462 case4(044):
1463 data = opx->offset;
1464 size = ins->addr_size >> 3;
1465 warn_overflow_opd(opx, size);
1466 out(offset, segment, &data, OUT_ADDRESS, size,
1467 opx->segment, opx->wrt);
1468 offset += size;
1469 break;
1470
1471 case4(050):
1472 if (opx->segment != segment) {
1473 data = opx->offset;
1474 out(offset, segment, &data,
1475 OUT_REL1ADR, insn_end - offset,
1476 opx->segment, opx->wrt);
1477 } else {
1478 data = opx->offset - insn_end;
1479 if (data > 127 || data < -128)
1480 errfunc(ERR_NONFATAL, "short jump is out of range");
1481 out(offset, segment, &data,
1482 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1483 }
1484 offset += 1;
1485 break;
1486
1487 case4(054):
1488 data = (int64_t)opx->offset;
1489 out(offset, segment, &data, OUT_ADDRESS, 8,
1490 opx->segment, opx->wrt);
1491 offset += 8;
1492 break;
1493
1494 case4(060):
1495 if (opx->segment != segment) {
1496 data = opx->offset;
1497 out(offset, segment, &data,
1498 OUT_REL2ADR, insn_end - offset,
1499 opx->segment, opx->wrt);
1500 } else {
1501 data = opx->offset - insn_end;
1502 out(offset, segment, &data,
1503 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1504 }
1505 offset += 2;
1506 break;
1507
1508 case4(064):
1509 if (opx->type & (BITS16 | BITS32 | BITS64))
1510 size = (opx->type & BITS16) ? 2 : 4;
1511 else
1512 size = (bits == 16) ? 2 : 4;
1513 if (opx->segment != segment) {
1514 data = opx->offset;
1515 out(offset, segment, &data,
1516 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1517 insn_end - offset, opx->segment, opx->wrt);
1518 } else {
1519 data = opx->offset - insn_end;
1520 out(offset, segment, &data,
1521 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1522 }
1523 offset += size;
1524 break;
1525
1526 case4(070):
1527 if (opx->segment != segment) {
1528 data = opx->offset;
1529 out(offset, segment, &data,
1530 OUT_REL4ADR, insn_end - offset,
1531 opx->segment, opx->wrt);
1532 } else {
1533 data = opx->offset - insn_end;
1534 out(offset, segment, &data,
1535 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1536 }
1537 offset += 4;
1538 break;
1539
1540 case4(074):
1541 if (opx->segment == NO_SEG)
1542 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1543 " relocatable");
1544 data = 0;
1545 out(offset, segment, &data, OUT_ADDRESS, 2,
1546 outfmt->segbase(1 + opx->segment),
1547 opx->wrt);
1548 offset += 2;
1549 break;
1550
1551 case 0172:
1552 c = *codes++;
1553 opx = &ins->oprs[c >> 3];
1554 bytes[0] = nasm_regvals[opx->basereg] << 4;
1555 opx = &ins->oprs[c & 7];
1556 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1557 errfunc(ERR_NONFATAL,
1558 "non-absolute expression not permitted as argument %d",
1559 c & 7);
1560 } else {
1561 if (opx->offset & ~15) {
1562 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1563 "four-bit argument exceeds bounds");
1564 }
1565 bytes[0] |= opx->offset & 15;
1566 }
1567 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1568 offset++;
1569 break;
1570
1571 case 0173:
1572 c = *codes++;
1573 opx = &ins->oprs[c >> 4];
1574 bytes[0] = nasm_regvals[opx->basereg] << 4;
1575 bytes[0] |= c & 15;
1576 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1577 offset++;
1578 break;
1579
1580 case4(0174):
1581 bytes[0] = nasm_regvals[opx->basereg] << 4;
1582 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1583 offset++;
1584 break;
1585
1586 case4(0254):
1587 data = opx->offset;
1588 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1589 (int32_t)data != (int64_t)data) {
1590 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1591 "signed dword immediate exceeds bounds");
1592 }
1593 out(offset, segment, &data, OUT_ADDRESS, 4,
1594 opx->segment, opx->wrt);
1595 offset += 4;
1596 break;
1597
1598 case4(0240):
1599 case 0250:
1600 codes += 3;
1601 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1602 EVEX_P2Z | EVEX_P2AAA, 2);
1603 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1604 bytes[0] = 0x62;
1605 /* EVEX.X can be set by either REX or EVEX for different reasons */
1606 bytes[1] = ((((ins->rex & 7) << 5) |
1607 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) ^ 0xf0) |
1608 (ins->vex_cm & 3);
1609 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1610 ((~ins->vexreg & 15) << 3) |
1611 (1 << 2) | (ins->vex_wlp & 3);
1612 bytes[3] = ins->evex_p[2];
1613 out(offset, segment, &bytes, OUT_RAWDATA, 4, NO_SEG, NO_SEG);
1614 offset += 4;
1615 break;
1616
1617 case4(0260):
1618 case 0270:
1619 codes += 2;
1620 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1621 ins->prefixes[PPS_VEX] == P_VEX3) {
1622 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1623 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1624 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1625 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1626 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1627 offset += 3;
1628 } else {
1629 bytes[0] = 0xc5;
1630 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1631 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1632 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1633 offset += 2;
1634 }
1635 break;
1636
1637 case 0271:
1638 case 0272:
1639 case 0273:
1640 break;
1641
1642 case4(0274):
1643 {
1644 uint64_t uv, um;
1645 int s;
1646
1647 if (ins->rex & REX_W)
1648 s = 64;
1649 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1650 s = 16;
1651 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1652 s = 32;
1653 else
1654 s = bits;
1655
1656 um = (uint64_t)2 << (s-1);
1657 uv = opx->offset;
1658
1659 if (uv > 127 && uv < (uint64_t)-128 &&
1660 (uv < um-128 || uv > um-1)) {
1661 /* If this wasn't explicitly byte-sized, warn as though we
1662 * had fallen through to the imm16/32/64 case.
1663 */
1664 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1665 "%s value exceeds bounds",
1666 (opx->type & BITS8) ? "signed byte" :
1667 s == 16 ? "word" :
1668 s == 32 ? "dword" :
1669 "signed dword");
1670 }
1671 if (opx->segment != NO_SEG) {
1672 data = uv;
1673 out(offset, segment, &data, OUT_ADDRESS, 1,
1674 opx->segment, opx->wrt);
1675 } else {
1676 bytes[0] = uv;
1677 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1678 NO_SEG);
1679 }
1680 offset += 1;
1681 break;
1682 }
1683
1684 case4(0300):
1685 break;
1686
1687 case 0310:
1688 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1689 *bytes = 0x67;
1690 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1691 offset += 1;
1692 } else
1693 offset += 0;
1694 break;
1695
1696 case 0311:
1697 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1698 *bytes = 0x67;
1699 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1700 offset += 1;
1701 } else
1702 offset += 0;
1703 break;
1704
1705 case 0312:
1706 break;
1707
1708 case 0313:
1709 ins->rex = 0;
1710 break;
1711
1712 case4(0314):
1713 break;
1714
1715 case 0320:
1716 case 0321:
1717 break;
1718
1719 case 0322:
1720 case 0323:
1721 break;
1722
1723 case 0324:
1724 ins->rex |= REX_W;
1725 break;
1726
1727 case 0325:
1728 break;
1729
1730 case 0326:
1731 break;
1732
1733 case 0330:
1734 *bytes = *codes++ ^ get_cond_opcode(ins->condition);
1735 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1736 offset += 1;
1737 break;
1738
1739 case 0331:
1740 break;
1741
1742 case 0332:
1743 case 0333:
1744 *bytes = c - 0332 + 0xF2;
1745 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1746 offset += 1;
1747 break;
1748
1749 case 0334:
1750 if (ins->rex & REX_R) {
1751 *bytes = 0xF0;
1752 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1753 offset += 1;
1754 }
1755 ins->rex &= ~(REX_L|REX_R);
1756 break;
1757
1758 case 0335:
1759 break;
1760
1761 case 0336:
1762 case 0337:
1763 break;
1764
1765 case 0340:
1766 if (ins->oprs[0].segment != NO_SEG)
1767 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1768 else {
1769 int64_t size = ins->oprs[0].offset;
1770 if (size > 0)
1771 out(offset, segment, NULL,
1772 OUT_RESERVE, size, NO_SEG, NO_SEG);
1773 offset += size;
1774 }
1775 break;
1776
1777 case 0341:
1778 break;
1779
1780 case 0360:
1781 break;
1782
1783 case 0361:
1784 bytes[0] = 0x66;
1785 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1786 offset += 1;
1787 break;
1788
1789 case 0364:
1790 case 0365:
1791 break;
1792
1793 case 0366:
1794 case 0367:
1795 *bytes = c - 0366 + 0x66;
1796 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1797 offset += 1;
1798 break;
1799
1800 case3(0370):
1801 break;
1802
1803 case 0373:
1804 *bytes = bits == 16 ? 3 : 5;
1805 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1806 offset += 1;
1807 break;
1808
1809 case 0374:
1810 eat = EA_XMMVSIB;
1811 break;
1812
1813 case 0375:
1814 eat = EA_YMMVSIB;
1815 break;
1816
1817 case 0376:
1818 eat = EA_ZMMVSIB;
1819 break;
1820
1821 case4(0100):
1822 case4(0110):
1823 case4(0120):
1824 case4(0130):
1825 case4(0200):
1826 case4(0204):
1827 case4(0210):
1828 case4(0214):
1829 case4(0220):
1830 case4(0224):
1831 case4(0230):
1832 case4(0234):
1833 {
1834 ea ea_data;
1835 int rfield;
1836 opflags_t rflags;
1837 uint8_t *p;
1838 int32_t s;
1839 struct operand *opy = &ins->oprs[op2];
1840
1841 if (c <= 0177) {
1842 /* pick rfield from operand b (opx) */
1843 rflags = regflag(opx);
1844 rfield = nasm_regvals[opx->basereg];
1845 } else {
1846 /* rfield is constant */
1847 rflags = 0;
1848 rfield = c & 7;
1849 }
1850
1851 if (process_ea(opy, &ea_data, bits,
1852 rfield, rflags, ins) != eat)
1853 errfunc(ERR_NONFATAL, "invalid effective address");
1854
1855 p = bytes;
1856 *p++ = ea_data.modrm;
1857 if (ea_data.sib_present)
1858 *p++ = ea_data.sib;
1859
1860 s = p - bytes;
1861 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1862
1863 /*
1864 * Make sure the address gets the right offset in case
1865 * the line breaks in the .lst file (BR 1197827)
1866 */
1867 offset += s;
1868 s = 0;
1869
1870 switch (ea_data.bytes) {
1871 case 0:
1872 break;
1873 case 1:
1874 case 2:
1875 case 4:
1876 case 8:
1877 /* use compressed displacement, if available */
1878 data = ea_data.disp8 ? ea_data.disp8 : opy->offset;
1879 s += ea_data.bytes;
1880 if (ea_data.rip) {
1881 if (opy->segment == segment) {
1882 data -= insn_end;
1883 if (overflow_signed(data, ea_data.bytes))
1884 warn_overflow(ERR_PASS2, ea_data.bytes);
1885 out(offset, segment, &data, OUT_ADDRESS,
1886 ea_data.bytes, NO_SEG, NO_SEG);
1887 } else {
1888 /* overflow check in output/linker? */
1889 out(offset, segment, &data, OUT_REL4ADR,
1890 insn_end - offset, opy->segment, opy->wrt);
1891 }
1892 } else {
1893 if (overflow_general(data, ins->addr_size >> 3) ||
1894 signed_bits(data, ins->addr_size) !=
1895 signed_bits(data, ea_data.bytes * 8))
1896 warn_overflow(ERR_PASS2, ea_data.bytes);
1897
1898 out(offset, segment, &data, OUT_ADDRESS,
1899 ea_data.bytes, opy->segment, opy->wrt);
1900 }
1901 break;
1902 default:
1903 /* Impossible! */
1904 errfunc(ERR_PANIC,
1905 "Invalid amount of bytes (%d) for offset?!",
1906 ea_data.bytes);
1907 break;
1908 }
1909 offset += s;
1910 }
1911 break;
1912
1913 default:
1914 errfunc(ERR_PANIC, "internal instruction table corrupt"
1915 ": instruction code \\%o (0x%02X) given", c, c);
1916 break;
1917 }
1918 }
1919 }
1920
1921 static opflags_t regflag(const operand * o)
1922 {
1923 if (!is_register(o->basereg))
1924 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1925 return nasm_reg_flags[o->basereg];
1926 }
1927
1928 static int32_t regval(const operand * o)
1929 {
1930 if (!is_register(o->basereg))
1931 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1932 return nasm_regvals[o->basereg];
1933 }
1934
1935 static int op_rexflags(const operand * o, int mask)
1936 {
1937 opflags_t flags;
1938 int val;
1939
1940 if (!is_register(o->basereg))
1941 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1942
1943 flags = nasm_reg_flags[o->basereg];
1944 val = nasm_regvals[o->basereg];
1945
1946 return rexflags(val, flags, mask);
1947 }
1948
1949 static int rexflags(int val, opflags_t flags, int mask)
1950 {
1951 int rex = 0;
1952
1953 if (val >= 0 && (val & 8))
1954 rex |= REX_B|REX_X|REX_R;
1955 if (flags & BITS64)
1956 rex |= REX_W;
1957 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1958 rex |= REX_H;
1959 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1960 rex |= REX_P;
1961
1962 return rex & mask;
1963 }
1964
1965 static int evexflags(int val, decoflags_t deco,
1966 int mask, uint8_t byte)
1967 {
1968 int evex = 0;
1969
1970 switch (byte) {
1971 case 0:
1972 if (val >= 0 && (val & 16))
1973 evex |= (EVEX_P0RP | EVEX_P0X);
1974 break;
1975 case 2:
1976 if (val >= 0 && (val & 16))
1977 evex |= EVEX_P2VP;
1978 if (deco & Z)
1979 evex |= EVEX_P2Z;
1980 if (deco & OPMASK_MASK)
1981 evex |= deco & EVEX_P2AAA;
1982 break;
1983 }
1984 return evex & mask;
1985 }
1986
1987 static int op_evexflags(const operand * o, int mask, uint8_t byte)
1988 {
1989 int val;
1990
1991 if (!is_register(o->basereg))
1992 errfunc(ERR_PANIC, "invalid operand passed to op_evexflags()");
1993
1994 val = nasm_regvals[o->basereg];
1995
1996 return evexflags(val, o->decoflags, mask, byte);
1997 }
1998
1999 static enum match_result find_match(const struct itemplate **tempp,
2000 insn *instruction,
2001 int32_t segment, int64_t offset, int bits)
2002 {
2003 const struct itemplate *temp;
2004 enum match_result m, merr;
2005 opflags_t xsizeflags[MAX_OPERANDS];
2006 bool opsizemissing = false;
2007 int8_t broadcast = instruction->evex_brerop;
2008 int i;
2009
2010 /* broadcasting uses a different data element size */
2011 for (i = 0; i < instruction->operands; i++)
2012 if (i == broadcast)
2013 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
2014 else
2015 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
2016
2017 merr = MERR_INVALOP;
2018
2019 for (temp = nasm_instructions[instruction->opcode];
2020 temp->opcode != I_none; temp++) {
2021 m = matches(temp, instruction, bits);
2022 if (m == MOK_JUMP) {
2023 if (jmp_match(segment, offset, bits, instruction, temp))
2024 m = MOK_GOOD;
2025 else
2026 m = MERR_INVALOP;
2027 } else if (m == MERR_OPSIZEMISSING && !itemp_has(temp, IF_SX)) {
2028 /*
2029 * Missing operand size and a candidate for fuzzy matching...
2030 */
2031 for (i = 0; i < temp->operands; i++)
2032 if (i == broadcast)
2033 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
2034 else
2035 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
2036 opsizemissing = true;
2037 }
2038 if (m > merr)
2039 merr = m;
2040 if (merr == MOK_GOOD)
2041 goto done;
2042 }
2043
2044 /* No match, but see if we can get a fuzzy operand size match... */
2045 if (!opsizemissing)
2046 goto done;
2047
2048 for (i = 0; i < instruction->operands; i++) {
2049 /*
2050 * We ignore extrinsic operand sizes on registers, so we should
2051 * never try to fuzzy-match on them. This also resolves the case
2052 * when we have e.g. "xmmrm128" in two different positions.
2053 */
2054 if (is_class(REGISTER, instruction->oprs[i].type))
2055 continue;
2056
2057 /* This tests if xsizeflags[i] has more than one bit set */
2058 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2059 goto done; /* No luck */
2060
2061 if (i == broadcast) {
2062 instruction->oprs[i].decoflags |= xsizeflags[i];
2063 instruction->oprs[i].type |= (xsizeflags[i] == BR_BITS32 ?
2064 BITS32 : BITS64);
2065 } else {
2066 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2067 }
2068 }
2069
2070 /* Try matching again... */
2071 for (temp = nasm_instructions[instruction->opcode];
2072 temp->opcode != I_none; temp++) {
2073 m = matches(temp, instruction, bits);
2074 if (m == MOK_JUMP) {
2075 if (jmp_match(segment, offset, bits, instruction, temp))
2076 m = MOK_GOOD;
2077 else
2078 m = MERR_INVALOP;
2079 }
2080 if (m > merr)
2081 merr = m;
2082 if (merr == MOK_GOOD)
2083 goto done;
2084 }
2085
2086 done:
2087 *tempp = temp;
2088 return merr;
2089 }
2090
2091 static enum match_result matches(const struct itemplate *itemp,
2092 insn *instruction, int bits)
2093 {
2094 opflags_t size[MAX_OPERANDS], asize;
2095 bool opsizemissing = false;
2096 int i, oprs;
2097
2098 /*
2099 * Check the opcode
2100 */
2101 if (itemp->opcode != instruction->opcode)
2102 return MERR_INVALOP;
2103
2104 /*
2105 * Count the operands
2106 */
2107 if (itemp->operands != instruction->operands)
2108 return MERR_INVALOP;
2109
2110 /*
2111 * Is it legal?
2112 */
2113 if (!(optimizing > 0) && itemp_has(itemp, IF_OPT))
2114 return MERR_INVALOP;
2115
2116 /*
2117 * {evex} available?
2118 */
2119 switch (instruction->prefixes[PPS_VEX]) {
2120 case P_EVEX:
2121 if (!itemp_has(itemp, IF_EVEX))
2122 return MERR_ENCMISMATCH;
2123 break;
2124 case P_VEX3:
2125 case P_VEX2:
2126 if (!itemp_has(itemp, IF_VEX))
2127 return MERR_ENCMISMATCH;
2128 break;
2129 default:
2130 break;
2131 }
2132
2133 /*
2134 * Check that no spurious colons or TOs are present
2135 */
2136 for (i = 0; i < itemp->operands; i++)
2137 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2138 return MERR_INVALOP;
2139
2140 /*
2141 * Process size flags
2142 */
2143 switch (itemp_smask(itemp)) {
2144 case IF_GENBIT(IF_SB):
2145 asize = BITS8;
2146 break;
2147 case IF_GENBIT(IF_SW):
2148 asize = BITS16;
2149 break;
2150 case IF_GENBIT(IF_SD):
2151 asize = BITS32;
2152 break;
2153 case IF_GENBIT(IF_SQ):
2154 asize = BITS64;
2155 break;
2156 case IF_GENBIT(IF_SO):
2157 asize = BITS128;
2158 break;
2159 case IF_GENBIT(IF_SY):
2160 asize = BITS256;
2161 break;
2162 case IF_GENBIT(IF_SZ):
2163 asize = BITS512;
2164 break;
2165 case IF_GENBIT(IF_SIZE):
2166 switch (bits) {
2167 case 16:
2168 asize = BITS16;
2169 break;
2170 case 32:
2171 asize = BITS32;
2172 break;
2173 case 64:
2174 asize = BITS64;
2175 break;
2176 default:
2177 asize = 0;
2178 break;
2179 }
2180 break;
2181 default:
2182 asize = 0;
2183 break;
2184 }
2185
2186 if (itemp_armask(itemp)) {
2187 /* S- flags only apply to a specific operand */
2188 i = itemp_arg(itemp);
2189 memset(size, 0, sizeof size);
2190 size[i] = asize;
2191 } else {
2192 /* S- flags apply to all operands */
2193 for (i = 0; i < MAX_OPERANDS; i++)
2194 size[i] = asize;
2195 }
2196
2197 /*
2198 * Check that the operand flags all match up,
2199 * it's a bit tricky so lets be verbose:
2200 *
2201 * 1) Find out the size of operand. If instruction
2202 * doesn't have one specified -- we're trying to
2203 * guess it either from template (IF_S* flag) or
2204 * from code bits.
2205 *
2206 * 2) If template operand do not match the instruction OR
2207 * template has an operand size specified AND this size differ
2208 * from which instruction has (perhaps we got it from code bits)
2209 * we are:
2210 * a) Check that only size of instruction and operand is differ
2211 * other characteristics do match
2212 * b) Perhaps it's a register specified in instruction so
2213 * for such a case we just mark that operand as "size
2214 * missing" and this will turn on fuzzy operand size
2215 * logic facility (handled by a caller)
2216 */
2217 for (i = 0; i < itemp->operands; i++) {
2218 opflags_t type = instruction->oprs[i].type;
2219 decoflags_t deco = instruction->oprs[i].decoflags;
2220 bool is_broadcast = deco & BRDCAST_MASK;
2221 uint8_t brcast_num = 0;
2222 opflags_t template_opsize, insn_opsize;
2223
2224 if (!(type & SIZE_MASK))
2225 type |= size[i];
2226
2227 insn_opsize = type & SIZE_MASK;
2228 if (!is_broadcast) {
2229 template_opsize = itemp->opd[i] & SIZE_MASK;
2230 } else {
2231 decoflags_t deco_brsize = itemp->deco[i] & BRSIZE_MASK;
2232 /*
2233 * when broadcasting, the element size depends on
2234 * the instruction type. decorator flag should match.
2235 */
2236
2237 if (deco_brsize) {
2238 template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
2239 /* calculate the proper number : {1to<brcast_num>} */
2240 brcast_num = (itemp->opd[i] & SIZE_MASK) / BITS128 *
2241 BITS64 / template_opsize * 2;
2242 } else {
2243 template_opsize = 0;
2244 }
2245 }
2246
2247 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2248 (deco & ~itemp->deco[i] & ~BRNUM_MASK)) {
2249 return MERR_INVALOP;
2250 } else if (template_opsize) {
2251 if (template_opsize != insn_opsize) {
2252 if (insn_opsize) {
2253 return MERR_INVALOP;
2254 } else if (!is_class(REGISTER, type)) {
2255 /*
2256 * Note: we don't honor extrinsic operand sizes for registers,
2257 * so "missing operand size" for a register should be
2258 * considered a wildcard match rather than an error.
2259 */
2260 opsizemissing = true;
2261 }
2262 } else if (is_broadcast &&
2263 (brcast_num !=
2264 (8U << ((deco & BRNUM_MASK) >> BRNUM_SHIFT)))) {
2265 /*
2266 * broadcasting opsize matches but the number of repeated memory
2267 * element does not match.
2268 * if 64b double precision float is broadcasted to zmm (512b),
2269 * broadcasting decorator must be {1to8}.
2270 */
2271 return MERR_BRNUMMISMATCH;
2272 }
2273 }
2274 }
2275
2276 if (opsizemissing)
2277 return MERR_OPSIZEMISSING;
2278
2279 /*
2280 * Check operand sizes
2281 */
2282 if (itemp_has(itemp, IF_SM) || itemp_has(itemp, IF_SM2)) {
2283 oprs = (itemp_has(itemp, IF_SM2) ? 2 : itemp->operands);
2284 for (i = 0; i < oprs; i++) {
2285 asize = itemp->opd[i] & SIZE_MASK;
2286 if (asize) {
2287 for (i = 0; i < oprs; i++)
2288 size[i] = asize;
2289 break;
2290 }
2291 }
2292 } else {
2293 oprs = itemp->operands;
2294 }
2295
2296 for (i = 0; i < itemp->operands; i++) {
2297 if (!(itemp->opd[i] & SIZE_MASK) &&
2298 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2299 return MERR_OPSIZEMISMATCH;
2300 }
2301
2302 /*
2303 * Check template is okay at the set cpu level
2304 */
2305 if (iflag_cmp_cpu_level(&insns_flags[itemp->iflag_idx], &cpu) > 0)
2306 return MERR_BADCPU;
2307
2308 /*
2309 * Verify the appropriate long mode flag.
2310 */
2311 if (itemp_has(itemp, (bits == 64 ? IF_NOLONG : IF_LONG)))
2312 return MERR_BADMODE;
2313
2314 /*
2315 * If we have a HLE prefix, look for the NOHLE flag
2316 */
2317 if (itemp_has(itemp, IF_NOHLE) &&
2318 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2319 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2320 return MERR_BADHLE;
2321
2322 /*
2323 * Check if special handling needed for Jumps
2324 */
2325 if ((itemp->code[0] & ~1) == 0370)
2326 return MOK_JUMP;
2327
2328 /*
2329 * Check if BND prefix is allowed
2330 */
2331 if (!itemp_has(itemp, IF_BND) &&
2332 has_prefix(instruction, PPS_REP, P_BND))
2333 return MERR_BADBND;
2334
2335 return MOK_GOOD;
2336 }
2337
2338 /*
2339 * Check if ModR/M.mod should/can be 01.
2340 * - EAF_BYTEOFFS is set
2341 * - offset can fit in a byte when EVEX is not used
2342 * - offset can be compressed when EVEX is used
2343 */
2344 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2345 (o >= -128 && o <= 127 && \
2346 seg == NO_SEG && !forw_ref && \
2347 !(input->eaflags & EAF_WORDOFFS) && \
2348 !(ins->rex & REX_EV)) || \
2349 (ins->rex & REX_EV && \
2350 is_disp8n(input, ins, &output->disp8)))
2351
2352 static enum ea_type process_ea(operand *input, ea *output, int bits,
2353 int rfield, opflags_t rflags, insn *ins)
2354 {
2355 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2356 int addrbits = ins->addr_size;
2357
2358 output->type = EA_SCALAR;
2359 output->rip = false;
2360 output->disp8 = 0;
2361
2362 /* REX flags for the rfield operand */
2363 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2364 /* EVEX.R' flag for the REG operand */
2365 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2366
2367 if (is_class(REGISTER, input->type)) {
2368 /*
2369 * It's a direct register.
2370 */
2371 if (!is_register(input->basereg))
2372 goto err;
2373
2374 if (!is_reg_class(REG_EA, input->basereg))
2375 goto err;
2376
2377 /* broadcasting is not available with a direct register operand. */
2378 if (input->decoflags & BRDCAST_MASK) {
2379 nasm_error(ERR_NONFATAL, "Broadcasting not allowed from a register");
2380 goto err;
2381 }
2382
2383 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2384 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2385 output->sib_present = false; /* no SIB necessary */
2386 output->bytes = 0; /* no offset necessary either */
2387 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2388 } else {
2389 /*
2390 * It's a memory reference.
2391 */
2392
2393 /* Embedded rounding or SAE is not available with a mem ref operand. */
2394 if (input->decoflags & (ER | SAE)) {
2395 nasm_error(ERR_NONFATAL,
2396 "Embedded rounding is available only with reg-reg op.");
2397 return -1;
2398 }
2399
2400 if (input->basereg == -1 &&
2401 (input->indexreg == -1 || input->scale == 0)) {
2402 /*
2403 * It's a pure offset.
2404 */
2405 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2406 input->segment == NO_SEG) {
2407 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2408 input->type &= ~IP_REL;
2409 input->type |= MEMORY;
2410 }
2411
2412 if (input->eaflags & EAF_BYTEOFFS ||
2413 (input->eaflags & EAF_WORDOFFS &&
2414 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2415 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2416 }
2417
2418 if (bits == 64 && (~input->type & IP_REL)) {
2419 output->sib_present = true;
2420 output->sib = GEN_SIB(0, 4, 5);
2421 output->bytes = 4;
2422 output->modrm = GEN_MODRM(0, rfield, 4);
2423 output->rip = false;
2424 } else {
2425 output->sib_present = false;
2426 output->bytes = (addrbits != 16 ? 4 : 2);
2427 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2428 output->rip = bits == 64;
2429 }
2430 } else {
2431 /*
2432 * It's an indirection.
2433 */
2434 int i = input->indexreg, b = input->basereg, s = input->scale;
2435 int32_t seg = input->segment;
2436 int hb = input->hintbase, ht = input->hinttype;
2437 int t, it, bt; /* register numbers */
2438 opflags_t x, ix, bx; /* register flags */
2439
2440 if (s == 0)
2441 i = -1; /* make this easy, at least */
2442
2443 if (is_register(i)) {
2444 it = nasm_regvals[i];
2445 ix = nasm_reg_flags[i];
2446 } else {
2447 it = -1;
2448 ix = 0;
2449 }
2450
2451 if (is_register(b)) {
2452 bt = nasm_regvals[b];
2453 bx = nasm_reg_flags[b];
2454 } else {
2455 bt = -1;
2456 bx = 0;
2457 }
2458
2459 /* if either one are a vector register... */
2460 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2461 opflags_t sok = BITS32 | BITS64;
2462 int32_t o = input->offset;
2463 int mod, scale, index, base;
2464
2465 /*
2466 * For a vector SIB, one has to be a vector and the other,
2467 * if present, a GPR. The vector must be the index operand.
2468 */
2469 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2470 if (s == 0)
2471 s = 1;
2472 else if (s != 1)
2473 goto err;
2474
2475 t = bt, bt = it, it = t;
2476 x = bx, bx = ix, ix = x;
2477 }
2478
2479 if (bt != -1) {
2480 if (REG_GPR & ~bx)
2481 goto err;
2482 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2483 sok &= bx;
2484 else
2485 goto err;
2486 }
2487
2488 /*
2489 * While we're here, ensure the user didn't specify
2490 * WORD or QWORD
2491 */
2492 if (input->disp_size == 16 || input->disp_size == 64)
2493 goto err;
2494
2495 if (addrbits == 16 ||
2496 (addrbits == 32 && !(sok & BITS32)) ||
2497 (addrbits == 64 && !(sok & BITS64)))
2498 goto err;
2499
2500 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2501 : ((ix & YMMREG & ~REG_EA)
2502 ? EA_YMMVSIB : EA_XMMVSIB));
2503
2504 output->rex |= rexflags(it, ix, REX_X);
2505 output->rex |= rexflags(bt, bx, REX_B);
2506 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2507
2508 index = it & 7; /* it is known to be != -1 */
2509
2510 switch (s) {
2511 case 1:
2512 scale = 0;
2513 break;
2514 case 2:
2515 scale = 1;
2516 break;
2517 case 4:
2518 scale = 2;
2519 break;
2520 case 8:
2521 scale = 3;
2522 break;
2523 default: /* then what the smeg is it? */
2524 goto err; /* panic */
2525 }
2526
2527 if (bt == -1) {
2528 base = 5;
2529 mod = 0;
2530 } else {
2531 base = (bt & 7);
2532 if (base != REG_NUM_EBP && o == 0 &&
2533 seg == NO_SEG && !forw_ref &&
2534 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2535 mod = 0;
2536 else if (IS_MOD_01())
2537 mod = 1;
2538 else
2539 mod = 2;
2540 }
2541
2542 output->sib_present = true;
2543 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2544 output->modrm = GEN_MODRM(mod, rfield, 4);
2545 output->sib = GEN_SIB(scale, index, base);
2546 } else if ((ix|bx) & (BITS32|BITS64)) {
2547 /*
2548 * it must be a 32/64-bit memory reference. Firstly we have
2549 * to check that all registers involved are type E/Rxx.
2550 */
2551 opflags_t sok = BITS32 | BITS64;
2552 int32_t o = input->offset;
2553
2554 if (it != -1) {
2555 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2556 sok &= ix;
2557 else
2558 goto err;
2559 }
2560
2561 if (bt != -1) {
2562 if (REG_GPR & ~bx)
2563 goto err; /* Invalid register */
2564 if (~sok & bx & SIZE_MASK)
2565 goto err; /* Invalid size */
2566 sok &= bx;
2567 }
2568
2569 /*
2570 * While we're here, ensure the user didn't specify
2571 * WORD or QWORD
2572 */
2573 if (input->disp_size == 16 || input->disp_size == 64)
2574 goto err;
2575
2576 if (addrbits == 16 ||
2577 (addrbits == 32 && !(sok & BITS32)) ||
2578 (addrbits == 64 && !(sok & BITS64)))
2579 goto err;
2580
2581 /* now reorganize base/index */
2582 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2583 ((hb == b && ht == EAH_NOTBASE) ||
2584 (hb == i && ht == EAH_MAKEBASE))) {
2585 /* swap if hints say so */
2586 t = bt, bt = it, it = t;
2587 x = bx, bx = ix, ix = x;
2588 }
2589 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2590 bt = -1, bx = 0, s++;
2591 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
2592 /* make single reg base, unless hint */
2593 bt = it, bx = ix, it = -1, ix = 0;
2594 }
2595 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2596 s == 3 || s == 5 || s == 9) && bt == -1)
2597 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2598 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2599 (input->eaflags & EAF_TIMESTWO))
2600 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2601 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2602 if (s == 1 && it == REG_NUM_ESP) {
2603 /* swap ESP into base if scale is 1 */
2604 t = it, it = bt, bt = t;
2605 x = ix, ix = bx, bx = x;
2606 }
2607 if (it == REG_NUM_ESP ||
2608 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2609 goto err; /* wrong, for various reasons */
2610
2611 output->rex |= rexflags(it, ix, REX_X);
2612 output->rex |= rexflags(bt, bx, REX_B);
2613
2614 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2615 /* no SIB needed */
2616 int mod, rm;
2617
2618 if (bt == -1) {
2619 rm = 5;
2620 mod = 0;
2621 } else {
2622 rm = (bt & 7);
2623 if (rm != REG_NUM_EBP && o == 0 &&
2624 seg == NO_SEG && !forw_ref &&
2625 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2626 mod = 0;
2627 else if (IS_MOD_01())
2628 mod = 1;
2629 else
2630 mod = 2;
2631 }
2632
2633 output->sib_present = false;
2634 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2635 output->modrm = GEN_MODRM(mod, rfield, rm);
2636 } else {
2637 /* we need a SIB */
2638 int mod, scale, index, base;
2639
2640 if (it == -1)
2641 index = 4, s = 1;
2642 else
2643 index = (it & 7);
2644
2645 switch (s) {
2646 case 1:
2647 scale = 0;
2648 break;
2649 case 2:
2650 scale = 1;
2651 break;
2652 case 4:
2653 scale = 2;
2654 break;
2655 case 8:
2656 scale = 3;
2657 break;
2658 default: /* then what the smeg is it? */
2659 goto err; /* panic */
2660 }
2661
2662 if (bt == -1) {
2663 base = 5;
2664 mod = 0;
2665 } else {
2666 base = (bt & 7);
2667 if (base != REG_NUM_EBP && o == 0 &&
2668 seg == NO_SEG && !forw_ref &&
2669 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2670 mod = 0;
2671 else if (IS_MOD_01())
2672 mod = 1;
2673 else
2674 mod = 2;
2675 }
2676
2677 output->sib_present = true;
2678 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2679 output->modrm = GEN_MODRM(mod, rfield, 4);
2680 output->sib = GEN_SIB(scale, index, base);
2681 }
2682 } else { /* it's 16-bit */
2683 int mod, rm;
2684 int16_t o = input->offset;
2685
2686 /* check for 64-bit long mode */
2687 if (addrbits == 64)
2688 goto err;
2689
2690 /* check all registers are BX, BP, SI or DI */
2691 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2692 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2693 goto err;
2694
2695 /* ensure the user didn't specify DWORD/QWORD */
2696 if (input->disp_size == 32 || input->disp_size == 64)
2697 goto err;
2698
2699 if (s != 1 && i != -1)
2700 goto err; /* no can do, in 16-bit EA */
2701 if (b == -1 && i != -1) {
2702 int tmp = b;
2703 b = i;
2704 i = tmp;
2705 } /* swap */
2706 if ((b == R_SI || b == R_DI) && i != -1) {
2707 int tmp = b;
2708 b = i;
2709 i = tmp;
2710 }
2711 /* have BX/BP as base, SI/DI index */
2712 if (b == i)
2713 goto err; /* shouldn't ever happen, in theory */
2714 if (i != -1 && b != -1 &&
2715 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2716 goto err; /* invalid combinations */
2717 if (b == -1) /* pure offset: handled above */
2718 goto err; /* so if it gets to here, panic! */
2719
2720 rm = -1;
2721 if (i != -1)
2722 switch (i * 256 + b) {
2723 case R_SI * 256 + R_BX:
2724 rm = 0;
2725 break;
2726 case R_DI * 256 + R_BX:
2727 rm = 1;
2728 break;
2729 case R_SI * 256 + R_BP:
2730 rm = 2;
2731 break;
2732 case R_DI * 256 + R_BP:
2733 rm = 3;
2734 break;
2735 } else
2736 switch (b) {
2737 case R_SI:
2738 rm = 4;
2739 break;
2740 case R_DI:
2741 rm = 5;
2742 break;
2743 case R_BP:
2744 rm = 6;
2745 break;
2746 case R_BX:
2747 rm = 7;
2748 break;
2749 }
2750 if (rm == -1) /* can't happen, in theory */
2751 goto err; /* so panic if it does */
2752
2753 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2754 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2755 mod = 0;
2756 else if (IS_MOD_01())
2757 mod = 1;
2758 else
2759 mod = 2;
2760
2761 output->sib_present = false; /* no SIB - it's 16-bit */
2762 output->bytes = mod; /* bytes of offset needed */
2763 output->modrm = GEN_MODRM(mod, rfield, rm);
2764 }
2765 }
2766 }
2767
2768 output->size = 1 + output->sib_present + output->bytes;
2769 return output->type;
2770
2771 err:
2772 return output->type = EA_INVALID;
2773 }
2774
2775 static void add_asp(insn *ins, int addrbits)
2776 {
2777 int j, valid;
2778 int defdisp;
2779
2780 valid = (addrbits == 64) ? 64|32 : 32|16;
2781
2782 switch (ins->prefixes[PPS_ASIZE]) {
2783 case P_A16:
2784 valid &= 16;
2785 break;
2786 case P_A32:
2787 valid &= 32;
2788 break;
2789 case P_A64:
2790 valid &= 64;
2791 break;
2792 case P_ASP:
2793 valid &= (addrbits == 32) ? 16 : 32;
2794 break;
2795 default:
2796 break;
2797 }
2798
2799 for (j = 0; j < ins->operands; j++) {
2800 if (is_class(MEMORY, ins->oprs[j].type)) {
2801 opflags_t i, b;
2802
2803 /* Verify as Register */
2804 if (!is_register(ins->oprs[j].indexreg))
2805 i = 0;
2806 else
2807 i = nasm_reg_flags[ins->oprs[j].indexreg];
2808
2809 /* Verify as Register */
2810 if (!is_register(ins->oprs[j].basereg))
2811 b = 0;
2812 else
2813 b = nasm_reg_flags[ins->oprs[j].basereg];
2814
2815 if (ins->oprs[j].scale == 0)
2816 i = 0;
2817
2818 if (!i && !b) {
2819 int ds = ins->oprs[j].disp_size;
2820 if ((addrbits != 64 && ds > 8) ||
2821 (addrbits == 64 && ds == 16))
2822 valid &= ds;
2823 } else {
2824 if (!(REG16 & ~b))
2825 valid &= 16;
2826 if (!(REG32 & ~b))
2827 valid &= 32;
2828 if (!(REG64 & ~b))
2829 valid &= 64;
2830
2831 if (!(REG16 & ~i))
2832 valid &= 16;
2833 if (!(REG32 & ~i))
2834 valid &= 32;
2835 if (!(REG64 & ~i))
2836 valid &= 64;
2837 }
2838 }
2839 }
2840
2841 if (valid & addrbits) {
2842 ins->addr_size = addrbits;
2843 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2844 /* Add an address size prefix */
2845 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2846 ins->addr_size = (addrbits == 32) ? 16 : 32;
2847 } else {
2848 /* Impossible... */
2849 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2850 ins->addr_size = addrbits; /* Error recovery */
2851 }
2852
2853 defdisp = ins->addr_size == 16 ? 16 : 32;
2854
2855 for (j = 0; j < ins->operands; j++) {
2856 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2857 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2858 /*
2859 * mem_offs sizes must match the address size; if not,
2860 * strip the MEM_OFFS bit and match only EA instructions
2861 */
2862 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2863 }
2864 }
2865 }
The Netwide Assembler