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assemble: Use case3/4 where appropriate
[nasm.git] / assemble.c
blob76b147faa3845859c9618d42fd55408e8d3b1e3a
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2012 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \20..\23 - a byte immediate operand, from operand 0..3
46 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
47 * \30..\33 - a word immediate operand, from operand 0..3
48 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
49 * assembly mode or the operand-size override on the operand
50 * \40..\43 - a long immediate operand, from operand 0..3
51 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
52 * depending on the address size of the instruction.
53 * \50..\53 - a byte relative operand, from operand 0..3
54 * \54..\57 - a qword immediate operand, from operand 0..3
55 * \60..\63 - a word relative operand, from operand 0..3
56 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
57 * assembly mode or the operand-size override on the operand
58 * \70..\73 - a long relative operand, from operand 0..3
59 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
60 * \1ab - a ModRM, calculated on EA in operand a, with the spare
61 * field the register value of operand b.
62 * \172\ab - the register number from operand a in bits 7..4, with
63 * the 4-bit immediate from operand b in bits 3..0.
64 * \173\xab - the register number from operand a in bits 7..4, with
65 * the value b in bits 3..0.
66 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
67 * an arbitrary value in bits 3..0 (assembled as zero.)
68 * \2ab - a ModRM, calculated on EA in operand a, with the spare
69 * field equal to digit b.
70 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
71 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
72 * V field taken from operand 0..3.
73 * \270 - this instruction uses VEX/XOP rather than REX, with the
74 * V field set to 1111b.
75 *
76 * VEX/XOP prefixes are followed by the sequence:
77 * \tmm\wlp where mm is the M field; and wlp is:
78 * 00 wwl lpp
79 * [l0] ll = 0 for L = 0 (.128, .lz)
80 * [l1] ll = 1 for L = 1 (.256)
81 * [lig] ll = 2 for L don't care (always assembled as 0)
82 *
83 * [w0] ww = 0 for W = 0
84 * [w1 ] ww = 1 for W = 1
85 * [wig] ww = 2 for W don't care (always assembled as 0)
86 * [ww] ww = 3 for W used as REX.W
87 *
88 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
89 *
90 * \271 - instruction takes XRELEASE (F3) with or without lock
91 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
92 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
93 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
94 * to the operand size (if o16/o32/o64 present) or the bit size
95 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
96 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
97 * \312 - (disassembler only) invalid with non-default address size.
98 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
99 * \314 - (disassembler only) invalid with REX.B
100 * \315 - (disassembler only) invalid with REX.X
101 * \316 - (disassembler only) invalid with REX.R
102 * \317 - (disassembler only) invalid with REX.W
103 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
104 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
105 * \322 - indicates that this instruction is only valid when the
106 * operand size is the default (instruction to disassembler,
107 * generates no code in the assembler)
108 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
109 * \324 - indicates 64-bit operand size requiring REX prefix.
110 * \325 - instruction which always uses spl/bpl/sil/dil
111 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
112 disassembler only; for SSE instructions.
113 * \330 - a literal byte follows in the code stream, to be added
114 * to the condition code value of the instruction.
115 * \331 - instruction not valid with REP prefix. Hint for
116 * disassembler only; for SSE instructions.
117 * \332 - REP prefix (0xF2 byte) used as opcode extension.
118 * \333 - REP prefix (0xF3 byte) used as opcode extension.
119 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
120 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
121 * \336 - force a REP(E) prefix (0xF3) even if not specified.
122 * \337 - force a REPNE prefix (0xF2) even if not specified.
123 * \336-\337 are still listed as prefixes in the disassembler.
124 * \340 - reserve <operand 0> bytes of uninitialized storage.
125 * Operand 0 had better be a segmentless constant.
126 * \341 - this instruction needs a WAIT "prefix"
127 * \344,\345 - the PUSH/POP (respectively) codes for CS, DS, ES, SS
128 * (POP is never used for CS) depending on operand 0
129 * \346,\347 - the second byte of PUSH/POP codes for FS, GS, depending
130 * on operand 0
131 * \360 - no SSE prefix (== \364\331)
132 * \361 - 66 SSE prefix (== \366\331)
133 * \362 - F2 SSE prefix (== \364\332)
134 * \363 - F3 SSE prefix (== \364\333)
135 * \364 - operand-size prefix (0x66) not permitted
136 * \365 - address-size prefix (0x67) not permitted
137 * \366 - operand-size prefix (0x66) used as opcode extension
138 * \367 - address-size prefix (0x67) used as opcode extension
139 * \370,\371 - match only if operand 0 meets byte jump criteria.
140 * 370 is used for Jcc, 371 is used for JMP.
141 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
142 * used for conditional jump over longer jump
143 * \374 - this instruction takes an XMM VSIB memory EA
144 * \375 - this instruction takes an YMM VSIB memory EA
145 */
146
147 #include "compiler.h"
148
149 #include <stdio.h>
150 #include <string.h>
151 #include <inttypes.h>
152
153 #include "nasm.h"
154 #include "nasmlib.h"
155 #include "assemble.h"
156 #include "insns.h"
157 #include "tables.h"
158
159 enum match_result {
160 /*
161 * Matching errors. These should be sorted so that more specific
162 * errors come later in the sequence.
163 */
164 MERR_INVALOP,
165 MERR_OPSIZEMISSING,
166 MERR_OPSIZEMISMATCH,
167 MERR_BADCPU,
168 MERR_BADMODE,
169 MERR_BADHLE,
170 /*
171 * Matching success; the conditional ones first
172 */
173 MOK_JUMP, /* Matching OK but needs jmp_match() */
174 MOK_GOOD /* Matching unconditionally OK */
175 };
176
177 typedef struct {
178 enum ea_type type; /* what kind of EA is this? */
179 int sib_present; /* is a SIB byte necessary? */
180 int bytes; /* # of bytes of offset needed */
181 int size; /* lazy - this is sib+bytes+1 */
182 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
183 } ea;
184
185 #define GEN_SIB(scale, index, base) \
186 (((scale) << 6) | ((index) << 3) | ((base)))
187
188 #define GEN_MODRM(mod, reg, rm) \
189 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
190
191 static uint32_t cpu; /* cpu level received from nasm.c */
192 static efunc errfunc;
193 static struct ofmt *outfmt;
194 static ListGen *list;
195
196 static int64_t calcsize(int32_t, int64_t, int, insn *,
197 const struct itemplate *);
198 static void gencode(int32_t segment, int64_t offset, int bits,
199 insn * ins, const struct itemplate *temp,
200 int64_t insn_end);
201 static enum match_result find_match(const struct itemplate **tempp,
202 insn *instruction,
203 int32_t segment, int64_t offset, int bits);
204 static enum match_result matches(const struct itemplate *, insn *, int bits);
205 static opflags_t regflag(const operand *);
206 static int32_t regval(const operand *);
207 static int rexflags(int, opflags_t, int);
208 static int op_rexflags(const operand *, int);
209 static void add_asp(insn *, int);
210
211 static enum ea_type process_ea(operand *, ea *, int, int, int, opflags_t);
212
213 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
214 {
215 return ins->prefixes[pos] == prefix;
216 }
217
218 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
219 {
220 if (ins->prefixes[pos])
221 errfunc(ERR_NONFATAL, "invalid %s prefix",
222 prefix_name(ins->prefixes[pos]));
223 }
224
225 static const char *size_name(int size)
226 {
227 switch (size) {
228 case 1:
229 return "byte";
230 case 2:
231 return "word";
232 case 4:
233 return "dword";
234 case 8:
235 return "qword";
236 case 10:
237 return "tword";
238 case 16:
239 return "oword";
240 case 32:
241 return "yword";
242 default:
243 return "???";
244 }
245 }
246
247 static void warn_overflow(int pass, int size)
248 {
249 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
250 "%s data exceeds bounds", size_name(size));
251 }
252
253 static void warn_overflow_const(int64_t data, int size)
254 {
255 if (overflow_general(data, size))
256 warn_overflow(ERR_PASS1, size);
257 }
258
259 static void warn_overflow_opd(const struct operand *o, int size)
260 {
261 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
262 if (overflow_general(o->offset, size))
263 warn_overflow(ERR_PASS2, size);
264 }
265 }
266
267 /*
268 * This routine wrappers the real output format's output routine,
269 * in order to pass a copy of the data off to the listing file
270 * generator at the same time.
271 */
272 static void out(int64_t offset, int32_t segto, const void *data,
273 enum out_type type, uint64_t size,
274 int32_t segment, int32_t wrt)
275 {
276 static int32_t lineno = 0; /* static!!! */
277 static char *lnfname = NULL;
278 uint8_t p[8];
279
280 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
281 /*
282 * This is a non-relocated address, and we're going to
283 * convert it into RAWDATA format.
284 */
285 uint8_t *q = p;
286
287 if (size > 8) {
288 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
289 return;
290 }
291
292 WRITEADDR(q, *(int64_t *)data, size);
293 data = p;
294 type = OUT_RAWDATA;
295 }
296
297 list->output(offset, data, type, size);
298
299 /*
300 * this call to src_get determines when we call the
301 * debug-format-specific "linenum" function
302 * it updates lineno and lnfname to the current values
303 * returning 0 if "same as last time", -2 if lnfname
304 * changed, and the amount by which lineno changed,
305 * if it did. thus, these variables must be static
306 */
307
308 if (src_get(&lineno, &lnfname))
309 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
310
311 outfmt->output(segto, data, type, size, segment, wrt);
312 }
313
314 static void out_imm8(int64_t offset, int32_t segment, struct operand *opx)
315 {
316 if (opx->segment != NO_SEG) {
317 uint64_t data = opx->offset;
318 out(offset, segment, &data, OUT_ADDRESS, 1, opx->segment, opx->wrt);
319 } else {
320 uint8_t byte = opx->offset;
321 out(offset, segment, &byte, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
322 }
323 }
324
325 static bool jmp_match(int32_t segment, int64_t offset, int bits,
326 insn * ins, const struct itemplate *temp)
327 {
328 int64_t isize;
329 const uint8_t *code = temp->code;
330 uint8_t c = code[0];
331
332 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
333 return false;
334 if (!optimizing)
335 return false;
336 if (optimizing < 0 && c == 0371)
337 return false;
338
339 isize = calcsize(segment, offset, bits, ins, temp);
340
341 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
342 /* Be optimistic in pass 1 */
343 return true;
344
345 if (ins->oprs[0].segment != segment)
346 return false;
347
348 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
349 return (isize >= -128 && isize <= 127); /* is it byte size? */
350 }
351
352 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
353 insn * instruction, struct ofmt *output, efunc error,
354 ListGen * listgen)
355 {
356 const struct itemplate *temp;
357 int j;
358 enum match_result m;
359 int64_t insn_end;
360 int32_t itimes;
361 int64_t start = offset;
362 int64_t wsize; /* size for DB etc. */
363
364 errfunc = error; /* to pass to other functions */
365 cpu = cp;
366 outfmt = output; /* likewise */
367 list = listgen; /* and again */
368
369 wsize = idata_bytes(instruction->opcode);
370 if (wsize == -1)
371 return 0;
372
373 if (wsize) {
374 extop *e;
375 int32_t t = instruction->times;
376 if (t < 0)
377 errfunc(ERR_PANIC,
378 "instruction->times < 0 (%ld) in assemble()", t);
379
380 while (t--) { /* repeat TIMES times */
381 list_for_each(e, instruction->eops) {
382 if (e->type == EOT_DB_NUMBER) {
383 if (wsize > 8) {
384 errfunc(ERR_NONFATAL,
385 "integer supplied to a DT, DO or DY"
386 " instruction");
387 } else {
388 out(offset, segment, &e->offset,
389 OUT_ADDRESS, wsize, e->segment, e->wrt);
390 offset += wsize;
391 }
392 } else if (e->type == EOT_DB_STRING ||
393 e->type == EOT_DB_STRING_FREE) {
394 int align;
395
396 out(offset, segment, e->stringval,
397 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
398 align = e->stringlen % wsize;
399
400 if (align) {
401 align = wsize - align;
402 out(offset, segment, zero_buffer,
403 OUT_RAWDATA, align, NO_SEG, NO_SEG);
404 }
405 offset += e->stringlen + align;
406 }
407 }
408 if (t > 0 && t == instruction->times - 1) {
409 /*
410 * Dummy call to list->output to give the offset to the
411 * listing module.
412 */
413 list->output(offset, NULL, OUT_RAWDATA, 0);
414 list->uplevel(LIST_TIMES);
415 }
416 }
417 if (instruction->times > 1)
418 list->downlevel(LIST_TIMES);
419 return offset - start;
420 }
421
422 if (instruction->opcode == I_INCBIN) {
423 const char *fname = instruction->eops->stringval;
424 FILE *fp;
425
426 fp = fopen(fname, "rb");
427 if (!fp) {
428 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
429 fname);
430 } else if (fseek(fp, 0L, SEEK_END) < 0) {
431 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
432 fname);
433 } else {
434 static char buf[4096];
435 size_t t = instruction->times;
436 size_t base = 0;
437 size_t len;
438
439 len = ftell(fp);
440 if (instruction->eops->next) {
441 base = instruction->eops->next->offset;
442 len -= base;
443 if (instruction->eops->next->next &&
444 len > (size_t)instruction->eops->next->next->offset)
445 len = (size_t)instruction->eops->next->next->offset;
446 }
447 /*
448 * Dummy call to list->output to give the offset to the
449 * listing module.
450 */
451 list->output(offset, NULL, OUT_RAWDATA, 0);
452 list->uplevel(LIST_INCBIN);
453 while (t--) {
454 size_t l;
455
456 fseek(fp, base, SEEK_SET);
457 l = len;
458 while (l > 0) {
459 int32_t m;
460 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
461 if (!m) {
462 /*
463 * This shouldn't happen unless the file
464 * actually changes while we are reading
465 * it.
466 */
467 error(ERR_NONFATAL,
468 "`incbin': unexpected EOF while"
469 " reading file `%s'", fname);
470 t = 0; /* Try to exit cleanly */
471 break;
472 }
473 out(offset, segment, buf, OUT_RAWDATA, m,
474 NO_SEG, NO_SEG);
475 l -= m;
476 }
477 }
478 list->downlevel(LIST_INCBIN);
479 if (instruction->times > 1) {
480 /*
481 * Dummy call to list->output to give the offset to the
482 * listing module.
483 */
484 list->output(offset, NULL, OUT_RAWDATA, 0);
485 list->uplevel(LIST_TIMES);
486 list->downlevel(LIST_TIMES);
487 }
488 fclose(fp);
489 return instruction->times * len;
490 }
491 return 0; /* if we're here, there's an error */
492 }
493
494 /* Check to see if we need an address-size prefix */
495 add_asp(instruction, bits);
496
497 m = find_match(&temp, instruction, segment, offset, bits);
498
499 if (m == MOK_GOOD) {
500 /* Matches! */
501 int64_t insn_size = calcsize(segment, offset, bits, instruction, temp);
502 itimes = instruction->times;
503 if (insn_size < 0) /* shouldn't be, on pass two */
504 error(ERR_PANIC, "errors made it through from pass one");
505 else
506 while (itimes--) {
507 for (j = 0; j < MAXPREFIX; j++) {
508 uint8_t c = 0;
509 switch (instruction->prefixes[j]) {
510 case P_WAIT:
511 c = 0x9B;
512 break;
513 case P_LOCK:
514 c = 0xF0;
515 break;
516 case P_REPNE:
517 case P_REPNZ:
518 case P_XACQUIRE:
519 c = 0xF2;
520 break;
521 case P_REPE:
522 case P_REPZ:
523 case P_REP:
524 case P_XRELEASE:
525 c = 0xF3;
526 break;
527 case R_CS:
528 if (bits == 64) {
529 error(ERR_WARNING | ERR_PASS2,
530 "cs segment base generated, but will be ignored in 64-bit mode");
531 }
532 c = 0x2E;
533 break;
534 case R_DS:
535 if (bits == 64) {
536 error(ERR_WARNING | ERR_PASS2,
537 "ds segment base generated, but will be ignored in 64-bit mode");
538 }
539 c = 0x3E;
540 break;
541 case R_ES:
542 if (bits == 64) {
543 error(ERR_WARNING | ERR_PASS2,
544 "es segment base generated, but will be ignored in 64-bit mode");
545 }
546 c = 0x26;
547 break;
548 case R_FS:
549 c = 0x64;
550 break;
551 case R_GS:
552 c = 0x65;
553 break;
554 case R_SS:
555 if (bits == 64) {
556 error(ERR_WARNING | ERR_PASS2,
557 "ss segment base generated, but will be ignored in 64-bit mode");
558 }
559 c = 0x36;
560 break;
561 case R_SEGR6:
562 case R_SEGR7:
563 error(ERR_NONFATAL,
564 "segr6 and segr7 cannot be used as prefixes");
565 break;
566 case P_A16:
567 if (bits == 64) {
568 error(ERR_NONFATAL,
569 "16-bit addressing is not supported "
570 "in 64-bit mode");
571 } else if (bits != 16)
572 c = 0x67;
573 break;
574 case P_A32:
575 if (bits != 32)
576 c = 0x67;
577 break;
578 case P_A64:
579 if (bits != 64) {
580 error(ERR_NONFATAL,
581 "64-bit addressing is only supported "
582 "in 64-bit mode");
583 }
584 break;
585 case P_ASP:
586 c = 0x67;
587 break;
588 case P_O16:
589 if (bits != 16)
590 c = 0x66;
591 break;
592 case P_O32:
593 if (bits == 16)
594 c = 0x66;
595 break;
596 case P_O64:
597 /* REX.W */
598 break;
599 case P_OSP:
600 c = 0x66;
601 break;
602 case P_none:
603 break;
604 default:
605 error(ERR_PANIC, "invalid instruction prefix");
606 }
607 if (c != 0) {
608 out(offset, segment, &c, OUT_RAWDATA, 1,
609 NO_SEG, NO_SEG);
610 offset++;
611 }
612 }
613 insn_end = offset + insn_size;
614 gencode(segment, offset, bits, instruction,
615 temp, insn_end);
616 offset += insn_size;
617 if (itimes > 0 && itimes == instruction->times - 1) {
618 /*
619 * Dummy call to list->output to give the offset to the
620 * listing module.
621 */
622 list->output(offset, NULL, OUT_RAWDATA, 0);
623 list->uplevel(LIST_TIMES);
624 }
625 }
626 if (instruction->times > 1)
627 list->downlevel(LIST_TIMES);
628 return offset - start;
629 } else {
630 /* No match */
631 switch (m) {
632 case MERR_OPSIZEMISSING:
633 error(ERR_NONFATAL, "operation size not specified");
634 break;
635 case MERR_OPSIZEMISMATCH:
636 error(ERR_NONFATAL, "mismatch in operand sizes");
637 break;
638 case MERR_BADCPU:
639 error(ERR_NONFATAL, "no instruction for this cpu level");
640 break;
641 case MERR_BADMODE:
642 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
643 bits);
644 break;
645 default:
646 error(ERR_NONFATAL,
647 "invalid combination of opcode and operands");
648 break;
649 }
650 }
651 return 0;
652 }
653
654 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
655 insn * instruction, efunc error)
656 {
657 const struct itemplate *temp;
658 enum match_result m;
659
660 errfunc = error; /* to pass to other functions */
661 cpu = cp;
662
663 if (instruction->opcode == I_none)
664 return 0;
665
666 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
667 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
668 instruction->opcode == I_DT || instruction->opcode == I_DO ||
669 instruction->opcode == I_DY) {
670 extop *e;
671 int32_t isize, osize, wsize;
672
673 isize = 0;
674 wsize = idata_bytes(instruction->opcode);
675
676 list_for_each(e, instruction->eops) {
677 int32_t align;
678
679 osize = 0;
680 if (e->type == EOT_DB_NUMBER) {
681 osize = 1;
682 warn_overflow_const(e->offset, wsize);
683 } else if (e->type == EOT_DB_STRING ||
684 e->type == EOT_DB_STRING_FREE)
685 osize = e->stringlen;
686
687 align = (-osize) % wsize;
688 if (align < 0)
689 align += wsize;
690 isize += osize + align;
691 }
692 return isize * instruction->times;
693 }
694
695 if (instruction->opcode == I_INCBIN) {
696 const char *fname = instruction->eops->stringval;
697 FILE *fp;
698 int64_t val = 0;
699 size_t len;
700
701 fp = fopen(fname, "rb");
702 if (!fp)
703 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
704 fname);
705 else if (fseek(fp, 0L, SEEK_END) < 0)
706 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
707 fname);
708 else {
709 len = ftell(fp);
710 if (instruction->eops->next) {
711 len -= instruction->eops->next->offset;
712 if (instruction->eops->next->next &&
713 len > (size_t)instruction->eops->next->next->offset) {
714 len = (size_t)instruction->eops->next->next->offset;
715 }
716 }
717 val = instruction->times * len;
718 }
719 if (fp)
720 fclose(fp);
721 return val;
722 }
723
724 /* Check to see if we need an address-size prefix */
725 add_asp(instruction, bits);
726
727 m = find_match(&temp, instruction, segment, offset, bits);
728 if (m == MOK_GOOD) {
729 /* we've matched an instruction. */
730 int64_t isize;
731 int j;
732
733 isize = calcsize(segment, offset, bits, instruction, temp);
734 if (isize < 0)
735 return -1;
736 for (j = 0; j < MAXPREFIX; j++) {
737 switch (instruction->prefixes[j]) {
738 case P_A16:
739 if (bits != 16)
740 isize++;
741 break;
742 case P_A32:
743 if (bits != 32)
744 isize++;
745 break;
746 case P_O16:
747 if (bits != 16)
748 isize++;
749 break;
750 case P_O32:
751 if (bits == 16)
752 isize++;
753 break;
754 case P_A64:
755 case P_O64:
756 case P_none:
757 break;
758 default:
759 isize++;
760 break;
761 }
762 }
763 return isize * instruction->times;
764 } else {
765 return -1; /* didn't match any instruction */
766 }
767 }
768
769 static void bad_hle_warn(const insn * ins, uint8_t hleok)
770 {
771 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
772 enum whatwarn { w_none, w_lock, w_inval } ww;
773 static const enum whatwarn warn[2][4] =
774 {
775 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
776 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
777 };
778 unsigned int n;
779
780 n = (unsigned int)rep_pfx - P_XACQUIRE;
781 if (n > 1)
782 return; /* Not XACQUIRE/XRELEASE */
783
784 ww = warn[n][hleok];
785 if (!is_class(MEMORY, ins->oprs[0].type))
786 ww = w_inval; /* HLE requires operand 0 to be memory */
787
788 switch (ww) {
789 case w_none:
790 break;
791
792 case w_lock:
793 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
794 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
795 "%s with this instruction requires lock",
796 prefix_name(rep_pfx));
797 }
798 break;
799
800 case w_inval:
801 errfunc(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
802 "%s invalid with this instruction",
803 prefix_name(rep_pfx));
804 break;
805 }
806 }
807
808 /* Common construct */
809 #define case3(x) case (x): case (x)+1: case (x)+2
810 #define case4(x) case3(x): case (x)+3
811
812 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
813 insn * ins, const struct itemplate *temp)
814 {
815 const uint8_t *codes = temp->code;
816 int64_t length = 0;
817 uint8_t c;
818 int rex_mask = ~0;
819 int op1, op2;
820 struct operand *opx;
821 uint8_t opex = 0;
822 enum ea_type eat;
823 uint8_t hleok = 0;
824 bool lockcheck = true;
825
826 ins->rex = 0; /* Ensure REX is reset */
827 eat = EA_SCALAR; /* Expect a scalar EA */
828
829 if (ins->prefixes[PPS_OSIZE] == P_O64)
830 ins->rex |= REX_W;
831
832 (void)segment; /* Don't warn that this parameter is unused */
833 (void)offset; /* Don't warn that this parameter is unused */
834
835 while (*codes) {
836 c = *codes++;
837 op1 = (c & 3) + ((opex & 1) << 2);
838 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
839 opx = &ins->oprs[op1];
840 opex = 0; /* For the next iteration */
841
842 switch (c) {
843 case4(01):
844 codes += c, length += c;
845 break;
846
847 case3(05):
848 opex = c;
849 break;
850
851 case4(010):
852 ins->rex |=
853 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
854 codes++, length++;
855 break;
856
857 case4(020):
858 case4(024):
859 length++;
860 break;
861
862 case4(030):
863 length += 2;
864 break;
865
866 case4(034):
867 if (opx->type & (BITS16 | BITS32 | BITS64))
868 length += (opx->type & BITS16) ? 2 : 4;
869 else
870 length += (bits == 16) ? 2 : 4;
871 break;
872
873 case4(040):
874 length += 4;
875 break;
876
877 case4(044):
878 length += ins->addr_size >> 3;
879 break;
880
881 case4(050):
882 length++;
883 break;
884
885 case4(054):
886 length += 8; /* MOV reg64/imm */
887 break;
888
889 case4(060):
890 length += 2;
891 break;
892
893 case4(064):
894 if (opx->type & (BITS16 | BITS32 | BITS64))
895 length += (opx->type & BITS16) ? 2 : 4;
896 else
897 length += (bits == 16) ? 2 : 4;
898 break;
899
900 case4(070):
901 length += 4;
902 break;
903
904 case4(074):
905 length += 2;
906 break;
907
908 case 0172:
909 case 0173:
910 codes++;
911 length++;
912 break;
913
914 case4(0174):
915 length++;
916 break;
917
918 case4(0254):
919 length += 4;
920 break;
921
922 case4(0260):
923 ins->rex |= REX_V;
924 ins->vexreg = regval(opx);
925 ins->vex_cm = *codes++;
926 ins->vex_wlp = *codes++;
927 break;
928
929 case 0270:
930 ins->rex |= REX_V;
931 ins->vexreg = 0;
932 ins->vex_cm = *codes++;
933 ins->vex_wlp = *codes++;
934 break;
935
936 case3(0271):
937 hleok = c & 3;
938 break;
939
940 case4(0274):
941 length++;
942 break;
943
944 case4(0300):
945 break;
946
947 case 0310:
948 if (bits == 64)
949 return -1;
950 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
951 break;
952
953 case 0311:
954 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
955 break;
956
957 case 0312:
958 break;
959
960 case 0313:
961 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
962 has_prefix(ins, PPS_ASIZE, P_A32))
963 return -1;
964 break;
965
966 case4(0314):
967 break;
968
969 case 0320:
970 {
971 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
972 if (pfx == P_O16)
973 break;
974 if (pfx != P_none)
975 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
976 else
977 ins->prefixes[PPS_OSIZE] = P_O16;
978 break;
979 }
980
981 case 0321:
982 {
983 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
984 if (pfx == P_O32)
985 break;
986 if (pfx != P_none)
987 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
988 else
989 ins->prefixes[PPS_OSIZE] = P_O32;
990 break;
991 }
992
993 case 0322:
994 break;
995
996 case 0323:
997 rex_mask &= ~REX_W;
998 break;
999
1000 case 0324:
1001 ins->rex |= REX_W;
1002 break;
1003
1004 case 0325:
1005 ins->rex |= REX_NH;
1006 break;
1007
1008 case 0326:
1009 break;
1010
1011 case 0330:
1012 codes++, length++;
1013 break;
1014
1015 case 0331:
1016 break;
1017
1018 case 0332:
1019 case 0333:
1020 length++;
1021 break;
1022
1023 case 0334:
1024 ins->rex |= REX_L;
1025 break;
1026
1027 case 0335:
1028 break;
1029
1030 case 0336:
1031 if (!ins->prefixes[PPS_REP])
1032 ins->prefixes[PPS_REP] = P_REP;
1033 break;
1034
1035 case 0337:
1036 if (!ins->prefixes[PPS_REP])
1037 ins->prefixes[PPS_REP] = P_REPNE;
1038 break;
1039
1040 case 0340:
1041 if (ins->oprs[0].segment != NO_SEG)
1042 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1043 " quantity of BSS space");
1044 else
1045 length += ins->oprs[0].offset;
1046 break;
1047
1048 case 0341:
1049 if (!ins->prefixes[PPS_WAIT])
1050 ins->prefixes[PPS_WAIT] = P_WAIT;
1051 break;
1052
1053 case4(0344):
1054 length++;
1055 break;
1056
1057 case 0360:
1058 break;
1059
1060 case3(0361):
1061 length++;
1062 break;
1063
1064 case 0364:
1065 case 0365:
1066 break;
1067
1068 case 0366:
1069 case 0367:
1070 length++;
1071 break;
1072
1073 case3(0370):
1074 break;
1075
1076 case 0373:
1077 length++;
1078 break;
1079
1080 case 0374:
1081 eat = EA_XMMVSIB;
1082 break;
1083
1084 case 0375:
1085 eat = EA_YMMVSIB;
1086 break;
1087
1088 case4(0100):
1089 case4(0110):
1090 case4(0120):
1091 case4(0130):
1092 case4(0200):
1093 case4(0204):
1094 case4(0210):
1095 case4(0214):
1096 case4(0220):
1097 case4(0224):
1098 case4(0230):
1099 case4(0234):
1100 {
1101 ea ea_data;
1102 int rfield;
1103 opflags_t rflags;
1104 struct operand *opy = &ins->oprs[op2];
1105
1106 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1107
1108 if (c <= 0177) {
1109 /* pick rfield from operand b (opx) */
1110 rflags = regflag(opx);
1111 rfield = nasm_regvals[opx->basereg];
1112 } else {
1113 rflags = 0;
1114 rfield = c & 7;
1115 }
1116 if (process_ea(opy, &ea_data, bits,ins->addr_size,
1117 rfield, rflags) != eat) {
1118 errfunc(ERR_NONFATAL, "invalid effective address");
1119 return -1;
1120 } else {
1121 ins->rex |= ea_data.rex;
1122 length += ea_data.size;
1123 }
1124 }
1125 break;
1126
1127 default:
1128 errfunc(ERR_PANIC, "internal instruction table corrupt"
1129 ": instruction code \\%o (0x%02X) given", c, c);
1130 break;
1131 }
1132 }
1133
1134 ins->rex &= rex_mask;
1135
1136 if (ins->rex & REX_NH) {
1137 if (ins->rex & REX_H) {
1138 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1139 return -1;
1140 }
1141 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1142 }
1143
1144 if (ins->rex & REX_V) {
1145 int bad32 = REX_R|REX_W|REX_X|REX_B;
1146
1147 if (ins->rex & REX_H) {
1148 errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
1149 return -1;
1150 }
1151 switch (ins->vex_wlp & 060) {
1152 case 000:
1153 case 040:
1154 ins->rex &= ~REX_W;
1155 break;
1156 case 020:
1157 ins->rex |= REX_W;
1158 bad32 &= ~REX_W;
1159 break;
1160 case 060:
1161 /* Follow REX_W */
1162 break;
1163 }
1164
1165 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1166 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1167 return -1;
1168 }
1169 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1170 length += 3;
1171 else
1172 length += 2;
1173 } else if (ins->rex & REX_REAL) {
1174 if (ins->rex & REX_H) {
1175 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1176 return -1;
1177 } else if (bits == 64) {
1178 length++;
1179 } else if ((ins->rex & REX_L) &&
1180 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1181 cpu >= IF_X86_64) {
1182 /* LOCK-as-REX.R */
1183 assert_no_prefix(ins, PPS_LOCK);
1184 lockcheck = false; /* Already errored, no need for warning */
1185 length++;
1186 } else {
1187 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1188 return -1;
1189 }
1190 }
1191
1192 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1193 (!(temp->flags & IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1194 errfunc(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1195 "instruction is not lockable");
1196 }
1197
1198 bad_hle_warn(ins, hleok);
1199
1200 return length;
1201 }
1202
1203 #define EMIT_REX() \
1204 if (!(ins->rex & REX_V) && (ins->rex & REX_REAL) && (bits == 64)) { \
1205 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1206 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1207 ins->rex = 0; \
1208 offset += 1; \
1209 }
1210
1211 static void gencode(int32_t segment, int64_t offset, int bits,
1212 insn * ins, const struct itemplate *temp,
1213 int64_t insn_end)
1214 {
1215 static const char condval[] = { /* conditional opcodes */
1216 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1217 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1218 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1219 };
1220 uint8_t c;
1221 uint8_t bytes[4];
1222 int64_t size;
1223 int64_t data;
1224 int op1, op2;
1225 struct operand *opx;
1226 const uint8_t *codes = temp->code;
1227 uint8_t opex = 0;
1228 enum ea_type eat = EA_SCALAR;
1229
1230 while (*codes) {
1231 c = *codes++;
1232 op1 = (c & 3) + ((opex & 1) << 2);
1233 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1234 opx = &ins->oprs[op1];
1235 opex = 0; /* For the next iteration */
1236
1237 switch (c) {
1238 case 01:
1239 case 02:
1240 case 03:
1241 case 04:
1242 EMIT_REX();
1243 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1244 codes += c;
1245 offset += c;
1246 break;
1247
1248 case 05:
1249 case 06:
1250 case 07:
1251 opex = c;
1252 break;
1253
1254 case4(010):
1255 EMIT_REX();
1256 bytes[0] = *codes++ + (regval(opx) & 7);
1257 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1258 offset += 1;
1259 break;
1260
1261 case4(020):
1262 if (opx->offset < -256 || opx->offset > 255) {
1263 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1264 "byte value exceeds bounds");
1265 }
1266 out_imm8(offset, segment, opx);
1267 offset += 1;
1268 break;
1269
1270 case4(024):
1271 if (opx->offset < 0 || opx->offset > 255)
1272 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1273 "unsigned byte value exceeds bounds");
1274 out_imm8(offset, segment, opx);
1275 offset += 1;
1276 break;
1277
1278 case4(030):
1279 warn_overflow_opd(opx, 2);
1280 data = opx->offset;
1281 out(offset, segment, &data, OUT_ADDRESS, 2,
1282 opx->segment, opx->wrt);
1283 offset += 2;
1284 break;
1285
1286 case4(034):
1287 if (opx->type & (BITS16 | BITS32))
1288 size = (opx->type & BITS16) ? 2 : 4;
1289 else
1290 size = (bits == 16) ? 2 : 4;
1291 warn_overflow_opd(opx, size);
1292 data = opx->offset;
1293 out(offset, segment, &data, OUT_ADDRESS, size,
1294 opx->segment, opx->wrt);
1295 offset += size;
1296 break;
1297
1298 case4(040):
1299 warn_overflow_opd(opx, 4);
1300 data = opx->offset;
1301 out(offset, segment, &data, OUT_ADDRESS, 4,
1302 opx->segment, opx->wrt);
1303 offset += 4;
1304 break;
1305
1306 case4(044):
1307 data = opx->offset;
1308 size = ins->addr_size >> 3;
1309 warn_overflow_opd(opx, size);
1310 out(offset, segment, &data, OUT_ADDRESS, size,
1311 opx->segment, opx->wrt);
1312 offset += size;
1313 break;
1314
1315 case4(050):
1316 if (opx->segment != segment) {
1317 data = opx->offset;
1318 out(offset, segment, &data,
1319 OUT_REL1ADR, insn_end - offset,
1320 opx->segment, opx->wrt);
1321 } else {
1322 data = opx->offset - insn_end;
1323 if (data > 127 || data < -128)
1324 errfunc(ERR_NONFATAL, "short jump is out of range");
1325 out(offset, segment, &data,
1326 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1327 }
1328 offset += 1;
1329 break;
1330
1331 case4(054):
1332 data = (int64_t)opx->offset;
1333 out(offset, segment, &data, OUT_ADDRESS, 8,
1334 opx->segment, opx->wrt);
1335 offset += 8;
1336 break;
1337
1338 case4(060):
1339 if (opx->segment != segment) {
1340 data = opx->offset;
1341 out(offset, segment, &data,
1342 OUT_REL2ADR, insn_end - offset,
1343 opx->segment, opx->wrt);
1344 } else {
1345 data = opx->offset - insn_end;
1346 out(offset, segment, &data,
1347 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1348 }
1349 offset += 2;
1350 break;
1351
1352 case4(064):
1353 if (opx->type & (BITS16 | BITS32 | BITS64))
1354 size = (opx->type & BITS16) ? 2 : 4;
1355 else
1356 size = (bits == 16) ? 2 : 4;
1357 if (opx->segment != segment) {
1358 data = opx->offset;
1359 out(offset, segment, &data,
1360 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1361 insn_end - offset, opx->segment, opx->wrt);
1362 } else {
1363 data = opx->offset - insn_end;
1364 out(offset, segment, &data,
1365 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1366 }
1367 offset += size;
1368 break;
1369
1370 case4(070):
1371 if (opx->segment != segment) {
1372 data = opx->offset;
1373 out(offset, segment, &data,
1374 OUT_REL4ADR, insn_end - offset,
1375 opx->segment, opx->wrt);
1376 } else {
1377 data = opx->offset - insn_end;
1378 out(offset, segment, &data,
1379 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1380 }
1381 offset += 4;
1382 break;
1383
1384 case4(074):
1385 if (opx->segment == NO_SEG)
1386 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1387 " relocatable");
1388 data = 0;
1389 out(offset, segment, &data, OUT_ADDRESS, 2,
1390 outfmt->segbase(1 + opx->segment),
1391 opx->wrt);
1392 offset += 2;
1393 break;
1394
1395 case 0172:
1396 c = *codes++;
1397 opx = &ins->oprs[c >> 3];
1398 bytes[0] = nasm_regvals[opx->basereg] << 4;
1399 opx = &ins->oprs[c & 7];
1400 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1401 errfunc(ERR_NONFATAL,
1402 "non-absolute expression not permitted as argument %d",
1403 c & 7);
1404 } else {
1405 if (opx->offset & ~15) {
1406 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1407 "four-bit argument exceeds bounds");
1408 }
1409 bytes[0] |= opx->offset & 15;
1410 }
1411 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1412 offset++;
1413 break;
1414
1415 case 0173:
1416 c = *codes++;
1417 opx = &ins->oprs[c >> 4];
1418 bytes[0] = nasm_regvals[opx->basereg] << 4;
1419 bytes[0] |= c & 15;
1420 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1421 offset++;
1422 break;
1423
1424 case4(0174):
1425 bytes[0] = nasm_regvals[opx->basereg] << 4;
1426 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1427 offset++;
1428 break;
1429
1430 case4(0254):
1431 data = opx->offset;
1432 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1433 (int32_t)data != (int64_t)data) {
1434 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1435 "signed dword immediate exceeds bounds");
1436 }
1437 out(offset, segment, &data, OUT_ADDRESS, 4,
1438 opx->segment, opx->wrt);
1439 offset += 4;
1440 break;
1441
1442 case4(0260):
1443 case 0270:
1444 codes += 2;
1445 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1446 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1447 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1448 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1449 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1450 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1451 offset += 3;
1452 } else {
1453 bytes[0] = 0xc5;
1454 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1455 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1456 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1457 offset += 2;
1458 }
1459 break;
1460
1461 case 0271:
1462 case 0272:
1463 case 0273:
1464 break;
1465
1466 case4(0274):
1467 {
1468 uint64_t uv, um;
1469 int s;
1470
1471 if (ins->rex & REX_W)
1472 s = 64;
1473 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1474 s = 16;
1475 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1476 s = 32;
1477 else
1478 s = bits;
1479
1480 um = (uint64_t)2 << (s-1);
1481 uv = opx->offset;
1482
1483 if (uv > 127 && uv < (uint64_t)-128 &&
1484 (uv < um-128 || uv > um-1)) {
1485 /* If this wasn't explicitly byte-sized, warn as though we
1486 * had fallen through to the imm16/32/64 case.
1487 */
1488 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1489 "%s value exceeds bounds",
1490 (opx->type & BITS8) ? "signed byte" :
1491 s == 16 ? "word" :
1492 s == 32 ? "dword" :
1493 "signed dword");
1494 }
1495 if (opx->segment != NO_SEG) {
1496 data = uv;
1497 out(offset, segment, &data, OUT_ADDRESS, 1,
1498 opx->segment, opx->wrt);
1499 } else {
1500 bytes[0] = uv;
1501 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1502 NO_SEG);
1503 }
1504 offset += 1;
1505 break;
1506 }
1507
1508 case4(0300):
1509 break;
1510
1511 case 0310:
1512 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1513 *bytes = 0x67;
1514 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1515 offset += 1;
1516 } else
1517 offset += 0;
1518 break;
1519
1520 case 0311:
1521 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1522 *bytes = 0x67;
1523 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1524 offset += 1;
1525 } else
1526 offset += 0;
1527 break;
1528
1529 case 0312:
1530 break;
1531
1532 case 0313:
1533 ins->rex = 0;
1534 break;
1535
1536 case4(0314):
1537 break;
1538
1539 case 0320:
1540 case 0321:
1541 break;
1542
1543 case 0322:
1544 case 0323:
1545 break;
1546
1547 case 0324:
1548 ins->rex |= REX_W;
1549 break;
1550
1551 case 0325:
1552 break;
1553
1554 case 0326:
1555 break;
1556
1557 case 0330:
1558 *bytes = *codes++ ^ condval[ins->condition];
1559 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1560 offset += 1;
1561 break;
1562
1563 case 0331:
1564 break;
1565
1566 case 0332:
1567 case 0333:
1568 *bytes = c - 0332 + 0xF2;
1569 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1570 offset += 1;
1571 break;
1572
1573 case 0334:
1574 if (ins->rex & REX_R) {
1575 *bytes = 0xF0;
1576 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1577 offset += 1;
1578 }
1579 ins->rex &= ~(REX_L|REX_R);
1580 break;
1581
1582 case 0335:
1583 break;
1584
1585 case 0336:
1586 case 0337:
1587 break;
1588
1589 case 0340:
1590 if (ins->oprs[0].segment != NO_SEG)
1591 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1592 else {
1593 int64_t size = ins->oprs[0].offset;
1594 if (size > 0)
1595 out(offset, segment, NULL,
1596 OUT_RESERVE, size, NO_SEG, NO_SEG);
1597 offset += size;
1598 }
1599 break;
1600
1601 case 0341:
1602 break;
1603
1604 case 0344:
1605 case 0345:
1606 bytes[0] = c & 1;
1607 switch (ins->oprs[0].basereg) {
1608 case R_CS:
1609 bytes[0] += 0x0E;
1610 break;
1611 case R_DS:
1612 bytes[0] += 0x1E;
1613 break;
1614 case R_ES:
1615 bytes[0] += 0x06;
1616 break;
1617 case R_SS:
1618 bytes[0] += 0x16;
1619 break;
1620 default:
1621 errfunc(ERR_PANIC,
1622 "bizarre 8086 segment register received");
1623 }
1624 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1625 offset++;
1626 break;
1627
1628 case 0346:
1629 case 0347:
1630 bytes[0] = c & 1;
1631 switch (ins->oprs[0].basereg) {
1632 case R_FS:
1633 bytes[0] += 0xA0;
1634 break;
1635 case R_GS:
1636 bytes[0] += 0xA8;
1637 break;
1638 default:
1639 errfunc(ERR_PANIC,
1640 "bizarre 386 segment register received");
1641 }
1642 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1643 offset++;
1644 break;
1645
1646 case 0360:
1647 break;
1648
1649 case 0361:
1650 bytes[0] = 0x66;
1651 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1652 offset += 1;
1653 break;
1654
1655 case 0362:
1656 case 0363:
1657 bytes[0] = c - 0362 + 0xf2;
1658 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1659 offset += 1;
1660 break;
1661
1662 case 0364:
1663 case 0365:
1664 break;
1665
1666 case 0366:
1667 case 0367:
1668 *bytes = c - 0366 + 0x66;
1669 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1670 offset += 1;
1671 break;
1672
1673 case 0370:
1674 case 0371:
1675 break;
1676
1677 case 0373:
1678 *bytes = bits == 16 ? 3 : 5;
1679 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1680 offset += 1;
1681 break;
1682
1683 case 0374:
1684 eat = EA_XMMVSIB;
1685 break;
1686
1687 case 0375:
1688 eat = EA_YMMVSIB;
1689 break;
1690
1691 case4(0100):
1692 case4(0110):
1693 case4(0120):
1694 case4(0130):
1695 case4(0200):
1696 case4(0204):
1697 case4(0210):
1698 case4(0214):
1699 case4(0220):
1700 case4(0224):
1701 case4(0230):
1702 case4(0234):
1703 {
1704 ea ea_data;
1705 int rfield;
1706 opflags_t rflags;
1707 uint8_t *p;
1708 int32_t s;
1709 struct operand *opy = &ins->oprs[op2];
1710
1711 if (c <= 0177) {
1712 /* pick rfield from operand b (opx) */
1713 rflags = regflag(opx);
1714 rfield = nasm_regvals[opx->basereg];
1715 } else {
1716 /* rfield is constant */
1717 rflags = 0;
1718 rfield = c & 7;
1719 }
1720
1721 if (process_ea(opy, &ea_data, bits, ins->addr_size,
1722 rfield, rflags) != eat)
1723 errfunc(ERR_NONFATAL, "invalid effective address");
1724
1725 p = bytes;
1726 *p++ = ea_data.modrm;
1727 if (ea_data.sib_present)
1728 *p++ = ea_data.sib;
1729
1730 s = p - bytes;
1731 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1732
1733 /*
1734 * Make sure the address gets the right offset in case
1735 * the line breaks in the .lst file (BR 1197827)
1736 */
1737 offset += s;
1738 s = 0;
1739
1740 switch (ea_data.bytes) {
1741 case 0:
1742 break;
1743 case 1:
1744 case 2:
1745 case 4:
1746 case 8:
1747 data = opy->offset;
1748 s += ea_data.bytes;
1749 if (ea_data.rip) {
1750 if (opy->segment == segment) {
1751 data -= insn_end;
1752 if (overflow_signed(data, ea_data.bytes))
1753 warn_overflow(ERR_PASS2, ea_data.bytes);
1754 out(offset, segment, &data, OUT_ADDRESS,
1755 ea_data.bytes, NO_SEG, NO_SEG);
1756 } else {
1757 /* overflow check in output/linker? */
1758 out(offset, segment, &data, OUT_REL4ADR,
1759 insn_end - offset, opy->segment, opy->wrt);
1760 }
1761 } else {
1762 if (overflow_general(opy->offset, ins->addr_size >> 3) ||
1763 signed_bits(opy->offset, ins->addr_size) !=
1764 signed_bits(opy->offset, ea_data.bytes * 8))
1765 warn_overflow(ERR_PASS2, ea_data.bytes);
1766
1767 out(offset, segment, &data, OUT_ADDRESS,
1768 ea_data.bytes, opy->segment, opy->wrt);
1769 }
1770 break;
1771 default:
1772 /* Impossible! */
1773 errfunc(ERR_PANIC,
1774 "Invalid amount of bytes (%d) for offset?!",
1775 ea_data.bytes);
1776 break;
1777 }
1778 offset += s;
1779 }
1780 break;
1781
1782 default:
1783 errfunc(ERR_PANIC, "internal instruction table corrupt"
1784 ": instruction code \\%o (0x%02X) given", c, c);
1785 break;
1786 }
1787 }
1788 }
1789
1790 static opflags_t regflag(const operand * o)
1791 {
1792 if (!is_register(o->basereg))
1793 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1794 return nasm_reg_flags[o->basereg];
1795 }
1796
1797 static int32_t regval(const operand * o)
1798 {
1799 if (!is_register(o->basereg))
1800 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1801 return nasm_regvals[o->basereg];
1802 }
1803
1804 static int op_rexflags(const operand * o, int mask)
1805 {
1806 opflags_t flags;
1807 int val;
1808
1809 if (!is_register(o->basereg))
1810 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1811
1812 flags = nasm_reg_flags[o->basereg];
1813 val = nasm_regvals[o->basereg];
1814
1815 return rexflags(val, flags, mask);
1816 }
1817
1818 static int rexflags(int val, opflags_t flags, int mask)
1819 {
1820 int rex = 0;
1821
1822 if (val >= 8)
1823 rex |= REX_B|REX_X|REX_R;
1824 if (flags & BITS64)
1825 rex |= REX_W;
1826 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1827 rex |= REX_H;
1828 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1829 rex |= REX_P;
1830
1831 return rex & mask;
1832 }
1833
1834 static enum match_result find_match(const struct itemplate **tempp,
1835 insn *instruction,
1836 int32_t segment, int64_t offset, int bits)
1837 {
1838 const struct itemplate *temp;
1839 enum match_result m, merr;
1840 opflags_t xsizeflags[MAX_OPERANDS];
1841 bool opsizemissing = false;
1842 int i;
1843
1844 for (i = 0; i < instruction->operands; i++)
1845 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1846
1847 merr = MERR_INVALOP;
1848
1849 for (temp = nasm_instructions[instruction->opcode];
1850 temp->opcode != I_none; temp++) {
1851 m = matches(temp, instruction, bits);
1852 if (m == MOK_JUMP) {
1853 if (jmp_match(segment, offset, bits, instruction, temp))
1854 m = MOK_GOOD;
1855 else
1856 m = MERR_INVALOP;
1857 } else if (m == MERR_OPSIZEMISSING &&
1858 (temp->flags & IF_SMASK) != IF_SX) {
1859 /*
1860 * Missing operand size and a candidate for fuzzy matching...
1861 */
1862 for (i = 0; i < temp->operands; i++) {
1863 if ((temp->opd[i] & SAME_AS) == 0)
1864 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
1865 }
1866 opsizemissing = true;
1867 }
1868 if (m > merr)
1869 merr = m;
1870 if (merr == MOK_GOOD)
1871 goto done;
1872 }
1873
1874 /* No match, but see if we can get a fuzzy operand size match... */
1875 if (!opsizemissing)
1876 goto done;
1877
1878 for (i = 0; i < instruction->operands; i++) {
1879 /*
1880 * We ignore extrinsic operand sizes on registers, so we should
1881 * never try to fuzzy-match on them. This also resolves the case
1882 * when we have e.g. "xmmrm128" in two different positions.
1883 */
1884 if (is_class(REGISTER, instruction->oprs[i].type))
1885 continue;
1886
1887 /* This tests if xsizeflags[i] has more than one bit set */
1888 if ((xsizeflags[i] & (xsizeflags[i]-1)))
1889 goto done; /* No luck */
1890
1891 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
1892 }
1893
1894 /* Try matching again... */
1895 for (temp = nasm_instructions[instruction->opcode];
1896 temp->opcode != I_none; temp++) {
1897 m = matches(temp, instruction, bits);
1898 if (m == MOK_JUMP) {
1899 if (jmp_match(segment, offset, bits, instruction, temp))
1900 m = MOK_GOOD;
1901 else
1902 m = MERR_INVALOP;
1903 }
1904 if (m > merr)
1905 merr = m;
1906 if (merr == MOK_GOOD)
1907 goto done;
1908 }
1909
1910 done:
1911 *tempp = temp;
1912 return merr;
1913 }
1914
1915 static enum match_result matches(const struct itemplate *itemp,
1916 insn *instruction, int bits)
1917 {
1918 opflags_t size[MAX_OPERANDS], asize;
1919 bool opsizemissing = false;
1920 int i, oprs;
1921
1922 /*
1923 * Check the opcode
1924 */
1925 if (itemp->opcode != instruction->opcode)
1926 return MERR_INVALOP;
1927
1928 /*
1929 * Count the operands
1930 */
1931 if (itemp->operands != instruction->operands)
1932 return MERR_INVALOP;
1933
1934 /*
1935 * Is it legal?
1936 */
1937 if (!(optimizing > 0) && (itemp->flags & IF_OPT))
1938 return MERR_INVALOP;
1939
1940 /*
1941 * Check that no spurious colons or TOs are present
1942 */
1943 for (i = 0; i < itemp->operands; i++)
1944 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
1945 return MERR_INVALOP;
1946
1947 /*
1948 * Process size flags
1949 */
1950 switch (itemp->flags & IF_SMASK) {
1951 case IF_SB:
1952 asize = BITS8;
1953 break;
1954 case IF_SW:
1955 asize = BITS16;
1956 break;
1957 case IF_SD:
1958 asize = BITS32;
1959 break;
1960 case IF_SQ:
1961 asize = BITS64;
1962 break;
1963 case IF_SO:
1964 asize = BITS128;
1965 break;
1966 case IF_SY:
1967 asize = BITS256;
1968 break;
1969 case IF_SZ:
1970 switch (bits) {
1971 case 16:
1972 asize = BITS16;
1973 break;
1974 case 32:
1975 asize = BITS32;
1976 break;
1977 case 64:
1978 asize = BITS64;
1979 break;
1980 default:
1981 asize = 0;
1982 break;
1983 }
1984 break;
1985 default:
1986 asize = 0;
1987 break;
1988 }
1989
1990 if (itemp->flags & IF_ARMASK) {
1991 /* S- flags only apply to a specific operand */
1992 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
1993 memset(size, 0, sizeof size);
1994 size[i] = asize;
1995 } else {
1996 /* S- flags apply to all operands */
1997 for (i = 0; i < MAX_OPERANDS; i++)
1998 size[i] = asize;
1999 }
2000
2001 /*
2002 * Check that the operand flags all match up,
2003 * it's a bit tricky so lets be verbose:
2004 *
2005 * 1) Find out the size of operand. If instruction
2006 * doesn't have one specified -- we're trying to
2007 * guess it either from template (IF_S* flag) or
2008 * from code bits.
2009 *
2010 * 2) If template operand (i) has SAME_AS flag [used for registers only]
2011 * (ie the same operand as was specified somewhere in template, and
2012 * this referred operand index is being achieved via ~SAME_AS)
2013 * we are to be sure that both registers (in template and instruction)
2014 * do exactly match.
2015 *
2016 * 3) If template operand do not match the instruction OR
2017 * template has an operand size specified AND this size differ
2018 * from which instruction has (perhaps we got it from code bits)
2019 * we are:
2020 * a) Check that only size of instruction and operand is differ
2021 * other characteristics do match
2022 * b) Perhaps it's a register specified in instruction so
2023 * for such a case we just mark that operand as "size
2024 * missing" and this will turn on fuzzy operand size
2025 * logic facility (handled by a caller)
2026 */
2027 for (i = 0; i < itemp->operands; i++) {
2028 opflags_t type = instruction->oprs[i].type;
2029 if (!(type & SIZE_MASK))
2030 type |= size[i];
2031
2032 if (itemp->opd[i] & SAME_AS) {
2033 int j = itemp->opd[i] & ~SAME_AS;
2034 if (type != instruction->oprs[j].type ||
2035 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
2036 return MERR_INVALOP;
2037 } else if (itemp->opd[i] & ~type & ~SIZE_MASK) {
2038 return MERR_INVALOP;
2039 } else if ((itemp->opd[i] & SIZE_MASK) &&
2040 (itemp->opd[i] & SIZE_MASK) != (type & SIZE_MASK)) {
2041 if (type & SIZE_MASK) {
2042 return MERR_INVALOP;
2043 } else if (!is_class(REGISTER, type)) {
2044 /*
2045 * Note: we don't honor extrinsic operand sizes for registers,
2046 * so "missing operand size" for a register should be
2047 * considered a wildcard match rather than an error.
2048 */
2049 opsizemissing = true;
2050 }
2051 }
2052 }
2053
2054 if (opsizemissing)
2055 return MERR_OPSIZEMISSING;
2056
2057 /*
2058 * Check operand sizes
2059 */
2060 if (itemp->flags & (IF_SM | IF_SM2)) {
2061 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2062 for (i = 0; i < oprs; i++) {
2063 asize = itemp->opd[i] & SIZE_MASK;
2064 if (asize) {
2065 for (i = 0; i < oprs; i++)
2066 size[i] = asize;
2067 break;
2068 }
2069 }
2070 } else {
2071 oprs = itemp->operands;
2072 }
2073
2074 for (i = 0; i < itemp->operands; i++) {
2075 if (!(itemp->opd[i] & SIZE_MASK) &&
2076 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2077 return MERR_OPSIZEMISMATCH;
2078 }
2079
2080 /*
2081 * Check template is okay at the set cpu level
2082 */
2083 if (((itemp->flags & IF_PLEVEL) > cpu))
2084 return MERR_BADCPU;
2085
2086 /*
2087 * Verify the appropriate long mode flag.
2088 */
2089 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2090 return MERR_BADMODE;
2091
2092 /*
2093 * If we have a HLE prefix, look for the NOHLE flag
2094 */
2095 if ((itemp->flags & IF_NOHLE) &&
2096 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2097 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2098 return MERR_BADHLE;
2099
2100 /*
2101 * Check if special handling needed for Jumps
2102 */
2103 if ((itemp->code[0] & ~1) == 0370)
2104 return MOK_JUMP;
2105
2106 return MOK_GOOD;
2107 }
2108
2109 static enum ea_type process_ea(operand *input, ea *output, int bits,
2110 int addrbits, int rfield, opflags_t rflags)
2111 {
2112 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2113
2114 output->type = EA_SCALAR;
2115 output->rip = false;
2116
2117 /* REX flags for the rfield operand */
2118 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2119
2120 if (is_class(REGISTER, input->type)) {
2121 /*
2122 * It's a direct register.
2123 */
2124 if (!is_register(input->basereg))
2125 goto err;
2126
2127 if (!is_class(REG_EA, regflag(input)))
2128 goto err;
2129
2130 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2131 output->sib_present = false; /* no SIB necessary */
2132 output->bytes = 0; /* no offset necessary either */
2133 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2134 } else {
2135 /*
2136 * It's a memory reference.
2137 */
2138 if (input->basereg == -1 &&
2139 (input->indexreg == -1 || input->scale == 0)) {
2140 /*
2141 * It's a pure offset.
2142 */
2143 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2144 input->segment == NO_SEG) {
2145 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2146 input->type &= ~IP_REL;
2147 input->type |= MEMORY;
2148 }
2149
2150 if (input->eaflags & EAF_BYTEOFFS ||
2151 (input->eaflags & EAF_WORDOFFS &&
2152 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2153 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2154 }
2155
2156 if (bits == 64 && (~input->type & IP_REL)) {
2157 output->sib_present = true;
2158 output->sib = GEN_SIB(0, 4, 5);
2159 output->bytes = 4;
2160 output->modrm = GEN_MODRM(0, rfield, 4);
2161 output->rip = false;
2162 } else {
2163 output->sib_present = false;
2164 output->bytes = (addrbits != 16 ? 4 : 2);
2165 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2166 output->rip = bits == 64;
2167 }
2168 } else {
2169 /*
2170 * It's an indirection.
2171 */
2172 int i = input->indexreg, b = input->basereg, s = input->scale;
2173 int32_t seg = input->segment;
2174 int hb = input->hintbase, ht = input->hinttype;
2175 int t, it, bt; /* register numbers */
2176 opflags_t x, ix, bx; /* register flags */
2177
2178 if (s == 0)
2179 i = -1; /* make this easy, at least */
2180
2181 if (is_register(i)) {
2182 it = nasm_regvals[i];
2183 ix = nasm_reg_flags[i];
2184 } else {
2185 it = -1;
2186 ix = 0;
2187 }
2188
2189 if (is_register(b)) {
2190 bt = nasm_regvals[b];
2191 bx = nasm_reg_flags[b];
2192 } else {
2193 bt = -1;
2194 bx = 0;
2195 }
2196
2197 /* if either one are a vector register... */
2198 if ((ix|bx) & (XMMREG|YMMREG) & ~REG_EA) {
2199 opflags_t sok = BITS32 | BITS64;
2200 int32_t o = input->offset;
2201 int mod, scale, index, base;
2202
2203 /*
2204 * For a vector SIB, one has to be a vector and the other,
2205 * if present, a GPR. The vector must be the index operand.
2206 */
2207 if (it == -1 || (bx & (XMMREG|YMMREG) & ~REG_EA)) {
2208 if (s == 0)
2209 s = 1;
2210 else if (s != 1)
2211 goto err;
2212
2213 t = bt, bt = it, it = t;
2214 x = bx, bx = ix, ix = x;
2215 }
2216
2217 if (bt != -1) {
2218 if (REG_GPR & ~bx)
2219 goto err;
2220 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2221 sok &= bx;
2222 else
2223 goto err;
2224 }
2225
2226 /*
2227 * While we're here, ensure the user didn't specify
2228 * WORD or QWORD
2229 */
2230 if (input->disp_size == 16 || input->disp_size == 64)
2231 goto err;
2232
2233 if (addrbits == 16 ||
2234 (addrbits == 32 && !(sok & BITS32)) ||
2235 (addrbits == 64 && !(sok & BITS64)))
2236 goto err;
2237
2238 output->type = (ix & YMMREG & ~REG_EA)
2239 ? EA_YMMVSIB : EA_XMMVSIB;
2240
2241 output->rex |= rexflags(it, ix, REX_X);
2242 output->rex |= rexflags(bt, bx, REX_B);
2243
2244 index = it & 7; /* it is known to be != -1 */
2245
2246 switch (s) {
2247 case 1:
2248 scale = 0;
2249 break;
2250 case 2:
2251 scale = 1;
2252 break;
2253 case 4:
2254 scale = 2;
2255 break;
2256 case 8:
2257 scale = 3;
2258 break;
2259 default: /* then what the smeg is it? */
2260 goto err; /* panic */
2261 }
2262
2263 if (bt == -1) {
2264 base = 5;
2265 mod = 0;
2266 } else {
2267 base = (bt & 7);
2268 if (base != REG_NUM_EBP && o == 0 &&
2269 seg == NO_SEG && !forw_ref &&
2270 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2271 mod = 0;
2272 else if (input->eaflags & EAF_BYTEOFFS ||
2273 (o >= -128 && o <= 127 &&
2274 seg == NO_SEG && !forw_ref &&
2275 !(input->eaflags & EAF_WORDOFFS)))
2276 mod = 1;
2277 else
2278 mod = 2;
2279 }
2280
2281 output->sib_present = true;
2282 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2283 output->modrm = GEN_MODRM(mod, rfield, 4);
2284 output->sib = GEN_SIB(scale, index, base);
2285 } else if ((ix|bx) & (BITS32|BITS64)) {
2286 /*
2287 * it must be a 32/64-bit memory reference. Firstly we have
2288 * to check that all registers involved are type E/Rxx.
2289 */
2290 opflags_t sok = BITS32 | BITS64;
2291 int32_t o = input->offset;
2292
2293 if (it != -1) {
2294 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2295 sok &= ix;
2296 else
2297 goto err;
2298 }
2299
2300 if (bt != -1) {
2301 if (REG_GPR & ~bx)
2302 goto err; /* Invalid register */
2303 if (~sok & bx & SIZE_MASK)
2304 goto err; /* Invalid size */
2305 sok &= bx;
2306 }
2307
2308 /*
2309 * While we're here, ensure the user didn't specify
2310 * WORD or QWORD
2311 */
2312 if (input->disp_size == 16 || input->disp_size == 64)
2313 goto err;
2314
2315 if (addrbits == 16 ||
2316 (addrbits == 32 && !(sok & BITS32)) ||
2317 (addrbits == 64 && !(sok & BITS64)))
2318 goto err;
2319
2320 /* now reorganize base/index */
2321 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2322 ((hb == b && ht == EAH_NOTBASE) ||
2323 (hb == i && ht == EAH_MAKEBASE))) {
2324 /* swap if hints say so */
2325 t = bt, bt = it, it = t;
2326 x = bx, bx = ix, ix = x;
2327 }
2328 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2329 bt = -1, bx = 0, s++;
2330 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2331 /* make single reg base, unless hint */
2332 bt = it, bx = ix, it = -1, ix = 0;
2333 }
2334 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2335 s == 3 || s == 5 || s == 9) && bt == -1)
2336 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2337 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2338 (input->eaflags & EAF_TIMESTWO))
2339 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2340 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2341 if (s == 1 && it == REG_NUM_ESP) {
2342 /* swap ESP into base if scale is 1 */
2343 t = it, it = bt, bt = t;
2344 x = ix, ix = bx, bx = x;
2345 }
2346 if (it == REG_NUM_ESP ||
2347 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2348 goto err; /* wrong, for various reasons */
2349
2350 output->rex |= rexflags(it, ix, REX_X);
2351 output->rex |= rexflags(bt, bx, REX_B);
2352
2353 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2354 /* no SIB needed */
2355 int mod, rm;
2356
2357 if (bt == -1) {
2358 rm = 5;
2359 mod = 0;
2360 } else {
2361 rm = (bt & 7);
2362 if (rm != REG_NUM_EBP && o == 0 &&
2363 seg == NO_SEG && !forw_ref &&
2364 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2365 mod = 0;
2366 else if (input->eaflags & EAF_BYTEOFFS ||
2367 (o >= -128 && o <= 127 &&
2368 seg == NO_SEG && !forw_ref &&
2369 !(input->eaflags & EAF_WORDOFFS)))
2370 mod = 1;
2371 else
2372 mod = 2;
2373 }
2374
2375 output->sib_present = false;
2376 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2377 output->modrm = GEN_MODRM(mod, rfield, rm);
2378 } else {
2379 /* we need a SIB */
2380 int mod, scale, index, base;
2381
2382 if (it == -1)
2383 index = 4, s = 1;
2384 else
2385 index = (it & 7);
2386
2387 switch (s) {
2388 case 1:
2389 scale = 0;
2390 break;
2391 case 2:
2392 scale = 1;
2393 break;
2394 case 4:
2395 scale = 2;
2396 break;
2397 case 8:
2398 scale = 3;
2399 break;
2400 default: /* then what the smeg is it? */
2401 goto err; /* panic */
2402 }
2403
2404 if (bt == -1) {
2405 base = 5;
2406 mod = 0;
2407 } else {
2408 base = (bt & 7);
2409 if (base != REG_NUM_EBP && o == 0 &&
2410 seg == NO_SEG && !forw_ref &&
2411 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2412 mod = 0;
2413 else if (input->eaflags & EAF_BYTEOFFS ||
2414 (o >= -128 && o <= 127 &&
2415 seg == NO_SEG && !forw_ref &&
2416 !(input->eaflags & EAF_WORDOFFS)))
2417 mod = 1;
2418 else
2419 mod = 2;
2420 }
2421
2422 output->sib_present = true;
2423 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2424 output->modrm = GEN_MODRM(mod, rfield, 4);
2425 output->sib = GEN_SIB(scale, index, base);
2426 }
2427 } else { /* it's 16-bit */
2428 int mod, rm;
2429 int16_t o = input->offset;
2430
2431 /* check for 64-bit long mode */
2432 if (addrbits == 64)
2433 goto err;
2434
2435 /* check all registers are BX, BP, SI or DI */
2436 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2437 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2438 goto err;
2439
2440 /* ensure the user didn't specify DWORD/QWORD */
2441 if (input->disp_size == 32 || input->disp_size == 64)
2442 goto err;
2443
2444 if (s != 1 && i != -1)
2445 goto err; /* no can do, in 16-bit EA */
2446 if (b == -1 && i != -1) {
2447 int tmp = b;
2448 b = i;
2449 i = tmp;
2450 } /* swap */
2451 if ((b == R_SI || b == R_DI) && i != -1) {
2452 int tmp = b;
2453 b = i;
2454 i = tmp;
2455 }
2456 /* have BX/BP as base, SI/DI index */
2457 if (b == i)
2458 goto err; /* shouldn't ever happen, in theory */
2459 if (i != -1 && b != -1 &&
2460 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2461 goto err; /* invalid combinations */
2462 if (b == -1) /* pure offset: handled above */
2463 goto err; /* so if it gets to here, panic! */
2464
2465 rm = -1;
2466 if (i != -1)
2467 switch (i * 256 + b) {
2468 case R_SI * 256 + R_BX:
2469 rm = 0;
2470 break;
2471 case R_DI * 256 + R_BX:
2472 rm = 1;
2473 break;
2474 case R_SI * 256 + R_BP:
2475 rm = 2;
2476 break;
2477 case R_DI * 256 + R_BP:
2478 rm = 3;
2479 break;
2480 } else
2481 switch (b) {
2482 case R_SI:
2483 rm = 4;
2484 break;
2485 case R_DI:
2486 rm = 5;
2487 break;
2488 case R_BP:
2489 rm = 6;
2490 break;
2491 case R_BX:
2492 rm = 7;
2493 break;
2494 }
2495 if (rm == -1) /* can't happen, in theory */
2496 goto err; /* so panic if it does */
2497
2498 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2499 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2500 mod = 0;
2501 else if (input->eaflags & EAF_BYTEOFFS ||
2502 (o >= -128 && o <= 127 && seg == NO_SEG &&
2503 !forw_ref && !(input->eaflags & EAF_WORDOFFS)))
2504 mod = 1;
2505 else
2506 mod = 2;
2507
2508 output->sib_present = false; /* no SIB - it's 16-bit */
2509 output->bytes = mod; /* bytes of offset needed */
2510 output->modrm = GEN_MODRM(mod, rfield, rm);
2511 }
2512 }
2513 }
2514
2515 output->size = 1 + output->sib_present + output->bytes;
2516 return output->type;
2517
2518 err:
2519 return output->type = EA_INVALID;
2520 }
2521
2522 static void add_asp(insn *ins, int addrbits)
2523 {
2524 int j, valid;
2525 int defdisp;
2526
2527 valid = (addrbits == 64) ? 64|32 : 32|16;
2528
2529 switch (ins->prefixes[PPS_ASIZE]) {
2530 case P_A16:
2531 valid &= 16;
2532 break;
2533 case P_A32:
2534 valid &= 32;
2535 break;
2536 case P_A64:
2537 valid &= 64;
2538 break;
2539 case P_ASP:
2540 valid &= (addrbits == 32) ? 16 : 32;
2541 break;
2542 default:
2543 break;
2544 }
2545
2546 for (j = 0; j < ins->operands; j++) {
2547 if (is_class(MEMORY, ins->oprs[j].type)) {
2548 opflags_t i, b;
2549
2550 /* Verify as Register */
2551 if (!is_register(ins->oprs[j].indexreg))
2552 i = 0;
2553 else
2554 i = nasm_reg_flags[ins->oprs[j].indexreg];
2555
2556 /* Verify as Register */
2557 if (!is_register(ins->oprs[j].basereg))
2558 b = 0;
2559 else
2560 b = nasm_reg_flags[ins->oprs[j].basereg];
2561
2562 if (ins->oprs[j].scale == 0)
2563 i = 0;
2564
2565 if (!i && !b) {
2566 int ds = ins->oprs[j].disp_size;
2567 if ((addrbits != 64 && ds > 8) ||
2568 (addrbits == 64 && ds == 16))
2569 valid &= ds;
2570 } else {
2571 if (!(REG16 & ~b))
2572 valid &= 16;
2573 if (!(REG32 & ~b))
2574 valid &= 32;
2575 if (!(REG64 & ~b))
2576 valid &= 64;
2577
2578 if (!(REG16 & ~i))
2579 valid &= 16;
2580 if (!(REG32 & ~i))
2581 valid &= 32;
2582 if (!(REG64 & ~i))
2583 valid &= 64;
2584 }
2585 }
2586 }
2587
2588 if (valid & addrbits) {
2589 ins->addr_size = addrbits;
2590 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2591 /* Add an address size prefix */
2592 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2593 ins->addr_size = (addrbits == 32) ? 16 : 32;
2594 } else {
2595 /* Impossible... */
2596 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2597 ins->addr_size = addrbits; /* Error recovery */
2598 }
2599
2600 defdisp = ins->addr_size == 16 ? 16 : 32;
2601
2602 for (j = 0; j < ins->operands; j++) {
2603 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2604 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2605 /*
2606 * mem_offs sizes must match the address size; if not,
2607 * strip the MEM_OFFS bit and match only EA instructions
2608 */
2609 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2610 }
2611 }
2612 }
The Netwide Assembler