BR3079777: Explain %00 in documentation
[nasm.git] / opflags.h
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1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2009 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
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8 * modification, are permitted provided that the following
9 * conditions are met:
11 * * Redistributions of source code must retain the above copyright
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13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * opflags.h - operand flags
38 #ifndef NASM_OPFLAGS_H
39 #define NASM_OPFLAGS_H
41 #include "compiler.h"
44 * Here we define the operand types. These are implemented as bit
45 * masks, since some are subsets of others; e.g. AX in a MOV
46 * instruction is a special operand type, whereas AX in other
47 * contexts is just another 16-bit register. (Also, consider CL in
48 * shift instructions, DX in OUT, etc.)
50 * The basic concept here is that
51 * (class & ~operand) == 0
53 * if and only if "operand" belongs to class type "class".
55 * The bits are assigned as follows:
57 * Bits 0-7, 23, 29: sizes
58 * 0: 8 bits (BYTE)
59 * 1: 16 bits (WORD)
60 * 2: 32 bits (DWORD)
61 * 3: 64 bits (QWORD)
62 * 4: 80 bits (TWORD)
63 * 5: FAR
64 * 6: NEAR
65 * 7: SHORT
66 * 23: 256 bits (YWORD)
67 * 29: 128 bits (OWORD)
69 * Bits 8-11 modifiers
70 * 8: TO
71 * 9: COLON
72 * 10: STRICT
73 * 11: (reserved)
75 * Bits 12-15: type of operand
76 * 12: REGISTER
77 * 13: IMMEDIATE
78 * 14: MEMORY (always has REGMEM attribute as well)
79 * 15: REGMEM (valid EA operand)
81 * Bits 16-19, 28: subclasses
82 * With REG_CDT:
83 * 16: REG_CREG (CRx)
84 * 17: REG_DREG (DRx)
85 * 18: REG_TREG (TRx)
87 * With REG_GPR:
88 * 16: REG_ACCUM (AL, AX, EAX, RAX)
89 * 17: REG_COUNT (CL, CX, ECX, RCX)
90 * 18: REG_DATA (DL, DX, EDX, RDX)
91 * 19: REG_HIGH (AH, CH, DH, BH)
92 * 28: REG_NOTACC (not REG_ACCUM)
94 * With REG_SREG:
95 * 16: REG_CS
96 * 17: REG_DESS (DS, ES, SS)
97 * 18: REG_FSGS
98 * 19: REG_SEG67
100 * With FPUREG:
101 * 16: FPU0
103 * With XMMREG:
104 * 16: XMM0
106 * With YMMREG:
107 * 16: YMM0
109 * With MEMORY:
110 * 16: MEM_OFFS (this is a simple offset)
111 * 17: IP_REL (IP-relative offset)
113 * With IMMEDIATE:
114 * 16: UNITY (1)
115 * 17: BYTENESS16 (-128..127)
116 * 18: BYTENESS32 (-128..127)
117 * 19: BYTENESS64 (-128..127)
119 * Bits 20-22, 24-27: register classes
120 * 20: REG_CDT (CRx, DRx, TRx)
121 * 21: RM_GPR (REG_GPR) (integer register)
122 * 22: REG_SREG
123 * 24: FPUREG
124 * 25: RM_MMX (MMXREG)
125 * 26: RM_XMM (XMMREG)
126 * 27: RM_YMM (YMMREG)
128 * Bit 31 is currently unallocated.
130 * 30: SAME_AS
131 * Special flag only used in instruction patterns; means this operand
132 * has to be identical to another operand. Currently only supported
133 * for registers.
136 typedef uint32_t opflags_t;
138 /* Size, and other attributes, of the operand */
139 #define BITS8 0x00000001U
140 #define BITS16 0x00000002U
141 #define BITS32 0x00000004U
142 #define BITS64 0x00000008U /* x64 and FPU only */
143 #define BITS80 0x00000010U /* FPU only */
144 #define BITS128 0x20000000U
145 #define BITS256 0x00800000U
146 #define FAR 0x00000020U /* grotty: this means 16:16 or */
147 /* 16:32, like in CALL/JMP */
148 #define NEAR 0x00000040U
149 #define SHORT 0x00000080U /* and this means what it says :) */
151 #define SIZE_MASK 0x208000FFU /* all the size attributes */
153 /* Modifiers */
154 #define MODIFIER_MASK 0x00000f00U
155 #define TO 0x00000100U /* reverse effect in FADD, FSUB &c */
156 #define COLON 0x00000200U /* operand is followed by a colon */
157 #define STRICT 0x00000400U /* do not optimize this operand */
159 /* Type of operand: memory reference, register, etc. */
160 #define OPTYPE_MASK 0x0000f000U
161 #define REGISTER 0x00001000U /* register number in 'basereg' */
162 #define IMMEDIATE 0x00002000U
163 #define MEMORY 0x0000c000U
164 #define REGMEM 0x00008000U /* for r/m, ie EA, operands */
166 #define is_class(class, op) (!((opflags_t)(class) & ~(opflags_t)(op)))
168 /* Register classes */
169 #define REG_EA 0x00009000U /* 'normal' reg, qualifies as EA */
170 #define RM_GPR 0x00208000U /* integer operand */
171 #define REG_GPR 0x00209000U /* integer register */
172 #define REG8 0x00209001U /* 8-bit GPR */
173 #define REG16 0x00209002U /* 16-bit GPR */
174 #define REG32 0x00209004U /* 32-bit GPR */
175 #define REG64 0x00209008U /* 64-bit GPR */
176 #define FPUREG 0x01001000U /* floating point stack registers */
177 #define FPU0 0x01011000U /* FPU stack register zero */
178 #define RM_MMX 0x02008000U /* MMX operand */
179 #define MMXREG 0x02009000U /* MMX register */
180 #define RM_XMM 0x04008000U /* XMM (SSE) operand */
181 #define XMMREG 0x04009000U /* XMM (SSE) register */
182 #define XMM0 0x04019000U /* XMM register zero */
183 #define RM_YMM 0x08008000U /* YMM (AVX) operand */
184 #define YMMREG 0x08009000U /* YMM (AVX) register */
185 #define YMM0 0x08019000U /* YMM register zero */
186 #define REG_CDT 0x00101004U /* CRn, DRn and TRn */
187 #define REG_CREG 0x00111004U /* CRn */
188 #define REG_DREG 0x00121004U /* DRn */
189 #define REG_TREG 0x00141004U /* TRn */
190 #define REG_SREG 0x00401002U /* any segment register */
191 #define REG_CS 0x00411002U /* CS */
192 #define REG_DESS 0x00421002U /* DS, ES, SS */
193 #define REG_FSGS 0x00441002U /* FS, GS */
194 #define REG_SEG67 0x00481002U /* Unimplemented segment registers */
196 #define REG_RIP 0x00801008U /* RIP relative addressing */
197 #define REG_EIP 0x00801004U /* EIP relative addressing */
199 /* Special GPRs */
200 #define REG_SMASK 0x100f0000U /* a mask for the following */
201 #define REG_ACCUM 0x00219000U /* accumulator: AL, AX, EAX, RAX */
202 #define REG_AL 0x00219001U
203 #define REG_AX 0x00219002U
204 #define REG_EAX 0x00219004U
205 #define REG_RAX 0x00219008U
206 #define REG_COUNT 0x10229000U /* counter: CL, CX, ECX, RCX */
207 #define REG_CL 0x10229001U
208 #define REG_CX 0x10229002U
209 #define REG_ECX 0x10229004U
210 #define REG_RCX 0x10229008U
211 #define REG_DL 0x10249001U /* data: DL, DX, EDX, RDX */
212 #define REG_DX 0x10249002U
213 #define REG_EDX 0x10249004U
214 #define REG_RDX 0x10249008U
215 #define REG_HIGH 0x10289001U /* high regs: AH, CH, DH, BH */
216 #define REG_NOTACC 0x10000000U /* non-accumulator register */
217 #define REG8NA 0x10209001U /* 8-bit non-acc GPR */
218 #define REG16NA 0x10209002U /* 16-bit non-acc GPR */
219 #define REG32NA 0x10209004U /* 32-bit non-acc GPR */
220 #define REG64NA 0x10209008U /* 64-bit non-acc GPR */
222 /* special types of EAs */
223 #define MEM_OFFS 0x0001c000U /* simple [address] offset - absolute! */
224 #define IP_REL 0x0002c000U /* IP-relative offset */
226 /* memory which matches any type of r/m operand */
227 #define MEMORY_ANY (MEMORY|RM_GPR|RM_MMX|RM_XMM|RM_YMM)
229 /* special type of immediate operand */
230 #define UNITY 0x00012000U /* for shift/rotate instructions */
231 #define SBYTE16 0x00022000U /* for op r16,immediate instrs. */
232 #define SBYTE32 0x00042000U /* for op r32,immediate instrs. */
233 #define SBYTE64 0x00082000U /* for op r64,immediate instrs. */
234 #define BYTENESS 0x000e0000U /* for testing for byteness */
236 /* special flags */
237 #define SAME_AS 0x40000000U
239 #endif /* NASM_OPFLAGS_H */