1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2016 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * assemble.c code generation for the Netwide Assembler
37 * Bytecode specification
38 * ----------------------
41 * Codes Mnemonic Explanation
43 * \0 terminates the code. (Unless it's a literal of course.)
44 * \1..\4 that many literal bytes follow in the code stream
45 * \5 add 4 to the primary operand number (b, low octdigit)
46 * \6 add 4 to the secondary operand number (a, middle octdigit)
47 * \7 add 4 to both the primary and the secondary operand number
48 * \10..\13 a literal byte follows in the code stream, to be added
49 * to the register value of operand 0..3
50 * \14..\17 the position of index register operand in MIB (BND insns)
51 * \20..\23 ib a byte immediate operand, from operand 0..3
52 * \24..\27 ib,u a zero-extended byte immediate operand, from operand 0..3
53 * \30..\33 iw a word immediate operand, from operand 0..3
54 * \34..\37 iwd select between \3[0-3] and \4[0-3] depending on 16/32 bit
55 * assembly mode or the operand-size override on the operand
56 * \40..\43 id a long immediate operand, from operand 0..3
57 * \44..\47 iwdq select between \3[0-3], \4[0-3] and \5[4-7]
58 * depending on the address size of the instruction.
59 * \50..\53 rel8 a byte relative operand, from operand 0..3
60 * \54..\57 iq a qword immediate operand, from operand 0..3
61 * \60..\63 rel16 a word relative operand, from operand 0..3
62 * \64..\67 rel select between \6[0-3] and \7[0-3] depending on 16/32 bit
63 * assembly mode or the operand-size override on the operand
64 * \70..\73 rel32 a long relative operand, from operand 0..3
65 * \74..\77 seg a word constant, from the _segment_ part of operand 0..3
66 * \1ab a ModRM, calculated on EA in operand a, with the spare
67 * field the register value of operand b.
68 * \172\ab the register number from operand a in bits 7..4, with
69 * the 4-bit immediate from operand b in bits 3..0.
70 * \173\xab the register number from operand a in bits 7..4, with
71 * the value b in bits 3..0.
72 * \174..\177 the register number from operand 0..3 in bits 7..4, and
73 * an arbitrary value in bits 3..0 (assembled as zero.)
74 * \2ab a ModRM, calculated on EA in operand a, with the spare
75 * field equal to digit b.
77 * \240..\243 this instruction uses EVEX rather than REX or VEX/XOP, with the
78 * V field taken from operand 0..3.
79 * \250 this instruction uses EVEX rather than REX or VEX/XOP, with the
80 * V field set to 1111b.
82 * EVEX prefixes are followed by the sequence:
83 * \cm\wlp\tup where cm is:
85 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
88 * [l0] ll = 0 (.128, .lz)
91 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
93 * [w0] ww = 0 for W = 0
94 * [w1] ww = 1 for W = 1
95 * [wig] ww = 2 for W don't care (always assembled as 0)
96 * [ww] ww = 3 for W used as REX.W
98 * [p0] pp = 0 for no prefix
99 * [60] pp = 1 for legacy prefix 60
103 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
104 * (compressed displacement encoding)
106 * \254..\257 id,s a signed 32-bit operand to be extended to 64 bits.
107 * \260..\263 this instruction uses VEX/XOP rather than REX, with the
108 * V field taken from operand 0..3.
109 * \270 this instruction uses VEX/XOP rather than REX, with the
110 * V field set to 1111b.
112 * VEX/XOP prefixes are followed by the sequence:
113 * \tmm\wlp where mm is the M field; and wlp is:
115 * [l0] ll = 0 for L = 0 (.128, .lz)
116 * [l1] ll = 1 for L = 1 (.256)
117 * [lig] ll = 2 for L don't care (always assembled as 0)
119 * [w0] ww = 0 for W = 0
120 * [w1 ] ww = 1 for W = 1
121 * [wig] ww = 2 for W don't care (always assembled as 0)
122 * [ww] ww = 3 for W used as REX.W
124 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
126 * \271 hlexr instruction takes XRELEASE (F3) with or without lock
127 * \272 hlenl instruction takes XACQUIRE/XRELEASE with or without lock
128 * \273 hle instruction takes XACQUIRE/XRELEASE with lock only
129 * \274..\277 ib,s a byte immediate operand, from operand 0..3, sign-extended
130 * to the operand size (if o16/o32/o64 present) or the bit size
131 * \310 a16 indicates fixed 16-bit address size, i.e. optional 0x67.
132 * \311 a32 indicates fixed 32-bit address size, i.e. optional 0x67.
133 * \312 adf (disassembler only) invalid with non-default address size.
134 * \313 a64 indicates fixed 64-bit address size, 0x67 invalid.
135 * \314 norexb (disassembler only) invalid with REX.B
136 * \315 norexx (disassembler only) invalid with REX.X
137 * \316 norexr (disassembler only) invalid with REX.R
138 * \317 norexw (disassembler only) invalid with REX.W
139 * \320 o16 indicates fixed 16-bit operand size, i.e. optional 0x66.
140 * \321 o32 indicates fixed 32-bit operand size, i.e. optional 0x66.
141 * \322 odf indicates that this instruction is only valid when the
142 * operand size is the default (instruction to disassembler,
143 * generates no code in the assembler)
144 * \323 o64nw indicates fixed 64-bit operand size, REX on extensions only.
145 * \324 o64 indicates 64-bit operand size requiring REX prefix.
146 * \325 nohi instruction which always uses spl/bpl/sil/dil
147 * \326 nof3 instruction not valid with 0xF3 REP prefix. Hint for
148 disassembler only; for SSE instructions.
149 * \330 a literal byte follows in the code stream, to be added
150 * to the condition code value of the instruction.
151 * \331 norep instruction not valid with REP prefix. Hint for
152 * disassembler only; for SSE instructions.
153 * \332 f2i REP prefix (0xF2 byte) used as opcode extension.
154 * \333 f3i REP prefix (0xF3 byte) used as opcode extension.
155 * \334 rex.l LOCK prefix used as REX.R (used in non-64-bit mode)
156 * \335 repe disassemble a rep (0xF3 byte) prefix as repe not rep.
157 * \336 mustrep force a REP(E) prefix (0xF3) even if not specified.
158 * \337 mustrepne force a REPNE prefix (0xF2) even if not specified.
159 * \336-\337 are still listed as prefixes in the disassembler.
160 * \340 resb reserve <operand 0> bytes of uninitialized storage.
161 * Operand 0 had better be a segmentless constant.
162 * \341 wait this instruction needs a WAIT "prefix"
163 * \360 np no SSE prefix (== \364\331)
164 * \361 66 SSE prefix (== \366\331)
165 * \364 !osp operand-size prefix (0x66) not permitted
166 * \365 !asp address-size prefix (0x67) not permitted
167 * \366 operand-size prefix (0x66) used as opcode extension
168 * \367 address-size prefix (0x67) used as opcode extension
169 * \370,\371 jcc8 match only if operand 0 meets byte jump criteria.
170 * jmp8 370 is used for Jcc, 371 is used for JMP.
171 * \373 jlen assemble 0x03 if bits==16, 0x05 if bits==32;
172 * used for conditional jump over longer jump
173 * \374 vsibx|vm32x|vm64x this instruction takes an XMM VSIB memory EA
174 * \375 vsiby|vm32y|vm64y this instruction takes an YMM VSIB memory EA
175 * \376 vsibz|vm32z|vm64z this instruction takes an ZMM VSIB memory EA
178 #include "compiler.h"
183 #include <inttypes.h>
187 #include "assemble.h"
194 * Matching errors. These should be sorted so that more specific
195 * errors come later in the sequence.
208 * Matching success; the conditional ones first
210 MOK_JUMP
, /* Matching OK but needs jmp_match() */
211 MOK_GOOD
/* Matching unconditionally OK */
215 enum ea_type type
; /* what kind of EA is this? */
216 int sib_present
; /* is a SIB byte necessary? */
217 int bytes
; /* # of bytes of offset needed */
218 int size
; /* lazy - this is sib+bytes+1 */
219 uint8_t modrm
, sib
, rex
, rip
; /* the bytes themselves */
220 int8_t disp8
; /* compressed displacement for EVEX */
223 #define GEN_SIB(scale, index, base) \
224 (((scale) << 6) | ((index) << 3) | ((base)))
226 #define GEN_MODRM(mod, reg, rm) \
227 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
229 static iflag_t cpu
; /* cpu level received from nasm.c */
230 static efunc errfunc
;
231 static struct ofmt
*outfmt
;
232 static ListGen
*list
;
234 static int64_t calcsize(int32_t, int64_t, int, insn
*,
235 const struct itemplate
*);
236 static void gencode(int32_t segment
, int64_t offset
, int bits
,
237 insn
* ins
, const struct itemplate
*temp
,
239 static enum match_result
find_match(const struct itemplate
**tempp
,
241 int32_t segment
, int64_t offset
, int bits
);
242 static enum match_result
matches(const struct itemplate
*, insn
*, int bits
);
243 static opflags_t
regflag(const operand
*);
244 static int32_t regval(const operand
*);
245 static int rexflags(int, opflags_t
, int);
246 static int op_rexflags(const operand
*, int);
247 static int op_evexflags(const operand
*, int, uint8_t);
248 static void add_asp(insn
*, int);
250 static enum ea_type
process_ea(operand
*, ea
*, int, int, opflags_t
, insn
*);
252 static int has_prefix(insn
* ins
, enum prefix_pos pos
, int prefix
)
254 return ins
->prefixes
[pos
] == prefix
;
257 static void assert_no_prefix(insn
* ins
, enum prefix_pos pos
)
259 if (ins
->prefixes
[pos
])
260 errfunc(ERR_NONFATAL
, "invalid %s prefix",
261 prefix_name(ins
->prefixes
[pos
]));
264 static const char *size_name(int size
)
288 static void warn_overflow(int pass
, int size
)
290 errfunc(ERR_WARNING
| pass
| ERR_WARN_NOV
,
291 "%s data exceeds bounds", size_name(size
));
294 static void warn_overflow_const(int64_t data
, int size
)
296 if (overflow_general(data
, size
))
297 warn_overflow(ERR_PASS1
, size
);
300 static void warn_overflow_opd(const struct operand
*o
, int size
)
302 if (o
->wrt
== NO_SEG
&& o
->segment
== NO_SEG
) {
303 if (overflow_general(o
->offset
, size
))
304 warn_overflow(ERR_PASS2
, size
);
309 * Size of an address relocation, or zero if not an address
311 static int addrsize(enum out_type type
, uint64_t size
)
315 return abs((int)size
);
330 * This routine wrappers the real output format's output routine,
331 * in order to pass a copy of the data off to the listing file
332 * generator at the same time, flatten unnecessary relocations,
333 * and verify backend compatibility.
335 static void out(int64_t offset
, int32_t segto
, const void *data
,
336 enum out_type type
, uint64_t size
,
337 int32_t segment
, int32_t wrt
)
339 static int32_t lineno
= 0; /* static!!! */
340 static char *lnfname
= NULL
;
342 int asize
= addrsize(type
, size
); /* Address size in bytes */
343 const int amax
= outfmt
->maxbits
>> 3; /* Maximum address size in bytes */
345 if (type
== OUT_ADDRESS
&& segment
== NO_SEG
&& wrt
== NO_SEG
) {
347 * This is a non-relocated address, and we're going to
348 * convert it into RAWDATA format.
353 errfunc(ERR_PANIC
, "OUT_ADDRESS with size > 8");
357 WRITEADDR(q
, *(int64_t *)data
, asize
);
361 asize
= 0; /* No longer an address */
364 list
->output(offset
, data
, type
, size
);
367 * this call to src_get determines when we call the
368 * debug-format-specific "linenum" function
369 * it updates lineno and lnfname to the current values
370 * returning 0 if "same as last time", -2 if lnfname
371 * changed, and the amount by which lineno changed,
372 * if it did. thus, these variables must be static
375 if (src_get(&lineno
, &lnfname
))
376 outfmt
->current_dfmt
->linenum(lnfname
, lineno
, segto
);
378 if (asize
&& asize
> amax
) {
379 if (type
!= OUT_ADDRESS
|| (int)size
< 0) {
380 errfunc(ERR_NONFATAL
,
381 "%d-bit signed relocation unsupported by output format %s\n",
382 asize
<< 3, outfmt
->shortname
);
385 errfunc(ERR_WARNING
| ERR_WARN_ZEXTRELOC
,
386 "%d-bit unsigned relocation zero-extended from %d bits\n",
387 asize
<< 3, outfmt
->maxbits
);
388 outfmt
->output(segto
, data
, type
, amax
, segment
, wrt
);
393 segment
= wrt
= NO_SEG
;
396 outfmt
->output(segto
, data
, type
, size
, segment
, wrt
);
399 static void out_imm8(int64_t offset
, int32_t segment
,
400 struct operand
*opx
, int asize
)
402 if (opx
->segment
!= NO_SEG
) {
403 uint64_t data
= opx
->offset
;
404 out(offset
, segment
, &data
, OUT_ADDRESS
, asize
, opx
->segment
, opx
->wrt
);
406 uint8_t byte
= opx
->offset
;
407 out(offset
, segment
, &byte
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
411 static bool jmp_match(int32_t segment
, int64_t offset
, int bits
,
412 insn
* ins
, const struct itemplate
*temp
)
415 const uint8_t *code
= temp
->code
;
419 if (((c
& ~1) != 0370) || (ins
->oprs
[0].type
& STRICT
))
423 if (optimizing
< 0 && c
== 0371)
426 isize
= calcsize(segment
, offset
, bits
, ins
, temp
);
428 if (ins
->oprs
[0].opflags
& OPFLAG_UNKNOWN
)
429 /* Be optimistic in pass 1 */
432 if (ins
->oprs
[0].segment
!= segment
)
435 isize
= ins
->oprs
[0].offset
- offset
- isize
; /* isize is delta */
436 is_byte
= (isize
>= -128 && isize
<= 127); /* is it byte size? */
438 if (is_byte
&& c
== 0371 && ins
->prefixes
[PPS_REP
] == P_BND
) {
439 /* jmp short (opcode eb) cannot be used with bnd prefix. */
440 ins
->prefixes
[PPS_REP
] = P_none
;
441 errfunc(ERR_WARNING
| ERR_WARN_BND
| ERR_PASS2
,
442 "jmp short does not init bnd regs - bnd prefix dropped.");
448 int64_t assemble(int32_t segment
, int64_t offset
, int bits
, iflag_t cp
,
449 insn
* instruction
, struct ofmt
*output
, efunc error
,
452 const struct itemplate
*temp
;
457 int64_t start
= offset
;
458 int64_t wsize
; /* size for DB etc. */
460 errfunc
= error
; /* to pass to other functions */
462 outfmt
= output
; /* likewise */
463 list
= listgen
; /* and again */
465 wsize
= idata_bytes(instruction
->opcode
);
471 int32_t t
= instruction
->times
;
474 "instruction->times < 0 (%ld) in assemble()", t
);
476 while (t
--) { /* repeat TIMES times */
477 list_for_each(e
, instruction
->eops
) {
478 if (e
->type
== EOT_DB_NUMBER
) {
480 errfunc(ERR_NONFATAL
,
481 "integer supplied to a DT, DO or DY"
484 out(offset
, segment
, &e
->offset
,
485 OUT_ADDRESS
, wsize
, e
->segment
, e
->wrt
);
488 } else if (e
->type
== EOT_DB_STRING
||
489 e
->type
== EOT_DB_STRING_FREE
) {
492 out(offset
, segment
, e
->stringval
,
493 OUT_RAWDATA
, e
->stringlen
, NO_SEG
, NO_SEG
);
494 align
= e
->stringlen
% wsize
;
497 align
= wsize
- align
;
498 out(offset
, segment
, zero_buffer
,
499 OUT_RAWDATA
, align
, NO_SEG
, NO_SEG
);
501 offset
+= e
->stringlen
+ align
;
504 if (t
> 0 && t
== instruction
->times
- 1) {
506 * Dummy call to list->output to give the offset to the
509 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
510 list
->uplevel(LIST_TIMES
);
513 if (instruction
->times
> 1)
514 list
->downlevel(LIST_TIMES
);
515 return offset
- start
;
518 if (instruction
->opcode
== I_INCBIN
) {
519 const char *fname
= instruction
->eops
->stringval
;
522 fp
= fopen(fname
, "rb");
524 error(ERR_NONFATAL
, "`incbin': unable to open file `%s'",
526 } else if (fseek(fp
, 0L, SEEK_END
) < 0) {
527 error(ERR_NONFATAL
, "`incbin': unable to seek on file `%s'",
531 static char buf
[4096];
532 size_t t
= instruction
->times
;
537 if (instruction
->eops
->next
) {
538 base
= instruction
->eops
->next
->offset
;
540 if (instruction
->eops
->next
->next
&&
541 len
> (size_t)instruction
->eops
->next
->next
->offset
)
542 len
= (size_t)instruction
->eops
->next
->next
->offset
;
545 * Dummy call to list->output to give the offset to the
548 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
549 list
->uplevel(LIST_INCBIN
);
553 fseek(fp
, base
, SEEK_SET
);
557 m
= fread(buf
, 1, l
> sizeof(buf
) ? sizeof(buf
) : l
, fp
);
560 * This shouldn't happen unless the file
561 * actually changes while we are reading
565 "`incbin': unexpected EOF while"
566 " reading file `%s'", fname
);
567 t
= 0; /* Try to exit cleanly */
570 out(offset
, segment
, buf
, OUT_RAWDATA
, m
,
575 list
->downlevel(LIST_INCBIN
);
576 if (instruction
->times
> 1) {
578 * Dummy call to list->output to give the offset to the
581 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
582 list
->uplevel(LIST_TIMES
);
583 list
->downlevel(LIST_TIMES
);
586 return instruction
->times
* len
;
588 return 0; /* if we're here, there's an error */
591 /* Check to see if we need an address-size prefix */
592 add_asp(instruction
, bits
);
594 m
= find_match(&temp
, instruction
, segment
, offset
, bits
);
598 int64_t insn_size
= calcsize(segment
, offset
, bits
, instruction
, temp
);
599 itimes
= instruction
->times
;
600 if (insn_size
< 0) /* shouldn't be, on pass two */
601 error(ERR_PANIC
, "errors made it through from pass one");
604 for (j
= 0; j
< MAXPREFIX
; j
++) {
606 switch (instruction
->prefixes
[j
]) {
627 error(ERR_WARNING
| ERR_PASS2
,
628 "cs segment base generated, but will be ignored in 64-bit mode");
634 error(ERR_WARNING
| ERR_PASS2
,
635 "ds segment base generated, but will be ignored in 64-bit mode");
641 error(ERR_WARNING
| ERR_PASS2
,
642 "es segment base generated, but will be ignored in 64-bit mode");
654 error(ERR_WARNING
| ERR_PASS2
,
655 "ss segment base generated, but will be ignored in 64-bit mode");
662 "segr6 and segr7 cannot be used as prefixes");
667 "16-bit addressing is not supported "
669 } else if (bits
!= 16)
679 "64-bit addressing is only supported "
707 error(ERR_PANIC
, "invalid instruction prefix");
710 out(offset
, segment
, &c
, OUT_RAWDATA
, 1,
715 insn_end
= offset
+ insn_size
;
716 gencode(segment
, offset
, bits
, instruction
,
719 if (itimes
> 0 && itimes
== instruction
->times
- 1) {
721 * Dummy call to list->output to give the offset to the
724 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
725 list
->uplevel(LIST_TIMES
);
728 if (instruction
->times
> 1)
729 list
->downlevel(LIST_TIMES
);
730 return offset
- start
;
734 case MERR_OPSIZEMISSING
:
735 error(ERR_NONFATAL
, "operation size not specified");
737 case MERR_OPSIZEMISMATCH
:
738 error(ERR_NONFATAL
, "mismatch in operand sizes");
740 case MERR_BRNUMMISMATCH
:
742 "mismatch in the number of broadcasting elements");
745 error(ERR_NONFATAL
, "no instruction for this cpu level");
748 error(ERR_NONFATAL
, "instruction not supported in %d-bit mode",
751 case MERR_ENCMISMATCH
:
752 error(ERR_NONFATAL
, "specific encoding scheme not available");
755 error(ERR_NONFATAL
, "bnd prefix is not allowed");
758 error(ERR_NONFATAL
, "%s prefix is not allowed",
759 (has_prefix(instruction
, PPS_REP
, P_REPNE
) ?
764 "invalid combination of opcode and operands");
771 int64_t insn_size(int32_t segment
, int64_t offset
, int bits
, iflag_t cp
,
772 insn
* instruction
, efunc error
)
774 const struct itemplate
*temp
;
777 errfunc
= error
; /* to pass to other functions */
780 if (instruction
->opcode
== I_none
)
783 if (instruction
->opcode
== I_DB
|| instruction
->opcode
== I_DW
||
784 instruction
->opcode
== I_DD
|| instruction
->opcode
== I_DQ
||
785 instruction
->opcode
== I_DT
|| instruction
->opcode
== I_DO
||
786 instruction
->opcode
== I_DY
) {
788 int32_t isize
, osize
, wsize
;
791 wsize
= idata_bytes(instruction
->opcode
);
793 list_for_each(e
, instruction
->eops
) {
797 if (e
->type
== EOT_DB_NUMBER
) {
799 warn_overflow_const(e
->offset
, wsize
);
800 } else if (e
->type
== EOT_DB_STRING
||
801 e
->type
== EOT_DB_STRING_FREE
)
802 osize
= e
->stringlen
;
804 align
= (-osize
) % wsize
;
807 isize
+= osize
+ align
;
809 return isize
* instruction
->times
;
812 if (instruction
->opcode
== I_INCBIN
) {
813 const char *fname
= instruction
->eops
->stringval
;
818 fp
= fopen(fname
, "rb");
820 error(ERR_NONFATAL
, "`incbin': unable to open file `%s'",
822 else if (fseek(fp
, 0L, SEEK_END
) < 0)
823 error(ERR_NONFATAL
, "`incbin': unable to seek on file `%s'",
827 if (instruction
->eops
->next
) {
828 len
-= instruction
->eops
->next
->offset
;
829 if (instruction
->eops
->next
->next
&&
830 len
> (size_t)instruction
->eops
->next
->next
->offset
) {
831 len
= (size_t)instruction
->eops
->next
->next
->offset
;
834 val
= instruction
->times
* len
;
841 /* Check to see if we need an address-size prefix */
842 add_asp(instruction
, bits
);
844 m
= find_match(&temp
, instruction
, segment
, offset
, bits
);
846 /* we've matched an instruction. */
850 isize
= calcsize(segment
, offset
, bits
, instruction
, temp
);
853 for (j
= 0; j
< MAXPREFIX
; j
++) {
854 switch (instruction
->prefixes
[j
]) {
884 return isize
* instruction
->times
;
886 return -1; /* didn't match any instruction */
890 static void bad_hle_warn(const insn
* ins
, uint8_t hleok
)
892 enum prefixes rep_pfx
= ins
->prefixes
[PPS_REP
];
893 enum whatwarn
{ w_none
, w_lock
, w_inval
} ww
;
894 static const enum whatwarn warn
[2][4] =
896 { w_inval
, w_inval
, w_none
, w_lock
}, /* XACQUIRE */
897 { w_inval
, w_none
, w_none
, w_lock
}, /* XRELEASE */
901 n
= (unsigned int)rep_pfx
- P_XACQUIRE
;
903 return; /* Not XACQUIRE/XRELEASE */
906 if (!is_class(MEMORY
, ins
->oprs
[0].type
))
907 ww
= w_inval
; /* HLE requires operand 0 to be memory */
914 if (ins
->prefixes
[PPS_LOCK
] != P_LOCK
) {
915 errfunc(ERR_WARNING
| ERR_WARN_HLE
| ERR_PASS2
,
916 "%s with this instruction requires lock",
917 prefix_name(rep_pfx
));
922 errfunc(ERR_WARNING
| ERR_WARN_HLE
| ERR_PASS2
,
923 "%s invalid with this instruction",
924 prefix_name(rep_pfx
));
929 /* Common construct */
930 #define case3(x) case (x): case (x)+1: case (x)+2
931 #define case4(x) case3(x): case (x)+3
933 static int64_t calcsize(int32_t segment
, int64_t offset
, int bits
,
934 insn
* ins
, const struct itemplate
*temp
)
936 const uint8_t *codes
= temp
->code
;
945 bool lockcheck
= true;
946 enum reg_enum mib_index
= R_none
; /* For a separate index MIB reg form */
948 ins
->rex
= 0; /* Ensure REX is reset */
949 eat
= EA_SCALAR
; /* Expect a scalar EA */
950 memset(ins
->evex_p
, 0, 3); /* Ensure EVEX is reset */
952 if (ins
->prefixes
[PPS_OSIZE
] == P_O64
)
955 (void)segment
; /* Don't warn that this parameter is unused */
956 (void)offset
; /* Don't warn that this parameter is unused */
960 op1
= (c
& 3) + ((opex
& 1) << 2);
961 op2
= ((c
>> 3) & 3) + ((opex
& 2) << 1);
962 opx
= &ins
->oprs
[op1
];
963 opex
= 0; /* For the next iteration */
967 codes
+= c
, length
+= c
;
976 op_rexflags(opx
, REX_B
|REX_H
|REX_P
|REX_W
);
981 /* this is an index reg of MIB operand */
982 mib_index
= opx
->basereg
;
995 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
996 length
+= (opx
->type
& BITS16
) ? 2 : 4;
998 length
+= (bits
== 16) ? 2 : 4;
1006 length
+= ins
->addr_size
>> 3;
1014 length
+= 8; /* MOV reg64/imm */
1022 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
1023 length
+= (opx
->type
& BITS16
) ? 2 : 4;
1025 length
+= (bits
== 16) ? 2 : 4;
1048 ins
->vexreg
= regval(opx
);
1049 ins
->evex_p
[2] |= op_evexflags(opx
, EVEX_P2VP
, 2); /* High-16 NDS */
1050 ins
->vex_cm
= *codes
++;
1051 ins
->vex_wlp
= *codes
++;
1052 ins
->evex_tuple
= (*codes
++ - 0300);
1058 ins
->vex_cm
= *codes
++;
1059 ins
->vex_wlp
= *codes
++;
1060 ins
->evex_tuple
= (*codes
++ - 0300);
1069 ins
->vexreg
= regval(opx
);
1070 ins
->vex_cm
= *codes
++;
1071 ins
->vex_wlp
= *codes
++;
1077 ins
->vex_cm
= *codes
++;
1078 ins
->vex_wlp
= *codes
++;
1095 length
+= (bits
!= 16) && !has_prefix(ins
, PPS_ASIZE
, P_A16
);
1099 length
+= (bits
!= 32) && !has_prefix(ins
, PPS_ASIZE
, P_A32
);
1106 if (bits
!= 64 || has_prefix(ins
, PPS_ASIZE
, P_A16
) ||
1107 has_prefix(ins
, PPS_ASIZE
, P_A32
))
1116 enum prefixes pfx
= ins
->prefixes
[PPS_OSIZE
];
1120 errfunc(ERR_WARNING
| ERR_PASS2
, "invalid operand size prefix");
1122 ins
->prefixes
[PPS_OSIZE
] = P_O16
;
1128 enum prefixes pfx
= ins
->prefixes
[PPS_OSIZE
];
1132 errfunc(ERR_WARNING
| ERR_PASS2
, "invalid operand size prefix");
1134 ins
->prefixes
[PPS_OSIZE
] = P_O32
;
1176 if (!ins
->prefixes
[PPS_REP
])
1177 ins
->prefixes
[PPS_REP
] = P_REP
;
1181 if (!ins
->prefixes
[PPS_REP
])
1182 ins
->prefixes
[PPS_REP
] = P_REPNE
;
1186 if (ins
->oprs
[0].segment
!= NO_SEG
)
1187 errfunc(ERR_NONFATAL
, "attempt to reserve non-constant"
1188 " quantity of BSS space");
1190 length
+= ins
->oprs
[0].offset
;
1194 if (!ins
->prefixes
[PPS_WAIT
])
1195 ins
->prefixes
[PPS_WAIT
] = P_WAIT
;
1250 struct operand
*opy
= &ins
->oprs
[op2
];
1251 struct operand
*op_er_sae
;
1253 ea_data
.rex
= 0; /* Ensure ea.REX is initially 0 */
1256 /* pick rfield from operand b (opx) */
1257 rflags
= regflag(opx
);
1258 rfield
= nasm_regvals
[opx
->basereg
];
1264 /* EVEX.b1 : evex_brerop contains the operand position */
1265 op_er_sae
= (ins
->evex_brerop
>= 0 ?
1266 &ins
->oprs
[ins
->evex_brerop
] : NULL
);
1268 if (op_er_sae
&& (op_er_sae
->decoflags
& (ER
| SAE
))) {
1270 ins
->evex_p
[2] |= EVEX_P2B
;
1271 if (op_er_sae
->decoflags
& ER
) {
1272 /* set EVEX.RC (rounding control) */
1273 ins
->evex_p
[2] |= ((ins
->evex_rm
- BRC_RN
) << 5)
1277 /* set EVEX.L'L (vector length) */
1278 ins
->evex_p
[2] |= ((ins
->vex_wlp
<< (5 - 2)) & EVEX_P2LL
);
1279 ins
->evex_p
[1] |= ((ins
->vex_wlp
<< (7 - 4)) & EVEX_P1W
);
1280 if (opy
->decoflags
& BRDCAST_MASK
) {
1282 ins
->evex_p
[2] |= EVEX_P2B
;
1286 if (itemp_has(temp
, IF_MIB
)) {
1287 opy
->eaflags
|= EAF_MIB
;
1289 * if a separate form of MIB (ICC style) is used,
1290 * the index reg info is merged into mem operand
1292 if (mib_index
!= R_none
) {
1293 opy
->indexreg
= mib_index
;
1295 opy
->hintbase
= mib_index
;
1296 opy
->hinttype
= EAH_NOTBASE
;
1300 if (process_ea(opy
, &ea_data
, bits
,
1301 rfield
, rflags
, ins
) != eat
) {
1302 errfunc(ERR_NONFATAL
, "invalid effective address");
1305 ins
->rex
|= ea_data
.rex
;
1306 length
+= ea_data
.size
;
1312 errfunc(ERR_PANIC
, "internal instruction table corrupt"
1313 ": instruction code \\%o (0x%02X) given", c
, c
);
1318 ins
->rex
&= rex_mask
;
1320 if (ins
->rex
& REX_NH
) {
1321 if (ins
->rex
& REX_H
) {
1322 errfunc(ERR_NONFATAL
, "instruction cannot use high registers");
1325 ins
->rex
&= ~REX_P
; /* Don't force REX prefix due to high reg */
1328 switch (ins
->prefixes
[PPS_VEX
]) {
1330 if (!(ins
->rex
& REX_EV
))
1335 if (!(ins
->rex
& REX_V
))
1342 if (ins
->rex
& (REX_V
| REX_EV
)) {
1343 int bad32
= REX_R
|REX_W
|REX_X
|REX_B
;
1345 if (ins
->rex
& REX_H
) {
1346 errfunc(ERR_NONFATAL
, "cannot use high register in AVX instruction");
1349 switch (ins
->vex_wlp
& 060) {
1363 if (bits
!= 64 && ((ins
->rex
& bad32
) || ins
->vexreg
> 7)) {
1364 errfunc(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1366 } else if (!(ins
->rex
& REX_EV
) &&
1367 ((ins
->vexreg
> 15) || (ins
->evex_p
[0] & 0xf0))) {
1368 errfunc(ERR_NONFATAL
, "invalid high-16 register in non-AVX-512");
1371 if (ins
->rex
& REX_EV
)
1373 else if (ins
->vex_cm
!= 1 || (ins
->rex
& (REX_W
|REX_X
|REX_B
)) ||
1374 ins
->prefixes
[PPS_VEX
] == P_VEX3
)
1378 } else if (ins
->rex
& REX_MASK
) {
1379 if (ins
->rex
& REX_H
) {
1380 errfunc(ERR_NONFATAL
, "cannot use high register in rex instruction");
1382 } else if (bits
== 64) {
1384 } else if ((ins
->rex
& REX_L
) &&
1385 !(ins
->rex
& (REX_P
|REX_W
|REX_X
|REX_B
)) &&
1386 iflag_ffs(&cpu
) >= IF_X86_64
) {
1388 assert_no_prefix(ins
, PPS_LOCK
);
1389 lockcheck
= false; /* Already errored, no need for warning */
1392 errfunc(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1397 if (has_prefix(ins
, PPS_LOCK
, P_LOCK
) && lockcheck
&&
1398 (!itemp_has(temp
,IF_LOCK
) || !is_class(MEMORY
, ins
->oprs
[0].type
))) {
1399 errfunc(ERR_WARNING
| ERR_WARN_LOCK
| ERR_PASS2
,
1400 "instruction is not lockable");
1403 bad_hle_warn(ins
, hleok
);
1406 * when BND prefix is set by DEFAULT directive,
1407 * BND prefix is added to every appropriate instruction line
1408 * unless it is overridden by NOBND prefix.
1411 (itemp_has(temp
, IF_BND
) && !has_prefix(ins
, PPS_REP
, P_NOBND
)))
1412 ins
->prefixes
[PPS_REP
] = P_BND
;
1417 static inline unsigned int emit_rex(insn
*ins
, int32_t segment
, int64_t offset
, int bits
)
1420 if ((ins
->rex
& REX_MASK
) &&
1421 !(ins
->rex
& (REX_V
| REX_EV
)) &&
1423 int rex
= (ins
->rex
& REX_MASK
) | REX_P
;
1424 out(offset
, segment
, &rex
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1425 ins
->rex_done
= true;
1433 static void gencode(int32_t segment
, int64_t offset
, int bits
,
1434 insn
* ins
, const struct itemplate
*temp
,
1442 struct operand
*opx
;
1443 const uint8_t *codes
= temp
->code
;
1445 enum ea_type eat
= EA_SCALAR
;
1447 ins
->rex_done
= false;
1451 op1
= (c
& 3) + ((opex
& 1) << 2);
1452 op2
= ((c
>> 3) & 3) + ((opex
& 2) << 1);
1453 opx
= &ins
->oprs
[op1
];
1454 opex
= 0; /* For the next iteration */
1461 offset
+= emit_rex(ins
, segment
, offset
, bits
);
1462 out(offset
, segment
, codes
, OUT_RAWDATA
, c
, NO_SEG
, NO_SEG
);
1474 offset
+= emit_rex(ins
, segment
, offset
, bits
);
1475 bytes
[0] = *codes
++ + (regval(opx
) & 7);
1476 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1484 if (opx
->offset
< -256 || opx
->offset
> 255) {
1485 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1486 "byte value exceeds bounds");
1488 out_imm8(offset
, segment
, opx
, -1);
1493 if (opx
->offset
< 0 || opx
->offset
> 255)
1494 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1495 "unsigned byte value exceeds bounds");
1496 out_imm8(offset
, segment
, opx
, 1);
1501 warn_overflow_opd(opx
, 2);
1503 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1504 opx
->segment
, opx
->wrt
);
1509 if (opx
->type
& (BITS16
| BITS32
))
1510 size
= (opx
->type
& BITS16
) ? 2 : 4;
1512 size
= (bits
== 16) ? 2 : 4;
1513 warn_overflow_opd(opx
, size
);
1515 out(offset
, segment
, &data
, OUT_ADDRESS
, size
,
1516 opx
->segment
, opx
->wrt
);
1521 warn_overflow_opd(opx
, 4);
1523 out(offset
, segment
, &data
, OUT_ADDRESS
, 4,
1524 opx
->segment
, opx
->wrt
);
1530 size
= ins
->addr_size
>> 3;
1531 warn_overflow_opd(opx
, size
);
1532 out(offset
, segment
, &data
, OUT_ADDRESS
, size
,
1533 opx
->segment
, opx
->wrt
);
1538 if (opx
->segment
!= segment
) {
1540 out(offset
, segment
, &data
,
1541 OUT_REL1ADR
, insn_end
- offset
,
1542 opx
->segment
, opx
->wrt
);
1544 data
= opx
->offset
- insn_end
;
1545 if (data
> 127 || data
< -128)
1546 errfunc(ERR_NONFATAL
, "short jump is out of range");
1547 out(offset
, segment
, &data
,
1548 OUT_ADDRESS
, 1, NO_SEG
, NO_SEG
);
1554 data
= (int64_t)opx
->offset
;
1555 out(offset
, segment
, &data
, OUT_ADDRESS
, 8,
1556 opx
->segment
, opx
->wrt
);
1561 if (opx
->segment
!= segment
) {
1563 out(offset
, segment
, &data
,
1564 OUT_REL2ADR
, insn_end
- offset
,
1565 opx
->segment
, opx
->wrt
);
1567 data
= opx
->offset
- insn_end
;
1568 out(offset
, segment
, &data
,
1569 OUT_ADDRESS
, 2, NO_SEG
, NO_SEG
);
1575 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
1576 size
= (opx
->type
& BITS16
) ? 2 : 4;
1578 size
= (bits
== 16) ? 2 : 4;
1579 if (opx
->segment
!= segment
) {
1581 out(offset
, segment
, &data
,
1582 size
== 2 ? OUT_REL2ADR
: OUT_REL4ADR
,
1583 insn_end
- offset
, opx
->segment
, opx
->wrt
);
1585 data
= opx
->offset
- insn_end
;
1586 out(offset
, segment
, &data
,
1587 OUT_ADDRESS
, size
, NO_SEG
, NO_SEG
);
1593 if (opx
->segment
!= segment
) {
1595 out(offset
, segment
, &data
,
1596 OUT_REL4ADR
, insn_end
- offset
,
1597 opx
->segment
, opx
->wrt
);
1599 data
= opx
->offset
- insn_end
;
1600 out(offset
, segment
, &data
,
1601 OUT_ADDRESS
, 4, NO_SEG
, NO_SEG
);
1607 if (opx
->segment
== NO_SEG
)
1608 errfunc(ERR_NONFATAL
, "value referenced by FAR is not"
1611 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1612 outfmt
->segbase(1 + opx
->segment
),
1619 opx
= &ins
->oprs
[c
>> 3];
1620 bytes
[0] = nasm_regvals
[opx
->basereg
] << 4;
1621 opx
= &ins
->oprs
[c
& 7];
1622 if (opx
->segment
!= NO_SEG
|| opx
->wrt
!= NO_SEG
) {
1623 errfunc(ERR_NONFATAL
,
1624 "non-absolute expression not permitted as argument %d",
1627 if (opx
->offset
& ~15) {
1628 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1629 "four-bit argument exceeds bounds");
1631 bytes
[0] |= opx
->offset
& 15;
1633 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1639 opx
= &ins
->oprs
[c
>> 4];
1640 bytes
[0] = nasm_regvals
[opx
->basereg
] << 4;
1642 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1647 bytes
[0] = nasm_regvals
[opx
->basereg
] << 4;
1648 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1654 if (opx
->wrt
== NO_SEG
&& opx
->segment
== NO_SEG
&&
1655 (int32_t)data
!= (int64_t)data
) {
1656 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1657 "signed dword immediate exceeds bounds");
1659 out(offset
, segment
, &data
, OUT_ADDRESS
, -4,
1660 opx
->segment
, opx
->wrt
);
1667 ins
->evex_p
[2] |= op_evexflags(&ins
->oprs
[0],
1668 EVEX_P2Z
| EVEX_P2AAA
, 2);
1669 ins
->evex_p
[2] ^= EVEX_P2VP
; /* 1's complement */
1671 /* EVEX.X can be set by either REX or EVEX for different reasons */
1672 bytes
[1] = ((((ins
->rex
& 7) << 5) |
1673 (ins
->evex_p
[0] & (EVEX_P0X
| EVEX_P0RP
))) ^ 0xf0) |
1675 bytes
[2] = ((ins
->rex
& REX_W
) << (7 - 3)) |
1676 ((~ins
->vexreg
& 15) << 3) |
1677 (1 << 2) | (ins
->vex_wlp
& 3);
1678 bytes
[3] = ins
->evex_p
[2];
1679 out(offset
, segment
, &bytes
, OUT_RAWDATA
, 4, NO_SEG
, NO_SEG
);
1686 if (ins
->vex_cm
!= 1 || (ins
->rex
& (REX_W
|REX_X
|REX_B
)) ||
1687 ins
->prefixes
[PPS_VEX
] == P_VEX3
) {
1688 bytes
[0] = (ins
->vex_cm
>> 6) ? 0x8f : 0xc4;
1689 bytes
[1] = (ins
->vex_cm
& 31) | ((~ins
->rex
& 7) << 5);
1690 bytes
[2] = ((ins
->rex
& REX_W
) << (7-3)) |
1691 ((~ins
->vexreg
& 15)<< 3) | (ins
->vex_wlp
& 07);
1692 out(offset
, segment
, &bytes
, OUT_RAWDATA
, 3, NO_SEG
, NO_SEG
);
1696 bytes
[1] = ((~ins
->rex
& REX_R
) << (7-2)) |
1697 ((~ins
->vexreg
& 15) << 3) | (ins
->vex_wlp
& 07);
1698 out(offset
, segment
, &bytes
, OUT_RAWDATA
, 2, NO_SEG
, NO_SEG
);
1713 if (ins
->rex
& REX_W
)
1715 else if (ins
->prefixes
[PPS_OSIZE
] == P_O16
)
1717 else if (ins
->prefixes
[PPS_OSIZE
] == P_O32
)
1722 um
= (uint64_t)2 << (s
-1);
1725 if (uv
> 127 && uv
< (uint64_t)-128 &&
1726 (uv
< um
-128 || uv
> um
-1)) {
1727 /* If this wasn't explicitly byte-sized, warn as though we
1728 * had fallen through to the imm16/32/64 case.
1730 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1731 "%s value exceeds bounds",
1732 (opx
->type
& BITS8
) ? "signed byte" :
1737 if (opx
->segment
!= NO_SEG
) {
1739 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1740 opx
->segment
, opx
->wrt
);
1743 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1754 if (bits
== 32 && !has_prefix(ins
, PPS_ASIZE
, P_A16
)) {
1756 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1763 if (bits
!= 32 && !has_prefix(ins
, PPS_ASIZE
, P_A32
)) {
1765 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1800 *bytes
= *codes
++ ^ get_cond_opcode(ins
->condition
);
1801 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1810 *bytes
= c
- 0332 + 0xF2;
1811 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1816 if (ins
->rex
& REX_R
) {
1818 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1821 ins
->rex
&= ~(REX_L
|REX_R
);
1832 if (ins
->oprs
[0].segment
!= NO_SEG
)
1833 errfunc(ERR_PANIC
, "non-constant BSS size in pass two");
1835 int64_t size
= ins
->oprs
[0].offset
;
1837 out(offset
, segment
, NULL
,
1838 OUT_RESERVE
, size
, NO_SEG
, NO_SEG
);
1851 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1861 *bytes
= c
- 0366 + 0x66;
1862 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1870 *bytes
= bits
== 16 ? 3 : 5;
1871 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1905 struct operand
*opy
= &ins
->oprs
[op2
];
1908 /* pick rfield from operand b (opx) */
1909 rflags
= regflag(opx
);
1910 rfield
= nasm_regvals
[opx
->basereg
];
1912 /* rfield is constant */
1917 if (process_ea(opy
, &ea_data
, bits
,
1918 rfield
, rflags
, ins
) != eat
)
1919 errfunc(ERR_NONFATAL
, "invalid effective address");
1922 *p
++ = ea_data
.modrm
;
1923 if (ea_data
.sib_present
)
1927 out(offset
, segment
, bytes
, OUT_RAWDATA
, s
, NO_SEG
, NO_SEG
);
1930 * Make sure the address gets the right offset in case
1931 * the line breaks in the .lst file (BR 1197827)
1936 if (ea_data
.bytes
) {
1937 /* use compressed displacement, if available */
1938 data
= ea_data
.disp8
? ea_data
.disp8
: opy
->offset
;
1941 if (opy
->segment
== segment
) {
1943 if (overflow_signed(data
, ea_data
.bytes
))
1944 warn_overflow(ERR_PASS2
, ea_data
.bytes
);
1945 out(offset
, segment
, &data
, OUT_ADDRESS
,
1946 ea_data
.bytes
, NO_SEG
, NO_SEG
);
1948 /* overflow check in output/linker? */
1949 out(offset
, segment
, &data
, OUT_REL4ADR
,
1950 insn_end
- offset
, opy
->segment
, opy
->wrt
);
1953 int asize
= ins
->addr_size
>> 3;
1954 int atype
= ea_data
.bytes
;
1956 if (overflow_general(data
, asize
) ||
1957 signed_bits(data
, ins
->addr_size
) !=
1958 signed_bits(data
, ea_data
.bytes
<< 3))
1959 warn_overflow(ERR_PASS2
, ea_data
.bytes
);
1961 if (asize
> ea_data
.bytes
) {
1963 * If the address isn't the full width of
1964 * the address size, treat is as signed...
1969 out(offset
, segment
, &data
, OUT_ADDRESS
,
1970 atype
, opy
->segment
, opy
->wrt
);
1978 errfunc(ERR_PANIC
, "internal instruction table corrupt"
1979 ": instruction code \\%o (0x%02X) given", c
, c
);
1985 static opflags_t
regflag(const operand
* o
)
1987 if (!is_register(o
->basereg
))
1988 errfunc(ERR_PANIC
, "invalid operand passed to regflag()");
1989 return nasm_reg_flags
[o
->basereg
];
1992 static int32_t regval(const operand
* o
)
1994 if (!is_register(o
->basereg
))
1995 errfunc(ERR_PANIC
, "invalid operand passed to regval()");
1996 return nasm_regvals
[o
->basereg
];
1999 static int op_rexflags(const operand
* o
, int mask
)
2004 if (!is_register(o
->basereg
))
2005 errfunc(ERR_PANIC
, "invalid operand passed to op_rexflags()");
2007 flags
= nasm_reg_flags
[o
->basereg
];
2008 val
= nasm_regvals
[o
->basereg
];
2010 return rexflags(val
, flags
, mask
);
2013 static int rexflags(int val
, opflags_t flags
, int mask
)
2017 if (val
>= 0 && (val
& 8))
2018 rex
|= REX_B
|REX_X
|REX_R
;
2021 if (!(REG_HIGH
& ~flags
)) /* AH, CH, DH, BH */
2023 else if (!(REG8
& ~flags
) && val
>= 4) /* SPL, BPL, SIL, DIL */
2029 static int evexflags(int val
, decoflags_t deco
,
2030 int mask
, uint8_t byte
)
2036 if (val
>= 0 && (val
& 16))
2037 evex
|= (EVEX_P0RP
| EVEX_P0X
);
2040 if (val
>= 0 && (val
& 16))
2044 if (deco
& OPMASK_MASK
)
2045 evex
|= deco
& EVEX_P2AAA
;
2051 static int op_evexflags(const operand
* o
, int mask
, uint8_t byte
)
2055 val
= nasm_regvals
[o
->basereg
];
2057 return evexflags(val
, o
->decoflags
, mask
, byte
);
2060 static enum match_result
find_match(const struct itemplate
**tempp
,
2062 int32_t segment
, int64_t offset
, int bits
)
2064 const struct itemplate
*temp
;
2065 enum match_result m
, merr
;
2066 opflags_t xsizeflags
[MAX_OPERANDS
];
2067 bool opsizemissing
= false;
2068 int8_t broadcast
= instruction
->evex_brerop
;
2071 /* broadcasting uses a different data element size */
2072 for (i
= 0; i
< instruction
->operands
; i
++)
2074 xsizeflags
[i
] = instruction
->oprs
[i
].decoflags
& BRSIZE_MASK
;
2076 xsizeflags
[i
] = instruction
->oprs
[i
].type
& SIZE_MASK
;
2078 merr
= MERR_INVALOP
;
2080 for (temp
= nasm_instructions
[instruction
->opcode
];
2081 temp
->opcode
!= I_none
; temp
++) {
2082 m
= matches(temp
, instruction
, bits
);
2083 if (m
== MOK_JUMP
) {
2084 if (jmp_match(segment
, offset
, bits
, instruction
, temp
))
2088 } else if (m
== MERR_OPSIZEMISSING
&& !itemp_has(temp
, IF_SX
)) {
2090 * Missing operand size and a candidate for fuzzy matching...
2092 for (i
= 0; i
< temp
->operands
; i
++)
2094 xsizeflags
[i
] |= temp
->deco
[i
] & BRSIZE_MASK
;
2096 xsizeflags
[i
] |= temp
->opd
[i
] & SIZE_MASK
;
2097 opsizemissing
= true;
2101 if (merr
== MOK_GOOD
)
2105 /* No match, but see if we can get a fuzzy operand size match... */
2109 for (i
= 0; i
< instruction
->operands
; i
++) {
2111 * We ignore extrinsic operand sizes on registers, so we should
2112 * never try to fuzzy-match on them. This also resolves the case
2113 * when we have e.g. "xmmrm128" in two different positions.
2115 if (is_class(REGISTER
, instruction
->oprs
[i
].type
))
2118 /* This tests if xsizeflags[i] has more than one bit set */
2119 if ((xsizeflags
[i
] & (xsizeflags
[i
]-1)))
2120 goto done
; /* No luck */
2122 if (i
== broadcast
) {
2123 instruction
->oprs
[i
].decoflags
|= xsizeflags
[i
];
2124 instruction
->oprs
[i
].type
|= (xsizeflags
[i
] == BR_BITS32
?
2127 instruction
->oprs
[i
].type
|= xsizeflags
[i
]; /* Set the size */
2131 /* Try matching again... */
2132 for (temp
= nasm_instructions
[instruction
->opcode
];
2133 temp
->opcode
!= I_none
; temp
++) {
2134 m
= matches(temp
, instruction
, bits
);
2135 if (m
== MOK_JUMP
) {
2136 if (jmp_match(segment
, offset
, bits
, instruction
, temp
))
2143 if (merr
== MOK_GOOD
)
2152 static uint8_t get_broadcast_num(opflags_t opflags
, opflags_t brsize
)
2154 opflags_t opsize
= opflags
& SIZE_MASK
;
2158 * Due to discontinuity between BITS64 and BITS128 (BITS80),
2159 * this cannot be a simple arithmetic calculation.
2161 if (brsize
> BITS64
)
2163 "size of broadcasting element is greater than 64 bits");
2167 brcast_num
= BITS64
/ brsize
;
2170 brcast_num
= (opsize
/ BITS128
) * (BITS64
/ brsize
) * 2;
2177 static enum match_result
matches(const struct itemplate
*itemp
,
2178 insn
*instruction
, int bits
)
2180 opflags_t size
[MAX_OPERANDS
], asize
;
2181 bool opsizemissing
= false;
2187 if (itemp
->opcode
!= instruction
->opcode
)
2188 return MERR_INVALOP
;
2191 * Count the operands
2193 if (itemp
->operands
!= instruction
->operands
)
2194 return MERR_INVALOP
;
2199 if (!(optimizing
> 0) && itemp_has(itemp
, IF_OPT
))
2200 return MERR_INVALOP
;
2205 switch (instruction
->prefixes
[PPS_VEX
]) {
2207 if (!itemp_has(itemp
, IF_EVEX
))
2208 return MERR_ENCMISMATCH
;
2212 if (!itemp_has(itemp
, IF_VEX
))
2213 return MERR_ENCMISMATCH
;
2220 * Check that no spurious colons or TOs are present
2222 for (i
= 0; i
< itemp
->operands
; i
++)
2223 if (instruction
->oprs
[i
].type
& ~itemp
->opd
[i
] & (COLON
| TO
))
2224 return MERR_INVALOP
;
2227 * Process size flags
2229 switch (itemp_smask(itemp
)) {
2230 case IF_GENBIT(IF_SB
):
2233 case IF_GENBIT(IF_SW
):
2236 case IF_GENBIT(IF_SD
):
2239 case IF_GENBIT(IF_SQ
):
2242 case IF_GENBIT(IF_SO
):
2245 case IF_GENBIT(IF_SY
):
2248 case IF_GENBIT(IF_SZ
):
2251 case IF_GENBIT(IF_SIZE
):
2272 if (itemp_armask(itemp
)) {
2273 /* S- flags only apply to a specific operand */
2274 i
= itemp_arg(itemp
);
2275 memset(size
, 0, sizeof size
);
2278 /* S- flags apply to all operands */
2279 for (i
= 0; i
< MAX_OPERANDS
; i
++)
2284 * Check that the operand flags all match up,
2285 * it's a bit tricky so lets be verbose:
2287 * 1) Find out the size of operand. If instruction
2288 * doesn't have one specified -- we're trying to
2289 * guess it either from template (IF_S* flag) or
2292 * 2) If template operand do not match the instruction OR
2293 * template has an operand size specified AND this size differ
2294 * from which instruction has (perhaps we got it from code bits)
2296 * a) Check that only size of instruction and operand is differ
2297 * other characteristics do match
2298 * b) Perhaps it's a register specified in instruction so
2299 * for such a case we just mark that operand as "size
2300 * missing" and this will turn on fuzzy operand size
2301 * logic facility (handled by a caller)
2303 for (i
= 0; i
< itemp
->operands
; i
++) {
2304 opflags_t type
= instruction
->oprs
[i
].type
;
2305 decoflags_t deco
= instruction
->oprs
[i
].decoflags
;
2306 bool is_broadcast
= deco
& BRDCAST_MASK
;
2307 uint8_t brcast_num
= 0;
2308 opflags_t template_opsize
, insn_opsize
;
2310 if (!(type
& SIZE_MASK
))
2313 insn_opsize
= type
& SIZE_MASK
;
2314 if (!is_broadcast
) {
2315 template_opsize
= itemp
->opd
[i
] & SIZE_MASK
;
2317 decoflags_t deco_brsize
= itemp
->deco
[i
] & BRSIZE_MASK
;
2319 * when broadcasting, the element size depends on
2320 * the instruction type. decorator flag should match.
2324 template_opsize
= (deco_brsize
== BR_BITS32
? BITS32
: BITS64
);
2325 /* calculate the proper number : {1to<brcast_num>} */
2326 brcast_num
= get_broadcast_num(itemp
->opd
[i
], template_opsize
);
2328 template_opsize
= 0;
2332 if ((itemp
->opd
[i
] & ~type
& ~SIZE_MASK
) ||
2333 (deco
& ~itemp
->deco
[i
] & ~BRNUM_MASK
)) {
2334 return MERR_INVALOP
;
2335 } else if (template_opsize
) {
2336 if (template_opsize
!= insn_opsize
) {
2338 return MERR_INVALOP
;
2339 } else if (!is_class(REGISTER
, type
)) {
2341 * Note: we don't honor extrinsic operand sizes for registers,
2342 * so "missing operand size" for a register should be
2343 * considered a wildcard match rather than an error.
2345 opsizemissing
= true;
2347 } else if (is_broadcast
&&
2349 (2U << ((deco
& BRNUM_MASK
) >> BRNUM_SHIFT
)))) {
2351 * broadcasting opsize matches but the number of repeated memory
2352 * element does not match.
2353 * if 64b double precision float is broadcasted to ymm (256b),
2354 * broadcasting decorator must be {1to4}.
2356 return MERR_BRNUMMISMATCH
;
2362 return MERR_OPSIZEMISSING
;
2365 * Check operand sizes
2367 if (itemp_has(itemp
, IF_SM
) || itemp_has(itemp
, IF_SM2
)) {
2368 oprs
= (itemp_has(itemp
, IF_SM2
) ? 2 : itemp
->operands
);
2369 for (i
= 0; i
< oprs
; i
++) {
2370 asize
= itemp
->opd
[i
] & SIZE_MASK
;
2372 for (i
= 0; i
< oprs
; i
++)
2378 oprs
= itemp
->operands
;
2381 for (i
= 0; i
< itemp
->operands
; i
++) {
2382 if (!(itemp
->opd
[i
] & SIZE_MASK
) &&
2383 (instruction
->oprs
[i
].type
& SIZE_MASK
& ~size
[i
]))
2384 return MERR_OPSIZEMISMATCH
;
2388 * Check template is okay at the set cpu level
2390 if (iflag_cmp_cpu_level(&insns_flags
[itemp
->iflag_idx
], &cpu
) > 0)
2394 * Verify the appropriate long mode flag.
2396 if (itemp_has(itemp
, (bits
== 64 ? IF_NOLONG
: IF_LONG
)))
2397 return MERR_BADMODE
;
2400 * If we have a HLE prefix, look for the NOHLE flag
2402 if (itemp_has(itemp
, IF_NOHLE
) &&
2403 (has_prefix(instruction
, PPS_REP
, P_XACQUIRE
) ||
2404 has_prefix(instruction
, PPS_REP
, P_XRELEASE
)))
2408 * Check if special handling needed for Jumps
2410 if ((itemp
->code
[0] & ~1) == 0370)
2414 * Check if BND prefix is allowed.
2415 * Other 0xF2 (REPNE/REPNZ) prefix is prohibited.
2417 if (!itemp_has(itemp
, IF_BND
) &&
2418 (has_prefix(instruction
, PPS_REP
, P_BND
) ||
2419 has_prefix(instruction
, PPS_REP
, P_NOBND
)))
2421 else if (itemp_has(itemp
, IF_BND
) &&
2422 (has_prefix(instruction
, PPS_REP
, P_REPNE
) ||
2423 has_prefix(instruction
, PPS_REP
, P_REPNZ
)))
2424 return MERR_BADREPNE
;
2430 * Check if ModR/M.mod should/can be 01.
2431 * - EAF_BYTEOFFS is set
2432 * - offset can fit in a byte when EVEX is not used
2433 * - offset can be compressed when EVEX is used
2435 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2436 (o >= -128 && o <= 127 && \
2437 seg == NO_SEG && !forw_ref && \
2438 !(input->eaflags & EAF_WORDOFFS) && \
2439 !(ins->rex & REX_EV)) || \
2440 (ins->rex & REX_EV && \
2441 is_disp8n(input, ins, &output->disp8)))
2443 static enum ea_type
process_ea(operand
*input
, ea
*output
, int bits
,
2444 int rfield
, opflags_t rflags
, insn
*ins
)
2446 bool forw_ref
= !!(input
->opflags
& OPFLAG_UNKNOWN
);
2447 int addrbits
= ins
->addr_size
;
2448 int eaflags
= input
->eaflags
;
2450 output
->type
= EA_SCALAR
;
2451 output
->rip
= false;
2454 /* REX flags for the rfield operand */
2455 output
->rex
|= rexflags(rfield
, rflags
, REX_R
| REX_P
| REX_W
| REX_H
);
2456 /* EVEX.R' flag for the REG operand */
2457 ins
->evex_p
[0] |= evexflags(rfield
, 0, EVEX_P0RP
, 0);
2459 if (is_class(REGISTER
, input
->type
)) {
2461 * It's a direct register.
2463 if (!is_register(input
->basereg
))
2466 if (!is_reg_class(REG_EA
, input
->basereg
))
2469 /* broadcasting is not available with a direct register operand. */
2470 if (input
->decoflags
& BRDCAST_MASK
) {
2471 nasm_error(ERR_NONFATAL
, "Broadcasting not allowed from a register");
2475 output
->rex
|= op_rexflags(input
, REX_B
| REX_P
| REX_W
| REX_H
);
2476 ins
->evex_p
[0] |= op_evexflags(input
, EVEX_P0X
, 0);
2477 output
->sib_present
= false; /* no SIB necessary */
2478 output
->bytes
= 0; /* no offset necessary either */
2479 output
->modrm
= GEN_MODRM(3, rfield
, nasm_regvals
[input
->basereg
]);
2482 * It's a memory reference.
2485 /* Embedded rounding or SAE is not available with a mem ref operand. */
2486 if (input
->decoflags
& (ER
| SAE
)) {
2487 nasm_error(ERR_NONFATAL
,
2488 "Embedded rounding is available only with reg-reg op.");
2492 if (input
->basereg
== -1 &&
2493 (input
->indexreg
== -1 || input
->scale
== 0)) {
2495 * It's a pure offset.
2497 if (bits
== 64 && ((input
->type
& IP_REL
) == IP_REL
) &&
2498 input
->segment
== NO_SEG
) {
2499 nasm_error(ERR_WARNING
| ERR_PASS1
, "absolute address can not be RIP-relative");
2500 input
->type
&= ~IP_REL
;
2501 input
->type
|= MEMORY
;
2505 !(IP_REL
& ~input
->type
) && (eaflags
& EAF_MIB
)) {
2506 nasm_error(ERR_NONFATAL
, "RIP-relative addressing is prohibited for mib.");
2510 if (eaflags
& EAF_BYTEOFFS
||
2511 (eaflags
& EAF_WORDOFFS
&&
2512 input
->disp_size
!= (addrbits
!= 16 ? 32 : 16))) {
2513 nasm_error(ERR_WARNING
| ERR_PASS1
, "displacement size ignored on absolute address");
2516 if (bits
== 64 && (~input
->type
& IP_REL
)) {
2517 output
->sib_present
= true;
2518 output
->sib
= GEN_SIB(0, 4, 5);
2520 output
->modrm
= GEN_MODRM(0, rfield
, 4);
2521 output
->rip
= false;
2523 output
->sib_present
= false;
2524 output
->bytes
= (addrbits
!= 16 ? 4 : 2);
2525 output
->modrm
= GEN_MODRM(0, rfield
, (addrbits
!= 16 ? 5 : 6));
2526 output
->rip
= bits
== 64;
2530 * It's an indirection.
2532 int i
= input
->indexreg
, b
= input
->basereg
, s
= input
->scale
;
2533 int32_t seg
= input
->segment
;
2534 int hb
= input
->hintbase
, ht
= input
->hinttype
;
2535 int t
, it
, bt
; /* register numbers */
2536 opflags_t x
, ix
, bx
; /* register flags */
2539 i
= -1; /* make this easy, at least */
2541 if (is_register(i
)) {
2542 it
= nasm_regvals
[i
];
2543 ix
= nasm_reg_flags
[i
];
2549 if (is_register(b
)) {
2550 bt
= nasm_regvals
[b
];
2551 bx
= nasm_reg_flags
[b
];
2557 /* if either one are a vector register... */
2558 if ((ix
|bx
) & (XMMREG
|YMMREG
|ZMMREG
) & ~REG_EA
) {
2559 opflags_t sok
= BITS32
| BITS64
;
2560 int32_t o
= input
->offset
;
2561 int mod
, scale
, index
, base
;
2564 * For a vector SIB, one has to be a vector and the other,
2565 * if present, a GPR. The vector must be the index operand.
2567 if (it
== -1 || (bx
& (XMMREG
|YMMREG
|ZMMREG
) & ~REG_EA
)) {
2573 t
= bt
, bt
= it
, it
= t
;
2574 x
= bx
, bx
= ix
, ix
= x
;
2580 if (!(REG64
& ~bx
) || !(REG32
& ~bx
))
2587 * While we're here, ensure the user didn't specify
2590 if (input
->disp_size
== 16 || input
->disp_size
== 64)
2593 if (addrbits
== 16 ||
2594 (addrbits
== 32 && !(sok
& BITS32
)) ||
2595 (addrbits
== 64 && !(sok
& BITS64
)))
2598 output
->type
= ((ix
& ZMMREG
& ~REG_EA
) ? EA_ZMMVSIB
2599 : ((ix
& YMMREG
& ~REG_EA
)
2600 ? EA_YMMVSIB
: EA_XMMVSIB
));
2602 output
->rex
|= rexflags(it
, ix
, REX_X
);
2603 output
->rex
|= rexflags(bt
, bx
, REX_B
);
2604 ins
->evex_p
[2] |= evexflags(it
, 0, EVEX_P2VP
, 2);
2606 index
= it
& 7; /* it is known to be != -1 */
2621 default: /* then what the smeg is it? */
2622 goto err
; /* panic */
2630 if (base
!= REG_NUM_EBP
&& o
== 0 &&
2631 seg
== NO_SEG
&& !forw_ref
&&
2632 !(eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2634 else if (IS_MOD_01())
2640 output
->sib_present
= true;
2641 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2642 output
->modrm
= GEN_MODRM(mod
, rfield
, 4);
2643 output
->sib
= GEN_SIB(scale
, index
, base
);
2644 } else if ((ix
|bx
) & (BITS32
|BITS64
)) {
2646 * it must be a 32/64-bit memory reference. Firstly we have
2647 * to check that all registers involved are type E/Rxx.
2649 opflags_t sok
= BITS32
| BITS64
;
2650 int32_t o
= input
->offset
;
2653 if (!(REG64
& ~ix
) || !(REG32
& ~ix
))
2661 goto err
; /* Invalid register */
2662 if (~sok
& bx
& SIZE_MASK
)
2663 goto err
; /* Invalid size */
2668 * While we're here, ensure the user didn't specify
2671 if (input
->disp_size
== 16 || input
->disp_size
== 64)
2674 if (addrbits
== 16 ||
2675 (addrbits
== 32 && !(sok
& BITS32
)) ||
2676 (addrbits
== 64 && !(sok
& BITS64
)))
2679 /* now reorganize base/index */
2680 if (s
== 1 && bt
!= it
&& bt
!= -1 && it
!= -1 &&
2681 ((hb
== b
&& ht
== EAH_NOTBASE
) ||
2682 (hb
== i
&& ht
== EAH_MAKEBASE
))) {
2683 /* swap if hints say so */
2684 t
= bt
, bt
= it
, it
= t
;
2685 x
= bx
, bx
= ix
, ix
= x
;
2688 if (bt
== -1 && s
== 1 && !(hb
== i
&& ht
== EAH_NOTBASE
)) {
2689 /* make single reg base, unless hint */
2690 bt
= it
, bx
= ix
, it
= -1, ix
= 0;
2692 if (eaflags
& EAF_MIB
) {
2693 /* only for mib operands */
2694 if (it
== -1 && (hb
== b
&& ht
== EAH_NOTBASE
)) {
2696 * make a single reg index [reg*1].
2697 * gas uses this form for an explicit index register.
2699 it
= bt
, ix
= bx
, bt
= -1, bx
= 0, s
= 1;
2701 if ((ht
== EAH_SUMMED
) && bt
== -1) {
2702 /* separate once summed index into [base, index] */
2703 bt
= it
, bx
= ix
, s
--;
2706 if (((s
== 2 && it
!= REG_NUM_ESP
&&
2707 (!(eaflags
& EAF_TIMESTWO
) || (ht
== EAH_SUMMED
))) ||
2708 s
== 3 || s
== 5 || s
== 9) && bt
== -1) {
2709 /* convert 3*EAX to EAX+2*EAX */
2710 bt
= it
, bx
= ix
, s
--;
2712 if (it
== -1 && (bt
& 7) != REG_NUM_ESP
&&
2713 (eaflags
& EAF_TIMESTWO
) &&
2714 (hb
== b
&& ht
== EAH_NOTBASE
)) {
2716 * convert [NOSPLIT EAX*1]
2717 * to sib format with 0x0 displacement - [EAX*1+0].
2719 it
= bt
, ix
= bx
, bt
= -1, bx
= 0, s
= 1;
2722 if (s
== 1 && it
== REG_NUM_ESP
) {
2723 /* swap ESP into base if scale is 1 */
2724 t
= it
, it
= bt
, bt
= t
;
2725 x
= ix
, ix
= bx
, bx
= x
;
2727 if (it
== REG_NUM_ESP
||
2728 (s
!= 1 && s
!= 2 && s
!= 4 && s
!= 8 && it
!= -1))
2729 goto err
; /* wrong, for various reasons */
2731 output
->rex
|= rexflags(it
, ix
, REX_X
);
2732 output
->rex
|= rexflags(bt
, bx
, REX_B
);
2734 if (it
== -1 && (bt
& 7) != REG_NUM_ESP
) {
2743 if (rm
!= REG_NUM_EBP
&& o
== 0 &&
2744 seg
== NO_SEG
&& !forw_ref
&&
2745 !(eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2747 else if (IS_MOD_01())
2753 output
->sib_present
= false;
2754 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2755 output
->modrm
= GEN_MODRM(mod
, rfield
, rm
);
2758 int mod
, scale
, index
, base
;
2778 default: /* then what the smeg is it? */
2779 goto err
; /* panic */
2787 if (base
!= REG_NUM_EBP
&& o
== 0 &&
2788 seg
== NO_SEG
&& !forw_ref
&&
2789 !(eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2791 else if (IS_MOD_01())
2797 output
->sib_present
= true;
2798 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2799 output
->modrm
= GEN_MODRM(mod
, rfield
, 4);
2800 output
->sib
= GEN_SIB(scale
, index
, base
);
2802 } else { /* it's 16-bit */
2804 int16_t o
= input
->offset
;
2806 /* check for 64-bit long mode */
2810 /* check all registers are BX, BP, SI or DI */
2811 if ((b
!= -1 && b
!= R_BP
&& b
!= R_BX
&& b
!= R_SI
&& b
!= R_DI
) ||
2812 (i
!= -1 && i
!= R_BP
&& i
!= R_BX
&& i
!= R_SI
&& i
!= R_DI
))
2815 /* ensure the user didn't specify DWORD/QWORD */
2816 if (input
->disp_size
== 32 || input
->disp_size
== 64)
2819 if (s
!= 1 && i
!= -1)
2820 goto err
; /* no can do, in 16-bit EA */
2821 if (b
== -1 && i
!= -1) {
2826 if ((b
== R_SI
|| b
== R_DI
) && i
!= -1) {
2831 /* have BX/BP as base, SI/DI index */
2833 goto err
; /* shouldn't ever happen, in theory */
2834 if (i
!= -1 && b
!= -1 &&
2835 (i
== R_BP
|| i
== R_BX
|| b
== R_SI
|| b
== R_DI
))
2836 goto err
; /* invalid combinations */
2837 if (b
== -1) /* pure offset: handled above */
2838 goto err
; /* so if it gets to here, panic! */
2842 switch (i
* 256 + b
) {
2843 case R_SI
* 256 + R_BX
:
2846 case R_DI
* 256 + R_BX
:
2849 case R_SI
* 256 + R_BP
:
2852 case R_DI
* 256 + R_BP
:
2870 if (rm
== -1) /* can't happen, in theory */
2871 goto err
; /* so panic if it does */
2873 if (o
== 0 && seg
== NO_SEG
&& !forw_ref
&& rm
!= 6 &&
2874 !(eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2876 else if (IS_MOD_01())
2881 output
->sib_present
= false; /* no SIB - it's 16-bit */
2882 output
->bytes
= mod
; /* bytes of offset needed */
2883 output
->modrm
= GEN_MODRM(mod
, rfield
, rm
);
2888 output
->size
= 1 + output
->sib_present
+ output
->bytes
;
2889 return output
->type
;
2892 return output
->type
= EA_INVALID
;
2895 static void add_asp(insn
*ins
, int addrbits
)
2900 valid
= (addrbits
== 64) ? 64|32 : 32|16;
2902 switch (ins
->prefixes
[PPS_ASIZE
]) {
2913 valid
&= (addrbits
== 32) ? 16 : 32;
2919 for (j
= 0; j
< ins
->operands
; j
++) {
2920 if (is_class(MEMORY
, ins
->oprs
[j
].type
)) {
2923 /* Verify as Register */
2924 if (!is_register(ins
->oprs
[j
].indexreg
))
2927 i
= nasm_reg_flags
[ins
->oprs
[j
].indexreg
];
2929 /* Verify as Register */
2930 if (!is_register(ins
->oprs
[j
].basereg
))
2933 b
= nasm_reg_flags
[ins
->oprs
[j
].basereg
];
2935 if (ins
->oprs
[j
].scale
== 0)
2939 int ds
= ins
->oprs
[j
].disp_size
;
2940 if ((addrbits
!= 64 && ds
> 8) ||
2941 (addrbits
== 64 && ds
== 16))
2961 if (valid
& addrbits
) {
2962 ins
->addr_size
= addrbits
;
2963 } else if (valid
& ((addrbits
== 32) ? 16 : 32)) {
2964 /* Add an address size prefix */
2965 ins
->prefixes
[PPS_ASIZE
] = (addrbits
== 32) ? P_A16
: P_A32
;;
2966 ins
->addr_size
= (addrbits
== 32) ? 16 : 32;
2969 errfunc(ERR_NONFATAL
, "impossible combination of address sizes");
2970 ins
->addr_size
= addrbits
; /* Error recovery */
2973 defdisp
= ins
->addr_size
== 16 ? 16 : 32;
2975 for (j
= 0; j
< ins
->operands
; j
++) {
2976 if (!(MEM_OFFS
& ~ins
->oprs
[j
].type
) &&
2977 (ins
->oprs
[j
].disp_size
? ins
->oprs
[j
].disp_size
: defdisp
) != ins
->addr_size
) {
2979 * mem_offs sizes must match the address size; if not,
2980 * strip the MEM_OFFS bit and match only EA instructions
2982 ins
->oprs
[j
].type
&= ~(MEM_OFFS
& ~MEMORY
);