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HLE: Implement the basic mechanism for XACQUIRE/XRELEASE
[nasm.git] / assemble.c
blob06fba53b6243924fd923617df056405aeb067e1b
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2012 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - a signed byte immediate operand, from operand 0..3
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - an unsigned byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \140..\143 - an immediate word or signed byte for operand 0..3
64 * \144..\147 - or 2 (s-field) into opcode byte if operand 0..3
65 * is a signed byte rather than a word. Opcode byte follows.
66 * \150..\153 - an immediate dword or signed byte for operand 0..3
67 * \154..\157 - or 2 (s-field) into opcode byte if operand 0..3
68 * is a signed byte rather than a dword. Opcode byte follows.
69 * \172\ab - the register number from operand a in bits 7..4, with
70 * the 4-bit immediate from operand b in bits 3..0.
71 * \173\xab - the register number from operand a in bits 7..4, with
72 * the value b in bits 3..0.
73 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
74 * an arbitrary value in bits 3..0 (assembled as zero.)
75 * \2ab - a ModRM, calculated on EA in operand a, with the spare
76 * field equal to digit b.
77 * \250..\253 - same as \150..\153, except warn if the 64-bit operand
78 * is not equal to the truncated and sign-extended 32-bit
79 * operand; used for 32-bit immediates in 64-bit mode.
80 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
81 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
82 * V field taken from operand 0..3.
83 * \270 - this instruction uses VEX/XOP rather than REX, with the
84 * V field set to 1111b.
85 *
86 * VEX/XOP prefixes are followed by the sequence:
87 * \tmm\wlp where mm is the M field; and wlp is:
88 * 00 wwl lpp
89 * [l0] ll = 0 for L = 0 (.128, .lz)
90 * [l1] ll = 1 for L = 1 (.256)
91 * [lig] ll = 2 for L don't care (always assembled as 0)
92 *
93 * [w0] ww = 0 for W = 0
94 * [w1 ] ww = 1 for W = 1
95 * [wig] ww = 2 for W don't care (always assembled as 0)
96 * [ww] ww = 3 for W used as REX.W
97 *
98 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
99 *
100 * \271 - instruction takes XRELEASE (F3) with or without lock
101 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
102 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
103 * \274..\277 - a signed byte immediate operand, from operand 0..3,
104 * which is to be extended to the operand size.
105 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
106 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
107 * \312 - (disassembler only) invalid with non-default address size.
108 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
109 * \314 - (disassembler only) invalid with REX.B
110 * \315 - (disassembler only) invalid with REX.X
111 * \316 - (disassembler only) invalid with REX.R
112 * \317 - (disassembler only) invalid with REX.W
113 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
114 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
115 * \322 - indicates that this instruction is only valid when the
116 * operand size is the default (instruction to disassembler,
117 * generates no code in the assembler)
118 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
119 * \324 - indicates 64-bit operand size requiring REX prefix.
120 * \325 - instruction which always uses spl/bpl/sil/dil
121 * \330 - a literal byte follows in the code stream, to be added
122 * to the condition code value of the instruction.
123 * \331 - instruction not valid with REP prefix. Hint for
124 * disassembler only; for SSE instructions.
125 * \332 - REP prefix (0xF2 byte) used as opcode extension.
126 * \333 - REP prefix (0xF3 byte) used as opcode extension.
127 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
128 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
129 * \336 - force a REP(E) prefix (0xF2) even if not specified.
130 * \337 - force a REPNE prefix (0xF3) even if not specified.
131 * \336-\337 are still listed as prefixes in the disassembler.
132 * \340 - reserve <operand 0> bytes of uninitialized storage.
133 * Operand 0 had better be a segmentless constant.
134 * \341 - this instruction needs a WAIT "prefix"
135 * \344,\345 - the PUSH/POP (respectively) codes for CS, DS, ES, SS
136 * (POP is never used for CS) depending on operand 0
137 * \346,\347 - the second byte of PUSH/POP codes for FS, GS, depending
138 * on operand 0
139 * \360 - no SSE prefix (== \364\331)
140 * \361 - 66 SSE prefix (== \366\331)
141 * \362 - F2 SSE prefix (== \364\332)
142 * \363 - F3 SSE prefix (== \364\333)
143 * \364 - operand-size prefix (0x66) not permitted
144 * \365 - address-size prefix (0x67) not permitted
145 * \366 - operand-size prefix (0x66) used as opcode extension
146 * \367 - address-size prefix (0x67) used as opcode extension
147 * \370,\371,\372 - match only if operand 0 meets byte jump criteria.
148 * 370 is used for Jcc, 371 is used for JMP.
149 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
150 * used for conditional jump over longer jump
151 * \374 - this instruction takes an XMM VSIB memory EA
152 * \375 - this instruction takes an YMM VSIB memory EA
153 */
154
155 #include "compiler.h"
156
157 #include <stdio.h>
158 #include <string.h>
159 #include <inttypes.h>
160
161 #include "nasm.h"
162 #include "nasmlib.h"
163 #include "assemble.h"
164 #include "insns.h"
165 #include "tables.h"
166
167 enum match_result {
168 /*
169 * Matching errors. These should be sorted so that more specific
170 * errors come later in the sequence.
171 */
172 MERR_INVALOP,
173 MERR_OPSIZEMISSING,
174 MERR_OPSIZEMISMATCH,
175 MERR_BADCPU,
176 MERR_BADMODE,
177 /*
178 * Matching success; the conditional ones first
179 */
180 MOK_JUMP, /* Matching OK but needs jmp_match() */
181 MOK_GOOD /* Matching unconditionally OK */
182 };
183
184 typedef struct {
185 enum ea_type type; /* what kind of EA is this? */
186 int sib_present; /* is a SIB byte necessary? */
187 int bytes; /* # of bytes of offset needed */
188 int size; /* lazy - this is sib+bytes+1 */
189 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
190 } ea;
191
192 #define GEN_SIB(scale, index, base) \
193 (((scale) << 6) | ((index) << 3) | ((base)))
194
195 #define GEN_MODRM(mod, reg, rm) \
196 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
197
198 static uint32_t cpu; /* cpu level received from nasm.c */
199 static efunc errfunc;
200 static struct ofmt *outfmt;
201 static ListGen *list;
202
203 static int64_t calcsize(int32_t, int64_t, int, insn *, const uint8_t *);
204 static void gencode(int32_t segment, int64_t offset, int bits,
205 insn * ins, const struct itemplate *temp,
206 int64_t insn_end);
207 static enum match_result find_match(const struct itemplate **tempp,
208 insn *instruction,
209 int32_t segment, int64_t offset, int bits);
210 static enum match_result matches(const struct itemplate *, insn *, int bits);
211 static opflags_t regflag(const operand *);
212 static int32_t regval(const operand *);
213 static int rexflags(int, opflags_t, int);
214 static int op_rexflags(const operand *, int);
215 static void add_asp(insn *, int);
216
217 static enum ea_type process_ea(operand *, ea *, int, int, int, opflags_t);
218
219 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
220 {
221 return ins->prefixes[pos] == prefix;
222 }
223
224 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
225 {
226 if (ins->prefixes[pos])
227 errfunc(ERR_NONFATAL, "invalid %s prefix",
228 prefix_name(ins->prefixes[pos]));
229 }
230
231 static const char *size_name(int size)
232 {
233 switch (size) {
234 case 1:
235 return "byte";
236 case 2:
237 return "word";
238 case 4:
239 return "dword";
240 case 8:
241 return "qword";
242 case 10:
243 return "tword";
244 case 16:
245 return "oword";
246 case 32:
247 return "yword";
248 default:
249 return "???";
250 }
251 }
252
253 static void warn_overflow(int pass, int size)
254 {
255 errfunc(ERR_WARNING | pass | ERR_WARN_NOV,
256 "%s data exceeds bounds", size_name(size));
257 }
258
259 static void warn_overflow_const(int64_t data, int size)
260 {
261 if (overflow_general(data, size))
262 warn_overflow(ERR_PASS1, size);
263 }
264
265 static void warn_overflow_opd(const struct operand *o, int size)
266 {
267 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
268 if (overflow_general(o->offset, size))
269 warn_overflow(ERR_PASS2, size);
270 }
271 }
272
273 /*
274 * This routine wrappers the real output format's output routine,
275 * in order to pass a copy of the data off to the listing file
276 * generator at the same time.
277 */
278 static void out(int64_t offset, int32_t segto, const void *data,
279 enum out_type type, uint64_t size,
280 int32_t segment, int32_t wrt)
281 {
282 static int32_t lineno = 0; /* static!!! */
283 static char *lnfname = NULL;
284 uint8_t p[8];
285
286 if (type == OUT_ADDRESS && segment == NO_SEG && wrt == NO_SEG) {
287 /*
288 * This is a non-relocated address, and we're going to
289 * convert it into RAWDATA format.
290 */
291 uint8_t *q = p;
292
293 if (size > 8) {
294 errfunc(ERR_PANIC, "OUT_ADDRESS with size > 8");
295 return;
296 }
297
298 WRITEADDR(q, *(int64_t *)data, size);
299 data = p;
300 type = OUT_RAWDATA;
301 }
302
303 list->output(offset, data, type, size);
304
305 /*
306 * this call to src_get determines when we call the
307 * debug-format-specific "linenum" function
308 * it updates lineno and lnfname to the current values
309 * returning 0 if "same as last time", -2 if lnfname
310 * changed, and the amount by which lineno changed,
311 * if it did. thus, these variables must be static
312 */
313
314 if (src_get(&lineno, &lnfname))
315 outfmt->current_dfmt->linenum(lnfname, lineno, segto);
316
317 outfmt->output(segto, data, type, size, segment, wrt);
318 }
319
320 static bool jmp_match(int32_t segment, int64_t offset, int bits,
321 insn * ins, const uint8_t *code)
322 {
323 int64_t isize;
324 uint8_t c = code[0];
325
326 if ((c != 0370 && c != 0371) || (ins->oprs[0].type & STRICT))
327 return false;
328 if (!optimizing)
329 return false;
330 if (optimizing < 0 && c == 0371)
331 return false;
332
333 isize = calcsize(segment, offset, bits, ins, code);
334
335 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
336 /* Be optimistic in pass 1 */
337 return true;
338
339 if (ins->oprs[0].segment != segment)
340 return false;
341
342 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
343 return (isize >= -128 && isize <= 127); /* is it byte size? */
344 }
345
346 int64_t assemble(int32_t segment, int64_t offset, int bits, uint32_t cp,
347 insn * instruction, struct ofmt *output, efunc error,
348 ListGen * listgen)
349 {
350 const struct itemplate *temp;
351 int j;
352 enum match_result m;
353 int64_t insn_end;
354 int32_t itimes;
355 int64_t start = offset;
356 int64_t wsize; /* size for DB etc. */
357
358 errfunc = error; /* to pass to other functions */
359 cpu = cp;
360 outfmt = output; /* likewise */
361 list = listgen; /* and again */
362
363 wsize = idata_bytes(instruction->opcode);
364 if (wsize == -1)
365 return 0;
366
367 if (wsize) {
368 extop *e;
369 int32_t t = instruction->times;
370 if (t < 0)
371 errfunc(ERR_PANIC,
372 "instruction->times < 0 (%ld) in assemble()", t);
373
374 while (t--) { /* repeat TIMES times */
375 list_for_each(e, instruction->eops) {
376 if (e->type == EOT_DB_NUMBER) {
377 if (wsize > 8) {
378 errfunc(ERR_NONFATAL,
379 "integer supplied to a DT, DO or DY"
380 " instruction");
381 } else {
382 out(offset, segment, &e->offset,
383 OUT_ADDRESS, wsize, e->segment, e->wrt);
384 offset += wsize;
385 }
386 } else if (e->type == EOT_DB_STRING ||
387 e->type == EOT_DB_STRING_FREE) {
388 int align;
389
390 out(offset, segment, e->stringval,
391 OUT_RAWDATA, e->stringlen, NO_SEG, NO_SEG);
392 align = e->stringlen % wsize;
393
394 if (align) {
395 align = wsize - align;
396 out(offset, segment, zero_buffer,
397 OUT_RAWDATA, align, NO_SEG, NO_SEG);
398 }
399 offset += e->stringlen + align;
400 }
401 }
402 if (t > 0 && t == instruction->times - 1) {
403 /*
404 * Dummy call to list->output to give the offset to the
405 * listing module.
406 */
407 list->output(offset, NULL, OUT_RAWDATA, 0);
408 list->uplevel(LIST_TIMES);
409 }
410 }
411 if (instruction->times > 1)
412 list->downlevel(LIST_TIMES);
413 return offset - start;
414 }
415
416 if (instruction->opcode == I_INCBIN) {
417 const char *fname = instruction->eops->stringval;
418 FILE *fp;
419
420 fp = fopen(fname, "rb");
421 if (!fp) {
422 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
423 fname);
424 } else if (fseek(fp, 0L, SEEK_END) < 0) {
425 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
426 fname);
427 } else {
428 static char buf[4096];
429 size_t t = instruction->times;
430 size_t base = 0;
431 size_t len;
432
433 len = ftell(fp);
434 if (instruction->eops->next) {
435 base = instruction->eops->next->offset;
436 len -= base;
437 if (instruction->eops->next->next &&
438 len > (size_t)instruction->eops->next->next->offset)
439 len = (size_t)instruction->eops->next->next->offset;
440 }
441 /*
442 * Dummy call to list->output to give the offset to the
443 * listing module.
444 */
445 list->output(offset, NULL, OUT_RAWDATA, 0);
446 list->uplevel(LIST_INCBIN);
447 while (t--) {
448 size_t l;
449
450 fseek(fp, base, SEEK_SET);
451 l = len;
452 while (l > 0) {
453 int32_t m;
454 m = fread(buf, 1, l > sizeof(buf) ? sizeof(buf) : l, fp);
455 if (!m) {
456 /*
457 * This shouldn't happen unless the file
458 * actually changes while we are reading
459 * it.
460 */
461 error(ERR_NONFATAL,
462 "`incbin': unexpected EOF while"
463 " reading file `%s'", fname);
464 t = 0; /* Try to exit cleanly */
465 break;
466 }
467 out(offset, segment, buf, OUT_RAWDATA, m,
468 NO_SEG, NO_SEG);
469 l -= m;
470 }
471 }
472 list->downlevel(LIST_INCBIN);
473 if (instruction->times > 1) {
474 /*
475 * Dummy call to list->output to give the offset to the
476 * listing module.
477 */
478 list->output(offset, NULL, OUT_RAWDATA, 0);
479 list->uplevel(LIST_TIMES);
480 list->downlevel(LIST_TIMES);
481 }
482 fclose(fp);
483 return instruction->times * len;
484 }
485 return 0; /* if we're here, there's an error */
486 }
487
488 /* Check to see if we need an address-size prefix */
489 add_asp(instruction, bits);
490
491 m = find_match(&temp, instruction, segment, offset, bits);
492
493 if (m == MOK_GOOD) {
494 /* Matches! */
495 int64_t insn_size = calcsize(segment, offset, bits,
496 instruction, temp->code);
497 itimes = instruction->times;
498 if (insn_size < 0) /* shouldn't be, on pass two */
499 error(ERR_PANIC, "errors made it through from pass one");
500 else
501 while (itimes--) {
502 for (j = 0; j < MAXPREFIX; j++) {
503 uint8_t c = 0;
504 switch (instruction->prefixes[j]) {
505 case P_WAIT:
506 c = 0x9B;
507 break;
508 case P_LOCK:
509 c = 0xF0;
510 break;
511 case P_REPNE:
512 case P_REPNZ:
513 case P_XACQUIRE:
514 c = 0xF2;
515 break;
516 case P_REPE:
517 case P_REPZ:
518 case P_REP:
519 case P_XRELEASE:
520 c = 0xF3;
521 break;
522 case R_CS:
523 if (bits == 64) {
524 error(ERR_WARNING | ERR_PASS2,
525 "cs segment base generated, but will be ignored in 64-bit mode");
526 }
527 c = 0x2E;
528 break;
529 case R_DS:
530 if (bits == 64) {
531 error(ERR_WARNING | ERR_PASS2,
532 "ds segment base generated, but will be ignored in 64-bit mode");
533 }
534 c = 0x3E;
535 break;
536 case R_ES:
537 if (bits == 64) {
538 error(ERR_WARNING | ERR_PASS2,
539 "es segment base generated, but will be ignored in 64-bit mode");
540 }
541 c = 0x26;
542 break;
543 case R_FS:
544 c = 0x64;
545 break;
546 case R_GS:
547 c = 0x65;
548 break;
549 case R_SS:
550 if (bits == 64) {
551 error(ERR_WARNING | ERR_PASS2,
552 "ss segment base generated, but will be ignored in 64-bit mode");
553 }
554 c = 0x36;
555 break;
556 case R_SEGR6:
557 case R_SEGR7:
558 error(ERR_NONFATAL,
559 "segr6 and segr7 cannot be used as prefixes");
560 break;
561 case P_A16:
562 if (bits == 64) {
563 error(ERR_NONFATAL,
564 "16-bit addressing is not supported "
565 "in 64-bit mode");
566 } else if (bits != 16)
567 c = 0x67;
568 break;
569 case P_A32:
570 if (bits != 32)
571 c = 0x67;
572 break;
573 case P_A64:
574 if (bits != 64) {
575 error(ERR_NONFATAL,
576 "64-bit addressing is only supported "
577 "in 64-bit mode");
578 }
579 break;
580 case P_ASP:
581 c = 0x67;
582 break;
583 case P_O16:
584 if (bits != 16)
585 c = 0x66;
586 break;
587 case P_O32:
588 if (bits == 16)
589 c = 0x66;
590 break;
591 case P_O64:
592 /* REX.W */
593 break;
594 case P_OSP:
595 c = 0x66;
596 break;
597 case P_none:
598 break;
599 default:
600 error(ERR_PANIC, "invalid instruction prefix");
601 }
602 if (c != 0) {
603 out(offset, segment, &c, OUT_RAWDATA, 1,
604 NO_SEG, NO_SEG);
605 offset++;
606 }
607 }
608 insn_end = offset + insn_size;
609 gencode(segment, offset, bits, instruction,
610 temp, insn_end);
611 offset += insn_size;
612 if (itimes > 0 && itimes == instruction->times - 1) {
613 /*
614 * Dummy call to list->output to give the offset to the
615 * listing module.
616 */
617 list->output(offset, NULL, OUT_RAWDATA, 0);
618 list->uplevel(LIST_TIMES);
619 }
620 }
621 if (instruction->times > 1)
622 list->downlevel(LIST_TIMES);
623 return offset - start;
624 } else {
625 /* No match */
626 switch (m) {
627 case MERR_OPSIZEMISSING:
628 error(ERR_NONFATAL, "operation size not specified");
629 break;
630 case MERR_OPSIZEMISMATCH:
631 error(ERR_NONFATAL, "mismatch in operand sizes");
632 break;
633 case MERR_BADCPU:
634 error(ERR_NONFATAL, "no instruction for this cpu level");
635 break;
636 case MERR_BADMODE:
637 error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
638 bits);
639 break;
640 default:
641 error(ERR_NONFATAL,
642 "invalid combination of opcode and operands");
643 break;
644 }
645 }
646 return 0;
647 }
648
649 int64_t insn_size(int32_t segment, int64_t offset, int bits, uint32_t cp,
650 insn * instruction, efunc error)
651 {
652 const struct itemplate *temp;
653 enum match_result m;
654
655 errfunc = error; /* to pass to other functions */
656 cpu = cp;
657
658 if (instruction->opcode == I_none)
659 return 0;
660
661 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
662 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
663 instruction->opcode == I_DT || instruction->opcode == I_DO ||
664 instruction->opcode == I_DY) {
665 extop *e;
666 int32_t isize, osize, wsize;
667
668 isize = 0;
669 wsize = idata_bytes(instruction->opcode);
670
671 list_for_each(e, instruction->eops) {
672 int32_t align;
673
674 osize = 0;
675 if (e->type == EOT_DB_NUMBER) {
676 osize = 1;
677 warn_overflow_const(e->offset, wsize);
678 } else if (e->type == EOT_DB_STRING ||
679 e->type == EOT_DB_STRING_FREE)
680 osize = e->stringlen;
681
682 align = (-osize) % wsize;
683 if (align < 0)
684 align += wsize;
685 isize += osize + align;
686 }
687 return isize * instruction->times;
688 }
689
690 if (instruction->opcode == I_INCBIN) {
691 const char *fname = instruction->eops->stringval;
692 FILE *fp;
693 int64_t val = 0;
694 size_t len;
695
696 fp = fopen(fname, "rb");
697 if (!fp)
698 error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
699 fname);
700 else if (fseek(fp, 0L, SEEK_END) < 0)
701 error(ERR_NONFATAL, "`incbin': unable to seek on file `%s'",
702 fname);
703 else {
704 len = ftell(fp);
705 if (instruction->eops->next) {
706 len -= instruction->eops->next->offset;
707 if (instruction->eops->next->next &&
708 len > (size_t)instruction->eops->next->next->offset) {
709 len = (size_t)instruction->eops->next->next->offset;
710 }
711 }
712 val = instruction->times * len;
713 }
714 if (fp)
715 fclose(fp);
716 return val;
717 }
718
719 /* Check to see if we need an address-size prefix */
720 add_asp(instruction, bits);
721
722 m = find_match(&temp, instruction, segment, offset, bits);
723 if (m == MOK_GOOD) {
724 /* we've matched an instruction. */
725 int64_t isize;
726 const uint8_t *codes = temp->code;
727 int j;
728
729 isize = calcsize(segment, offset, bits, instruction, codes);
730 if (isize < 0)
731 return -1;
732 for (j = 0; j < MAXPREFIX; j++) {
733 switch (instruction->prefixes[j]) {
734 case P_A16:
735 if (bits != 16)
736 isize++;
737 break;
738 case P_A32:
739 if (bits != 32)
740 isize++;
741 break;
742 case P_O16:
743 if (bits != 16)
744 isize++;
745 break;
746 case P_O32:
747 if (bits == 16)
748 isize++;
749 break;
750 case P_A64:
751 case P_O64:
752 case P_none:
753 break;
754 default:
755 isize++;
756 break;
757 }
758 }
759 return isize * instruction->times;
760 } else {
761 return -1; /* didn't match any instruction */
762 }
763 }
764
765 static bool possible_sbyte(operand *o)
766 {
767 return o->wrt == NO_SEG && o->segment == NO_SEG &&
768 !(o->opflags & OPFLAG_UNKNOWN) &&
769 optimizing >= 0 && !(o->type & STRICT);
770 }
771
772 /* check that opn[op] is a signed byte of size 16 or 32 */
773 static bool is_sbyte16(operand *o)
774 {
775 int16_t v;
776
777 if (!possible_sbyte(o))
778 return false;
779
780 v = o->offset;
781 return v >= -128 && v <= 127;
782 }
783
784 static bool is_sbyte32(operand *o)
785 {
786 int32_t v;
787
788 if (!possible_sbyte(o))
789 return false;
790
791 v = o->offset;
792 return v >= -128 && v <= 127;
793 }
794
795 static void bad_hle_warn(const insn * ins, uint8_t hleok)
796 {
797 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
798 enum whatwarn { w_none, w_lock, w_inval };
799 static const enum whatwarn warn[2][4] =
800 {
801 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
802 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
803 };
804 unsigned int n;
805
806 n = (unsigned int)rep_pfx - P_XACQUIRE;
807 if (n > 1)
808 return; /* Not XACQUIRE/XRELEASE */
809
810 switch (warn[n][hleok]) {
811 case w_none:
812 break;
813
814 case w_lock:
815 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
816 errfunc(ERR_WARNING | ERR_PASS2,
817 "%s with this instruction requires lock",
818 prefix_name(rep_pfx));
819 }
820 break;
821
822 case w_inval:
823 errfunc(ERR_WARNING | ERR_PASS2,
824 "%s invalid with this instruction",
825 prefix_name(rep_pfx));
826 break;
827 }
828 }
829
830 /* Common construct */
831 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
832
833 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
834 insn * ins, const uint8_t *codes)
835 {
836 int64_t length = 0;
837 uint8_t c;
838 int rex_mask = ~0;
839 int op1, op2;
840 struct operand *opx;
841 uint8_t opex = 0;
842 enum ea_type eat;
843 uint8_t hleok = 0;
844
845 ins->rex = 0; /* Ensure REX is reset */
846 eat = EA_SCALAR; /* Expect a scalar EA */
847
848 if (ins->prefixes[PPS_OSIZE] == P_O64)
849 ins->rex |= REX_W;
850
851 (void)segment; /* Don't warn that this parameter is unused */
852 (void)offset; /* Don't warn that this parameter is unused */
853
854 while (*codes) {
855 c = *codes++;
856 op1 = (c & 3) + ((opex & 1) << 2);
857 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
858 opx = &ins->oprs[op1];
859 opex = 0; /* For the next iteration */
860
861 switch (c) {
862 case 01:
863 case 02:
864 case 03:
865 case 04:
866 codes += c, length += c;
867 break;
868
869 case 05:
870 case 06:
871 case 07:
872 opex = c;
873 break;
874
875 case4(010):
876 ins->rex |=
877 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
878 codes++, length++;
879 break;
880
881 case4(014):
882 case4(020):
883 case4(024):
884 length++;
885 break;
886
887 case4(030):
888 length += 2;
889 break;
890
891 case4(034):
892 if (opx->type & (BITS16 | BITS32 | BITS64))
893 length += (opx->type & BITS16) ? 2 : 4;
894 else
895 length += (bits == 16) ? 2 : 4;
896 break;
897
898 case4(040):
899 length += 4;
900 break;
901
902 case4(044):
903 length += ins->addr_size >> 3;
904 break;
905
906 case4(050):
907 length++;
908 break;
909
910 case4(054):
911 length += 8; /* MOV reg64/imm */
912 break;
913
914 case4(060):
915 length += 2;
916 break;
917
918 case4(064):
919 if (opx->type & (BITS16 | BITS32 | BITS64))
920 length += (opx->type & BITS16) ? 2 : 4;
921 else
922 length += (bits == 16) ? 2 : 4;
923 break;
924
925 case4(070):
926 length += 4;
927 break;
928
929 case4(074):
930 length += 2;
931 break;
932
933 case4(0140):
934 length += is_sbyte16(opx) ? 1 : 2;
935 break;
936
937 case4(0144):
938 codes++;
939 length++;
940 break;
941
942 case4(0150):
943 length += is_sbyte32(opx) ? 1 : 4;
944 break;
945
946 case4(0154):
947 codes++;
948 length++;
949 break;
950
951 case 0172:
952 case 0173:
953 codes++;
954 length++;
955 break;
956
957 case4(0174):
958 length++;
959 break;
960
961 case4(0250):
962 length += is_sbyte32(opx) ? 1 : 4;
963 break;
964
965 case4(0254):
966 length += 4;
967 break;
968
969 case4(0260):
970 ins->rex |= REX_V;
971 ins->vexreg = regval(opx);
972 ins->vex_cm = *codes++;
973 ins->vex_wlp = *codes++;
974 break;
975
976 case 0270:
977 ins->rex |= REX_V;
978 ins->vexreg = 0;
979 ins->vex_cm = *codes++;
980 ins->vex_wlp = *codes++;
981 break;
982
983 case 0271:
984 case 0272:
985 case 0273:
986 hleok = c & 3;
987 break;
988
989 case4(0274):
990 length++;
991 break;
992
993 case4(0300):
994 break;
995
996 case 0310:
997 if (bits == 64)
998 return -1;
999 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1000 break;
1001
1002 case 0311:
1003 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1004 break;
1005
1006 case 0312:
1007 break;
1008
1009 case 0313:
1010 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1011 has_prefix(ins, PPS_ASIZE, P_A32))
1012 return -1;
1013 break;
1014
1015 case4(0314):
1016 break;
1017
1018 case 0320:
1019 {
1020 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1021 if (pfx == P_O16)
1022 break;
1023 if (pfx != P_none)
1024 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1025 else
1026 ins->prefixes[PPS_OSIZE] = P_O16;
1027 break;
1028 }
1029
1030 case 0321:
1031 {
1032 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1033 if (pfx == P_O32)
1034 break;
1035 if (pfx != P_none)
1036 errfunc(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1037 else
1038 ins->prefixes[PPS_OSIZE] = P_O32;
1039 break;
1040 }
1041
1042 case 0322:
1043 break;
1044
1045 case 0323:
1046 rex_mask &= ~REX_W;
1047 break;
1048
1049 case 0324:
1050 ins->rex |= REX_W;
1051 break;
1052
1053 case 0325:
1054 ins->rex |= REX_NH;
1055 break;
1056
1057 case 0330:
1058 codes++, length++;
1059 break;
1060
1061 case 0331:
1062 break;
1063
1064 case 0332:
1065 case 0333:
1066 length++;
1067 break;
1068
1069 case 0334:
1070 ins->rex |= REX_L;
1071 break;
1072
1073 case 0335:
1074 break;
1075
1076 case 0336:
1077 if (!ins->prefixes[PPS_REP])
1078 ins->prefixes[PPS_REP] = P_REP;
1079 break;
1080
1081 case 0337:
1082 if (!ins->prefixes[PPS_REP])
1083 ins->prefixes[PPS_REP] = P_REPNE;
1084 break;
1085
1086 case 0340:
1087 if (ins->oprs[0].segment != NO_SEG)
1088 errfunc(ERR_NONFATAL, "attempt to reserve non-constant"
1089 " quantity of BSS space");
1090 else
1091 length += ins->oprs[0].offset;
1092 break;
1093
1094 case 0341:
1095 if (!ins->prefixes[PPS_WAIT])
1096 ins->prefixes[PPS_WAIT] = P_WAIT;
1097 break;
1098
1099 case4(0344):
1100 length++;
1101 break;
1102
1103 case 0360:
1104 break;
1105
1106 case 0361:
1107 case 0362:
1108 case 0363:
1109 length++;
1110 break;
1111
1112 case 0364:
1113 case 0365:
1114 break;
1115
1116 case 0366:
1117 case 0367:
1118 length++;
1119 break;
1120
1121 case 0370:
1122 case 0371:
1123 case 0372:
1124 break;
1125
1126 case 0373:
1127 length++;
1128 break;
1129
1130 case 0374:
1131 eat = EA_XMMVSIB;
1132 break;
1133
1134 case 0375:
1135 eat = EA_YMMVSIB;
1136 break;
1137
1138 case4(0100):
1139 case4(0110):
1140 case4(0120):
1141 case4(0130):
1142 case4(0200):
1143 case4(0204):
1144 case4(0210):
1145 case4(0214):
1146 case4(0220):
1147 case4(0224):
1148 case4(0230):
1149 case4(0234):
1150 {
1151 ea ea_data;
1152 int rfield;
1153 opflags_t rflags;
1154 struct operand *opy = &ins->oprs[op2];
1155
1156 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1157
1158 if (c <= 0177) {
1159 /* pick rfield from operand b (opx) */
1160 rflags = regflag(opx);
1161 rfield = nasm_regvals[opx->basereg];
1162 } else {
1163 rflags = 0;
1164 rfield = c & 7;
1165 }
1166 if (process_ea(opy, &ea_data, bits,ins->addr_size,
1167 rfield, rflags) != eat) {
1168 errfunc(ERR_NONFATAL, "invalid effective address");
1169 return -1;
1170 } else {
1171 ins->rex |= ea_data.rex;
1172 length += ea_data.size;
1173 }
1174 }
1175 break;
1176
1177 default:
1178 errfunc(ERR_PANIC, "internal instruction table corrupt"
1179 ": instruction code \\%o (0x%02X) given", c, c);
1180 break;
1181 }
1182 }
1183
1184 ins->rex &= rex_mask;
1185
1186 if (ins->rex & REX_NH) {
1187 if (ins->rex & REX_H) {
1188 errfunc(ERR_NONFATAL, "instruction cannot use high registers");
1189 return -1;
1190 }
1191 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1192 }
1193
1194 if (ins->rex & REX_V) {
1195 int bad32 = REX_R|REX_W|REX_X|REX_B;
1196
1197 if (ins->rex & REX_H) {
1198 errfunc(ERR_NONFATAL, "cannot use high register in vex instruction");
1199 return -1;
1200 }
1201 switch (ins->vex_wlp & 060) {
1202 case 000:
1203 case 040:
1204 ins->rex &= ~REX_W;
1205 break;
1206 case 020:
1207 ins->rex |= REX_W;
1208 bad32 &= ~REX_W;
1209 break;
1210 case 060:
1211 /* Follow REX_W */
1212 break;
1213 }
1214
1215 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1216 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1217 return -1;
1218 }
1219 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)))
1220 length += 3;
1221 else
1222 length += 2;
1223 } else if (ins->rex & REX_REAL) {
1224 if (ins->rex & REX_H) {
1225 errfunc(ERR_NONFATAL, "cannot use high register in rex instruction");
1226 return -1;
1227 } else if (bits == 64) {
1228 length++;
1229 } else if ((ins->rex & REX_L) &&
1230 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1231 cpu >= IF_X86_64) {
1232 /* LOCK-as-REX.R */
1233 assert_no_prefix(ins, PPS_LOCK);
1234 length++;
1235 } else {
1236 errfunc(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1237 return -1;
1238 }
1239 }
1240
1241 bad_hle_warn(ins, hleok);
1242
1243 return length;
1244 }
1245
1246 #define EMIT_REX() \
1247 if (!(ins->rex & REX_V) && (ins->rex & REX_REAL) && (bits == 64)) { \
1248 ins->rex = (ins->rex & REX_REAL)|REX_P; \
1249 out(offset, segment, &ins->rex, OUT_RAWDATA, 1, NO_SEG, NO_SEG); \
1250 ins->rex = 0; \
1251 offset += 1; \
1252 }
1253
1254 static void gencode(int32_t segment, int64_t offset, int bits,
1255 insn * ins, const struct itemplate *temp,
1256 int64_t insn_end)
1257 {
1258 static const char condval[] = { /* conditional opcodes */
1259 0x7, 0x3, 0x2, 0x6, 0x2, 0x4, 0xF, 0xD, 0xC, 0xE, 0x6, 0x2,
1260 0x3, 0x7, 0x3, 0x5, 0xE, 0xC, 0xD, 0xF, 0x1, 0xB, 0x9, 0x5,
1261 0x0, 0xA, 0xA, 0xB, 0x8, 0x4
1262 };
1263 uint8_t c;
1264 uint8_t bytes[4];
1265 int64_t size;
1266 int64_t data;
1267 int op1, op2;
1268 struct operand *opx;
1269 const uint8_t *codes = temp->code;
1270 uint8_t opex = 0;
1271 enum ea_type eat = EA_SCALAR;
1272
1273 while (*codes) {
1274 c = *codes++;
1275 op1 = (c & 3) + ((opex & 1) << 2);
1276 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1277 opx = &ins->oprs[op1];
1278 opex = 0; /* For the next iteration */
1279
1280 switch (c) {
1281 case 01:
1282 case 02:
1283 case 03:
1284 case 04:
1285 EMIT_REX();
1286 out(offset, segment, codes, OUT_RAWDATA, c, NO_SEG, NO_SEG);
1287 codes += c;
1288 offset += c;
1289 break;
1290
1291 case 05:
1292 case 06:
1293 case 07:
1294 opex = c;
1295 break;
1296
1297 case4(010):
1298 EMIT_REX();
1299 bytes[0] = *codes++ + (regval(opx) & 7);
1300 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1301 offset += 1;
1302 break;
1303
1304 case4(014):
1305 /*
1306 * The test for BITS8 and SBYTE here is intended to avoid
1307 * warning on optimizer actions due to SBYTE, while still
1308 * warn on explicit BYTE directives. Also warn, obviously,
1309 * if the optimizer isn't enabled.
1310 */
1311 if (((opx->type & BITS8) ||
1312 !(opx->type & temp->opd[op1] & BYTENESS)) &&
1313 (opx->offset < -128 || opx->offset > 127)) {
1314 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1315 "signed byte value exceeds bounds");
1316 }
1317 if (opx->segment != NO_SEG) {
1318 data = opx->offset;
1319 out(offset, segment, &data, OUT_ADDRESS, 1,
1320 opx->segment, opx->wrt);
1321 } else {
1322 bytes[0] = opx->offset;
1323 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1324 NO_SEG);
1325 }
1326 offset += 1;
1327 break;
1328
1329 case4(020):
1330 if (opx->offset < -256 || opx->offset > 255) {
1331 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1332 "byte value exceeds bounds");
1333 }
1334 if (opx->segment != NO_SEG) {
1335 data = opx->offset;
1336 out(offset, segment, &data, OUT_ADDRESS, 1,
1337 opx->segment, opx->wrt);
1338 } else {
1339 bytes[0] = opx->offset;
1340 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1341 NO_SEG);
1342 }
1343 offset += 1;
1344 break;
1345
1346 case4(024):
1347 if (opx->offset < 0 || opx->offset > 255)
1348 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1349 "unsigned byte value exceeds bounds");
1350 if (opx->segment != NO_SEG) {
1351 data = opx->offset;
1352 out(offset, segment, &data, OUT_ADDRESS, 1,
1353 opx->segment, opx->wrt);
1354 } else {
1355 bytes[0] = opx->offset;
1356 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1357 NO_SEG);
1358 }
1359 offset += 1;
1360 break;
1361
1362 case4(030):
1363 warn_overflow_opd(opx, 2);
1364 data = opx->offset;
1365 out(offset, segment, &data, OUT_ADDRESS, 2,
1366 opx->segment, opx->wrt);
1367 offset += 2;
1368 break;
1369
1370 case4(034):
1371 if (opx->type & (BITS16 | BITS32))
1372 size = (opx->type & BITS16) ? 2 : 4;
1373 else
1374 size = (bits == 16) ? 2 : 4;
1375 warn_overflow_opd(opx, size);
1376 data = opx->offset;
1377 out(offset, segment, &data, OUT_ADDRESS, size,
1378 opx->segment, opx->wrt);
1379 offset += size;
1380 break;
1381
1382 case4(040):
1383 warn_overflow_opd(opx, 4);
1384 data = opx->offset;
1385 out(offset, segment, &data, OUT_ADDRESS, 4,
1386 opx->segment, opx->wrt);
1387 offset += 4;
1388 break;
1389
1390 case4(044):
1391 data = opx->offset;
1392 size = ins->addr_size >> 3;
1393 warn_overflow_opd(opx, size);
1394 out(offset, segment, &data, OUT_ADDRESS, size,
1395 opx->segment, opx->wrt);
1396 offset += size;
1397 break;
1398
1399 case4(050):
1400 if (opx->segment != segment) {
1401 data = opx->offset;
1402 out(offset, segment, &data,
1403 OUT_REL1ADR, insn_end - offset,
1404 opx->segment, opx->wrt);
1405 } else {
1406 data = opx->offset - insn_end;
1407 if (data > 127 || data < -128)
1408 errfunc(ERR_NONFATAL, "short jump is out of range");
1409 out(offset, segment, &data,
1410 OUT_ADDRESS, 1, NO_SEG, NO_SEG);
1411 }
1412 offset += 1;
1413 break;
1414
1415 case4(054):
1416 data = (int64_t)opx->offset;
1417 out(offset, segment, &data, OUT_ADDRESS, 8,
1418 opx->segment, opx->wrt);
1419 offset += 8;
1420 break;
1421
1422 case4(060):
1423 if (opx->segment != segment) {
1424 data = opx->offset;
1425 out(offset, segment, &data,
1426 OUT_REL2ADR, insn_end - offset,
1427 opx->segment, opx->wrt);
1428 } else {
1429 data = opx->offset - insn_end;
1430 out(offset, segment, &data,
1431 OUT_ADDRESS, 2, NO_SEG, NO_SEG);
1432 }
1433 offset += 2;
1434 break;
1435
1436 case4(064):
1437 if (opx->type & (BITS16 | BITS32 | BITS64))
1438 size = (opx->type & BITS16) ? 2 : 4;
1439 else
1440 size = (bits == 16) ? 2 : 4;
1441 if (opx->segment != segment) {
1442 data = opx->offset;
1443 out(offset, segment, &data,
1444 size == 2 ? OUT_REL2ADR : OUT_REL4ADR,
1445 insn_end - offset, opx->segment, opx->wrt);
1446 } else {
1447 data = opx->offset - insn_end;
1448 out(offset, segment, &data,
1449 OUT_ADDRESS, size, NO_SEG, NO_SEG);
1450 }
1451 offset += size;
1452 break;
1453
1454 case4(070):
1455 if (opx->segment != segment) {
1456 data = opx->offset;
1457 out(offset, segment, &data,
1458 OUT_REL4ADR, insn_end - offset,
1459 opx->segment, opx->wrt);
1460 } else {
1461 data = opx->offset - insn_end;
1462 out(offset, segment, &data,
1463 OUT_ADDRESS, 4, NO_SEG, NO_SEG);
1464 }
1465 offset += 4;
1466 break;
1467
1468 case4(074):
1469 if (opx->segment == NO_SEG)
1470 errfunc(ERR_NONFATAL, "value referenced by FAR is not"
1471 " relocatable");
1472 data = 0;
1473 out(offset, segment, &data, OUT_ADDRESS, 2,
1474 outfmt->segbase(1 + opx->segment),
1475 opx->wrt);
1476 offset += 2;
1477 break;
1478
1479 case4(0140):
1480 data = opx->offset;
1481 warn_overflow_opd(opx, 2);
1482 if (is_sbyte16(opx)) {
1483 bytes[0] = data;
1484 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1485 NO_SEG);
1486 offset++;
1487 } else {
1488 out(offset, segment, &data, OUT_ADDRESS, 2,
1489 opx->segment, opx->wrt);
1490 offset += 2;
1491 }
1492 break;
1493
1494 case4(0144):
1495 EMIT_REX();
1496 bytes[0] = *codes++;
1497 if (is_sbyte16(opx))
1498 bytes[0] |= 2; /* s-bit */
1499 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1500 offset++;
1501 break;
1502
1503 case4(0150):
1504 data = opx->offset;
1505 warn_overflow_opd(opx, 4);
1506 if (is_sbyte32(opx)) {
1507 bytes[0] = data;
1508 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1509 NO_SEG);
1510 offset++;
1511 } else {
1512 out(offset, segment, &data, OUT_ADDRESS, 4,
1513 opx->segment, opx->wrt);
1514 offset += 4;
1515 }
1516 break;
1517
1518 case4(0154):
1519 EMIT_REX();
1520 bytes[0] = *codes++;
1521 if (is_sbyte32(opx))
1522 bytes[0] |= 2; /* s-bit */
1523 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1524 offset++;
1525 break;
1526
1527 case 0172:
1528 c = *codes++;
1529 opx = &ins->oprs[c >> 3];
1530 bytes[0] = nasm_regvals[opx->basereg] << 4;
1531 opx = &ins->oprs[c & 7];
1532 if (opx->segment != NO_SEG || opx->wrt != NO_SEG) {
1533 errfunc(ERR_NONFATAL,
1534 "non-absolute expression not permitted as argument %d",
1535 c & 7);
1536 } else {
1537 if (opx->offset & ~15) {
1538 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1539 "four-bit argument exceeds bounds");
1540 }
1541 bytes[0] |= opx->offset & 15;
1542 }
1543 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1544 offset++;
1545 break;
1546
1547 case 0173:
1548 c = *codes++;
1549 opx = &ins->oprs[c >> 4];
1550 bytes[0] = nasm_regvals[opx->basereg] << 4;
1551 bytes[0] |= c & 15;
1552 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1553 offset++;
1554 break;
1555
1556 case4(0174):
1557 bytes[0] = nasm_regvals[opx->basereg] << 4;
1558 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1559 offset++;
1560 break;
1561
1562 case4(0250):
1563 data = opx->offset;
1564 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1565 (int32_t)data != (int64_t)data) {
1566 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1567 "signed dword immediate exceeds bounds");
1568 }
1569 if (is_sbyte32(opx)) {
1570 bytes[0] = data;
1571 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1572 NO_SEG);
1573 offset++;
1574 } else {
1575 out(offset, segment, &data, OUT_ADDRESS, 4,
1576 opx->segment, opx->wrt);
1577 offset += 4;
1578 }
1579 break;
1580
1581 case4(0254):
1582 data = opx->offset;
1583 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1584 (int32_t)data != (int64_t)data) {
1585 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1586 "signed dword immediate exceeds bounds");
1587 }
1588 out(offset, segment, &data, OUT_ADDRESS, 4,
1589 opx->segment, opx->wrt);
1590 offset += 4;
1591 break;
1592
1593 case4(0260):
1594 case 0270:
1595 codes += 2;
1596 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B))) {
1597 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1598 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1599 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1600 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1601 out(offset, segment, &bytes, OUT_RAWDATA, 3, NO_SEG, NO_SEG);
1602 offset += 3;
1603 } else {
1604 bytes[0] = 0xc5;
1605 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1606 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1607 out(offset, segment, &bytes, OUT_RAWDATA, 2, NO_SEG, NO_SEG);
1608 offset += 2;
1609 }
1610 break;
1611
1612 case4(0274):
1613 {
1614 uint64_t uv, um;
1615 int s;
1616
1617 if (ins->rex & REX_W)
1618 s = 64;
1619 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1620 s = 16;
1621 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1622 s = 32;
1623 else
1624 s = bits;
1625
1626 um = (uint64_t)2 << (s-1);
1627 uv = opx->offset;
1628
1629 if (uv > 127 && uv < (uint64_t)-128 &&
1630 (uv < um-128 || uv > um-1)) {
1631 errfunc(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1632 "signed byte value exceeds bounds");
1633 }
1634 if (opx->segment != NO_SEG) {
1635 data = uv;
1636 out(offset, segment, &data, OUT_ADDRESS, 1,
1637 opx->segment, opx->wrt);
1638 } else {
1639 bytes[0] = uv;
1640 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG,
1641 NO_SEG);
1642 }
1643 offset += 1;
1644 break;
1645 }
1646
1647 case4(0300):
1648 break;
1649
1650 case 0310:
1651 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16)) {
1652 *bytes = 0x67;
1653 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1654 offset += 1;
1655 } else
1656 offset += 0;
1657 break;
1658
1659 case 0311:
1660 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32)) {
1661 *bytes = 0x67;
1662 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1663 offset += 1;
1664 } else
1665 offset += 0;
1666 break;
1667
1668 case 0312:
1669 break;
1670
1671 case 0313:
1672 ins->rex = 0;
1673 break;
1674
1675 case4(0314):
1676 break;
1677
1678 case 0320:
1679 case 0321:
1680 break;
1681
1682 case 0322:
1683 case 0323:
1684 break;
1685
1686 case 0324:
1687 ins->rex |= REX_W;
1688 break;
1689
1690 case 0325:
1691 break;
1692
1693 case 0330:
1694 *bytes = *codes++ ^ condval[ins->condition];
1695 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1696 offset += 1;
1697 break;
1698
1699 case 0331:
1700 break;
1701
1702 case 0332:
1703 case 0333:
1704 *bytes = c - 0332 + 0xF2;
1705 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1706 offset += 1;
1707 break;
1708
1709 case 0334:
1710 if (ins->rex & REX_R) {
1711 *bytes = 0xF0;
1712 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1713 offset += 1;
1714 }
1715 ins->rex &= ~(REX_L|REX_R);
1716 break;
1717
1718 case 0335:
1719 break;
1720
1721 case 0336:
1722 case 0337:
1723 break;
1724
1725 case 0340:
1726 if (ins->oprs[0].segment != NO_SEG)
1727 errfunc(ERR_PANIC, "non-constant BSS size in pass two");
1728 else {
1729 int64_t size = ins->oprs[0].offset;
1730 if (size > 0)
1731 out(offset, segment, NULL,
1732 OUT_RESERVE, size, NO_SEG, NO_SEG);
1733 offset += size;
1734 }
1735 break;
1736
1737 case 0341:
1738 break;
1739
1740 case 0344:
1741 case 0345:
1742 bytes[0] = c & 1;
1743 switch (ins->oprs[0].basereg) {
1744 case R_CS:
1745 bytes[0] += 0x0E;
1746 break;
1747 case R_DS:
1748 bytes[0] += 0x1E;
1749 break;
1750 case R_ES:
1751 bytes[0] += 0x06;
1752 break;
1753 case R_SS:
1754 bytes[0] += 0x16;
1755 break;
1756 default:
1757 errfunc(ERR_PANIC,
1758 "bizarre 8086 segment register received");
1759 }
1760 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1761 offset++;
1762 break;
1763
1764 case 0346:
1765 case 0347:
1766 bytes[0] = c & 1;
1767 switch (ins->oprs[0].basereg) {
1768 case R_FS:
1769 bytes[0] += 0xA0;
1770 break;
1771 case R_GS:
1772 bytes[0] += 0xA8;
1773 break;
1774 default:
1775 errfunc(ERR_PANIC,
1776 "bizarre 386 segment register received");
1777 }
1778 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1779 offset++;
1780 break;
1781
1782 case 0360:
1783 break;
1784
1785 case 0361:
1786 bytes[0] = 0x66;
1787 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1788 offset += 1;
1789 break;
1790
1791 case 0362:
1792 case 0363:
1793 bytes[0] = c - 0362 + 0xf2;
1794 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1795 offset += 1;
1796 break;
1797
1798 case 0364:
1799 case 0365:
1800 break;
1801
1802 case 0366:
1803 case 0367:
1804 *bytes = c - 0366 + 0x66;
1805 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1806 offset += 1;
1807 break;
1808
1809 case 0370:
1810 case 0371:
1811 case 0372:
1812 break;
1813
1814 case 0373:
1815 *bytes = bits == 16 ? 3 : 5;
1816 out(offset, segment, bytes, OUT_RAWDATA, 1, NO_SEG, NO_SEG);
1817 offset += 1;
1818 break;
1819
1820 case 0374:
1821 eat = EA_XMMVSIB;
1822 break;
1823
1824 case 0375:
1825 eat = EA_YMMVSIB;
1826 break;
1827
1828 case4(0100):
1829 case4(0110):
1830 case4(0120):
1831 case4(0130):
1832 case4(0200):
1833 case4(0204):
1834 case4(0210):
1835 case4(0214):
1836 case4(0220):
1837 case4(0224):
1838 case4(0230):
1839 case4(0234):
1840 {
1841 ea ea_data;
1842 int rfield;
1843 opflags_t rflags;
1844 uint8_t *p;
1845 int32_t s;
1846 struct operand *opy = &ins->oprs[op2];
1847
1848 if (c <= 0177) {
1849 /* pick rfield from operand b (opx) */
1850 rflags = regflag(opx);
1851 rfield = nasm_regvals[opx->basereg];
1852 } else {
1853 /* rfield is constant */
1854 rflags = 0;
1855 rfield = c & 7;
1856 }
1857
1858 if (process_ea(opy, &ea_data, bits, ins->addr_size,
1859 rfield, rflags) != eat)
1860 errfunc(ERR_NONFATAL, "invalid effective address");
1861
1862 p = bytes;
1863 *p++ = ea_data.modrm;
1864 if (ea_data.sib_present)
1865 *p++ = ea_data.sib;
1866
1867 s = p - bytes;
1868 out(offset, segment, bytes, OUT_RAWDATA, s, NO_SEG, NO_SEG);
1869
1870 /*
1871 * Make sure the address gets the right offset in case
1872 * the line breaks in the .lst file (BR 1197827)
1873 */
1874 offset += s;
1875 s = 0;
1876
1877 switch (ea_data.bytes) {
1878 case 0:
1879 break;
1880 case 1:
1881 case 2:
1882 case 4:
1883 case 8:
1884 data = opy->offset;
1885 s += ea_data.bytes;
1886 if (ea_data.rip) {
1887 if (opy->segment == segment) {
1888 data -= insn_end;
1889 if (overflow_signed(data, ea_data.bytes))
1890 warn_overflow(ERR_PASS2, ea_data.bytes);
1891 out(offset, segment, &data, OUT_ADDRESS,
1892 ea_data.bytes, NO_SEG, NO_SEG);
1893 } else {
1894 /* overflow check in output/linker? */
1895 out(offset, segment, &data, OUT_REL4ADR,
1896 insn_end - offset, opy->segment, opy->wrt);
1897 }
1898 } else {
1899 if (overflow_general(opy->offset, ins->addr_size >> 3) ||
1900 signed_bits(opy->offset, ins->addr_size) !=
1901 signed_bits(opy->offset, ea_data.bytes * 8))
1902 warn_overflow(ERR_PASS2, ea_data.bytes);
1903
1904 out(offset, segment, &data, OUT_ADDRESS,
1905 ea_data.bytes, opy->segment, opy->wrt);
1906 }
1907 break;
1908 default:
1909 /* Impossible! */
1910 errfunc(ERR_PANIC,
1911 "Invalid amount of bytes (%d) for offset?!",
1912 ea_data.bytes);
1913 break;
1914 }
1915 offset += s;
1916 }
1917 break;
1918
1919 default:
1920 errfunc(ERR_PANIC, "internal instruction table corrupt"
1921 ": instruction code \\%o (0x%02X) given", c, c);
1922 break;
1923 }
1924 }
1925 }
1926
1927 static opflags_t regflag(const operand * o)
1928 {
1929 if (!is_register(o->basereg))
1930 errfunc(ERR_PANIC, "invalid operand passed to regflag()");
1931 return nasm_reg_flags[o->basereg];
1932 }
1933
1934 static int32_t regval(const operand * o)
1935 {
1936 if (!is_register(o->basereg))
1937 errfunc(ERR_PANIC, "invalid operand passed to regval()");
1938 return nasm_regvals[o->basereg];
1939 }
1940
1941 static int op_rexflags(const operand * o, int mask)
1942 {
1943 opflags_t flags;
1944 int val;
1945
1946 if (!is_register(o->basereg))
1947 errfunc(ERR_PANIC, "invalid operand passed to op_rexflags()");
1948
1949 flags = nasm_reg_flags[o->basereg];
1950 val = nasm_regvals[o->basereg];
1951
1952 return rexflags(val, flags, mask);
1953 }
1954
1955 static int rexflags(int val, opflags_t flags, int mask)
1956 {
1957 int rex = 0;
1958
1959 if (val >= 8)
1960 rex |= REX_B|REX_X|REX_R;
1961 if (flags & BITS64)
1962 rex |= REX_W;
1963 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1964 rex |= REX_H;
1965 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1966 rex |= REX_P;
1967
1968 return rex & mask;
1969 }
1970
1971 static enum match_result find_match(const struct itemplate **tempp,
1972 insn *instruction,
1973 int32_t segment, int64_t offset, int bits)
1974 {
1975 const struct itemplate *temp;
1976 enum match_result m, merr;
1977 opflags_t xsizeflags[MAX_OPERANDS];
1978 bool opsizemissing = false;
1979 int i;
1980
1981 for (i = 0; i < instruction->operands; i++)
1982 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
1983
1984 merr = MERR_INVALOP;
1985
1986 for (temp = nasm_instructions[instruction->opcode];
1987 temp->opcode != I_none; temp++) {
1988 m = matches(temp, instruction, bits);
1989 if (m == MOK_JUMP) {
1990 if (jmp_match(segment, offset, bits, instruction, temp->code))
1991 m = MOK_GOOD;
1992 else
1993 m = MERR_INVALOP;
1994 } else if (m == MERR_OPSIZEMISSING &&
1995 (temp->flags & IF_SMASK) != IF_SX) {
1996 /*
1997 * Missing operand size and a candidate for fuzzy matching...
1998 */
1999 for (i = 0; i < temp->operands; i++) {
2000 if ((temp->opd[i] & SAME_AS) == 0)
2001 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
2002 }
2003 opsizemissing = true;
2004 }
2005 if (m > merr)
2006 merr = m;
2007 if (merr == MOK_GOOD)
2008 goto done;
2009 }
2010
2011 /* No match, but see if we can get a fuzzy operand size match... */
2012 if (!opsizemissing)
2013 goto done;
2014
2015 for (i = 0; i < instruction->operands; i++) {
2016 /*
2017 * We ignore extrinsic operand sizes on registers, so we should
2018 * never try to fuzzy-match on them. This also resolves the case
2019 * when we have e.g. "xmmrm128" in two different positions.
2020 */
2021 if (is_class(REGISTER, instruction->oprs[i].type))
2022 continue;
2023
2024 /* This tests if xsizeflags[i] has more than one bit set */
2025 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2026 goto done; /* No luck */
2027
2028 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2029 }
2030
2031 /* Try matching again... */
2032 for (temp = nasm_instructions[instruction->opcode];
2033 temp->opcode != I_none; temp++) {
2034 m = matches(temp, instruction, bits);
2035 if (m == MOK_JUMP) {
2036 if (jmp_match(segment, offset, bits, instruction, temp->code))
2037 m = MOK_GOOD;
2038 else
2039 m = MERR_INVALOP;
2040 }
2041 if (m > merr)
2042 merr = m;
2043 if (merr == MOK_GOOD)
2044 goto done;
2045 }
2046
2047 done:
2048 *tempp = temp;
2049 return merr;
2050 }
2051
2052 static enum match_result matches(const struct itemplate *itemp,
2053 insn *instruction, int bits)
2054 {
2055 int i, size[MAX_OPERANDS], asize, oprs;
2056 bool opsizemissing = false;
2057
2058 /*
2059 * Check the opcode
2060 */
2061 if (itemp->opcode != instruction->opcode)
2062 return MERR_INVALOP;
2063
2064 /*
2065 * Count the operands
2066 */
2067 if (itemp->operands != instruction->operands)
2068 return MERR_INVALOP;
2069
2070 /*
2071 * Is it legal?
2072 */
2073 if (!(optimizing > 0) && (itemp->flags & IF_OPT))
2074 return MERR_INVALOP;
2075
2076 /*
2077 * Check that no spurious colons or TOs are present
2078 */
2079 for (i = 0; i < itemp->operands; i++)
2080 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2081 return MERR_INVALOP;
2082
2083 /*
2084 * Process size flags
2085 */
2086 switch (itemp->flags & IF_SMASK) {
2087 case IF_SB:
2088 asize = BITS8;
2089 break;
2090 case IF_SW:
2091 asize = BITS16;
2092 break;
2093 case IF_SD:
2094 asize = BITS32;
2095 break;
2096 case IF_SQ:
2097 asize = BITS64;
2098 break;
2099 case IF_SO:
2100 asize = BITS128;
2101 break;
2102 case IF_SY:
2103 asize = BITS256;
2104 break;
2105 case IF_SZ:
2106 switch (bits) {
2107 case 16:
2108 asize = BITS16;
2109 break;
2110 case 32:
2111 asize = BITS32;
2112 break;
2113 case 64:
2114 asize = BITS64;
2115 break;
2116 default:
2117 asize = 0;
2118 break;
2119 }
2120 break;
2121 default:
2122 asize = 0;
2123 break;
2124 }
2125
2126 if (itemp->flags & IF_ARMASK) {
2127 /* S- flags only apply to a specific operand */
2128 i = ((itemp->flags & IF_ARMASK) >> IF_ARSHFT) - 1;
2129 memset(size, 0, sizeof size);
2130 size[i] = asize;
2131 } else {
2132 /* S- flags apply to all operands */
2133 for (i = 0; i < MAX_OPERANDS; i++)
2134 size[i] = asize;
2135 }
2136
2137 /*
2138 * Check that the operand flags all match up,
2139 * it's a bit tricky so lets be verbose:
2140 *
2141 * 1) Find out the size of operand. If instruction
2142 * doesn't have one specified -- we're trying to
2143 * guess it either from template (IF_S* flag) or
2144 * from code bits.
2145 *
2146 * 2) If template operand (i) has SAME_AS flag [used for registers only]
2147 * (ie the same operand as was specified somewhere in template, and
2148 * this referred operand index is being achieved via ~SAME_AS)
2149 * we are to be sure that both registers (in template and instruction)
2150 * do exactly match.
2151 *
2152 * 3) If template operand do not match the instruction OR
2153 * template has an operand size specified AND this size differ
2154 * from which instruction has (perhaps we got it from code bits)
2155 * we are:
2156 * a) Check that only size of instruction and operand is differ
2157 * other characteristics do match
2158 * b) Perhaps it's a register specified in instruction so
2159 * for such a case we just mark that operand as "size
2160 * missing" and this will turn on fuzzy operand size
2161 * logic facility (handled by a caller)
2162 */
2163 for (i = 0; i < itemp->operands; i++) {
2164 opflags_t type = instruction->oprs[i].type;
2165 if (!(type & SIZE_MASK))
2166 type |= size[i];
2167
2168 if (itemp->opd[i] & SAME_AS) {
2169 int j = itemp->opd[i] & ~SAME_AS;
2170 if (type != instruction->oprs[j].type ||
2171 instruction->oprs[i].basereg != instruction->oprs[j].basereg)
2172 return MERR_INVALOP;
2173 } else if (itemp->opd[i] & ~type ||
2174 ((itemp->opd[i] & SIZE_MASK) &&
2175 ((itemp->opd[i] ^ type) & SIZE_MASK))) {
2176 if ((itemp->opd[i] & ~type & ~SIZE_MASK) || (type & SIZE_MASK)) {
2177 return MERR_INVALOP;
2178 } else if (!is_class(REGISTER, type)) {
2179 /*
2180 * Note: we don't honor extrinsic operand sizes for registers,
2181 * so "missing operand size" for a register should be
2182 * considered a wildcard match rather than an error.
2183 */
2184 opsizemissing = true;
2185 }
2186 }
2187 }
2188
2189 if (opsizemissing)
2190 return MERR_OPSIZEMISSING;
2191
2192 /*
2193 * Check operand sizes
2194 */
2195 if (itemp->flags & (IF_SM | IF_SM2)) {
2196 oprs = (itemp->flags & IF_SM2 ? 2 : itemp->operands);
2197 for (i = 0; i < oprs; i++) {
2198 asize = itemp->opd[i] & SIZE_MASK;
2199 if (asize) {
2200 for (i = 0; i < oprs; i++)
2201 size[i] = asize;
2202 break;
2203 }
2204 }
2205 } else {
2206 oprs = itemp->operands;
2207 }
2208
2209 for (i = 0; i < itemp->operands; i++) {
2210 if (!(itemp->opd[i] & SIZE_MASK) &&
2211 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2212 return MERR_OPSIZEMISMATCH;
2213 }
2214
2215 /*
2216 * Check template is okay at the set cpu level
2217 */
2218 if (((itemp->flags & IF_PLEVEL) > cpu))
2219 return MERR_BADCPU;
2220
2221 /*
2222 * Verify the appropriate long mode flag.
2223 */
2224 if ((itemp->flags & (bits == 64 ? IF_NOLONG : IF_LONG)))
2225 return MERR_BADMODE;
2226
2227 /*
2228 * Check if special handling needed for Jumps
2229 */
2230 if ((itemp->code[0] & 0374) == 0370)
2231 return MOK_JUMP;
2232
2233 return MOK_GOOD;
2234 }
2235
2236 static enum ea_type process_ea(operand *input, ea *output, int bits,
2237 int addrbits, int rfield, opflags_t rflags)
2238 {
2239 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2240
2241 output->type = EA_SCALAR;
2242 output->rip = false;
2243
2244 /* REX flags for the rfield operand */
2245 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2246
2247 if (is_class(REGISTER, input->type)) {
2248 /*
2249 * It's a direct register.
2250 */
2251 opflags_t f;
2252
2253 if (!is_register(input->basereg))
2254 goto err;
2255
2256 f = regflag(input);
2257
2258 if (!is_class(REG_EA, f))
2259 goto err;
2260
2261 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2262 output->sib_present = false; /* no SIB necessary */
2263 output->bytes = 0; /* no offset necessary either */
2264 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2265 } else {
2266 /*
2267 * It's a memory reference.
2268 */
2269 if (input->basereg == -1 &&
2270 (input->indexreg == -1 || input->scale == 0)) {
2271 /*
2272 * It's a pure offset.
2273 */
2274 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2275 input->segment == NO_SEG) {
2276 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2277 input->type &= ~IP_REL;
2278 input->type |= MEMORY;
2279 }
2280
2281 if (input->eaflags & EAF_BYTEOFFS ||
2282 (input->eaflags & EAF_WORDOFFS &&
2283 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2284 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2285 }
2286
2287 if (bits == 64 && (~input->type & IP_REL)) {
2288 output->sib_present = true;
2289 output->sib = GEN_SIB(0, 4, 5);
2290 output->bytes = 4;
2291 output->modrm = GEN_MODRM(0, rfield, 4);
2292 output->rip = false;
2293 } else {
2294 output->sib_present = false;
2295 output->bytes = (addrbits != 16 ? 4 : 2);
2296 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2297 output->rip = bits == 64;
2298 }
2299 } else {
2300 /*
2301 * It's an indirection.
2302 */
2303 int i = input->indexreg, b = input->basereg, s = input->scale;
2304 int32_t seg = input->segment;
2305 int hb = input->hintbase, ht = input->hinttype;
2306 int t, it, bt; /* register numbers */
2307 opflags_t x, ix, bx; /* register flags */
2308
2309 if (s == 0)
2310 i = -1; /* make this easy, at least */
2311
2312 if (is_register(i)) {
2313 it = nasm_regvals[i];
2314 ix = nasm_reg_flags[i];
2315 } else {
2316 it = -1;
2317 ix = 0;
2318 }
2319
2320 if (is_register(b)) {
2321 bt = nasm_regvals[b];
2322 bx = nasm_reg_flags[b];
2323 } else {
2324 bt = -1;
2325 bx = 0;
2326 }
2327
2328 /* if either one are a vector register... */
2329 if ((ix|bx) & (XMMREG|YMMREG) & ~REG_EA) {
2330 int32_t sok = BITS32 | BITS64;
2331 int32_t o = input->offset;
2332 int mod, scale, index, base;
2333
2334 /*
2335 * For a vector SIB, one has to be a vector and the other,
2336 * if present, a GPR. The vector must be the index operand.
2337 */
2338 if (it == -1 || (bx & (XMMREG|YMMREG) & ~REG_EA)) {
2339 if (s == 0)
2340 s = 1;
2341 else if (s != 1)
2342 goto err;
2343
2344 t = bt, bt = it, it = t;
2345 x = bx, bx = ix, ix = x;
2346 }
2347
2348 if (bt != -1) {
2349 if (REG_GPR & ~bx)
2350 goto err;
2351 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2352 sok &= bx;
2353 else
2354 goto err;
2355 }
2356
2357 /*
2358 * While we're here, ensure the user didn't specify
2359 * WORD or QWORD
2360 */
2361 if (input->disp_size == 16 || input->disp_size == 64)
2362 goto err;
2363
2364 if (addrbits == 16 ||
2365 (addrbits == 32 && !(sok & BITS32)) ||
2366 (addrbits == 64 && !(sok & BITS64)))
2367 goto err;
2368
2369 output->type = (ix & YMMREG & ~REG_EA)
2370 ? EA_YMMVSIB : EA_XMMVSIB;
2371
2372 output->rex |= rexflags(it, ix, REX_X);
2373 output->rex |= rexflags(bt, bx, REX_B);
2374
2375 index = it & 7; /* it is known to be != -1 */
2376
2377 switch (s) {
2378 case 1:
2379 scale = 0;
2380 break;
2381 case 2:
2382 scale = 1;
2383 break;
2384 case 4:
2385 scale = 2;
2386 break;
2387 case 8:
2388 scale = 3;
2389 break;
2390 default: /* then what the smeg is it? */
2391 goto err; /* panic */
2392 }
2393
2394 if (bt == -1) {
2395 base = 5;
2396 mod = 0;
2397 } else {
2398 base = (bt & 7);
2399 if (base != REG_NUM_EBP && o == 0 &&
2400 seg == NO_SEG && !forw_ref &&
2401 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2402 mod = 0;
2403 else if (input->eaflags & EAF_BYTEOFFS ||
2404 (o >= -128 && o <= 127 &&
2405 seg == NO_SEG && !forw_ref &&
2406 !(input->eaflags & EAF_WORDOFFS)))
2407 mod = 1;
2408 else
2409 mod = 2;
2410 }
2411
2412 output->sib_present = true;
2413 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2414 output->modrm = GEN_MODRM(mod, rfield, 4);
2415 output->sib = GEN_SIB(scale, index, base);
2416 } else if ((ix|bx) & (BITS32|BITS64)) {
2417 /*
2418 * it must be a 32/64-bit memory reference. Firstly we have
2419 * to check that all registers involved are type E/Rxx.
2420 */
2421 int32_t sok = BITS32 | BITS64;
2422 int32_t o = input->offset;
2423
2424 if (it != -1) {
2425 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2426 sok &= ix;
2427 else
2428 goto err;
2429 }
2430
2431 if (bt != -1) {
2432 if (REG_GPR & ~bx)
2433 goto err; /* Invalid register */
2434 if (~sok & bx & SIZE_MASK)
2435 goto err; /* Invalid size */
2436 sok &= bx;
2437 }
2438
2439 /*
2440 * While we're here, ensure the user didn't specify
2441 * WORD or QWORD
2442 */
2443 if (input->disp_size == 16 || input->disp_size == 64)
2444 goto err;
2445
2446 if (addrbits == 16 ||
2447 (addrbits == 32 && !(sok & BITS32)) ||
2448 (addrbits == 64 && !(sok & BITS64)))
2449 goto err;
2450
2451 /* now reorganize base/index */
2452 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2453 ((hb == b && ht == EAH_NOTBASE) ||
2454 (hb == i && ht == EAH_MAKEBASE))) {
2455 /* swap if hints say so */
2456 t = bt, bt = it, it = t;
2457 x = bx, bx = ix, ix = x;
2458 }
2459 if (bt == it) /* convert EAX+2*EAX to 3*EAX */
2460 bt = -1, bx = 0, s++;
2461 if (bt == -1 && s == 1 && !(hb == it && ht == EAH_NOTBASE)) {
2462 /* make single reg base, unless hint */
2463 bt = it, bx = ix, it = -1, ix = 0;
2464 }
2465 if (((s == 2 && it != REG_NUM_ESP && !(input->eaflags & EAF_TIMESTWO)) ||
2466 s == 3 || s == 5 || s == 9) && bt == -1)
2467 bt = it, bx = ix, s--; /* convert 3*EAX to EAX+2*EAX */
2468 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2469 (input->eaflags & EAF_TIMESTWO))
2470 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2471 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2472 if (s == 1 && it == REG_NUM_ESP) {
2473 /* swap ESP into base if scale is 1 */
2474 t = it, it = bt, bt = t;
2475 x = ix, ix = bx, bx = x;
2476 }
2477 if (it == REG_NUM_ESP ||
2478 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2479 goto err; /* wrong, for various reasons */
2480
2481 output->rex |= rexflags(it, ix, REX_X);
2482 output->rex |= rexflags(bt, bx, REX_B);
2483
2484 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2485 /* no SIB needed */
2486 int mod, rm;
2487
2488 if (bt == -1) {
2489 rm = 5;
2490 mod = 0;
2491 } else {
2492 rm = (bt & 7);
2493 if (rm != REG_NUM_EBP && o == 0 &&
2494 seg == NO_SEG && !forw_ref &&
2495 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2496 mod = 0;
2497 else if (input->eaflags & EAF_BYTEOFFS ||
2498 (o >= -128 && o <= 127 &&
2499 seg == NO_SEG && !forw_ref &&
2500 !(input->eaflags & EAF_WORDOFFS)))
2501 mod = 1;
2502 else
2503 mod = 2;
2504 }
2505
2506 output->sib_present = false;
2507 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2508 output->modrm = GEN_MODRM(mod, rfield, rm);
2509 } else {
2510 /* we need a SIB */
2511 int mod, scale, index, base;
2512
2513 if (it == -1)
2514 index = 4, s = 1;
2515 else
2516 index = (it & 7);
2517
2518 switch (s) {
2519 case 1:
2520 scale = 0;
2521 break;
2522 case 2:
2523 scale = 1;
2524 break;
2525 case 4:
2526 scale = 2;
2527 break;
2528 case 8:
2529 scale = 3;
2530 break;
2531 default: /* then what the smeg is it? */
2532 goto err; /* panic */
2533 }
2534
2535 if (bt == -1) {
2536 base = 5;
2537 mod = 0;
2538 } else {
2539 base = (bt & 7);
2540 if (base != REG_NUM_EBP && o == 0 &&
2541 seg == NO_SEG && !forw_ref &&
2542 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2543 mod = 0;
2544 else if (input->eaflags & EAF_BYTEOFFS ||
2545 (o >= -128 && o <= 127 &&
2546 seg == NO_SEG && !forw_ref &&
2547 !(input->eaflags & EAF_WORDOFFS)))
2548 mod = 1;
2549 else
2550 mod = 2;
2551 }
2552
2553 output->sib_present = true;
2554 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2555 output->modrm = GEN_MODRM(mod, rfield, 4);
2556 output->sib = GEN_SIB(scale, index, base);
2557 }
2558 } else { /* it's 16-bit */
2559 int mod, rm;
2560 int16_t o = input->offset;
2561
2562 /* check for 64-bit long mode */
2563 if (addrbits == 64)
2564 goto err;
2565
2566 /* check all registers are BX, BP, SI or DI */
2567 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2568 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2569 goto err;
2570
2571 /* ensure the user didn't specify DWORD/QWORD */
2572 if (input->disp_size == 32 || input->disp_size == 64)
2573 goto err;
2574
2575 if (s != 1 && i != -1)
2576 goto err; /* no can do, in 16-bit EA */
2577 if (b == -1 && i != -1) {
2578 int tmp = b;
2579 b = i;
2580 i = tmp;
2581 } /* swap */
2582 if ((b == R_SI || b == R_DI) && i != -1) {
2583 int tmp = b;
2584 b = i;
2585 i = tmp;
2586 }
2587 /* have BX/BP as base, SI/DI index */
2588 if (b == i)
2589 goto err; /* shouldn't ever happen, in theory */
2590 if (i != -1 && b != -1 &&
2591 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2592 goto err; /* invalid combinations */
2593 if (b == -1) /* pure offset: handled above */
2594 goto err; /* so if it gets to here, panic! */
2595
2596 rm = -1;
2597 if (i != -1)
2598 switch (i * 256 + b) {
2599 case R_SI * 256 + R_BX:
2600 rm = 0;
2601 break;
2602 case R_DI * 256 + R_BX:
2603 rm = 1;
2604 break;
2605 case R_SI * 256 + R_BP:
2606 rm = 2;
2607 break;
2608 case R_DI * 256 + R_BP:
2609 rm = 3;
2610 break;
2611 } else
2612 switch (b) {
2613 case R_SI:
2614 rm = 4;
2615 break;
2616 case R_DI:
2617 rm = 5;
2618 break;
2619 case R_BP:
2620 rm = 6;
2621 break;
2622 case R_BX:
2623 rm = 7;
2624 break;
2625 }
2626 if (rm == -1) /* can't happen, in theory */
2627 goto err; /* so panic if it does */
2628
2629 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2630 !(input->eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2631 mod = 0;
2632 else if (input->eaflags & EAF_BYTEOFFS ||
2633 (o >= -128 && o <= 127 && seg == NO_SEG &&
2634 !forw_ref && !(input->eaflags & EAF_WORDOFFS)))
2635 mod = 1;
2636 else
2637 mod = 2;
2638
2639 output->sib_present = false; /* no SIB - it's 16-bit */
2640 output->bytes = mod; /* bytes of offset needed */
2641 output->modrm = GEN_MODRM(mod, rfield, rm);
2642 }
2643 }
2644 }
2645
2646 output->size = 1 + output->sib_present + output->bytes;
2647 return output->type;
2648
2649 err:
2650 return output->type = EA_INVALID;
2651 }
2652
2653 static void add_asp(insn *ins, int addrbits)
2654 {
2655 int j, valid;
2656 int defdisp;
2657
2658 valid = (addrbits == 64) ? 64|32 : 32|16;
2659
2660 switch (ins->prefixes[PPS_ASIZE]) {
2661 case P_A16:
2662 valid &= 16;
2663 break;
2664 case P_A32:
2665 valid &= 32;
2666 break;
2667 case P_A64:
2668 valid &= 64;
2669 break;
2670 case P_ASP:
2671 valid &= (addrbits == 32) ? 16 : 32;
2672 break;
2673 default:
2674 break;
2675 }
2676
2677 for (j = 0; j < ins->operands; j++) {
2678 if (is_class(MEMORY, ins->oprs[j].type)) {
2679 opflags_t i, b;
2680
2681 /* Verify as Register */
2682 if (!is_register(ins->oprs[j].indexreg))
2683 i = 0;
2684 else
2685 i = nasm_reg_flags[ins->oprs[j].indexreg];
2686
2687 /* Verify as Register */
2688 if (!is_register(ins->oprs[j].basereg))
2689 b = 0;
2690 else
2691 b = nasm_reg_flags[ins->oprs[j].basereg];
2692
2693 if (ins->oprs[j].scale == 0)
2694 i = 0;
2695
2696 if (!i && !b) {
2697 int ds = ins->oprs[j].disp_size;
2698 if ((addrbits != 64 && ds > 8) ||
2699 (addrbits == 64 && ds == 16))
2700 valid &= ds;
2701 } else {
2702 if (!(REG16 & ~b))
2703 valid &= 16;
2704 if (!(REG32 & ~b))
2705 valid &= 32;
2706 if (!(REG64 & ~b))
2707 valid &= 64;
2708
2709 if (!(REG16 & ~i))
2710 valid &= 16;
2711 if (!(REG32 & ~i))
2712 valid &= 32;
2713 if (!(REG64 & ~i))
2714 valid &= 64;
2715 }
2716 }
2717 }
2718
2719 if (valid & addrbits) {
2720 ins->addr_size = addrbits;
2721 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2722 /* Add an address size prefix */
2723 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2724 ins->addr_size = (addrbits == 32) ? 16 : 32;
2725 } else {
2726 /* Impossible... */
2727 errfunc(ERR_NONFATAL, "impossible combination of address sizes");
2728 ins->addr_size = addrbits; /* Error recovery */
2729 }
2730
2731 defdisp = ins->addr_size == 16 ? 16 : 32;
2732
2733 for (j = 0; j < ins->operands; j++) {
2734 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2735 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2736 /*
2737 * mem_offs sizes must match the address size; if not,
2738 * strip the MEM_OFFS bit and match only EA instructions
2739 */
2740 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2741 }
2742 }
2743 }
The Netwide Assembler