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nasm_build_assert(): use better fallback implementation
[nasm.git] / asm / assemble.c
bloba4f8c88311fc1dcf368fde43b3746bad50bb92f6
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2016 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * Bytecode specification
38 * ----------------------
39 *
40 *
41 * Codes Mnemonic Explanation
42 *
43 * \0 terminates the code. (Unless it's a literal of course.)
44 * \1..\4 that many literal bytes follow in the code stream
45 * \5 add 4 to the primary operand number (b, low octdigit)
46 * \6 add 4 to the secondary operand number (a, middle octdigit)
47 * \7 add 4 to both the primary and the secondary operand number
48 * \10..\13 a literal byte follows in the code stream, to be added
49 * to the register value of operand 0..3
50 * \14..\17 the position of index register operand in MIB (BND insns)
51 * \20..\23 ib a byte immediate operand, from operand 0..3
52 * \24..\27 ib,u a zero-extended byte immediate operand, from operand 0..3
53 * \30..\33 iw a word immediate operand, from operand 0..3
54 * \34..\37 iwd select between \3[0-3] and \4[0-3] depending on 16/32 bit
55 * assembly mode or the operand-size override on the operand
56 * \40..\43 id a long immediate operand, from operand 0..3
57 * \44..\47 iwdq select between \3[0-3], \4[0-3] and \5[4-7]
58 * depending on the address size of the instruction.
59 * \50..\53 rel8 a byte relative operand, from operand 0..3
60 * \54..\57 iq a qword immediate operand, from operand 0..3
61 * \60..\63 rel16 a word relative operand, from operand 0..3
62 * \64..\67 rel select between \6[0-3] and \7[0-3] depending on 16/32 bit
63 * assembly mode or the operand-size override on the operand
64 * \70..\73 rel32 a long relative operand, from operand 0..3
65 * \74..\77 seg a word constant, from the _segment_ part of operand 0..3
66 * \1ab a ModRM, calculated on EA in operand a, with the spare
67 * field the register value of operand b.
68 * \172\ab the register number from operand a in bits 7..4, with
69 * the 4-bit immediate from operand b in bits 3..0.
70 * \173\xab the register number from operand a in bits 7..4, with
71 * the value b in bits 3..0.
72 * \174..\177 the register number from operand 0..3 in bits 7..4, and
73 * an arbitrary value in bits 3..0 (assembled as zero.)
74 * \2ab a ModRM, calculated on EA in operand a, with the spare
75 * field equal to digit b.
76 *
77 * \240..\243 this instruction uses EVEX rather than REX or VEX/XOP, with the
78 * V field taken from operand 0..3.
79 * \250 this instruction uses EVEX rather than REX or VEX/XOP, with the
80 * V field set to 1111b.
81 *
82 * EVEX prefixes are followed by the sequence:
83 * \cm\wlp\tup where cm is:
84 * cc 00m mmm
85 * c = 2 for EVEX and mmmm is the M field (EVEX.P0[3:0])
86 * and wlp is:
87 * 00 wwl lpp
88 * [l0] ll = 0 (.128, .lz)
89 * [l1] ll = 1 (.256)
90 * [l2] ll = 2 (.512)
91 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
92 *
93 * [w0] ww = 0 for W = 0
94 * [w1] ww = 1 for W = 1
95 * [wig] ww = 2 for W don't care (always assembled as 0)
96 * [ww] ww = 3 for W used as REX.W
97 *
98 * [p0] pp = 0 for no prefix
99 * [60] pp = 1 for legacy prefix 60
100 * [f3] pp = 2
101 * [f2] pp = 3
102 *
103 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
104 * (compressed displacement encoding)
105 *
106 * \254..\257 id,s a signed 32-bit operand to be extended to 64 bits.
107 * \260..\263 this instruction uses VEX/XOP rather than REX, with the
108 * V field taken from operand 0..3.
109 * \270 this instruction uses VEX/XOP rather than REX, with the
110 * V field set to 1111b.
111 *
112 * VEX/XOP prefixes are followed by the sequence:
113 * \tmm\wlp where mm is the M field; and wlp is:
114 * 00 wwl lpp
115 * [l0] ll = 0 for L = 0 (.128, .lz)
116 * [l1] ll = 1 for L = 1 (.256)
117 * [lig] ll = 2 for L don't care (always assembled as 0)
118 *
119 * [w0] ww = 0 for W = 0
120 * [w1 ] ww = 1 for W = 1
121 * [wig] ww = 2 for W don't care (always assembled as 0)
122 * [ww] ww = 3 for W used as REX.W
123 *
124 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
125 *
126 * \271 hlexr instruction takes XRELEASE (F3) with or without lock
127 * \272 hlenl instruction takes XACQUIRE/XRELEASE with or without lock
128 * \273 hle instruction takes XACQUIRE/XRELEASE with lock only
129 * \274..\277 ib,s a byte immediate operand, from operand 0..3, sign-extended
130 * to the operand size (if o16/o32/o64 present) or the bit size
131 * \310 a16 indicates fixed 16-bit address size, i.e. optional 0x67.
132 * \311 a32 indicates fixed 32-bit address size, i.e. optional 0x67.
133 * \312 adf (disassembler only) invalid with non-default address size.
134 * \313 a64 indicates fixed 64-bit address size, 0x67 invalid.
135 * \314 norexb (disassembler only) invalid with REX.B
136 * \315 norexx (disassembler only) invalid with REX.X
137 * \316 norexr (disassembler only) invalid with REX.R
138 * \317 norexw (disassembler only) invalid with REX.W
139 * \320 o16 indicates fixed 16-bit operand size, i.e. optional 0x66.
140 * \321 o32 indicates fixed 32-bit operand size, i.e. optional 0x66.
141 * \322 odf indicates that this instruction is only valid when the
142 * operand size is the default (instruction to disassembler,
143 * generates no code in the assembler)
144 * \323 o64nw indicates fixed 64-bit operand size, REX on extensions only.
145 * \324 o64 indicates 64-bit operand size requiring REX prefix.
146 * \325 nohi instruction which always uses spl/bpl/sil/dil
147 * \326 nof3 instruction not valid with 0xF3 REP prefix. Hint for
148 disassembler only; for SSE instructions.
149 * \330 a literal byte follows in the code stream, to be added
150 * to the condition code value of the instruction.
151 * \331 norep instruction not valid with REP prefix. Hint for
152 * disassembler only; for SSE instructions.
153 * \332 f2i REP prefix (0xF2 byte) used as opcode extension.
154 * \333 f3i REP prefix (0xF3 byte) used as opcode extension.
155 * \334 rex.l LOCK prefix used as REX.R (used in non-64-bit mode)
156 * \335 repe disassemble a rep (0xF3 byte) prefix as repe not rep.
157 * \336 mustrep force a REP(E) prefix (0xF3) even if not specified.
158 * \337 mustrepne force a REPNE prefix (0xF2) even if not specified.
159 * \336-\337 are still listed as prefixes in the disassembler.
160 * \340 resb reserve <operand 0> bytes of uninitialized storage.
161 * Operand 0 had better be a segmentless constant.
162 * \341 wait this instruction needs a WAIT "prefix"
163 * \360 np no SSE prefix (== \364\331)
164 * \361 66 SSE prefix (== \366\331)
165 * \364 !osp operand-size prefix (0x66) not permitted
166 * \365 !asp address-size prefix (0x67) not permitted
167 * \366 operand-size prefix (0x66) used as opcode extension
168 * \367 address-size prefix (0x67) used as opcode extension
169 * \370,\371 jcc8 match only if operand 0 meets byte jump criteria.
170 * jmp8 370 is used for Jcc, 371 is used for JMP.
171 * \373 jlen assemble 0x03 if bits==16, 0x05 if bits==32;
172 * used for conditional jump over longer jump
173 * \374 vsibx|vm32x|vm64x this instruction takes an XMM VSIB memory EA
174 * \375 vsiby|vm32y|vm64y this instruction takes an YMM VSIB memory EA
175 * \376 vsibz|vm32z|vm64z this instruction takes an ZMM VSIB memory EA
176 */
177
178 #include "compiler.h"
179
180 #include <stdio.h>
181 #include <string.h>
182 #include <stdlib.h>
183
184 #include "nasm.h"
185 #include "nasmlib.h"
186 #include "assemble.h"
187 #include "insns.h"
188 #include "tables.h"
189 #include "disp8.h"
190 #include "listing.h"
191
192 enum match_result {
193 /*
194 * Matching errors. These should be sorted so that more specific
195 * errors come later in the sequence.
196 */
197 MERR_INVALOP,
198 MERR_OPSIZEMISSING,
199 MERR_OPSIZEMISMATCH,
200 MERR_BRNUMMISMATCH,
201 MERR_BADCPU,
202 MERR_BADMODE,
203 MERR_BADHLE,
204 MERR_ENCMISMATCH,
205 MERR_BADBND,
206 MERR_BADREPNE,
207 /*
208 * Matching success; the conditional ones first
209 */
210 MOK_JUMP, /* Matching OK but needs jmp_match() */
211 MOK_GOOD /* Matching unconditionally OK */
212 };
213
214 typedef struct {
215 enum ea_type type; /* what kind of EA is this? */
216 int sib_present; /* is a SIB byte necessary? */
217 int bytes; /* # of bytes of offset needed */
218 int size; /* lazy - this is sib+bytes+1 */
219 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
220 int8_t disp8; /* compressed displacement for EVEX */
221 } ea;
222
223 #define GEN_SIB(scale, index, base) \
224 (((scale) << 6) | ((index) << 3) | ((base)))
225
226 #define GEN_MODRM(mod, reg, rm) \
227 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
228
229 static iflag_t cpu; /* cpu level received from nasm.c */
230
231 static int64_t calcsize(int32_t, int64_t, int, insn *,
232 const struct itemplate *);
233 static int emit_prefix(struct out_data *data, const int bits, insn *ins);
234 static void gencode(struct out_data *data, insn *ins);
235 static enum match_result find_match(const struct itemplate **tempp,
236 insn *instruction,
237 int32_t segment, int64_t offset, int bits);
238 static enum match_result matches(const struct itemplate *, insn *, int bits);
239 static opflags_t regflag(const operand *);
240 static int32_t regval(const operand *);
241 static int rexflags(int, opflags_t, int);
242 static int op_rexflags(const operand *, int);
243 static int op_evexflags(const operand *, int, uint8_t);
244 static void add_asp(insn *, int);
245
246 static enum ea_type process_ea(operand *, ea *, int, int, opflags_t, insn *);
247
248 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
249 {
250 return ins->prefixes[pos] == prefix;
251 }
252
253 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
254 {
255 if (ins->prefixes[pos])
256 nasm_error(ERR_NONFATAL, "invalid %s prefix",
257 prefix_name(ins->prefixes[pos]));
258 }
259
260 static const char *size_name(int size)
261 {
262 switch (size) {
263 case 1:
264 return "byte";
265 case 2:
266 return "word";
267 case 4:
268 return "dword";
269 case 8:
270 return "qword";
271 case 10:
272 return "tword";
273 case 16:
274 return "oword";
275 case 32:
276 return "yword";
277 case 64:
278 return "zword";
279 default:
280 return "???";
281 }
282 }
283
284 static void warn_overflow(int pass, int size)
285 {
286 nasm_error(ERR_WARNING | pass | ERR_WARN_NOV,
287 "%s data exceeds bounds", size_name(size));
288 }
289
290 static void warn_overflow_const(int64_t data, int size)
291 {
292 if (overflow_general(data, size))
293 warn_overflow(ERR_PASS1, size);
294 }
295
296 static void warn_overflow_opd(const struct operand *o, int size)
297 {
298 if (o->wrt == NO_SEG && o->segment == NO_SEG) {
299 if (overflow_general(o->offset, size))
300 warn_overflow(ERR_PASS2, size);
301 }
302 }
303
304 /*
305 * This routine wrappers the real output format's output routine,
306 * in order to pass a copy of the data off to the listing file
307 * generator at the same time, flatten unnecessary relocations,
308 * and verify backend compatibility.
309 */
310 static void out(struct out_data *data)
311 {
312 static int32_t lineno = 0; /* static!!! */
313 static const char *lnfname = NULL;
314 int asize;
315 const int amax = ofmt->maxbits >> 3; /* Maximum address size in bytes */
316 union {
317 uint8_t b[8];
318 uint64_t q;
319 } xdata;
320 uint64_t size = data->size;
321
322 if (!data->size)
323 return; /* Nothing to do */
324
325 /*
326 * Convert addresses to RAWDATA if possible
327 * XXX: not all backends want this for global symbols!!!!
328 */
329 switch (data->type) {
330 case OUT_ADDRESS:
331 asize = data->size;
332 nasm_assert(asize <= 8);
333 if (data->tsegment == NO_SEG && data->twrt == NO_SEG) {
334 /* XXX: check for overflow */
335 uint8_t *q = xdata.b;
336
337 WRITEADDR(q, data->toffset, asize);
338 data->data = xdata.b;
339 data->type = OUT_RAWDATA;
340 asize = 0; /* No longer an address */
341 }
342 break;
343
344 case OUT_RELADDR:
345 asize = data->size;
346 nasm_assert(asize <= 8);
347 if (data->tsegment == data->segment && data->twrt == NO_SEG) {
348 uint8_t *q = xdata.b;
349 int64_t delta = data->toffset - data->offset
350 - (data->inslen - data->insoffs);
351
352 if (overflow_signed(delta, asize))
353 warn_overflow(ERR_PASS2, asize);
354
355 WRITEADDR(q, delta, asize);
356 data->data = xdata.b;
357 data->type = OUT_RAWDATA;
358 asize = 0; /* No longer an address */
359 }
360 break;
361
362 default:
363 asize = 0; /* Not an address */
364 break;
365 }
366
367 lfmt->output(data);
368
369 /*
370 * this call to src_get determines when we call the
371 * debug-format-specific "linenum" function
372 * it updates lineno and lnfname to the current values
373 * returning 0 if "same as last time", -2 if lnfname
374 * changed, and the amount by which lineno changed,
375 * if it did. thus, these variables must be static
376 */
377
378 if (src_get(&lineno, &lnfname))
379 dfmt->linenum(lnfname, lineno, data->segment);
380
381 if (asize && asize > amax) {
382 if (data->type != OUT_ADDRESS || data->sign == OUT_SIGNED) {
383 nasm_error(ERR_NONFATAL,
384 "%d-bit signed relocation unsupported by output format %s\n",
385 asize << 3, ofmt->shortname);
386 } else {
387 nasm_error(ERR_WARNING | ERR_WARN_ZEXTRELOC,
388 "%d-bit unsigned relocation zero-extended from %d bits\n",
389 asize << 3, ofmt->maxbits);
390 data->size = amax;
391 ofmt->output(data);
392 data->insoffs += amax;
393 data->offset += amax;
394 data->size = size = asize - amax;
395 }
396 data->data = zero_buffer;
397 data->type = OUT_RAWDATA;
398 }
399
400 ofmt->output(data);
401 data->offset += size;
402 data->insoffs += size;
403 }
404
405 static inline void out_rawdata(struct out_data *data, const void *rawdata,
406 size_t size)
407 {
408 data->type = OUT_RAWDATA;
409 data->data = rawdata;
410 data->size = size;
411 out(data);
412 }
413
414 static void out_rawbyte(struct out_data *data, uint8_t byte)
415 {
416 data->type = OUT_RAWDATA;
417 data->data = &byte;
418 data->size = 1;
419 out(data);
420 }
421
422 static inline void out_reserve(struct out_data *data, uint64_t size)
423 {
424 data->type = OUT_RESERVE;
425 data->size = size;
426 out(data);
427 }
428
429 static inline void out_imm(struct out_data *data, struct operand *opx,
430 int size, enum out_sign sign)
431 {
432 data->type = OUT_ADDRESS;
433 data->sign = sign;
434 data->size = size;
435 data->toffset = opx->offset;
436 data->tsegment = opx->segment;
437 data->twrt = opx->wrt;
438 out(data);
439 }
440
441 static inline void out_reladdr(struct out_data *data, struct operand *opx,
442 int size)
443 {
444 data->type = OUT_RELADDR;
445 data->sign = OUT_SIGNED;
446 data->size = size;
447 data->toffset = opx->offset;
448 data->tsegment = opx->segment;
449 data->twrt = opx->wrt;
450 out(data);
451 }
452
453 static inline void out_segment(struct out_data *data, struct operand *opx)
454 {
455 data->type = OUT_SEGMENT;
456 data->sign = OUT_UNSIGNED;
457 data->size = 2;
458 data->toffset = opx->offset;
459 data->tsegment = ofmt->segbase(opx->segment + 1);
460 data->twrt = opx->wrt;
461 out(data);
462 }
463
464 static bool jmp_match(int32_t segment, int64_t offset, int bits,
465 insn * ins, const struct itemplate *temp)
466 {
467 int64_t isize;
468 const uint8_t *code = temp->code;
469 uint8_t c = code[0];
470 bool is_byte;
471
472 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
473 return false;
474 if (!optimizing)
475 return false;
476 if (optimizing < 0 && c == 0371)
477 return false;
478
479 isize = calcsize(segment, offset, bits, ins, temp);
480
481 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
482 /* Be optimistic in pass 1 */
483 return true;
484
485 if (ins->oprs[0].segment != segment)
486 return false;
487
488 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
489 is_byte = (isize >= -128 && isize <= 127); /* is it byte size? */
490
491 if (is_byte && c == 0371 && ins->prefixes[PPS_REP] == P_BND) {
492 /* jmp short (opcode eb) cannot be used with bnd prefix. */
493 ins->prefixes[PPS_REP] = P_none;
494 nasm_error(ERR_WARNING | ERR_WARN_BND | ERR_PASS2 ,
495 "jmp short does not init bnd regs - bnd prefix dropped.");
496 }
497
498 return is_byte;
499 }
500
501 /* This is totally just a wild guess what is reasonable... */
502 #define INCBIN_MAX_BUF (ZERO_BUF_SIZE * 16)
503
504 int64_t assemble(int32_t segment, int64_t start, int bits, iflag_t cp,
505 insn * instruction)
506 {
507 struct out_data data;
508 const struct itemplate *temp;
509 enum match_result m;
510 int32_t itimes;
511 int64_t wsize; /* size for DB etc. */
512
513 cpu = cp;
514
515 data.offset = start;
516 data.segment = segment;
517 data.itemp = NULL;
518 data.sign = OUT_WRAP;
519 data.bits = bits;
520
521 wsize = idata_bytes(instruction->opcode);
522 if (wsize == -1)
523 return 0;
524
525 if (wsize) {
526 extop *e;
527 int32_t t = instruction->times;
528 if (t < 0)
529 nasm_panic(0, "instruction->times < 0 (%"PRId32") in assemble()", t);
530
531 while (t--) { /* repeat TIMES times */
532 list_for_each(e, instruction->eops) {
533 if (e->type == EOT_DB_NUMBER) {
534 if (wsize > 8) {
535 nasm_error(ERR_NONFATAL,
536 "integer supplied to a DT, DO or DY"
537 " instruction");
538 } else {
539 data.insoffs = 0;
540 data.type = e->relative ? OUT_RELADDR : OUT_ADDRESS;
541 data.inslen = data.size = wsize;
542 data.toffset = e->offset;
543 data.tsegment = e->segment;
544 data.twrt = e->wrt;
545 out(&data);
546 }
547 } else if (e->type == EOT_DB_STRING ||
548 e->type == EOT_DB_STRING_FREE) {
549 int align = e->stringlen % wsize;
550 if (align)
551 align = wsize - align;
552
553 data.insoffs = 0;
554 data.inslen = e->stringlen + align;
555
556 out_rawdata(&data, e->stringval, e->stringlen);
557 out_rawdata(&data, zero_buffer, align);
558 }
559 }
560 if (t > 0 && t == instruction->times - 1) {
561 lfmt->set_offset(data.offset);
562 lfmt->uplevel(LIST_TIMES);
563 }
564 }
565 if (instruction->times > 1)
566 lfmt->downlevel(LIST_TIMES);
567 } else if (instruction->opcode == I_INCBIN) {
568 const char *fname = instruction->eops->stringval;
569 FILE *fp;
570 size_t t = instruction->times;
571 off_t base = 0;
572 off_t len;
573 const void *map = NULL;
574 char *buf = NULL;
575 size_t blk = 0; /* Buffered I/O block size */
576 size_t m = 0; /* Bytes last read */
577
578 fp = nasm_open_read(fname, NF_BINARY|NF_FORMAP);
579 if (!fp) {
580 nasm_error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
581 fname);
582 goto done;
583 }
584
585 len = nasm_file_size(fp);
586
587 if (len == (off_t)-1) {
588 nasm_error(ERR_NONFATAL, "`incbin': unable to get length of file `%s'",
589 fname);
590 goto close_done;
591 }
592
593 if (instruction->eops->next) {
594 base = instruction->eops->next->offset;
595 if (base >= len) {
596 len = 0;
597 } else {
598 len -= base;
599 if (instruction->eops->next->next &&
600 len > (off_t)instruction->eops->next->next->offset)
601 len = (off_t)instruction->eops->next->next->offset;
602 }
603 }
604
605 lfmt->set_offset(data.offset);
606 lfmt->uplevel(LIST_INCBIN);
607
608 if (!len)
609 goto end_incbin;
610
611 /* Try to map file data */
612 map = nasm_map_file(fp, base, len);
613 if (!map) {
614 blk = len < (off_t)INCBIN_MAX_BUF ? (size_t)len : INCBIN_MAX_BUF;
615 buf = nasm_malloc(blk);
616 }
617
618 while (t--) {
619 /*
620 * Consider these irrelevant for INCBIN, since it is fully
621 * possible that these might be (way) bigger than an int
622 * can hold; there is, however, no reason to widen these
623 * types just for INCBIN. data.inslen == 0 signals to the
624 * backend that these fields are meaningless, if at all
625 * needed.
626 */
627 data.insoffs = 0;
628 data.inslen = 0;
629
630 if (map) {
631 out_rawdata(&data, map, len);
632 } else if ((off_t)m == len) {
633 out_rawdata(&data, buf, len);
634 } else {
635 off_t l = len;
636
637 if (fseeko(fp, base, SEEK_SET) < 0 || ferror(fp)) {
638 nasm_error(ERR_NONFATAL,
639 "`incbin': unable to seek on file `%s'",
640 fname);
641 goto end_incbin;
642 }
643 while (l > 0) {
644 m = fread(buf, 1, l < (off_t)blk ? (size_t)l : blk, fp);
645 if (!m || feof(fp)) {
646 /*
647 * This shouldn't happen unless the file
648 * actually changes while we are reading
649 * it.
650 */
651 nasm_error(ERR_NONFATAL,
652 "`incbin': unexpected EOF while"
653 " reading file `%s'", fname);
654 goto end_incbin;
655 }
656 out_rawdata(&data, buf, m);
657 l -= m;
658 }
659 }
660 }
661 end_incbin:
662 lfmt->downlevel(LIST_INCBIN);
663 if (instruction->times > 1) {
664 lfmt->set_offset(data.offset);
665 lfmt->uplevel(LIST_TIMES);
666 lfmt->downlevel(LIST_TIMES);
667 }
668 if (ferror(fp)) {
669 nasm_error(ERR_NONFATAL,
670 "`incbin': error while"
671 " reading file `%s'", fname);
672 }
673 close_done:
674 if (buf)
675 nasm_free(buf);
676 if (map)
677 nasm_unmap_file(map, len);
678 fclose(fp);
679 done:
680 ;
681 } else {
682 /* "Real" instruction */
683
684 /* Check to see if we need an address-size prefix */
685 add_asp(instruction, bits);
686
687 m = find_match(&temp, instruction, data.segment, data.offset, bits);
688
689 if (m == MOK_GOOD) {
690 /* Matches! */
691 int64_t insn_size = calcsize(data.segment, data.offset,
692 bits, instruction, temp);
693 itimes = instruction->times;
694 if (insn_size < 0) /* shouldn't be, on pass two */
695 nasm_panic(0, "errors made it through from pass one");
696
697 data.itemp = temp;
698 data.bits = bits;
699
700 while (itimes--) {
701 data.insoffs = 0;
702 data.inslen = insn_size;
703
704 gencode(&data, instruction);
705 nasm_assert(data.insoffs == insn_size);
706
707 if (itimes > 0 && itimes == instruction->times - 1) {
708 lfmt->set_offset(data.offset);
709 lfmt->uplevel(LIST_TIMES);
710 }
711 }
712 if (instruction->times > 1)
713 lfmt->downlevel(LIST_TIMES);
714 } else {
715 /* No match */
716 switch (m) {
717 case MERR_OPSIZEMISSING:
718 nasm_error(ERR_NONFATAL, "operation size not specified");
719 break;
720 case MERR_OPSIZEMISMATCH:
721 nasm_error(ERR_NONFATAL, "mismatch in operand sizes");
722 break;
723 case MERR_BRNUMMISMATCH:
724 nasm_error(ERR_NONFATAL,
725 "mismatch in the number of broadcasting elements");
726 break;
727 case MERR_BADCPU:
728 nasm_error(ERR_NONFATAL, "no instruction for this cpu level");
729 break;
730 case MERR_BADMODE:
731 nasm_error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
732 bits);
733 break;
734 case MERR_ENCMISMATCH:
735 nasm_error(ERR_NONFATAL, "specific encoding scheme not available");
736 break;
737 case MERR_BADBND:
738 nasm_error(ERR_NONFATAL, "bnd prefix is not allowed");
739 break;
740 case MERR_BADREPNE:
741 nasm_error(ERR_NONFATAL, "%s prefix is not allowed",
742 (has_prefix(instruction, PPS_REP, P_REPNE) ?
743 "repne" : "repnz"));
744 break;
745 default:
746 nasm_error(ERR_NONFATAL,
747 "invalid combination of opcode and operands");
748 break;
749 }
750 }
751 }
752 return data.offset - start;
753 }
754
755 int64_t insn_size(int32_t segment, int64_t offset, int bits, iflag_t cp,
756 insn * instruction)
757 {
758 const struct itemplate *temp;
759 enum match_result m;
760
761 cpu = cp;
762
763 if (instruction->opcode == I_none)
764 return 0;
765
766 if (instruction->opcode == I_DB || instruction->opcode == I_DW ||
767 instruction->opcode == I_DD || instruction->opcode == I_DQ ||
768 instruction->opcode == I_DT || instruction->opcode == I_DO ||
769 instruction->opcode == I_DY) {
770 extop *e;
771 int32_t isize, osize, wsize;
772
773 isize = 0;
774 wsize = idata_bytes(instruction->opcode);
775
776 list_for_each(e, instruction->eops) {
777 int32_t align;
778
779 osize = 0;
780 if (e->type == EOT_DB_NUMBER) {
781 osize = 1;
782 warn_overflow_const(e->offset, wsize);
783 } else if (e->type == EOT_DB_STRING ||
784 e->type == EOT_DB_STRING_FREE)
785 osize = e->stringlen;
786
787 align = (-osize) % wsize;
788 if (align < 0)
789 align += wsize;
790 isize += osize + align;
791 }
792 return isize;
793 }
794
795 if (instruction->opcode == I_INCBIN) {
796 const char *fname = instruction->eops->stringval;
797 off_t len;
798
799 len = nasm_file_size_by_path(fname);
800 if (len == (off_t)-1) {
801 nasm_error(ERR_NONFATAL, "`incbin': unable to get length of file `%s'",
802 fname);
803 return 0;
804 }
805
806 if (instruction->eops->next) {
807 if (len <= (off_t)instruction->eops->next->offset) {
808 len = 0;
809 } else {
810 len -= instruction->eops->next->offset;
811 if (instruction->eops->next->next &&
812 len > (off_t)instruction->eops->next->next->offset) {
813 len = (off_t)instruction->eops->next->next->offset;
814 }
815 }
816 }
817
818 return len;
819 }
820
821 /* Check to see if we need an address-size prefix */
822 add_asp(instruction, bits);
823
824 m = find_match(&temp, instruction, segment, offset, bits);
825 if (m == MOK_GOOD) {
826 /* we've matched an instruction. */
827 return calcsize(segment, offset, bits, instruction, temp);
828 } else {
829 return -1; /* didn't match any instruction */
830 }
831 }
832
833 static void bad_hle_warn(const insn * ins, uint8_t hleok)
834 {
835 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
836 enum whatwarn { w_none, w_lock, w_inval } ww;
837 static const enum whatwarn warn[2][4] =
838 {
839 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
840 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
841 };
842 unsigned int n;
843
844 n = (unsigned int)rep_pfx - P_XACQUIRE;
845 if (n > 1)
846 return; /* Not XACQUIRE/XRELEASE */
847
848 ww = warn[n][hleok];
849 if (!is_class(MEMORY, ins->oprs[0].type))
850 ww = w_inval; /* HLE requires operand 0 to be memory */
851
852 switch (ww) {
853 case w_none:
854 break;
855
856 case w_lock:
857 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
858 nasm_error(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
859 "%s with this instruction requires lock",
860 prefix_name(rep_pfx));
861 }
862 break;
863
864 case w_inval:
865 nasm_error(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
866 "%s invalid with this instruction",
867 prefix_name(rep_pfx));
868 break;
869 }
870 }
871
872 /* Common construct */
873 #define case3(x) case (x): case (x)+1: case (x)+2
874 #define case4(x) case3(x): case (x)+3
875
876 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
877 insn * ins, const struct itemplate *temp)
878 {
879 const uint8_t *codes = temp->code;
880 int64_t length = 0;
881 uint8_t c;
882 int rex_mask = ~0;
883 int op1, op2;
884 struct operand *opx;
885 uint8_t opex = 0;
886 enum ea_type eat;
887 uint8_t hleok = 0;
888 bool lockcheck = true;
889 enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
890
891 ins->rex = 0; /* Ensure REX is reset */
892 eat = EA_SCALAR; /* Expect a scalar EA */
893 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
894
895 if (ins->prefixes[PPS_OSIZE] == P_O64)
896 ins->rex |= REX_W;
897
898 (void)segment; /* Don't warn that this parameter is unused */
899 (void)offset; /* Don't warn that this parameter is unused */
900
901 while (*codes) {
902 c = *codes++;
903 op1 = (c & 3) + ((opex & 1) << 2);
904 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
905 opx = &ins->oprs[op1];
906 opex = 0; /* For the next iteration */
907
908 switch (c) {
909 case4(01):
910 codes += c, length += c;
911 break;
912
913 case3(05):
914 opex = c;
915 break;
916
917 case4(010):
918 ins->rex |=
919 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
920 codes++, length++;
921 break;
922
923 case4(014):
924 /* this is an index reg of MIB operand */
925 mib_index = opx->basereg;
926 break;
927
928 case4(020):
929 case4(024):
930 length++;
931 break;
932
933 case4(030):
934 length += 2;
935 break;
936
937 case4(034):
938 if (opx->type & (BITS16 | BITS32 | BITS64))
939 length += (opx->type & BITS16) ? 2 : 4;
940 else
941 length += (bits == 16) ? 2 : 4;
942 break;
943
944 case4(040):
945 length += 4;
946 break;
947
948 case4(044):
949 length += ins->addr_size >> 3;
950 break;
951
952 case4(050):
953 length++;
954 break;
955
956 case4(054):
957 length += 8; /* MOV reg64/imm */
958 break;
959
960 case4(060):
961 length += 2;
962 break;
963
964 case4(064):
965 if (opx->type & (BITS16 | BITS32 | BITS64))
966 length += (opx->type & BITS16) ? 2 : 4;
967 else
968 length += (bits == 16) ? 2 : 4;
969 break;
970
971 case4(070):
972 length += 4;
973 break;
974
975 case4(074):
976 length += 2;
977 break;
978
979 case 0172:
980 case 0173:
981 codes++;
982 length++;
983 break;
984
985 case4(0174):
986 length++;
987 break;
988
989 case4(0240):
990 ins->rex |= REX_EV;
991 ins->vexreg = regval(opx);
992 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
993 ins->vex_cm = *codes++;
994 ins->vex_wlp = *codes++;
995 ins->evex_tuple = (*codes++ - 0300);
996 break;
997
998 case 0250:
999 ins->rex |= REX_EV;
1000 ins->vexreg = 0;
1001 ins->vex_cm = *codes++;
1002 ins->vex_wlp = *codes++;
1003 ins->evex_tuple = (*codes++ - 0300);
1004 break;
1005
1006 case4(0254):
1007 length += 4;
1008 break;
1009
1010 case4(0260):
1011 ins->rex |= REX_V;
1012 ins->vexreg = regval(opx);
1013 ins->vex_cm = *codes++;
1014 ins->vex_wlp = *codes++;
1015 break;
1016
1017 case 0270:
1018 ins->rex |= REX_V;
1019 ins->vexreg = 0;
1020 ins->vex_cm = *codes++;
1021 ins->vex_wlp = *codes++;
1022 break;
1023
1024 case3(0271):
1025 hleok = c & 3;
1026 break;
1027
1028 case4(0274):
1029 length++;
1030 break;
1031
1032 case4(0300):
1033 break;
1034
1035 case 0310:
1036 if (bits == 64)
1037 return -1;
1038 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1039 break;
1040
1041 case 0311:
1042 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1043 break;
1044
1045 case 0312:
1046 break;
1047
1048 case 0313:
1049 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1050 has_prefix(ins, PPS_ASIZE, P_A32))
1051 return -1;
1052 break;
1053
1054 case4(0314):
1055 break;
1056
1057 case 0320:
1058 {
1059 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1060 if (pfx == P_O16)
1061 break;
1062 if (pfx != P_none)
1063 nasm_error(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1064 else
1065 ins->prefixes[PPS_OSIZE] = P_O16;
1066 break;
1067 }
1068
1069 case 0321:
1070 {
1071 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1072 if (pfx == P_O32)
1073 break;
1074 if (pfx != P_none)
1075 nasm_error(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1076 else
1077 ins->prefixes[PPS_OSIZE] = P_O32;
1078 break;
1079 }
1080
1081 case 0322:
1082 break;
1083
1084 case 0323:
1085 rex_mask &= ~REX_W;
1086 break;
1087
1088 case 0324:
1089 ins->rex |= REX_W;
1090 break;
1091
1092 case 0325:
1093 ins->rex |= REX_NH;
1094 break;
1095
1096 case 0326:
1097 break;
1098
1099 case 0330:
1100 codes++, length++;
1101 break;
1102
1103 case 0331:
1104 break;
1105
1106 case 0332:
1107 case 0333:
1108 length++;
1109 break;
1110
1111 case 0334:
1112 ins->rex |= REX_L;
1113 break;
1114
1115 case 0335:
1116 break;
1117
1118 case 0336:
1119 if (!ins->prefixes[PPS_REP])
1120 ins->prefixes[PPS_REP] = P_REP;
1121 break;
1122
1123 case 0337:
1124 if (!ins->prefixes[PPS_REP])
1125 ins->prefixes[PPS_REP] = P_REPNE;
1126 break;
1127
1128 case 0340:
1129 if (ins->oprs[0].segment != NO_SEG)
1130 nasm_error(ERR_NONFATAL, "attempt to reserve non-constant"
1131 " quantity of BSS space");
1132 else if (ins->oprs[0].opflags & OPFLAG_FORWARD)
1133 nasm_error(ERR_WARNING | ERR_PASS1,
1134 "forward reference in RESx can have unpredictable results");
1135 else
1136 length += ins->oprs[0].offset;
1137 break;
1138
1139 case 0341:
1140 if (!ins->prefixes[PPS_WAIT])
1141 ins->prefixes[PPS_WAIT] = P_WAIT;
1142 break;
1143
1144 case 0360:
1145 break;
1146
1147 case 0361:
1148 length++;
1149 break;
1150
1151 case 0364:
1152 case 0365:
1153 break;
1154
1155 case 0366:
1156 case 0367:
1157 length++;
1158 break;
1159
1160 case 0370:
1161 case 0371:
1162 break;
1163
1164 case 0373:
1165 length++;
1166 break;
1167
1168 case 0374:
1169 eat = EA_XMMVSIB;
1170 break;
1171
1172 case 0375:
1173 eat = EA_YMMVSIB;
1174 break;
1175
1176 case 0376:
1177 eat = EA_ZMMVSIB;
1178 break;
1179
1180 case4(0100):
1181 case4(0110):
1182 case4(0120):
1183 case4(0130):
1184 case4(0200):
1185 case4(0204):
1186 case4(0210):
1187 case4(0214):
1188 case4(0220):
1189 case4(0224):
1190 case4(0230):
1191 case4(0234):
1192 {
1193 ea ea_data;
1194 int rfield;
1195 opflags_t rflags;
1196 struct operand *opy = &ins->oprs[op2];
1197 struct operand *op_er_sae;
1198
1199 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1200
1201 if (c <= 0177) {
1202 /* pick rfield from operand b (opx) */
1203 rflags = regflag(opx);
1204 rfield = nasm_regvals[opx->basereg];
1205 } else {
1206 rflags = 0;
1207 rfield = c & 7;
1208 }
1209
1210 /* EVEX.b1 : evex_brerop contains the operand position */
1211 op_er_sae = (ins->evex_brerop >= 0 ?
1212 &ins->oprs[ins->evex_brerop] : NULL);
1213
1214 if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
1215 /* set EVEX.b */
1216 ins->evex_p[2] |= EVEX_P2B;
1217 if (op_er_sae->decoflags & ER) {
1218 /* set EVEX.RC (rounding control) */
1219 ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
1220 & EVEX_P2RC;
1221 }
1222 } else {
1223 /* set EVEX.L'L (vector length) */
1224 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1225 ins->evex_p[1] |= ((ins->vex_wlp << (7 - 4)) & EVEX_P1W);
1226 if (opy->decoflags & BRDCAST_MASK) {
1227 /* set EVEX.b */
1228 ins->evex_p[2] |= EVEX_P2B;
1229 }
1230 }
1231
1232 if (itemp_has(temp, IF_MIB)) {
1233 opy->eaflags |= EAF_MIB;
1234 /*
1235 * if a separate form of MIB (ICC style) is used,
1236 * the index reg info is merged into mem operand
1237 */
1238 if (mib_index != R_none) {
1239 opy->indexreg = mib_index;
1240 opy->scale = 1;
1241 opy->hintbase = mib_index;
1242 opy->hinttype = EAH_NOTBASE;
1243 }
1244 }
1245
1246 if (process_ea(opy, &ea_data, bits,
1247 rfield, rflags, ins) != eat) {
1248 nasm_error(ERR_NONFATAL, "invalid effective address");
1249 return -1;
1250 } else {
1251 ins->rex |= ea_data.rex;
1252 length += ea_data.size;
1253 }
1254 }
1255 break;
1256
1257 default:
1258 nasm_panic(0, "internal instruction table corrupt"
1259 ": instruction code \\%o (0x%02X) given", c, c);
1260 break;
1261 }
1262 }
1263
1264 ins->rex &= rex_mask;
1265
1266 if (ins->rex & REX_NH) {
1267 if (ins->rex & REX_H) {
1268 nasm_error(ERR_NONFATAL, "instruction cannot use high registers");
1269 return -1;
1270 }
1271 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1272 }
1273
1274 switch (ins->prefixes[PPS_VEX]) {
1275 case P_EVEX:
1276 if (!(ins->rex & REX_EV))
1277 return -1;
1278 break;
1279 case P_VEX3:
1280 case P_VEX2:
1281 if (!(ins->rex & REX_V))
1282 return -1;
1283 break;
1284 default:
1285 break;
1286 }
1287
1288 if (ins->rex & (REX_V | REX_EV)) {
1289 int bad32 = REX_R|REX_W|REX_X|REX_B;
1290
1291 if (ins->rex & REX_H) {
1292 nasm_error(ERR_NONFATAL, "cannot use high register in AVX instruction");
1293 return -1;
1294 }
1295 switch (ins->vex_wlp & 060) {
1296 case 000:
1297 case 040:
1298 ins->rex &= ~REX_W;
1299 break;
1300 case 020:
1301 ins->rex |= REX_W;
1302 bad32 &= ~REX_W;
1303 break;
1304 case 060:
1305 /* Follow REX_W */
1306 break;
1307 }
1308
1309 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1310 nasm_error(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1311 return -1;
1312 } else if (!(ins->rex & REX_EV) &&
1313 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1314 nasm_error(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1315 return -1;
1316 }
1317 if (ins->rex & REX_EV)
1318 length += 4;
1319 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1320 ins->prefixes[PPS_VEX] == P_VEX3)
1321 length += 3;
1322 else
1323 length += 2;
1324 } else if (ins->rex & REX_MASK) {
1325 if (ins->rex & REX_H) {
1326 nasm_error(ERR_NONFATAL, "cannot use high register in rex instruction");
1327 return -1;
1328 } else if (bits == 64) {
1329 length++;
1330 } else if ((ins->rex & REX_L) &&
1331 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1332 iflag_ffs(&cpu) >= IF_X86_64) {
1333 /* LOCK-as-REX.R */
1334 assert_no_prefix(ins, PPS_LOCK);
1335 lockcheck = false; /* Already errored, no need for warning */
1336 length++;
1337 } else {
1338 nasm_error(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1339 return -1;
1340 }
1341 }
1342
1343 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1344 (!itemp_has(temp,IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1345 nasm_error(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1346 "instruction is not lockable");
1347 }
1348
1349 bad_hle_warn(ins, hleok);
1350
1351 /*
1352 * when BND prefix is set by DEFAULT directive,
1353 * BND prefix is added to every appropriate instruction line
1354 * unless it is overridden by NOBND prefix.
1355 */
1356 if (globalbnd &&
1357 (itemp_has(temp, IF_BND) && !has_prefix(ins, PPS_REP, P_NOBND)))
1358 ins->prefixes[PPS_REP] = P_BND;
1359
1360 /*
1361 * Add length of legacy prefixes
1362 */
1363 length += emit_prefix(NULL, bits, ins);
1364
1365 return length;
1366 }
1367
1368 static inline void emit_rex(struct out_data *data, insn *ins)
1369 {
1370 if (data->bits == 64) {
1371 if ((ins->rex & REX_MASK) &&
1372 !(ins->rex & (REX_V | REX_EV)) &&
1373 !ins->rex_done) {
1374 uint8_t rex = (ins->rex & REX_MASK) | REX_P;
1375 out_rawbyte(data, rex);
1376 ins->rex_done = true;
1377 }
1378 }
1379 }
1380
1381 static int emit_prefix(struct out_data *data, const int bits, insn *ins)
1382 {
1383 int bytes = 0;
1384 int j;
1385
1386 for (j = 0; j < MAXPREFIX; j++) {
1387 uint8_t c = 0;
1388 switch (ins->prefixes[j]) {
1389 case P_WAIT:
1390 c = 0x9B;
1391 break;
1392 case P_LOCK:
1393 c = 0xF0;
1394 break;
1395 case P_REPNE:
1396 case P_REPNZ:
1397 case P_XACQUIRE:
1398 case P_BND:
1399 c = 0xF2;
1400 break;
1401 case P_REPE:
1402 case P_REPZ:
1403 case P_REP:
1404 case P_XRELEASE:
1405 c = 0xF3;
1406 break;
1407 case R_CS:
1408 if (bits == 64) {
1409 nasm_error(ERR_WARNING | ERR_PASS2,
1410 "cs segment base generated, but will be ignored in 64-bit mode");
1411 }
1412 c = 0x2E;
1413 break;
1414 case R_DS:
1415 if (bits == 64) {
1416 nasm_error(ERR_WARNING | ERR_PASS2,
1417 "ds segment base generated, but will be ignored in 64-bit mode");
1418 }
1419 c = 0x3E;
1420 break;
1421 case R_ES:
1422 if (bits == 64) {
1423 nasm_error(ERR_WARNING | ERR_PASS2,
1424 "es segment base generated, but will be ignored in 64-bit mode");
1425 }
1426 c = 0x26;
1427 break;
1428 case R_FS:
1429 c = 0x64;
1430 break;
1431 case R_GS:
1432 c = 0x65;
1433 break;
1434 case R_SS:
1435 if (bits == 64) {
1436 nasm_error(ERR_WARNING | ERR_PASS2,
1437 "ss segment base generated, but will be ignored in 64-bit mode");
1438 }
1439 c = 0x36;
1440 break;
1441 case R_SEGR6:
1442 case R_SEGR7:
1443 nasm_error(ERR_NONFATAL,
1444 "segr6 and segr7 cannot be used as prefixes");
1445 break;
1446 case P_A16:
1447 if (bits == 64) {
1448 nasm_error(ERR_NONFATAL,
1449 "16-bit addressing is not supported "
1450 "in 64-bit mode");
1451 } else if (bits != 16)
1452 c = 0x67;
1453 break;
1454 case P_A32:
1455 if (bits != 32)
1456 c = 0x67;
1457 break;
1458 case P_A64:
1459 if (bits != 64) {
1460 nasm_error(ERR_NONFATAL,
1461 "64-bit addressing is only supported "
1462 "in 64-bit mode");
1463 }
1464 break;
1465 case P_ASP:
1466 c = 0x67;
1467 break;
1468 case P_O16:
1469 if (bits != 16)
1470 c = 0x66;
1471 break;
1472 case P_O32:
1473 if (bits == 16)
1474 c = 0x66;
1475 break;
1476 case P_O64:
1477 /* REX.W */
1478 break;
1479 case P_OSP:
1480 c = 0x66;
1481 break;
1482 case P_EVEX:
1483 case P_VEX3:
1484 case P_VEX2:
1485 case P_NOBND:
1486 case P_none:
1487 break;
1488 default:
1489 nasm_panic(0, "invalid instruction prefix");
1490 }
1491 if (c) {
1492 if (data)
1493 out_rawbyte(data, c);
1494 bytes++;
1495 }
1496 }
1497 return bytes;
1498 }
1499
1500 static void gencode(struct out_data *data, insn *ins)
1501 {
1502 uint8_t c;
1503 uint8_t bytes[4];
1504 int64_t size;
1505 int op1, op2;
1506 struct operand *opx;
1507 const uint8_t *codes = data->itemp->code;
1508 uint8_t opex = 0;
1509 enum ea_type eat = EA_SCALAR;
1510 int r;
1511 const int bits = data->bits;
1512
1513 ins->rex_done = false;
1514
1515 emit_prefix(data, bits, ins);
1516
1517 while (*codes) {
1518 c = *codes++;
1519 op1 = (c & 3) + ((opex & 1) << 2);
1520 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1521 opx = &ins->oprs[op1];
1522 opex = 0; /* For the next iteration */
1523
1524
1525 switch (c) {
1526 case 01:
1527 case 02:
1528 case 03:
1529 case 04:
1530 emit_rex(data, ins);
1531 out_rawdata(data, codes, c);
1532 codes += c;
1533 break;
1534
1535 case 05:
1536 case 06:
1537 case 07:
1538 opex = c;
1539 break;
1540
1541 case4(010):
1542 emit_rex(data, ins);
1543 out_rawbyte(data, *codes++ + (regval(opx) & 7));
1544 break;
1545
1546 case4(014):
1547 break;
1548
1549 case4(020):
1550 if (opx->offset < -256 || opx->offset > 255)
1551 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1552 "byte value exceeds bounds");
1553 out_imm(data, opx, 1, OUT_WRAP);
1554 break;
1555
1556 case4(024):
1557 if (opx->offset < 0 || opx->offset > 255)
1558 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1559 "unsigned byte value exceeds bounds");
1560 out_imm(data, opx, 1, OUT_UNSIGNED);
1561 break;
1562
1563 case4(030):
1564 warn_overflow_opd(opx, 2);
1565 out_imm(data, opx, 2, OUT_WRAP);
1566 break;
1567
1568 case4(034):
1569 if (opx->type & (BITS16 | BITS32))
1570 size = (opx->type & BITS16) ? 2 : 4;
1571 else
1572 size = (bits == 16) ? 2 : 4;
1573 warn_overflow_opd(opx, size);
1574 out_imm(data, opx, size, OUT_WRAP);
1575 break;
1576
1577 case4(040):
1578 warn_overflow_opd(opx, 4);
1579 out_imm(data, opx, 4, OUT_WRAP);
1580 break;
1581
1582 case4(044):
1583 size = ins->addr_size >> 3;
1584 warn_overflow_opd(opx, size);
1585 out_imm(data, opx, size, OUT_WRAP);
1586 break;
1587
1588 case4(050):
1589 if (opx->segment == data->segment) {
1590 int64_t delta = opx->offset - data->offset
1591 - (data->inslen - data->insoffs);
1592 if (delta > 127 || delta < -128)
1593 nasm_error(ERR_NONFATAL, "short jump is out of range");
1594 }
1595 out_reladdr(data, opx, 1);
1596 break;
1597
1598 case4(054):
1599 out_imm(data, opx, 8, OUT_WRAP);
1600 break;
1601
1602 case4(060):
1603 out_reladdr(data, opx, 2);
1604 break;
1605
1606 case4(064):
1607 if (opx->type & (BITS16 | BITS32 | BITS64))
1608 size = (opx->type & BITS16) ? 2 : 4;
1609 else
1610 size = (bits == 16) ? 2 : 4;
1611
1612 out_reladdr(data, opx, size);
1613 break;
1614
1615 case4(070):
1616 out_reladdr(data, opx, 4);
1617 break;
1618
1619 case4(074):
1620 if (opx->segment == NO_SEG)
1621 nasm_error(ERR_NONFATAL, "value referenced by FAR is not"
1622 " relocatable");
1623 out_segment(data, opx);
1624 break;
1625
1626 case 0172:
1627 {
1628 int mask = ins->prefixes[PPS_VEX] == P_EVEX ? 7 : 15;
1629 const struct operand *opy;
1630
1631 c = *codes++;
1632 opx = &ins->oprs[c >> 3];
1633 opy = &ins->oprs[c & 7];
1634 if (opy->segment != NO_SEG || opy->wrt != NO_SEG) {
1635 nasm_error(ERR_NONFATAL,
1636 "non-absolute expression not permitted as argument %d",
1637 c & 7);
1638 } else if (opy->offset & ~mask) {
1639 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1640 "is4 argument exceeds bounds");
1641 }
1642 c = opy->offset & mask;
1643 goto emit_is4;
1644 }
1645
1646 case 0173:
1647 c = *codes++;
1648 opx = &ins->oprs[c >> 4];
1649 c &= 15;
1650 goto emit_is4;
1651
1652 case4(0174):
1653 c = 0;
1654 emit_is4:
1655 r = nasm_regvals[opx->basereg];
1656 out_rawbyte(data, (r << 4) | ((r & 0x10) >> 1) | c);
1657 break;
1658
1659 case4(0254):
1660 if (opx->wrt == NO_SEG && opx->segment == NO_SEG &&
1661 (int32_t)opx->offset != (int64_t)opx->offset) {
1662 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1663 "signed dword immediate exceeds bounds");
1664 }
1665 out_imm(data, opx, 4, OUT_SIGNED);
1666 break;
1667
1668 case4(0240):
1669 case 0250:
1670 codes += 3;
1671 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1672 EVEX_P2Z | EVEX_P2AAA, 2);
1673 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1674 bytes[0] = 0x62;
1675 /* EVEX.X can be set by either REX or EVEX for different reasons */
1676 bytes[1] = ((((ins->rex & 7) << 5) |
1677 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) ^ 0xf0) |
1678 (ins->vex_cm & EVEX_P0MM);
1679 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1680 ((~ins->vexreg & 15) << 3) |
1681 (1 << 2) | (ins->vex_wlp & 3);
1682 bytes[3] = ins->evex_p[2];
1683 out_rawdata(data, bytes, 4);
1684 break;
1685
1686 case4(0260):
1687 case 0270:
1688 codes += 2;
1689 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1690 ins->prefixes[PPS_VEX] == P_VEX3) {
1691 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1692 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1693 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1694 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1695 out_rawdata(data, bytes, 3);
1696 } else {
1697 bytes[0] = 0xc5;
1698 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1699 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1700 out_rawdata(data, bytes, 2);
1701 }
1702 break;
1703
1704 case 0271:
1705 case 0272:
1706 case 0273:
1707 break;
1708
1709 case4(0274):
1710 {
1711 uint64_t uv, um;
1712 int s;
1713
1714 if (ins->rex & REX_W)
1715 s = 64;
1716 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1717 s = 16;
1718 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1719 s = 32;
1720 else
1721 s = bits;
1722
1723 um = (uint64_t)2 << (s-1);
1724 uv = opx->offset;
1725
1726 if (uv > 127 && uv < (uint64_t)-128 &&
1727 (uv < um-128 || uv > um-1)) {
1728 /* If this wasn't explicitly byte-sized, warn as though we
1729 * had fallen through to the imm16/32/64 case.
1730 */
1731 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1732 "%s value exceeds bounds",
1733 (opx->type & BITS8) ? "signed byte" :
1734 s == 16 ? "word" :
1735 s == 32 ? "dword" :
1736 "signed dword");
1737 }
1738 out_imm(data, opx, 1, OUT_WRAP); /* XXX: OUT_SIGNED? */
1739 break;
1740 }
1741
1742 case4(0300):
1743 break;
1744
1745 case 0310:
1746 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16))
1747 out_rawbyte(data, 0x67);
1748 break;
1749
1750 case 0311:
1751 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32))
1752 out_rawbyte(data, 0x67);
1753 break;
1754
1755 case 0312:
1756 break;
1757
1758 case 0313:
1759 ins->rex = 0;
1760 break;
1761
1762 case4(0314):
1763 break;
1764
1765 case 0320:
1766 case 0321:
1767 break;
1768
1769 case 0322:
1770 case 0323:
1771 break;
1772
1773 case 0324:
1774 ins->rex |= REX_W;
1775 break;
1776
1777 case 0325:
1778 break;
1779
1780 case 0326:
1781 break;
1782
1783 case 0330:
1784 out_rawbyte(data, *codes++ ^ get_cond_opcode(ins->condition));
1785 break;
1786
1787 case 0331:
1788 break;
1789
1790 case 0332:
1791 case 0333:
1792 out_rawbyte(data, c - 0332 + 0xF2);
1793 break;
1794
1795 case 0334:
1796 if (ins->rex & REX_R)
1797 out_rawbyte(data, 0xF0);
1798 ins->rex &= ~(REX_L|REX_R);
1799 break;
1800
1801 case 0335:
1802 break;
1803
1804 case 0336:
1805 case 0337:
1806 break;
1807
1808 case 0340:
1809 if (ins->oprs[0].segment != NO_SEG)
1810 nasm_panic(0, "non-constant BSS size in pass two");
1811
1812 out_reserve(data, ins->oprs[0].offset);
1813 break;
1814
1815 case 0341:
1816 break;
1817
1818 case 0360:
1819 break;
1820
1821 case 0361:
1822 out_rawbyte(data, 0x66);
1823 break;
1824
1825 case 0364:
1826 case 0365:
1827 break;
1828
1829 case 0366:
1830 case 0367:
1831 out_rawbyte(data, c - 0366 + 0x66);
1832 break;
1833
1834 case3(0370):
1835 break;
1836
1837 case 0373:
1838 out_rawbyte(data, bits == 16 ? 3 : 5);
1839 break;
1840
1841 case 0374:
1842 eat = EA_XMMVSIB;
1843 break;
1844
1845 case 0375:
1846 eat = EA_YMMVSIB;
1847 break;
1848
1849 case 0376:
1850 eat = EA_ZMMVSIB;
1851 break;
1852
1853 case4(0100):
1854 case4(0110):
1855 case4(0120):
1856 case4(0130):
1857 case4(0200):
1858 case4(0204):
1859 case4(0210):
1860 case4(0214):
1861 case4(0220):
1862 case4(0224):
1863 case4(0230):
1864 case4(0234):
1865 {
1866 ea ea_data;
1867 int rfield;
1868 opflags_t rflags;
1869 uint8_t *p;
1870 struct operand *opy = &ins->oprs[op2];
1871
1872 if (c <= 0177) {
1873 /* pick rfield from operand b (opx) */
1874 rflags = regflag(opx);
1875 rfield = nasm_regvals[opx->basereg];
1876 } else {
1877 /* rfield is constant */
1878 rflags = 0;
1879 rfield = c & 7;
1880 }
1881
1882 if (process_ea(opy, &ea_data, bits,
1883 rfield, rflags, ins) != eat)
1884 nasm_error(ERR_NONFATAL, "invalid effective address");
1885
1886 p = bytes;
1887 *p++ = ea_data.modrm;
1888 if (ea_data.sib_present)
1889 *p++ = ea_data.sib;
1890 out_rawdata(data, bytes, p - bytes);
1891
1892 /*
1893 * Make sure the address gets the right offset in case
1894 * the line breaks in the .lst file (BR 1197827)
1895 */
1896
1897 if (ea_data.bytes) {
1898 /* use compressed displacement, if available */
1899 if (ea_data.disp8) {
1900 out_rawbyte(data, ea_data.disp8);
1901 } else if (ea_data.rip) {
1902 out_reladdr(data, opy, ea_data.bytes);
1903 } else {
1904 int asize = ins->addr_size >> 3;
1905
1906 if (overflow_general(opy->offset, asize) ||
1907 signed_bits(opy->offset, ins->addr_size) !=
1908 signed_bits(opy->offset, ea_data.bytes << 3))
1909 warn_overflow(ERR_PASS2, ea_data.bytes);
1910
1911 out_imm(data, opy, ea_data.bytes,
1912 (asize > ea_data.bytes) ? OUT_SIGNED : OUT_UNSIGNED);
1913 }
1914 }
1915 }
1916 break;
1917
1918 default:
1919 nasm_panic(0, "internal instruction table corrupt"
1920 ": instruction code \\%o (0x%02X) given", c, c);
1921 break;
1922 }
1923 }
1924 }
1925
1926 static opflags_t regflag(const operand * o)
1927 {
1928 if (!is_register(o->basereg))
1929 nasm_panic(0, "invalid operand passed to regflag()");
1930 return nasm_reg_flags[o->basereg];
1931 }
1932
1933 static int32_t regval(const operand * o)
1934 {
1935 if (!is_register(o->basereg))
1936 nasm_panic(0, "invalid operand passed to regval()");
1937 return nasm_regvals[o->basereg];
1938 }
1939
1940 static int op_rexflags(const operand * o, int mask)
1941 {
1942 opflags_t flags;
1943 int val;
1944
1945 if (!is_register(o->basereg))
1946 nasm_panic(0, "invalid operand passed to op_rexflags()");
1947
1948 flags = nasm_reg_flags[o->basereg];
1949 val = nasm_regvals[o->basereg];
1950
1951 return rexflags(val, flags, mask);
1952 }
1953
1954 static int rexflags(int val, opflags_t flags, int mask)
1955 {
1956 int rex = 0;
1957
1958 if (val >= 0 && (val & 8))
1959 rex |= REX_B|REX_X|REX_R;
1960 if (flags & BITS64)
1961 rex |= REX_W;
1962 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
1963 rex |= REX_H;
1964 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
1965 rex |= REX_P;
1966
1967 return rex & mask;
1968 }
1969
1970 static int evexflags(int val, decoflags_t deco,
1971 int mask, uint8_t byte)
1972 {
1973 int evex = 0;
1974
1975 switch (byte) {
1976 case 0:
1977 if (val >= 0 && (val & 16))
1978 evex |= (EVEX_P0RP | EVEX_P0X);
1979 break;
1980 case 2:
1981 if (val >= 0 && (val & 16))
1982 evex |= EVEX_P2VP;
1983 if (deco & Z)
1984 evex |= EVEX_P2Z;
1985 if (deco & OPMASK_MASK)
1986 evex |= deco & EVEX_P2AAA;
1987 break;
1988 }
1989 return evex & mask;
1990 }
1991
1992 static int op_evexflags(const operand * o, int mask, uint8_t byte)
1993 {
1994 int val;
1995
1996 val = nasm_regvals[o->basereg];
1997
1998 return evexflags(val, o->decoflags, mask, byte);
1999 }
2000
2001 static enum match_result find_match(const struct itemplate **tempp,
2002 insn *instruction,
2003 int32_t segment, int64_t offset, int bits)
2004 {
2005 const struct itemplate *temp;
2006 enum match_result m, merr;
2007 opflags_t xsizeflags[MAX_OPERANDS];
2008 bool opsizemissing = false;
2009 int8_t broadcast = instruction->evex_brerop;
2010 int i;
2011
2012 /* broadcasting uses a different data element size */
2013 for (i = 0; i < instruction->operands; i++)
2014 if (i == broadcast)
2015 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
2016 else
2017 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
2018
2019 merr = MERR_INVALOP;
2020
2021 for (temp = nasm_instructions[instruction->opcode];
2022 temp->opcode != I_none; temp++) {
2023 m = matches(temp, instruction, bits);
2024 if (m == MOK_JUMP) {
2025 if (jmp_match(segment, offset, bits, instruction, temp))
2026 m = MOK_GOOD;
2027 else
2028 m = MERR_INVALOP;
2029 } else if (m == MERR_OPSIZEMISSING && !itemp_has(temp, IF_SX)) {
2030 /*
2031 * Missing operand size and a candidate for fuzzy matching...
2032 */
2033 for (i = 0; i < temp->operands; i++)
2034 if (i == broadcast)
2035 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
2036 else
2037 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
2038 opsizemissing = true;
2039 }
2040 if (m > merr)
2041 merr = m;
2042 if (merr == MOK_GOOD)
2043 goto done;
2044 }
2045
2046 /* No match, but see if we can get a fuzzy operand size match... */
2047 if (!opsizemissing)
2048 goto done;
2049
2050 for (i = 0; i < instruction->operands; i++) {
2051 /*
2052 * We ignore extrinsic operand sizes on registers, so we should
2053 * never try to fuzzy-match on them. This also resolves the case
2054 * when we have e.g. "xmmrm128" in two different positions.
2055 */
2056 if (is_class(REGISTER, instruction->oprs[i].type))
2057 continue;
2058
2059 /* This tests if xsizeflags[i] has more than one bit set */
2060 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2061 goto done; /* No luck */
2062
2063 if (i == broadcast) {
2064 instruction->oprs[i].decoflags |= xsizeflags[i];
2065 instruction->oprs[i].type |= (xsizeflags[i] == BR_BITS32 ?
2066 BITS32 : BITS64);
2067 } else {
2068 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2069 }
2070 }
2071
2072 /* Try matching again... */
2073 for (temp = nasm_instructions[instruction->opcode];
2074 temp->opcode != I_none; temp++) {
2075 m = matches(temp, instruction, bits);
2076 if (m == MOK_JUMP) {
2077 if (jmp_match(segment, offset, bits, instruction, temp))
2078 m = MOK_GOOD;
2079 else
2080 m = MERR_INVALOP;
2081 }
2082 if (m > merr)
2083 merr = m;
2084 if (merr == MOK_GOOD)
2085 goto done;
2086 }
2087
2088 done:
2089 *tempp = temp;
2090 return merr;
2091 }
2092
2093 static uint8_t get_broadcast_num(opflags_t opflags, opflags_t brsize)
2094 {
2095 opflags_t opsize = opflags & SIZE_MASK;
2096 uint8_t brcast_num;
2097
2098 /*
2099 * Due to discontinuity between BITS64 and BITS128 (BITS80),
2100 * this cannot be a simple arithmetic calculation.
2101 */
2102 if (brsize > BITS64)
2103 nasm_error(ERR_FATAL,
2104 "size of broadcasting element is greater than 64 bits");
2105
2106 switch (opsize) {
2107 case BITS64:
2108 brcast_num = BITS64 / brsize;
2109 break;
2110 default:
2111 brcast_num = (opsize / BITS128) * (BITS64 / brsize) * 2;
2112 break;
2113 }
2114
2115 return brcast_num;
2116 }
2117
2118 static enum match_result matches(const struct itemplate *itemp,
2119 insn *instruction, int bits)
2120 {
2121 opflags_t size[MAX_OPERANDS], asize;
2122 bool opsizemissing = false;
2123 int i, oprs;
2124
2125 /*
2126 * Check the opcode
2127 */
2128 if (itemp->opcode != instruction->opcode)
2129 return MERR_INVALOP;
2130
2131 /*
2132 * Count the operands
2133 */
2134 if (itemp->operands != instruction->operands)
2135 return MERR_INVALOP;
2136
2137 /*
2138 * Is it legal?
2139 */
2140 if (!(optimizing > 0) && itemp_has(itemp, IF_OPT))
2141 return MERR_INVALOP;
2142
2143 /*
2144 * {evex} available?
2145 */
2146 switch (instruction->prefixes[PPS_VEX]) {
2147 case P_EVEX:
2148 if (!itemp_has(itemp, IF_EVEX))
2149 return MERR_ENCMISMATCH;
2150 break;
2151 case P_VEX3:
2152 case P_VEX2:
2153 if (!itemp_has(itemp, IF_VEX))
2154 return MERR_ENCMISMATCH;
2155 break;
2156 default:
2157 break;
2158 }
2159
2160 /*
2161 * Check that no spurious colons or TOs are present
2162 */
2163 for (i = 0; i < itemp->operands; i++)
2164 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2165 return MERR_INVALOP;
2166
2167 /*
2168 * Process size flags
2169 */
2170 switch (itemp_smask(itemp)) {
2171 case IF_GENBIT(IF_SB):
2172 asize = BITS8;
2173 break;
2174 case IF_GENBIT(IF_SW):
2175 asize = BITS16;
2176 break;
2177 case IF_GENBIT(IF_SD):
2178 asize = BITS32;
2179 break;
2180 case IF_GENBIT(IF_SQ):
2181 asize = BITS64;
2182 break;
2183 case IF_GENBIT(IF_SO):
2184 asize = BITS128;
2185 break;
2186 case IF_GENBIT(IF_SY):
2187 asize = BITS256;
2188 break;
2189 case IF_GENBIT(IF_SZ):
2190 asize = BITS512;
2191 break;
2192 case IF_GENBIT(IF_SIZE):
2193 switch (bits) {
2194 case 16:
2195 asize = BITS16;
2196 break;
2197 case 32:
2198 asize = BITS32;
2199 break;
2200 case 64:
2201 asize = BITS64;
2202 break;
2203 default:
2204 asize = 0;
2205 break;
2206 }
2207 break;
2208 default:
2209 asize = 0;
2210 break;
2211 }
2212
2213 if (itemp_armask(itemp)) {
2214 /* S- flags only apply to a specific operand */
2215 i = itemp_arg(itemp);
2216 memset(size, 0, sizeof size);
2217 size[i] = asize;
2218 } else {
2219 /* S- flags apply to all operands */
2220 for (i = 0; i < MAX_OPERANDS; i++)
2221 size[i] = asize;
2222 }
2223
2224 /*
2225 * Check that the operand flags all match up,
2226 * it's a bit tricky so lets be verbose:
2227 *
2228 * 1) Find out the size of operand. If instruction
2229 * doesn't have one specified -- we're trying to
2230 * guess it either from template (IF_S* flag) or
2231 * from code bits.
2232 *
2233 * 2) If template operand do not match the instruction OR
2234 * template has an operand size specified AND this size differ
2235 * from which instruction has (perhaps we got it from code bits)
2236 * we are:
2237 * a) Check that only size of instruction and operand is differ
2238 * other characteristics do match
2239 * b) Perhaps it's a register specified in instruction so
2240 * for such a case we just mark that operand as "size
2241 * missing" and this will turn on fuzzy operand size
2242 * logic facility (handled by a caller)
2243 */
2244 for (i = 0; i < itemp->operands; i++) {
2245 opflags_t type = instruction->oprs[i].type;
2246 decoflags_t deco = instruction->oprs[i].decoflags;
2247 bool is_broadcast = deco & BRDCAST_MASK;
2248 uint8_t brcast_num = 0;
2249 opflags_t template_opsize, insn_opsize;
2250
2251 if (!(type & SIZE_MASK))
2252 type |= size[i];
2253
2254 insn_opsize = type & SIZE_MASK;
2255 if (!is_broadcast) {
2256 template_opsize = itemp->opd[i] & SIZE_MASK;
2257 } else {
2258 decoflags_t deco_brsize = itemp->deco[i] & BRSIZE_MASK;
2259 /*
2260 * when broadcasting, the element size depends on
2261 * the instruction type. decorator flag should match.
2262 */
2263
2264 if (deco_brsize) {
2265 template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
2266 /* calculate the proper number : {1to<brcast_num>} */
2267 brcast_num = get_broadcast_num(itemp->opd[i], template_opsize);
2268 } else {
2269 template_opsize = 0;
2270 }
2271 }
2272
2273 if ((itemp->opd[i] & ~type & ~SIZE_MASK) ||
2274 (deco & ~itemp->deco[i] & ~BRNUM_MASK)) {
2275 return MERR_INVALOP;
2276 } else if (template_opsize) {
2277 if (template_opsize != insn_opsize) {
2278 if (insn_opsize) {
2279 return MERR_INVALOP;
2280 } else if (!is_class(REGISTER, type)) {
2281 /*
2282 * Note: we don't honor extrinsic operand sizes for registers,
2283 * so "missing operand size" for a register should be
2284 * considered a wildcard match rather than an error.
2285 */
2286 opsizemissing = true;
2287 }
2288 } else if (is_broadcast &&
2289 (brcast_num !=
2290 (2U << ((deco & BRNUM_MASK) >> BRNUM_SHIFT)))) {
2291 /*
2292 * broadcasting opsize matches but the number of repeated memory
2293 * element does not match.
2294 * if 64b double precision float is broadcasted to ymm (256b),
2295 * broadcasting decorator must be {1to4}.
2296 */
2297 return MERR_BRNUMMISMATCH;
2298 }
2299 }
2300 }
2301
2302 if (opsizemissing)
2303 return MERR_OPSIZEMISSING;
2304
2305 /*
2306 * Check operand sizes
2307 */
2308 if (itemp_has(itemp, IF_SM) || itemp_has(itemp, IF_SM2)) {
2309 oprs = (itemp_has(itemp, IF_SM2) ? 2 : itemp->operands);
2310 for (i = 0; i < oprs; i++) {
2311 asize = itemp->opd[i] & SIZE_MASK;
2312 if (asize) {
2313 for (i = 0; i < oprs; i++)
2314 size[i] = asize;
2315 break;
2316 }
2317 }
2318 } else {
2319 oprs = itemp->operands;
2320 }
2321
2322 for (i = 0; i < itemp->operands; i++) {
2323 if (!(itemp->opd[i] & SIZE_MASK) &&
2324 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2325 return MERR_OPSIZEMISMATCH;
2326 }
2327
2328 /*
2329 * Check template is okay at the set cpu level
2330 */
2331 if (iflag_cmp_cpu_level(&insns_flags[itemp->iflag_idx], &cpu) > 0)
2332 return MERR_BADCPU;
2333
2334 /*
2335 * Verify the appropriate long mode flag.
2336 */
2337 if (itemp_has(itemp, (bits == 64 ? IF_NOLONG : IF_LONG)))
2338 return MERR_BADMODE;
2339
2340 /*
2341 * If we have a HLE prefix, look for the NOHLE flag
2342 */
2343 if (itemp_has(itemp, IF_NOHLE) &&
2344 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2345 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2346 return MERR_BADHLE;
2347
2348 /*
2349 * Check if special handling needed for Jumps
2350 */
2351 if ((itemp->code[0] & ~1) == 0370)
2352 return MOK_JUMP;
2353
2354 /*
2355 * Check if BND prefix is allowed.
2356 * Other 0xF2 (REPNE/REPNZ) prefix is prohibited.
2357 */
2358 if (!itemp_has(itemp, IF_BND) &&
2359 (has_prefix(instruction, PPS_REP, P_BND) ||
2360 has_prefix(instruction, PPS_REP, P_NOBND)))
2361 return MERR_BADBND;
2362 else if (itemp_has(itemp, IF_BND) &&
2363 (has_prefix(instruction, PPS_REP, P_REPNE) ||
2364 has_prefix(instruction, PPS_REP, P_REPNZ)))
2365 return MERR_BADREPNE;
2366
2367 return MOK_GOOD;
2368 }
2369
2370 /*
2371 * Check if ModR/M.mod should/can be 01.
2372 * - EAF_BYTEOFFS is set
2373 * - offset can fit in a byte when EVEX is not used
2374 * - offset can be compressed when EVEX is used
2375 */
2376 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2377 (o >= -128 && o <= 127 && \
2378 seg == NO_SEG && !forw_ref && \
2379 !(input->eaflags & EAF_WORDOFFS) && \
2380 !(ins->rex & REX_EV)) || \
2381 (ins->rex & REX_EV && \
2382 is_disp8n(input, ins, &output->disp8)))
2383
2384 static enum ea_type process_ea(operand *input, ea *output, int bits,
2385 int rfield, opflags_t rflags, insn *ins)
2386 {
2387 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2388 int addrbits = ins->addr_size;
2389 int eaflags = input->eaflags;
2390
2391 output->type = EA_SCALAR;
2392 output->rip = false;
2393 output->disp8 = 0;
2394
2395 /* REX flags for the rfield operand */
2396 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2397 /* EVEX.R' flag for the REG operand */
2398 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2399
2400 if (is_class(REGISTER, input->type)) {
2401 /*
2402 * It's a direct register.
2403 */
2404 if (!is_register(input->basereg))
2405 goto err;
2406
2407 if (!is_reg_class(REG_EA, input->basereg))
2408 goto err;
2409
2410 /* broadcasting is not available with a direct register operand. */
2411 if (input->decoflags & BRDCAST_MASK) {
2412 nasm_error(ERR_NONFATAL, "Broadcasting not allowed from a register");
2413 goto err;
2414 }
2415
2416 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2417 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2418 output->sib_present = false; /* no SIB necessary */
2419 output->bytes = 0; /* no offset necessary either */
2420 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2421 } else {
2422 /*
2423 * It's a memory reference.
2424 */
2425
2426 /* Embedded rounding or SAE is not available with a mem ref operand. */
2427 if (input->decoflags & (ER | SAE)) {
2428 nasm_error(ERR_NONFATAL,
2429 "Embedded rounding is available only with reg-reg op.");
2430 return -1;
2431 }
2432
2433 if (input->basereg == -1 &&
2434 (input->indexreg == -1 || input->scale == 0)) {
2435 /*
2436 * It's a pure offset.
2437 */
2438 if (bits == 64 && ((input->type & IP_REL) == IP_REL) &&
2439 input->segment == NO_SEG) {
2440 nasm_error(ERR_WARNING | ERR_PASS1, "absolute address can not be RIP-relative");
2441 input->type &= ~IP_REL;
2442 input->type |= MEMORY;
2443 }
2444
2445 if (bits == 64 &&
2446 !(IP_REL & ~input->type) && (eaflags & EAF_MIB)) {
2447 nasm_error(ERR_NONFATAL, "RIP-relative addressing is prohibited for mib.");
2448 return -1;
2449 }
2450
2451 if (eaflags & EAF_BYTEOFFS ||
2452 (eaflags & EAF_WORDOFFS &&
2453 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2454 nasm_error(ERR_WARNING | ERR_PASS1, "displacement size ignored on absolute address");
2455 }
2456
2457 if (bits == 64 && (~input->type & IP_REL)) {
2458 output->sib_present = true;
2459 output->sib = GEN_SIB(0, 4, 5);
2460 output->bytes = 4;
2461 output->modrm = GEN_MODRM(0, rfield, 4);
2462 output->rip = false;
2463 } else {
2464 output->sib_present = false;
2465 output->bytes = (addrbits != 16 ? 4 : 2);
2466 output->modrm = GEN_MODRM(0, rfield, (addrbits != 16 ? 5 : 6));
2467 output->rip = bits == 64;
2468 }
2469 } else {
2470 /*
2471 * It's an indirection.
2472 */
2473 int i = input->indexreg, b = input->basereg, s = input->scale;
2474 int32_t seg = input->segment;
2475 int hb = input->hintbase, ht = input->hinttype;
2476 int t, it, bt; /* register numbers */
2477 opflags_t x, ix, bx; /* register flags */
2478
2479 if (s == 0)
2480 i = -1; /* make this easy, at least */
2481
2482 if (is_register(i)) {
2483 it = nasm_regvals[i];
2484 ix = nasm_reg_flags[i];
2485 } else {
2486 it = -1;
2487 ix = 0;
2488 }
2489
2490 if (is_register(b)) {
2491 bt = nasm_regvals[b];
2492 bx = nasm_reg_flags[b];
2493 } else {
2494 bt = -1;
2495 bx = 0;
2496 }
2497
2498 /* if either one are a vector register... */
2499 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2500 opflags_t sok = BITS32 | BITS64;
2501 int32_t o = input->offset;
2502 int mod, scale, index, base;
2503
2504 /*
2505 * For a vector SIB, one has to be a vector and the other,
2506 * if present, a GPR. The vector must be the index operand.
2507 */
2508 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2509 if (s == 0)
2510 s = 1;
2511 else if (s != 1)
2512 goto err;
2513
2514 t = bt, bt = it, it = t;
2515 x = bx, bx = ix, ix = x;
2516 }
2517
2518 if (bt != -1) {
2519 if (REG_GPR & ~bx)
2520 goto err;
2521 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2522 sok &= bx;
2523 else
2524 goto err;
2525 }
2526
2527 /*
2528 * While we're here, ensure the user didn't specify
2529 * WORD or QWORD
2530 */
2531 if (input->disp_size == 16 || input->disp_size == 64)
2532 goto err;
2533
2534 if (addrbits == 16 ||
2535 (addrbits == 32 && !(sok & BITS32)) ||
2536 (addrbits == 64 && !(sok & BITS64)))
2537 goto err;
2538
2539 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2540 : ((ix & YMMREG & ~REG_EA)
2541 ? EA_YMMVSIB : EA_XMMVSIB));
2542
2543 output->rex |= rexflags(it, ix, REX_X);
2544 output->rex |= rexflags(bt, bx, REX_B);
2545 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2546
2547 index = it & 7; /* it is known to be != -1 */
2548
2549 switch (s) {
2550 case 1:
2551 scale = 0;
2552 break;
2553 case 2:
2554 scale = 1;
2555 break;
2556 case 4:
2557 scale = 2;
2558 break;
2559 case 8:
2560 scale = 3;
2561 break;
2562 default: /* then what the smeg is it? */
2563 goto err; /* panic */
2564 }
2565
2566 if (bt == -1) {
2567 base = 5;
2568 mod = 0;
2569 } else {
2570 base = (bt & 7);
2571 if (base != REG_NUM_EBP && o == 0 &&
2572 seg == NO_SEG && !forw_ref &&
2573 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2574 mod = 0;
2575 else if (IS_MOD_01())
2576 mod = 1;
2577 else
2578 mod = 2;
2579 }
2580
2581 output->sib_present = true;
2582 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2583 output->modrm = GEN_MODRM(mod, rfield, 4);
2584 output->sib = GEN_SIB(scale, index, base);
2585 } else if ((ix|bx) & (BITS32|BITS64)) {
2586 /*
2587 * it must be a 32/64-bit memory reference. Firstly we have
2588 * to check that all registers involved are type E/Rxx.
2589 */
2590 opflags_t sok = BITS32 | BITS64;
2591 int32_t o = input->offset;
2592
2593 if (it != -1) {
2594 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2595 sok &= ix;
2596 else
2597 goto err;
2598 }
2599
2600 if (bt != -1) {
2601 if (REG_GPR & ~bx)
2602 goto err; /* Invalid register */
2603 if (~sok & bx & SIZE_MASK)
2604 goto err; /* Invalid size */
2605 sok &= bx;
2606 }
2607
2608 /*
2609 * While we're here, ensure the user didn't specify
2610 * WORD or QWORD
2611 */
2612 if (input->disp_size == 16 || input->disp_size == 64)
2613 goto err;
2614
2615 if (addrbits == 16 ||
2616 (addrbits == 32 && !(sok & BITS32)) ||
2617 (addrbits == 64 && !(sok & BITS64)))
2618 goto err;
2619
2620 /* now reorganize base/index */
2621 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2622 ((hb == b && ht == EAH_NOTBASE) ||
2623 (hb == i && ht == EAH_MAKEBASE))) {
2624 /* swap if hints say so */
2625 t = bt, bt = it, it = t;
2626 x = bx, bx = ix, ix = x;
2627 }
2628
2629 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
2630 /* make single reg base, unless hint */
2631 bt = it, bx = ix, it = -1, ix = 0;
2632 }
2633 if (eaflags & EAF_MIB) {
2634 /* only for mib operands */
2635 if (it == -1 && (hb == b && ht == EAH_NOTBASE)) {
2636 /*
2637 * make a single reg index [reg*1].
2638 * gas uses this form for an explicit index register.
2639 */
2640 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2641 }
2642 if ((ht == EAH_SUMMED) && bt == -1) {
2643 /* separate once summed index into [base, index] */
2644 bt = it, bx = ix, s--;
2645 }
2646 } else {
2647 if (((s == 2 && it != REG_NUM_ESP &&
2648 (!(eaflags & EAF_TIMESTWO) || (ht == EAH_SUMMED))) ||
2649 s == 3 || s == 5 || s == 9) && bt == -1) {
2650 /* convert 3*EAX to EAX+2*EAX */
2651 bt = it, bx = ix, s--;
2652 }
2653 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2654 (eaflags & EAF_TIMESTWO) &&
2655 (hb == b && ht == EAH_NOTBASE)) {
2656 /*
2657 * convert [NOSPLIT EAX*1]
2658 * to sib format with 0x0 displacement - [EAX*1+0].
2659 */
2660 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2661 }
2662 }
2663 if (s == 1 && it == REG_NUM_ESP) {
2664 /* swap ESP into base if scale is 1 */
2665 t = it, it = bt, bt = t;
2666 x = ix, ix = bx, bx = x;
2667 }
2668 if (it == REG_NUM_ESP ||
2669 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2670 goto err; /* wrong, for various reasons */
2671
2672 output->rex |= rexflags(it, ix, REX_X);
2673 output->rex |= rexflags(bt, bx, REX_B);
2674
2675 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2676 /* no SIB needed */
2677 int mod, rm;
2678
2679 if (bt == -1) {
2680 rm = 5;
2681 mod = 0;
2682 } else {
2683 rm = (bt & 7);
2684 if (rm != REG_NUM_EBP && o == 0 &&
2685 seg == NO_SEG && !forw_ref &&
2686 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2687 mod = 0;
2688 else if (IS_MOD_01())
2689 mod = 1;
2690 else
2691 mod = 2;
2692 }
2693
2694 output->sib_present = false;
2695 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2696 output->modrm = GEN_MODRM(mod, rfield, rm);
2697 } else {
2698 /* we need a SIB */
2699 int mod, scale, index, base;
2700
2701 if (it == -1)
2702 index = 4, s = 1;
2703 else
2704 index = (it & 7);
2705
2706 switch (s) {
2707 case 1:
2708 scale = 0;
2709 break;
2710 case 2:
2711 scale = 1;
2712 break;
2713 case 4:
2714 scale = 2;
2715 break;
2716 case 8:
2717 scale = 3;
2718 break;
2719 default: /* then what the smeg is it? */
2720 goto err; /* panic */
2721 }
2722
2723 if (bt == -1) {
2724 base = 5;
2725 mod = 0;
2726 } else {
2727 base = (bt & 7);
2728 if (base != REG_NUM_EBP && o == 0 &&
2729 seg == NO_SEG && !forw_ref &&
2730 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2731 mod = 0;
2732 else if (IS_MOD_01())
2733 mod = 1;
2734 else
2735 mod = 2;
2736 }
2737
2738 output->sib_present = true;
2739 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2740 output->modrm = GEN_MODRM(mod, rfield, 4);
2741 output->sib = GEN_SIB(scale, index, base);
2742 }
2743 } else { /* it's 16-bit */
2744 int mod, rm;
2745 int16_t o = input->offset;
2746
2747 /* check for 64-bit long mode */
2748 if (addrbits == 64)
2749 goto err;
2750
2751 /* check all registers are BX, BP, SI or DI */
2752 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2753 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2754 goto err;
2755
2756 /* ensure the user didn't specify DWORD/QWORD */
2757 if (input->disp_size == 32 || input->disp_size == 64)
2758 goto err;
2759
2760 if (s != 1 && i != -1)
2761 goto err; /* no can do, in 16-bit EA */
2762 if (b == -1 && i != -1) {
2763 int tmp = b;
2764 b = i;
2765 i = tmp;
2766 } /* swap */
2767 if ((b == R_SI || b == R_DI) && i != -1) {
2768 int tmp = b;
2769 b = i;
2770 i = tmp;
2771 }
2772 /* have BX/BP as base, SI/DI index */
2773 if (b == i)
2774 goto err; /* shouldn't ever happen, in theory */
2775 if (i != -1 && b != -1 &&
2776 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2777 goto err; /* invalid combinations */
2778 if (b == -1) /* pure offset: handled above */
2779 goto err; /* so if it gets to here, panic! */
2780
2781 rm = -1;
2782 if (i != -1)
2783 switch (i * 256 + b) {
2784 case R_SI * 256 + R_BX:
2785 rm = 0;
2786 break;
2787 case R_DI * 256 + R_BX:
2788 rm = 1;
2789 break;
2790 case R_SI * 256 + R_BP:
2791 rm = 2;
2792 break;
2793 case R_DI * 256 + R_BP:
2794 rm = 3;
2795 break;
2796 } else
2797 switch (b) {
2798 case R_SI:
2799 rm = 4;
2800 break;
2801 case R_DI:
2802 rm = 5;
2803 break;
2804 case R_BP:
2805 rm = 6;
2806 break;
2807 case R_BX:
2808 rm = 7;
2809 break;
2810 }
2811 if (rm == -1) /* can't happen, in theory */
2812 goto err; /* so panic if it does */
2813
2814 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2815 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2816 mod = 0;
2817 else if (IS_MOD_01())
2818 mod = 1;
2819 else
2820 mod = 2;
2821
2822 output->sib_present = false; /* no SIB - it's 16-bit */
2823 output->bytes = mod; /* bytes of offset needed */
2824 output->modrm = GEN_MODRM(mod, rfield, rm);
2825 }
2826 }
2827 }
2828
2829 output->size = 1 + output->sib_present + output->bytes;
2830 return output->type;
2831
2832 err:
2833 return output->type = EA_INVALID;
2834 }
2835
2836 static void add_asp(insn *ins, int addrbits)
2837 {
2838 int j, valid;
2839 int defdisp;
2840
2841 valid = (addrbits == 64) ? 64|32 : 32|16;
2842
2843 switch (ins->prefixes[PPS_ASIZE]) {
2844 case P_A16:
2845 valid &= 16;
2846 break;
2847 case P_A32:
2848 valid &= 32;
2849 break;
2850 case P_A64:
2851 valid &= 64;
2852 break;
2853 case P_ASP:
2854 valid &= (addrbits == 32) ? 16 : 32;
2855 break;
2856 default:
2857 break;
2858 }
2859
2860 for (j = 0; j < ins->operands; j++) {
2861 if (is_class(MEMORY, ins->oprs[j].type)) {
2862 opflags_t i, b;
2863
2864 /* Verify as Register */
2865 if (!is_register(ins->oprs[j].indexreg))
2866 i = 0;
2867 else
2868 i = nasm_reg_flags[ins->oprs[j].indexreg];
2869
2870 /* Verify as Register */
2871 if (!is_register(ins->oprs[j].basereg))
2872 b = 0;
2873 else
2874 b = nasm_reg_flags[ins->oprs[j].basereg];
2875
2876 if (ins->oprs[j].scale == 0)
2877 i = 0;
2878
2879 if (!i && !b) {
2880 int ds = ins->oprs[j].disp_size;
2881 if ((addrbits != 64 && ds > 8) ||
2882 (addrbits == 64 && ds == 16))
2883 valid &= ds;
2884 } else {
2885 if (!(REG16 & ~b))
2886 valid &= 16;
2887 if (!(REG32 & ~b))
2888 valid &= 32;
2889 if (!(REG64 & ~b))
2890 valid &= 64;
2891
2892 if (!(REG16 & ~i))
2893 valid &= 16;
2894 if (!(REG32 & ~i))
2895 valid &= 32;
2896 if (!(REG64 & ~i))
2897 valid &= 64;
2898 }
2899 }
2900 }
2901
2902 if (valid & addrbits) {
2903 ins->addr_size = addrbits;
2904 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2905 /* Add an address size prefix */
2906 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2907 ins->addr_size = (addrbits == 32) ? 16 : 32;
2908 } else {
2909 /* Impossible... */
2910 nasm_error(ERR_NONFATAL, "impossible combination of address sizes");
2911 ins->addr_size = addrbits; /* Error recovery */
2912 }
2913
2914 defdisp = ins->addr_size == 16 ? 16 : 32;
2915
2916 for (j = 0; j < ins->operands; j++) {
2917 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2918 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2919 /*
2920 * mem_offs sizes must match the address size; if not,
2921 * strip the MEM_OFFS bit and match only EA instructions
2922 */
2923 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2924 }
2925 }
2926 }
The Netwide Assembler