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Makefile.in: fix typo in pathname
[nasm.git] / asm / assemble.c
blobfc72065ea55f447c1d4138ed35b9e25c4d471351
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2017 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * Bytecode specification
38 * ----------------------
39 *
40 *
41 * Codes Mnemonic Explanation
42 *
43 * \0 terminates the code. (Unless it's a literal of course.)
44 * \1..\4 that many literal bytes follow in the code stream
45 * \5 add 4 to the primary operand number (b, low octdigit)
46 * \6 add 4 to the secondary operand number (a, middle octdigit)
47 * \7 add 4 to both the primary and the secondary operand number
48 * \10..\13 a literal byte follows in the code stream, to be added
49 * to the register value of operand 0..3
50 * \14..\17 the position of index register operand in MIB (BND insns)
51 * \20..\23 ib a byte immediate operand, from operand 0..3
52 * \24..\27 ib,u a zero-extended byte immediate operand, from operand 0..3
53 * \30..\33 iw a word immediate operand, from operand 0..3
54 * \34..\37 iwd select between \3[0-3] and \4[0-3] depending on 16/32 bit
55 * assembly mode or the operand-size override on the operand
56 * \40..\43 id a long immediate operand, from operand 0..3
57 * \44..\47 iwdq select between \3[0-3], \4[0-3] and \5[4-7]
58 * depending on the address size of the instruction.
59 * \50..\53 rel8 a byte relative operand, from operand 0..3
60 * \54..\57 iq a qword immediate operand, from operand 0..3
61 * \60..\63 rel16 a word relative operand, from operand 0..3
62 * \64..\67 rel select between \6[0-3] and \7[0-3] depending on 16/32 bit
63 * assembly mode or the operand-size override on the operand
64 * \70..\73 rel32 a long relative operand, from operand 0..3
65 * \74..\77 seg a word constant, from the _segment_ part of operand 0..3
66 * \1ab a ModRM, calculated on EA in operand a, with the spare
67 * field the register value of operand b.
68 * \172\ab the register number from operand a in bits 7..4, with
69 * the 4-bit immediate from operand b in bits 3..0.
70 * \173\xab the register number from operand a in bits 7..4, with
71 * the value b in bits 3..0.
72 * \174..\177 the register number from operand 0..3 in bits 7..4, and
73 * an arbitrary value in bits 3..0 (assembled as zero.)
74 * \2ab a ModRM, calculated on EA in operand a, with the spare
75 * field equal to digit b.
76 *
77 * \240..\243 this instruction uses EVEX rather than REX or VEX/XOP, with the
78 * V field taken from operand 0..3.
79 * \250 this instruction uses EVEX rather than REX or VEX/XOP, with the
80 * V field set to 1111b.
81 *
82 * EVEX prefixes are followed by the sequence:
83 * \cm\wlp\tup where cm is:
84 * cc 00m mmm
85 * c = 2 for EVEX and mmmm is the M field (EVEX.P0[3:0])
86 * and wlp is:
87 * 00 wwl lpp
88 * [l0] ll = 0 (.128, .lz)
89 * [l1] ll = 1 (.256)
90 * [l2] ll = 2 (.512)
91 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
92 *
93 * [w0] ww = 0 for W = 0
94 * [w1] ww = 1 for W = 1
95 * [wig] ww = 2 for W don't care (always assembled as 0)
96 * [ww] ww = 3 for W used as REX.W
97 *
98 * [p0] pp = 0 for no prefix
99 * [60] pp = 1 for legacy prefix 60
100 * [f3] pp = 2
101 * [f2] pp = 3
102 *
103 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
104 * (compressed displacement encoding)
105 *
106 * \254..\257 id,s a signed 32-bit operand to be extended to 64 bits.
107 * \260..\263 this instruction uses VEX/XOP rather than REX, with the
108 * V field taken from operand 0..3.
109 * \270 this instruction uses VEX/XOP rather than REX, with the
110 * V field set to 1111b.
111 *
112 * VEX/XOP prefixes are followed by the sequence:
113 * \tmm\wlp where mm is the M field; and wlp is:
114 * 00 wwl lpp
115 * [l0] ll = 0 for L = 0 (.128, .lz)
116 * [l1] ll = 1 for L = 1 (.256)
117 * [lig] ll = 2 for L don't care (always assembled as 0)
118 *
119 * [w0] ww = 0 for W = 0
120 * [w1 ] ww = 1 for W = 1
121 * [wig] ww = 2 for W don't care (always assembled as 0)
122 * [ww] ww = 3 for W used as REX.W
123 *
124 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
125 *
126 * \271 hlexr instruction takes XRELEASE (F3) with or without lock
127 * \272 hlenl instruction takes XACQUIRE/XRELEASE with or without lock
128 * \273 hle instruction takes XACQUIRE/XRELEASE with lock only
129 * \274..\277 ib,s a byte immediate operand, from operand 0..3, sign-extended
130 * to the operand size (if o16/o32/o64 present) or the bit size
131 * \310 a16 indicates fixed 16-bit address size, i.e. optional 0x67.
132 * \311 a32 indicates fixed 32-bit address size, i.e. optional 0x67.
133 * \312 adf (disassembler only) invalid with non-default address size.
134 * \313 a64 indicates fixed 64-bit address size, 0x67 invalid.
135 * \314 norexb (disassembler only) invalid with REX.B
136 * \315 norexx (disassembler only) invalid with REX.X
137 * \316 norexr (disassembler only) invalid with REX.R
138 * \317 norexw (disassembler only) invalid with REX.W
139 * \320 o16 indicates fixed 16-bit operand size, i.e. optional 0x66.
140 * \321 o32 indicates fixed 32-bit operand size, i.e. optional 0x66.
141 * \322 odf indicates that this instruction is only valid when the
142 * operand size is the default (instruction to disassembler,
143 * generates no code in the assembler)
144 * \323 o64nw indicates fixed 64-bit operand size, REX on extensions only.
145 * \324 o64 indicates 64-bit operand size requiring REX prefix.
146 * \325 nohi instruction which always uses spl/bpl/sil/dil
147 * \326 nof3 instruction not valid with 0xF3 REP prefix. Hint for
148 disassembler only; for SSE instructions.
149 * \330 a literal byte follows in the code stream, to be added
150 * to the condition code value of the instruction.
151 * \331 norep instruction not valid with REP prefix. Hint for
152 * disassembler only; for SSE instructions.
153 * \332 f2i REP prefix (0xF2 byte) used as opcode extension.
154 * \333 f3i REP prefix (0xF3 byte) used as opcode extension.
155 * \334 rex.l LOCK prefix used as REX.R (used in non-64-bit mode)
156 * \335 repe disassemble a rep (0xF3 byte) prefix as repe not rep.
157 * \336 mustrep force a REP(E) prefix (0xF3) even if not specified.
158 * \337 mustrepne force a REPNE prefix (0xF2) even if not specified.
159 * \336-\337 are still listed as prefixes in the disassembler.
160 * \340 resb reserve <operand 0> bytes of uninitialized storage.
161 * Operand 0 had better be a segmentless constant.
162 * \341 wait this instruction needs a WAIT "prefix"
163 * \360 np no SSE prefix (== \364\331)
164 * \361 66 SSE prefix (== \366\331)
165 * \364 !osp operand-size prefix (0x66) not permitted
166 * \365 !asp address-size prefix (0x67) not permitted
167 * \366 operand-size prefix (0x66) used as opcode extension
168 * \367 address-size prefix (0x67) used as opcode extension
169 * \370,\371 jcc8 match only if operand 0 meets byte jump criteria.
170 * jmp8 370 is used for Jcc, 371 is used for JMP.
171 * \373 jlen assemble 0x03 if bits==16, 0x05 if bits==32;
172 * used for conditional jump over longer jump
173 * \374 vsibx|vm32x|vm64x this instruction takes an XMM VSIB memory EA
174 * \375 vsiby|vm32y|vm64y this instruction takes an YMM VSIB memory EA
175 * \376 vsibz|vm32z|vm64z this instruction takes an ZMM VSIB memory EA
176 */
177
178 #include "compiler.h"
179
180 #include <stdio.h>
181 #include <string.h>
182 #include <stdlib.h>
183
184 #include "nasm.h"
185 #include "nasmlib.h"
186 #include "error.h"
187 #include "assemble.h"
188 #include "insns.h"
189 #include "tables.h"
190 #include "disp8.h"
191 #include "listing.h"
192
193 enum match_result {
194 /*
195 * Matching errors. These should be sorted so that more specific
196 * errors come later in the sequence.
197 */
198 MERR_INVALOP,
199 MERR_OPSIZEMISSING,
200 MERR_OPSIZEMISMATCH,
201 MERR_BRNOTHERE,
202 MERR_BRNUMMISMATCH,
203 MERR_MASKNOTHERE,
204 MERR_DECONOTHERE,
205 MERR_BADCPU,
206 MERR_BADMODE,
207 MERR_BADHLE,
208 MERR_ENCMISMATCH,
209 MERR_BADBND,
210 MERR_BADREPNE,
211 /*
212 * Matching success; the conditional ones first
213 */
214 MOK_JUMP, /* Matching OK but needs jmp_match() */
215 MOK_GOOD /* Matching unconditionally OK */
216 };
217
218 typedef struct {
219 enum ea_type type; /* what kind of EA is this? */
220 int sib_present; /* is a SIB byte necessary? */
221 int bytes; /* # of bytes of offset needed */
222 int size; /* lazy - this is sib+bytes+1 */
223 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
224 int8_t disp8; /* compressed displacement for EVEX */
225 } ea;
226
227 #define GEN_SIB(scale, index, base) \
228 (((scale) << 6) | ((index) << 3) | ((base)))
229
230 #define GEN_MODRM(mod, reg, rm) \
231 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
232
233 static int64_t calcsize(int32_t, int64_t, int, insn *,
234 const struct itemplate *);
235 static int emit_prefix(struct out_data *data, const int bits, insn *ins);
236 static void gencode(struct out_data *data, insn *ins);
237 static enum match_result find_match(const struct itemplate **tempp,
238 insn *instruction,
239 int32_t segment, int64_t offset, int bits);
240 static enum match_result matches(const struct itemplate *, insn *, int bits);
241 static opflags_t regflag(const operand *);
242 static int32_t regval(const operand *);
243 static int rexflags(int, opflags_t, int);
244 static int op_rexflags(const operand *, int);
245 static int op_evexflags(const operand *, int, uint8_t);
246 static void add_asp(insn *, int);
247
248 static enum ea_type process_ea(operand *, ea *, int, int,
249 opflags_t, insn *, const char **);
250
251 static inline bool absolute_op(const struct operand *o)
252 {
253 return o->segment == NO_SEG && o->wrt == NO_SEG &&
254 !(o->opflags & OPFLAG_RELATIVE);
255 }
256
257 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
258 {
259 return ins->prefixes[pos] == prefix;
260 }
261
262 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
263 {
264 if (ins->prefixes[pos])
265 nasm_error(ERR_NONFATAL, "invalid %s prefix",
266 prefix_name(ins->prefixes[pos]));
267 }
268
269 static const char *size_name(int size)
270 {
271 switch (size) {
272 case 1:
273 return "byte";
274 case 2:
275 return "word";
276 case 4:
277 return "dword";
278 case 8:
279 return "qword";
280 case 10:
281 return "tword";
282 case 16:
283 return "oword";
284 case 32:
285 return "yword";
286 case 64:
287 return "zword";
288 default:
289 return "???";
290 }
291 }
292
293 static void warn_overflow(int size)
294 {
295 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
296 "%s data exceeds bounds", size_name(size));
297 }
298
299 static void warn_overflow_const(int64_t data, int size)
300 {
301 if (overflow_general(data, size))
302 warn_overflow(size);
303 }
304
305 static void warn_overflow_out(int64_t data, int size, enum out_sign sign)
306 {
307 bool err;
308
309 switch (sign) {
310 case OUT_WRAP:
311 err = overflow_general(data, size);
312 break;
313 case OUT_SIGNED:
314 err = overflow_signed(data, size);
315 break;
316 case OUT_UNSIGNED:
317 err = overflow_unsigned(data, size);
318 break;
319 default:
320 panic();
321 break;
322 }
323
324 if (err)
325 warn_overflow(size);
326 }
327
328 /*
329 * This routine wrappers the real output format's output routine,
330 * in order to pass a copy of the data off to the listing file
331 * generator at the same time, flatten unnecessary relocations,
332 * and verify backend compatibility.
333 */
334 static void out(struct out_data *data)
335 {
336 static int32_t lineno = 0; /* static!!! */
337 static const char *lnfname = NULL;
338 union {
339 uint8_t b[8];
340 uint64_t q;
341 } xdata;
342 size_t asize, amax;
343 uint64_t zeropad = 0;
344 int64_t addrval;
345 int32_t fixseg; /* Segment for which to produce fixed data */
346
347 if (!data->size)
348 return; /* Nothing to do */
349
350 /*
351 * Convert addresses to RAWDATA if possible
352 * XXX: not all backends want this for global symbols!!!!
353 */
354 switch (data->type) {
355 case OUT_ADDRESS:
356 addrval = data->toffset;
357 fixseg = NO_SEG; /* Absolute address is fixed data */
358 goto address;
359
360 case OUT_RELADDR:
361 addrval = data->toffset - data->relbase;
362 fixseg = data->segment; /* Our own segment is fixed data */
363 goto address;
364
365 address:
366 nasm_assert(data->size <= 8);
367 asize = data->size;
368 amax = ofmt->maxbits >> 3; /* Maximum address size in bytes */
369 if (data->tsegment == fixseg && data->twrt == NO_SEG) {
370 warn_overflow_out(addrval, asize, data->sign);
371 xdata.q = cpu_to_le64(addrval);
372 data->data = xdata.b;
373 data->type = OUT_RAWDATA;
374 asize = amax = 0; /* No longer an address */
375 }
376 break;
377
378 case OUT_SEGMENT:
379 nasm_assert(data->size <= 8);
380 asize = data->size;
381 amax = 2;
382 break;
383
384 default:
385 asize = amax = 0; /* Not an address */
386 break;
387 }
388
389 /*
390 * this call to src_get determines when we call the
391 * debug-format-specific "linenum" function
392 * it updates lineno and lnfname to the current values
393 * returning 0 if "same as last time", -2 if lnfname
394 * changed, and the amount by which lineno changed,
395 * if it did. thus, these variables must be static
396 */
397
398 if (src_get(&lineno, &lnfname))
399 dfmt->linenum(lnfname, lineno, data->segment);
400
401 if (asize > amax) {
402 if (data->type == OUT_RELADDR || data->sign == OUT_SIGNED) {
403 nasm_error(ERR_NONFATAL,
404 "%u-bit signed relocation unsupported by output format %s",
405 (unsigned int)(asize << 3), ofmt->shortname);
406 } else {
407 nasm_error(ERR_WARNING | ERR_WARN_ZEXTRELOC,
408 "%u-bit %s relocation zero-extended from %u bits",
409 (unsigned int)(asize << 3),
410 data->type == OUT_SEGMENT ? "segment" : "unsigned",
411 (unsigned int)(amax << 3));
412 }
413 zeropad = data->size - amax;
414 data->size = amax;
415 }
416 lfmt->output(data);
417 ofmt->output(data);
418 data->offset += data->size;
419 data->insoffs += data->size;
420
421 if (zeropad) {
422 data->type = OUT_ZERODATA;
423 data->size = zeropad;
424 lfmt->output(data);
425 ofmt->output(data);
426 data->offset += zeropad;
427 data->insoffs += zeropad;
428 data->size += zeropad; /* Restore original size value */
429 }
430 }
431
432 static inline void out_rawdata(struct out_data *data, const void *rawdata,
433 size_t size)
434 {
435 data->type = OUT_RAWDATA;
436 data->data = rawdata;
437 data->size = size;
438 out(data);
439 }
440
441 static void out_rawbyte(struct out_data *data, uint8_t byte)
442 {
443 data->type = OUT_RAWDATA;
444 data->data = &byte;
445 data->size = 1;
446 out(data);
447 }
448
449 static inline void out_reserve(struct out_data *data, uint64_t size)
450 {
451 data->type = OUT_RESERVE;
452 data->size = size;
453 out(data);
454 }
455
456 static void out_segment(struct out_data *data, const struct operand *opx)
457 {
458 if (opx->opflags & OPFLAG_RELATIVE)
459 nasm_error(ERR_NONFATAL, "segment references cannot be relative");
460
461 data->type = OUT_SEGMENT;
462 data->sign = OUT_UNSIGNED;
463 data->size = 2;
464 data->toffset = opx->offset;
465 data->tsegment = ofmt->segbase(opx->segment | 1);
466 data->twrt = opx->wrt;
467 out(data);
468 }
469
470 static void out_imm(struct out_data *data, const struct operand *opx,
471 int size, enum out_sign sign)
472 {
473 if (opx->segment != NO_SEG && (opx->segment & 1)) {
474 /*
475 * This is actually a segment reference, but eval() has
476 * already called ofmt->segbase() for us. Sigh.
477 */
478 if (size < 2)
479 nasm_error(ERR_NONFATAL, "segment reference must be 16 bits");
480
481 data->type = OUT_SEGMENT;
482 } else {
483 data->type = (opx->opflags & OPFLAG_RELATIVE)
484 ? OUT_RELADDR : OUT_ADDRESS;
485 }
486 data->sign = sign;
487 data->toffset = opx->offset;
488 data->tsegment = opx->segment;
489 data->twrt = opx->wrt;
490 /*
491 * XXX: improve this if at some point in the future we can
492 * distinguish the subtrahend in expressions like [foo - bar]
493 * where bar is a symbol in the current segment. However, at the
494 * current point, if OPFLAG_RELATIVE is set that subtraction has
495 * already occurred.
496 */
497 data->relbase = 0;
498 data->size = size;
499 out(data);
500 }
501
502 static void out_reladdr(struct out_data *data, const struct operand *opx,
503 int size)
504 {
505 if (opx->opflags & OPFLAG_RELATIVE)
506 nasm_error(ERR_NONFATAL, "invalid use of self-relative expression");
507
508 data->type = OUT_RELADDR;
509 data->sign = OUT_SIGNED;
510 data->size = size;
511 data->toffset = opx->offset;
512 data->tsegment = opx->segment;
513 data->twrt = opx->wrt;
514 data->relbase = data->offset + (data->inslen - data->insoffs);
515 out(data);
516 }
517
518 static bool jmp_match(int32_t segment, int64_t offset, int bits,
519 insn * ins, const struct itemplate *temp)
520 {
521 int64_t isize;
522 const uint8_t *code = temp->code;
523 uint8_t c = code[0];
524 bool is_byte;
525
526 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
527 return false;
528 if (!optimizing)
529 return false;
530 if (optimizing < 0 && c == 0371)
531 return false;
532
533 isize = calcsize(segment, offset, bits, ins, temp);
534
535 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
536 /* Be optimistic in pass 1 */
537 return true;
538
539 if (ins->oprs[0].segment != segment)
540 return false;
541
542 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
543 is_byte = (isize >= -128 && isize <= 127); /* is it byte size? */
544
545 if (is_byte && c == 0371 && ins->prefixes[PPS_REP] == P_BND) {
546 /* jmp short (opcode eb) cannot be used with bnd prefix. */
547 ins->prefixes[PPS_REP] = P_none;
548 nasm_error(ERR_WARNING | ERR_WARN_BND | ERR_PASS2 ,
549 "jmp short does not init bnd regs - bnd prefix dropped.");
550 }
551
552 return is_byte;
553 }
554
555 /* This is totally just a wild guess what is reasonable... */
556 #define INCBIN_MAX_BUF (ZERO_BUF_SIZE * 16)
557
558 int64_t assemble(int32_t segment, int64_t start, int bits, insn *instruction)
559 {
560 struct out_data data;
561 const struct itemplate *temp;
562 enum match_result m;
563 int64_t wsize; /* size for DB etc. */
564
565 nasm_zero(data);
566 data.offset = start;
567 data.segment = segment;
568 data.itemp = NULL;
569 data.bits = bits;
570
571 wsize = db_bytes(instruction->opcode);
572 if (wsize == -1)
573 return 0;
574
575 if (wsize) {
576 extop *e;
577
578 list_for_each(e, instruction->eops) {
579 if (e->type == EOT_DB_NUMBER) {
580 if (wsize > 8) {
581 nasm_error(ERR_NONFATAL,
582 "integer supplied to a DT, DO, DY or DZ"
583 " instruction");
584 } else {
585 data.insoffs = 0;
586 data.inslen = data.size = wsize;
587 data.toffset = e->offset;
588 data.twrt = e->wrt;
589 data.relbase = 0;
590 if (e->segment != NO_SEG && (e->segment & 1)) {
591 data.tsegment = e->segment;
592 data.type = OUT_SEGMENT;
593 data.sign = OUT_UNSIGNED;
594 } else {
595 data.tsegment = e->segment;
596 data.type = e->relative ? OUT_RELADDR : OUT_ADDRESS;
597 data.sign = OUT_WRAP;
598 }
599 out(&data);
600 }
601 } else if (e->type == EOT_DB_STRING ||
602 e->type == EOT_DB_STRING_FREE) {
603 int align = e->stringlen % wsize;
604 if (align)
605 align = wsize - align;
606
607 data.insoffs = 0;
608 data.inslen = e->stringlen + align;
609
610 out_rawdata(&data, e->stringval, e->stringlen);
611 out_rawdata(&data, zero_buffer, align);
612 }
613 }
614 } else if (instruction->opcode == I_INCBIN) {
615 const char *fname = instruction->eops->stringval;
616 FILE *fp;
617 size_t t = instruction->times; /* INCBIN handles TIMES by itself */
618 off_t base = 0;
619 off_t len;
620 const void *map = NULL;
621 char *buf = NULL;
622 size_t blk = 0; /* Buffered I/O block size */
623 size_t m = 0; /* Bytes last read */
624
625 if (!t)
626 goto done;
627
628 fp = nasm_open_read(fname, NF_BINARY|NF_FORMAP);
629 if (!fp) {
630 nasm_error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
631 fname);
632 goto done;
633 }
634
635 len = nasm_file_size(fp);
636
637 if (len == (off_t)-1) {
638 nasm_error(ERR_NONFATAL, "`incbin': unable to get length of file `%s'",
639 fname);
640 goto close_done;
641 }
642
643 if (instruction->eops->next) {
644 base = instruction->eops->next->offset;
645 if (base >= len) {
646 len = 0;
647 } else {
648 len -= base;
649 if (instruction->eops->next->next &&
650 len > (off_t)instruction->eops->next->next->offset)
651 len = (off_t)instruction->eops->next->next->offset;
652 }
653 }
654
655 lfmt->set_offset(data.offset);
656 lfmt->uplevel(LIST_INCBIN);
657
658 if (!len)
659 goto end_incbin;
660
661 /* Try to map file data */
662 map = nasm_map_file(fp, base, len);
663 if (!map) {
664 blk = len < (off_t)INCBIN_MAX_BUF ? (size_t)len : INCBIN_MAX_BUF;
665 buf = nasm_malloc(blk);
666 }
667
668 while (t--) {
669 /*
670 * Consider these irrelevant for INCBIN, since it is fully
671 * possible that these might be (way) bigger than an int
672 * can hold; there is, however, no reason to widen these
673 * types just for INCBIN. data.inslen == 0 signals to the
674 * backend that these fields are meaningless, if at all
675 * needed.
676 */
677 data.insoffs = 0;
678 data.inslen = 0;
679
680 if (map) {
681 out_rawdata(&data, map, len);
682 } else if ((off_t)m == len) {
683 out_rawdata(&data, buf, len);
684 } else {
685 off_t l = len;
686
687 if (fseeko(fp, base, SEEK_SET) < 0 || ferror(fp)) {
688 nasm_error(ERR_NONFATAL,
689 "`incbin': unable to seek on file `%s'",
690 fname);
691 goto end_incbin;
692 }
693 while (l > 0) {
694 m = fread(buf, 1, l < (off_t)blk ? (size_t)l : blk, fp);
695 if (!m || feof(fp)) {
696 /*
697 * This shouldn't happen unless the file
698 * actually changes while we are reading
699 * it.
700 */
701 nasm_error(ERR_NONFATAL,
702 "`incbin': unexpected EOF while"
703 " reading file `%s'", fname);
704 goto end_incbin;
705 }
706 out_rawdata(&data, buf, m);
707 l -= m;
708 }
709 }
710 }
711 end_incbin:
712 lfmt->downlevel(LIST_INCBIN);
713 if (instruction->times > 1) {
714 lfmt->uplevel(LIST_TIMES);
715 lfmt->downlevel(LIST_TIMES);
716 }
717 if (ferror(fp)) {
718 nasm_error(ERR_NONFATAL,
719 "`incbin': error while"
720 " reading file `%s'", fname);
721 }
722 close_done:
723 if (buf)
724 nasm_free(buf);
725 if (map)
726 nasm_unmap_file(map, len);
727 fclose(fp);
728 done:
729 instruction->times = 1; /* Tell the upper layer not to iterate */
730 ;
731 } else {
732 /* "Real" instruction */
733
734 /* Check to see if we need an address-size prefix */
735 add_asp(instruction, bits);
736
737 m = find_match(&temp, instruction, data.segment, data.offset, bits);
738
739 if (m == MOK_GOOD) {
740 /* Matches! */
741 int64_t insn_size = calcsize(data.segment, data.offset,
742 bits, instruction, temp);
743 nasm_assert(insn_size >= 0);
744
745 data.itemp = temp;
746 data.bits = bits;
747 data.insoffs = 0;
748 data.inslen = insn_size;
749
750 gencode(&data, instruction);
751 nasm_assert(data.insoffs == insn_size);
752 } else {
753 /* No match */
754 switch (m) {
755 case MERR_OPSIZEMISSING:
756 nasm_error(ERR_NONFATAL, "operation size not specified");
757 break;
758 case MERR_OPSIZEMISMATCH:
759 nasm_error(ERR_NONFATAL, "mismatch in operand sizes");
760 break;
761 case MERR_BRNOTHERE:
762 nasm_error(ERR_NONFATAL,
763 "broadcast not permitted on this operand");
764 break;
765 case MERR_BRNUMMISMATCH:
766 nasm_error(ERR_NONFATAL,
767 "mismatch in the number of broadcasting elements");
768 break;
769 case MERR_MASKNOTHERE:
770 nasm_error(ERR_NONFATAL,
771 "mask not permitted on this operand");
772 break;
773 case MERR_DECONOTHERE:
774 nasm_error(ERR_NONFATAL, "unsupported mode decorator for instruction");
775 break;
776 case MERR_BADCPU:
777 nasm_error(ERR_NONFATAL, "no instruction for this cpu level");
778 break;
779 case MERR_BADMODE:
780 nasm_error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
781 bits);
782 break;
783 case MERR_ENCMISMATCH:
784 nasm_error(ERR_NONFATAL, "specific encoding scheme not available");
785 break;
786 case MERR_BADBND:
787 nasm_error(ERR_NONFATAL, "bnd prefix is not allowed");
788 break;
789 case MERR_BADREPNE:
790 nasm_error(ERR_NONFATAL, "%s prefix is not allowed",
791 (has_prefix(instruction, PPS_REP, P_REPNE) ?
792 "repne" : "repnz"));
793 break;
794 default:
795 nasm_error(ERR_NONFATAL,
796 "invalid combination of opcode and operands");
797 break;
798 }
799
800 instruction->times = 1; /* Avoid repeated error messages */
801 }
802 }
803 return data.offset - start;
804 }
805
806 int64_t insn_size(int32_t segment, int64_t offset, int bits, insn *instruction)
807 {
808 const struct itemplate *temp;
809 enum match_result m;
810
811 if (instruction->opcode == I_none)
812 return 0;
813
814 if (opcode_is_db(instruction->opcode)) {
815 extop *e;
816 int32_t isize, osize, wsize;
817
818 isize = 0;
819 wsize = db_bytes(instruction->opcode);
820 nasm_assert(wsize > 0);
821
822 list_for_each(e, instruction->eops) {
823 int32_t align;
824
825 osize = 0;
826 if (e->type == EOT_DB_NUMBER) {
827 osize = 1;
828 warn_overflow_const(e->offset, wsize);
829 } else if (e->type == EOT_DB_STRING ||
830 e->type == EOT_DB_STRING_FREE)
831 osize = e->stringlen;
832
833 align = (-osize) % wsize;
834 if (align < 0)
835 align += wsize;
836 isize += osize + align;
837 }
838 return isize;
839 }
840
841 if (instruction->opcode == I_INCBIN) {
842 const char *fname = instruction->eops->stringval;
843 off_t len;
844
845 len = nasm_file_size_by_path(fname);
846 if (len == (off_t)-1) {
847 nasm_error(ERR_NONFATAL, "`incbin': unable to get length of file `%s'",
848 fname);
849 return 0;
850 }
851
852 if (instruction->eops->next) {
853 if (len <= (off_t)instruction->eops->next->offset) {
854 len = 0;
855 } else {
856 len -= instruction->eops->next->offset;
857 if (instruction->eops->next->next &&
858 len > (off_t)instruction->eops->next->next->offset) {
859 len = (off_t)instruction->eops->next->next->offset;
860 }
861 }
862 }
863
864 len *= instruction->times;
865 instruction->times = 1; /* Tell the upper layer to not iterate */
866
867 return len;
868 }
869
870 /* Check to see if we need an address-size prefix */
871 add_asp(instruction, bits);
872
873 m = find_match(&temp, instruction, segment, offset, bits);
874 if (m == MOK_GOOD) {
875 /* we've matched an instruction. */
876 return calcsize(segment, offset, bits, instruction, temp);
877 } else {
878 return -1; /* didn't match any instruction */
879 }
880 }
881
882 static void bad_hle_warn(const insn * ins, uint8_t hleok)
883 {
884 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
885 enum whatwarn { w_none, w_lock, w_inval } ww;
886 static const enum whatwarn warn[2][4] =
887 {
888 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
889 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
890 };
891 unsigned int n;
892
893 n = (unsigned int)rep_pfx - P_XACQUIRE;
894 if (n > 1)
895 return; /* Not XACQUIRE/XRELEASE */
896
897 ww = warn[n][hleok];
898 if (!is_class(MEMORY, ins->oprs[0].type))
899 ww = w_inval; /* HLE requires operand 0 to be memory */
900
901 switch (ww) {
902 case w_none:
903 break;
904
905 case w_lock:
906 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
907 nasm_error(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
908 "%s with this instruction requires lock",
909 prefix_name(rep_pfx));
910 }
911 break;
912
913 case w_inval:
914 nasm_error(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
915 "%s invalid with this instruction",
916 prefix_name(rep_pfx));
917 break;
918 }
919 }
920
921 /* Common construct */
922 #define case3(x) case (x): case (x)+1: case (x)+2
923 #define case4(x) case3(x): case (x)+3
924
925 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
926 insn * ins, const struct itemplate *temp)
927 {
928 const uint8_t *codes = temp->code;
929 int64_t length = 0;
930 uint8_t c;
931 int rex_mask = ~0;
932 int op1, op2;
933 struct operand *opx;
934 uint8_t opex = 0;
935 enum ea_type eat;
936 uint8_t hleok = 0;
937 bool lockcheck = true;
938 enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
939 const char *errmsg;
940
941 ins->rex = 0; /* Ensure REX is reset */
942 eat = EA_SCALAR; /* Expect a scalar EA */
943 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
944
945 if (ins->prefixes[PPS_OSIZE] == P_O64)
946 ins->rex |= REX_W;
947
948 (void)segment; /* Don't warn that this parameter is unused */
949 (void)offset; /* Don't warn that this parameter is unused */
950
951 while (*codes) {
952 c = *codes++;
953 op1 = (c & 3) + ((opex & 1) << 2);
954 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
955 opx = &ins->oprs[op1];
956 opex = 0; /* For the next iteration */
957
958 switch (c) {
959 case4(01):
960 codes += c, length += c;
961 break;
962
963 case3(05):
964 opex = c;
965 break;
966
967 case4(010):
968 ins->rex |=
969 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
970 codes++, length++;
971 break;
972
973 case4(014):
974 /* this is an index reg of MIB operand */
975 mib_index = opx->basereg;
976 break;
977
978 case4(020):
979 case4(024):
980 length++;
981 break;
982
983 case4(030):
984 length += 2;
985 break;
986
987 case4(034):
988 if (opx->type & (BITS16 | BITS32 | BITS64))
989 length += (opx->type & BITS16) ? 2 : 4;
990 else
991 length += (bits == 16) ? 2 : 4;
992 break;
993
994 case4(040):
995 length += 4;
996 break;
997
998 case4(044):
999 length += ins->addr_size >> 3;
1000 break;
1001
1002 case4(050):
1003 length++;
1004 break;
1005
1006 case4(054):
1007 length += 8; /* MOV reg64/imm */
1008 break;
1009
1010 case4(060):
1011 length += 2;
1012 break;
1013
1014 case4(064):
1015 if (opx->type & (BITS16 | BITS32 | BITS64))
1016 length += (opx->type & BITS16) ? 2 : 4;
1017 else
1018 length += (bits == 16) ? 2 : 4;
1019 break;
1020
1021 case4(070):
1022 length += 4;
1023 break;
1024
1025 case4(074):
1026 length += 2;
1027 break;
1028
1029 case 0172:
1030 case 0173:
1031 codes++;
1032 length++;
1033 break;
1034
1035 case4(0174):
1036 length++;
1037 break;
1038
1039 case4(0240):
1040 ins->rex |= REX_EV;
1041 ins->vexreg = regval(opx);
1042 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
1043 ins->vex_cm = *codes++;
1044 ins->vex_wlp = *codes++;
1045 ins->evex_tuple = (*codes++ - 0300);
1046 break;
1047
1048 case 0250:
1049 ins->rex |= REX_EV;
1050 ins->vexreg = 0;
1051 ins->vex_cm = *codes++;
1052 ins->vex_wlp = *codes++;
1053 ins->evex_tuple = (*codes++ - 0300);
1054 break;
1055
1056 case4(0254):
1057 length += 4;
1058 break;
1059
1060 case4(0260):
1061 ins->rex |= REX_V;
1062 ins->vexreg = regval(opx);
1063 ins->vex_cm = *codes++;
1064 ins->vex_wlp = *codes++;
1065 break;
1066
1067 case 0270:
1068 ins->rex |= REX_V;
1069 ins->vexreg = 0;
1070 ins->vex_cm = *codes++;
1071 ins->vex_wlp = *codes++;
1072 break;
1073
1074 case3(0271):
1075 hleok = c & 3;
1076 break;
1077
1078 case4(0274):
1079 length++;
1080 break;
1081
1082 case4(0300):
1083 break;
1084
1085 case 0310:
1086 if (bits == 64)
1087 return -1;
1088 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1089 break;
1090
1091 case 0311:
1092 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1093 break;
1094
1095 case 0312:
1096 break;
1097
1098 case 0313:
1099 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1100 has_prefix(ins, PPS_ASIZE, P_A32))
1101 return -1;
1102 break;
1103
1104 case4(0314):
1105 break;
1106
1107 case 0320:
1108 {
1109 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1110 if (pfx == P_O16)
1111 break;
1112 if (pfx != P_none)
1113 nasm_error(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1114 else
1115 ins->prefixes[PPS_OSIZE] = P_O16;
1116 break;
1117 }
1118
1119 case 0321:
1120 {
1121 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1122 if (pfx == P_O32)
1123 break;
1124 if (pfx != P_none)
1125 nasm_error(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1126 else
1127 ins->prefixes[PPS_OSIZE] = P_O32;
1128 break;
1129 }
1130
1131 case 0322:
1132 break;
1133
1134 case 0323:
1135 rex_mask &= ~REX_W;
1136 break;
1137
1138 case 0324:
1139 ins->rex |= REX_W;
1140 break;
1141
1142 case 0325:
1143 ins->rex |= REX_NH;
1144 break;
1145
1146 case 0326:
1147 break;
1148
1149 case 0330:
1150 codes++, length++;
1151 break;
1152
1153 case 0331:
1154 break;
1155
1156 case 0332:
1157 case 0333:
1158 length++;
1159 break;
1160
1161 case 0334:
1162 ins->rex |= REX_L;
1163 break;
1164
1165 case 0335:
1166 break;
1167
1168 case 0336:
1169 if (!ins->prefixes[PPS_REP])
1170 ins->prefixes[PPS_REP] = P_REP;
1171 break;
1172
1173 case 0337:
1174 if (!ins->prefixes[PPS_REP])
1175 ins->prefixes[PPS_REP] = P_REPNE;
1176 break;
1177
1178 case 0340:
1179 if (!absolute_op(&ins->oprs[0]))
1180 nasm_error(ERR_NONFATAL, "attempt to reserve non-constant"
1181 " quantity of BSS space");
1182 else if (ins->oprs[0].opflags & OPFLAG_FORWARD)
1183 nasm_error(ERR_WARNING | ERR_PASS1,
1184 "forward reference in RESx can have unpredictable results");
1185 else
1186 length += ins->oprs[0].offset;
1187 break;
1188
1189 case 0341:
1190 if (!ins->prefixes[PPS_WAIT])
1191 ins->prefixes[PPS_WAIT] = P_WAIT;
1192 break;
1193
1194 case 0360:
1195 break;
1196
1197 case 0361:
1198 length++;
1199 break;
1200
1201 case 0364:
1202 case 0365:
1203 break;
1204
1205 case 0366:
1206 case 0367:
1207 length++;
1208 break;
1209
1210 case 0370:
1211 case 0371:
1212 break;
1213
1214 case 0373:
1215 length++;
1216 break;
1217
1218 case 0374:
1219 eat = EA_XMMVSIB;
1220 break;
1221
1222 case 0375:
1223 eat = EA_YMMVSIB;
1224 break;
1225
1226 case 0376:
1227 eat = EA_ZMMVSIB;
1228 break;
1229
1230 case4(0100):
1231 case4(0110):
1232 case4(0120):
1233 case4(0130):
1234 case4(0200):
1235 case4(0204):
1236 case4(0210):
1237 case4(0214):
1238 case4(0220):
1239 case4(0224):
1240 case4(0230):
1241 case4(0234):
1242 {
1243 ea ea_data;
1244 int rfield;
1245 opflags_t rflags;
1246 struct operand *opy = &ins->oprs[op2];
1247 struct operand *op_er_sae;
1248
1249 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1250
1251 if (c <= 0177) {
1252 /* pick rfield from operand b (opx) */
1253 rflags = regflag(opx);
1254 rfield = nasm_regvals[opx->basereg];
1255 } else {
1256 rflags = 0;
1257 rfield = c & 7;
1258 }
1259
1260 /* EVEX.b1 : evex_brerop contains the operand position */
1261 op_er_sae = (ins->evex_brerop >= 0 ?
1262 &ins->oprs[ins->evex_brerop] : NULL);
1263
1264 if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
1265 /* set EVEX.b */
1266 ins->evex_p[2] |= EVEX_P2B;
1267 if (op_er_sae->decoflags & ER) {
1268 /* set EVEX.RC (rounding control) */
1269 ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
1270 & EVEX_P2RC;
1271 }
1272 } else {
1273 /* set EVEX.L'L (vector length) */
1274 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1275 ins->evex_p[1] |= ((ins->vex_wlp << (7 - 4)) & EVEX_P1W);
1276 if (opy->decoflags & BRDCAST_MASK) {
1277 /* set EVEX.b */
1278 ins->evex_p[2] |= EVEX_P2B;
1279 }
1280 }
1281
1282 if (itemp_has(temp, IF_MIB)) {
1283 opy->eaflags |= EAF_MIB;
1284 /*
1285 * if a separate form of MIB (ICC style) is used,
1286 * the index reg info is merged into mem operand
1287 */
1288 if (mib_index != R_none) {
1289 opy->indexreg = mib_index;
1290 opy->scale = 1;
1291 opy->hintbase = mib_index;
1292 opy->hinttype = EAH_NOTBASE;
1293 }
1294 }
1295
1296 if (process_ea(opy, &ea_data, bits,
1297 rfield, rflags, ins, &errmsg) != eat) {
1298 nasm_error(ERR_NONFATAL, "%s", errmsg);
1299 return -1;
1300 } else {
1301 ins->rex |= ea_data.rex;
1302 length += ea_data.size;
1303 }
1304 }
1305 break;
1306
1307 default:
1308 nasm_panic(0, "internal instruction table corrupt"
1309 ": instruction code \\%o (0x%02X) given", c, c);
1310 break;
1311 }
1312 }
1313
1314 ins->rex &= rex_mask;
1315
1316 if (ins->rex & REX_NH) {
1317 if (ins->rex & REX_H) {
1318 nasm_error(ERR_NONFATAL, "instruction cannot use high registers");
1319 return -1;
1320 }
1321 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1322 }
1323
1324 switch (ins->prefixes[PPS_VEX]) {
1325 case P_EVEX:
1326 if (!(ins->rex & REX_EV))
1327 return -1;
1328 break;
1329 case P_VEX3:
1330 case P_VEX2:
1331 if (!(ins->rex & REX_V))
1332 return -1;
1333 break;
1334 default:
1335 break;
1336 }
1337
1338 if (ins->rex & (REX_V | REX_EV)) {
1339 int bad32 = REX_R|REX_W|REX_X|REX_B;
1340
1341 if (ins->rex & REX_H) {
1342 nasm_error(ERR_NONFATAL, "cannot use high register in AVX instruction");
1343 return -1;
1344 }
1345 switch (ins->vex_wlp & 060) {
1346 case 000:
1347 case 040:
1348 ins->rex &= ~REX_W;
1349 break;
1350 case 020:
1351 ins->rex |= REX_W;
1352 bad32 &= ~REX_W;
1353 break;
1354 case 060:
1355 /* Follow REX_W */
1356 break;
1357 }
1358
1359 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1360 nasm_error(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1361 return -1;
1362 } else if (!(ins->rex & REX_EV) &&
1363 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1364 nasm_error(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1365 return -1;
1366 }
1367 if (ins->rex & REX_EV)
1368 length += 4;
1369 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1370 ins->prefixes[PPS_VEX] == P_VEX3)
1371 length += 3;
1372 else
1373 length += 2;
1374 } else if (ins->rex & REX_MASK) {
1375 if (ins->rex & REX_H) {
1376 nasm_error(ERR_NONFATAL, "cannot use high register in rex instruction");
1377 return -1;
1378 } else if (bits == 64) {
1379 length++;
1380 } else if ((ins->rex & REX_L) &&
1381 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1382 iflag_ffs(&cpu) >= IF_X86_64) {
1383 /* LOCK-as-REX.R */
1384 assert_no_prefix(ins, PPS_LOCK);
1385 lockcheck = false; /* Already errored, no need for warning */
1386 length++;
1387 } else {
1388 nasm_error(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1389 return -1;
1390 }
1391 }
1392
1393 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1394 (!itemp_has(temp,IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1395 nasm_error(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1396 "instruction is not lockable");
1397 }
1398
1399 bad_hle_warn(ins, hleok);
1400
1401 /*
1402 * when BND prefix is set by DEFAULT directive,
1403 * BND prefix is added to every appropriate instruction line
1404 * unless it is overridden by NOBND prefix.
1405 */
1406 if (globalbnd &&
1407 (itemp_has(temp, IF_BND) && !has_prefix(ins, PPS_REP, P_NOBND)))
1408 ins->prefixes[PPS_REP] = P_BND;
1409
1410 /*
1411 * Add length of legacy prefixes
1412 */
1413 length += emit_prefix(NULL, bits, ins);
1414
1415 return length;
1416 }
1417
1418 static inline void emit_rex(struct out_data *data, insn *ins)
1419 {
1420 if (data->bits == 64) {
1421 if ((ins->rex & REX_MASK) &&
1422 !(ins->rex & (REX_V | REX_EV)) &&
1423 !ins->rex_done) {
1424 uint8_t rex = (ins->rex & REX_MASK) | REX_P;
1425 out_rawbyte(data, rex);
1426 ins->rex_done = true;
1427 }
1428 }
1429 }
1430
1431 static int emit_prefix(struct out_data *data, const int bits, insn *ins)
1432 {
1433 int bytes = 0;
1434 int j;
1435
1436 for (j = 0; j < MAXPREFIX; j++) {
1437 uint8_t c = 0;
1438 switch (ins->prefixes[j]) {
1439 case P_WAIT:
1440 c = 0x9B;
1441 break;
1442 case P_LOCK:
1443 c = 0xF0;
1444 break;
1445 case P_REPNE:
1446 case P_REPNZ:
1447 case P_XACQUIRE:
1448 case P_BND:
1449 c = 0xF2;
1450 break;
1451 case P_REPE:
1452 case P_REPZ:
1453 case P_REP:
1454 case P_XRELEASE:
1455 c = 0xF3;
1456 break;
1457 case R_CS:
1458 if (bits == 64) {
1459 nasm_error(ERR_WARNING | ERR_PASS2,
1460 "cs segment base generated, but will be ignored in 64-bit mode");
1461 }
1462 c = 0x2E;
1463 break;
1464 case R_DS:
1465 if (bits == 64) {
1466 nasm_error(ERR_WARNING | ERR_PASS2,
1467 "ds segment base generated, but will be ignored in 64-bit mode");
1468 }
1469 c = 0x3E;
1470 break;
1471 case R_ES:
1472 if (bits == 64) {
1473 nasm_error(ERR_WARNING | ERR_PASS2,
1474 "es segment base generated, but will be ignored in 64-bit mode");
1475 }
1476 c = 0x26;
1477 break;
1478 case R_FS:
1479 c = 0x64;
1480 break;
1481 case R_GS:
1482 c = 0x65;
1483 break;
1484 case R_SS:
1485 if (bits == 64) {
1486 nasm_error(ERR_WARNING | ERR_PASS2,
1487 "ss segment base generated, but will be ignored in 64-bit mode");
1488 }
1489 c = 0x36;
1490 break;
1491 case R_SEGR6:
1492 case R_SEGR7:
1493 nasm_error(ERR_NONFATAL,
1494 "segr6 and segr7 cannot be used as prefixes");
1495 break;
1496 case P_A16:
1497 if (bits == 64) {
1498 nasm_error(ERR_NONFATAL,
1499 "16-bit addressing is not supported "
1500 "in 64-bit mode");
1501 } else if (bits != 16)
1502 c = 0x67;
1503 break;
1504 case P_A32:
1505 if (bits != 32)
1506 c = 0x67;
1507 break;
1508 case P_A64:
1509 if (bits != 64) {
1510 nasm_error(ERR_NONFATAL,
1511 "64-bit addressing is only supported "
1512 "in 64-bit mode");
1513 }
1514 break;
1515 case P_ASP:
1516 c = 0x67;
1517 break;
1518 case P_O16:
1519 if (bits != 16)
1520 c = 0x66;
1521 break;
1522 case P_O32:
1523 if (bits == 16)
1524 c = 0x66;
1525 break;
1526 case P_O64:
1527 /* REX.W */
1528 break;
1529 case P_OSP:
1530 c = 0x66;
1531 break;
1532 case P_EVEX:
1533 case P_VEX3:
1534 case P_VEX2:
1535 case P_NOBND:
1536 case P_none:
1537 break;
1538 default:
1539 nasm_panic(0, "invalid instruction prefix");
1540 }
1541 if (c) {
1542 if (data)
1543 out_rawbyte(data, c);
1544 bytes++;
1545 }
1546 }
1547 return bytes;
1548 }
1549
1550 static void gencode(struct out_data *data, insn *ins)
1551 {
1552 uint8_t c;
1553 uint8_t bytes[4];
1554 int64_t size;
1555 int op1, op2;
1556 struct operand *opx;
1557 const uint8_t *codes = data->itemp->code;
1558 uint8_t opex = 0;
1559 enum ea_type eat = EA_SCALAR;
1560 int r;
1561 const int bits = data->bits;
1562 const char *errmsg;
1563
1564 ins->rex_done = false;
1565
1566 emit_prefix(data, bits, ins);
1567
1568 while (*codes) {
1569 c = *codes++;
1570 op1 = (c & 3) + ((opex & 1) << 2);
1571 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1572 opx = &ins->oprs[op1];
1573 opex = 0; /* For the next iteration */
1574
1575
1576 switch (c) {
1577 case 01:
1578 case 02:
1579 case 03:
1580 case 04:
1581 emit_rex(data, ins);
1582 out_rawdata(data, codes, c);
1583 codes += c;
1584 break;
1585
1586 case 05:
1587 case 06:
1588 case 07:
1589 opex = c;
1590 break;
1591
1592 case4(010):
1593 emit_rex(data, ins);
1594 out_rawbyte(data, *codes++ + (regval(opx) & 7));
1595 break;
1596
1597 case4(014):
1598 break;
1599
1600 case4(020):
1601 out_imm(data, opx, 1, OUT_WRAP);
1602 break;
1603
1604 case4(024):
1605 out_imm(data, opx, 1, OUT_UNSIGNED);
1606 break;
1607
1608 case4(030):
1609 out_imm(data, opx, 2, OUT_WRAP);
1610 break;
1611
1612 case4(034):
1613 if (opx->type & (BITS16 | BITS32))
1614 size = (opx->type & BITS16) ? 2 : 4;
1615 else
1616 size = (bits == 16) ? 2 : 4;
1617 out_imm(data, opx, size, OUT_WRAP);
1618 break;
1619
1620 case4(040):
1621 out_imm(data, opx, 4, OUT_WRAP);
1622 break;
1623
1624 case4(044):
1625 size = ins->addr_size >> 3;
1626 out_imm(data, opx, size, OUT_WRAP);
1627 break;
1628
1629 case4(050):
1630 if (opx->segment == data->segment) {
1631 int64_t delta = opx->offset - data->offset
1632 - (data->inslen - data->insoffs);
1633 if (delta > 127 || delta < -128)
1634 nasm_error(ERR_NONFATAL, "short jump is out of range");
1635 }
1636 out_reladdr(data, opx, 1);
1637 break;
1638
1639 case4(054):
1640 out_imm(data, opx, 8, OUT_WRAP);
1641 break;
1642
1643 case4(060):
1644 out_reladdr(data, opx, 2);
1645 break;
1646
1647 case4(064):
1648 if (opx->type & (BITS16 | BITS32 | BITS64))
1649 size = (opx->type & BITS16) ? 2 : 4;
1650 else
1651 size = (bits == 16) ? 2 : 4;
1652
1653 out_reladdr(data, opx, size);
1654 break;
1655
1656 case4(070):
1657 out_reladdr(data, opx, 4);
1658 break;
1659
1660 case4(074):
1661 if (opx->segment == NO_SEG)
1662 nasm_error(ERR_NONFATAL, "value referenced by FAR is not"
1663 " relocatable");
1664 out_segment(data, opx);
1665 break;
1666
1667 case 0172:
1668 {
1669 int mask = ins->prefixes[PPS_VEX] == P_EVEX ? 7 : 15;
1670 const struct operand *opy;
1671
1672 c = *codes++;
1673 opx = &ins->oprs[c >> 3];
1674 opy = &ins->oprs[c & 7];
1675 if (!absolute_op(opy)) {
1676 nasm_error(ERR_NONFATAL,
1677 "non-absolute expression not permitted as argument %d",
1678 c & 7);
1679 } else if (opy->offset & ~mask) {
1680 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1681 "is4 argument exceeds bounds");
1682 }
1683 c = opy->offset & mask;
1684 goto emit_is4;
1685 }
1686
1687 case 0173:
1688 c = *codes++;
1689 opx = &ins->oprs[c >> 4];
1690 c &= 15;
1691 goto emit_is4;
1692
1693 case4(0174):
1694 c = 0;
1695 emit_is4:
1696 r = nasm_regvals[opx->basereg];
1697 out_rawbyte(data, (r << 4) | ((r & 0x10) >> 1) | c);
1698 break;
1699
1700 case4(0254):
1701 if (absolute_op(opx) &&
1702 (int32_t)opx->offset != (int64_t)opx->offset) {
1703 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1704 "signed dword immediate exceeds bounds");
1705 }
1706 out_imm(data, opx, 4, OUT_SIGNED);
1707 break;
1708
1709 case4(0240):
1710 case 0250:
1711 codes += 3;
1712 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1713 EVEX_P2Z | EVEX_P2AAA, 2);
1714 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1715 bytes[0] = 0x62;
1716 /* EVEX.X can be set by either REX or EVEX for different reasons */
1717 bytes[1] = ((((ins->rex & 7) << 5) |
1718 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) ^ 0xf0) |
1719 (ins->vex_cm & EVEX_P0MM);
1720 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1721 ((~ins->vexreg & 15) << 3) |
1722 (1 << 2) | (ins->vex_wlp & 3);
1723 bytes[3] = ins->evex_p[2];
1724 out_rawdata(data, bytes, 4);
1725 break;
1726
1727 case4(0260):
1728 case 0270:
1729 codes += 2;
1730 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1731 ins->prefixes[PPS_VEX] == P_VEX3) {
1732 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1733 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1734 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1735 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1736 out_rawdata(data, bytes, 3);
1737 } else {
1738 bytes[0] = 0xc5;
1739 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1740 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1741 out_rawdata(data, bytes, 2);
1742 }
1743 break;
1744
1745 case 0271:
1746 case 0272:
1747 case 0273:
1748 break;
1749
1750 case4(0274):
1751 {
1752 uint64_t uv, um;
1753 int s;
1754
1755 if (absolute_op(opx)) {
1756 if (ins->rex & REX_W)
1757 s = 64;
1758 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1759 s = 16;
1760 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1761 s = 32;
1762 else
1763 s = bits;
1764
1765 um = (uint64_t)2 << (s-1);
1766 uv = opx->offset;
1767
1768 if (uv > 127 && uv < (uint64_t)-128 &&
1769 (uv < um-128 || uv > um-1)) {
1770 /* If this wasn't explicitly byte-sized, warn as though we
1771 * had fallen through to the imm16/32/64 case.
1772 */
1773 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1774 "%s value exceeds bounds",
1775 (opx->type & BITS8) ? "signed byte" :
1776 s == 16 ? "word" :
1777 s == 32 ? "dword" :
1778 "signed dword");
1779 }
1780
1781 /* Output as a raw byte to avoid byte overflow check */
1782 out_rawbyte(data, (uint8_t)uv);
1783 } else {
1784 out_imm(data, opx, 1, OUT_WRAP); /* XXX: OUT_SIGNED? */
1785 }
1786 break;
1787 }
1788
1789 case4(0300):
1790 break;
1791
1792 case 0310:
1793 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16))
1794 out_rawbyte(data, 0x67);
1795 break;
1796
1797 case 0311:
1798 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32))
1799 out_rawbyte(data, 0x67);
1800 break;
1801
1802 case 0312:
1803 break;
1804
1805 case 0313:
1806 ins->rex = 0;
1807 break;
1808
1809 case4(0314):
1810 break;
1811
1812 case 0320:
1813 case 0321:
1814 break;
1815
1816 case 0322:
1817 case 0323:
1818 break;
1819
1820 case 0324:
1821 ins->rex |= REX_W;
1822 break;
1823
1824 case 0325:
1825 break;
1826
1827 case 0326:
1828 break;
1829
1830 case 0330:
1831 out_rawbyte(data, *codes++ ^ get_cond_opcode(ins->condition));
1832 break;
1833
1834 case 0331:
1835 break;
1836
1837 case 0332:
1838 case 0333:
1839 out_rawbyte(data, c - 0332 + 0xF2);
1840 break;
1841
1842 case 0334:
1843 if (ins->rex & REX_R)
1844 out_rawbyte(data, 0xF0);
1845 ins->rex &= ~(REX_L|REX_R);
1846 break;
1847
1848 case 0335:
1849 break;
1850
1851 case 0336:
1852 case 0337:
1853 break;
1854
1855 case 0340:
1856 if (ins->oprs[0].segment != NO_SEG)
1857 nasm_panic(0, "non-constant BSS size in pass two");
1858
1859 out_reserve(data, ins->oprs[0].offset);
1860 break;
1861
1862 case 0341:
1863 break;
1864
1865 case 0360:
1866 break;
1867
1868 case 0361:
1869 out_rawbyte(data, 0x66);
1870 break;
1871
1872 case 0364:
1873 case 0365:
1874 break;
1875
1876 case 0366:
1877 case 0367:
1878 out_rawbyte(data, c - 0366 + 0x66);
1879 break;
1880
1881 case3(0370):
1882 break;
1883
1884 case 0373:
1885 out_rawbyte(data, bits == 16 ? 3 : 5);
1886 break;
1887
1888 case 0374:
1889 eat = EA_XMMVSIB;
1890 break;
1891
1892 case 0375:
1893 eat = EA_YMMVSIB;
1894 break;
1895
1896 case 0376:
1897 eat = EA_ZMMVSIB;
1898 break;
1899
1900 case4(0100):
1901 case4(0110):
1902 case4(0120):
1903 case4(0130):
1904 case4(0200):
1905 case4(0204):
1906 case4(0210):
1907 case4(0214):
1908 case4(0220):
1909 case4(0224):
1910 case4(0230):
1911 case4(0234):
1912 {
1913 ea ea_data;
1914 int rfield;
1915 opflags_t rflags;
1916 uint8_t *p;
1917 struct operand *opy = &ins->oprs[op2];
1918
1919 if (c <= 0177) {
1920 /* pick rfield from operand b (opx) */
1921 rflags = regflag(opx);
1922 rfield = nasm_regvals[opx->basereg];
1923 } else {
1924 /* rfield is constant */
1925 rflags = 0;
1926 rfield = c & 7;
1927 }
1928
1929 if (process_ea(opy, &ea_data, bits,
1930 rfield, rflags, ins, &errmsg) != eat)
1931 nasm_error(ERR_NONFATAL, "%s", errmsg);
1932
1933 p = bytes;
1934 *p++ = ea_data.modrm;
1935 if (ea_data.sib_present)
1936 *p++ = ea_data.sib;
1937 out_rawdata(data, bytes, p - bytes);
1938
1939 /*
1940 * Make sure the address gets the right offset in case
1941 * the line breaks in the .lst file (BR 1197827)
1942 */
1943
1944 if (ea_data.bytes) {
1945 /* use compressed displacement, if available */
1946 if (ea_data.disp8) {
1947 out_rawbyte(data, ea_data.disp8);
1948 } else if (ea_data.rip) {
1949 out_reladdr(data, opy, ea_data.bytes);
1950 } else {
1951 int asize = ins->addr_size >> 3;
1952
1953 if (overflow_general(opy->offset, asize) ||
1954 signed_bits(opy->offset, ins->addr_size) !=
1955 signed_bits(opy->offset, ea_data.bytes << 3))
1956 warn_overflow(ea_data.bytes);
1957
1958 out_imm(data, opy, ea_data.bytes,
1959 (asize > ea_data.bytes)
1960 ? OUT_SIGNED : OUT_WRAP);
1961 }
1962 }
1963 }
1964 break;
1965
1966 default:
1967 nasm_panic(0, "internal instruction table corrupt"
1968 ": instruction code \\%o (0x%02X) given", c, c);
1969 break;
1970 }
1971 }
1972 }
1973
1974 static opflags_t regflag(const operand * o)
1975 {
1976 if (!is_register(o->basereg))
1977 nasm_panic(0, "invalid operand passed to regflag()");
1978 return nasm_reg_flags[o->basereg];
1979 }
1980
1981 static int32_t regval(const operand * o)
1982 {
1983 if (!is_register(o->basereg))
1984 nasm_panic(0, "invalid operand passed to regval()");
1985 return nasm_regvals[o->basereg];
1986 }
1987
1988 static int op_rexflags(const operand * o, int mask)
1989 {
1990 opflags_t flags;
1991 int val;
1992
1993 if (!is_register(o->basereg))
1994 nasm_panic(0, "invalid operand passed to op_rexflags()");
1995
1996 flags = nasm_reg_flags[o->basereg];
1997 val = nasm_regvals[o->basereg];
1998
1999 return rexflags(val, flags, mask);
2000 }
2001
2002 static int rexflags(int val, opflags_t flags, int mask)
2003 {
2004 int rex = 0;
2005
2006 if (val >= 0 && (val & 8))
2007 rex |= REX_B|REX_X|REX_R;
2008 if (flags & BITS64)
2009 rex |= REX_W;
2010 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
2011 rex |= REX_H;
2012 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
2013 rex |= REX_P;
2014
2015 return rex & mask;
2016 }
2017
2018 static int evexflags(int val, decoflags_t deco,
2019 int mask, uint8_t byte)
2020 {
2021 int evex = 0;
2022
2023 switch (byte) {
2024 case 0:
2025 if (val >= 0 && (val & 16))
2026 evex |= (EVEX_P0RP | EVEX_P0X);
2027 break;
2028 case 2:
2029 if (val >= 0 && (val & 16))
2030 evex |= EVEX_P2VP;
2031 if (deco & Z)
2032 evex |= EVEX_P2Z;
2033 if (deco & OPMASK_MASK)
2034 evex |= deco & EVEX_P2AAA;
2035 break;
2036 }
2037 return evex & mask;
2038 }
2039
2040 static int op_evexflags(const operand * o, int mask, uint8_t byte)
2041 {
2042 int val;
2043
2044 val = nasm_regvals[o->basereg];
2045
2046 return evexflags(val, o->decoflags, mask, byte);
2047 }
2048
2049 static enum match_result find_match(const struct itemplate **tempp,
2050 insn *instruction,
2051 int32_t segment, int64_t offset, int bits)
2052 {
2053 const struct itemplate *temp;
2054 enum match_result m, merr;
2055 opflags_t xsizeflags[MAX_OPERANDS];
2056 bool opsizemissing = false;
2057 int8_t broadcast = instruction->evex_brerop;
2058 int i;
2059
2060 /* broadcasting uses a different data element size */
2061 for (i = 0; i < instruction->operands; i++)
2062 if (i == broadcast)
2063 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
2064 else
2065 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
2066
2067 merr = MERR_INVALOP;
2068
2069 for (temp = nasm_instructions[instruction->opcode];
2070 temp->opcode != I_none; temp++) {
2071 m = matches(temp, instruction, bits);
2072 if (m == MOK_JUMP) {
2073 if (jmp_match(segment, offset, bits, instruction, temp))
2074 m = MOK_GOOD;
2075 else
2076 m = MERR_INVALOP;
2077 } else if (m == MERR_OPSIZEMISSING && !itemp_has(temp, IF_SX)) {
2078 /*
2079 * Missing operand size and a candidate for fuzzy matching...
2080 */
2081 for (i = 0; i < temp->operands; i++)
2082 if (i == broadcast)
2083 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
2084 else
2085 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
2086 opsizemissing = true;
2087 }
2088 if (m > merr)
2089 merr = m;
2090 if (merr == MOK_GOOD)
2091 goto done;
2092 }
2093
2094 /* No match, but see if we can get a fuzzy operand size match... */
2095 if (!opsizemissing)
2096 goto done;
2097
2098 for (i = 0; i < instruction->operands; i++) {
2099 /*
2100 * We ignore extrinsic operand sizes on registers, so we should
2101 * never try to fuzzy-match on them. This also resolves the case
2102 * when we have e.g. "xmmrm128" in two different positions.
2103 */
2104 if (is_class(REGISTER, instruction->oprs[i].type))
2105 continue;
2106
2107 /* This tests if xsizeflags[i] has more than one bit set */
2108 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2109 goto done; /* No luck */
2110
2111 if (i == broadcast) {
2112 instruction->oprs[i].decoflags |= xsizeflags[i];
2113 instruction->oprs[i].type |= (xsizeflags[i] == BR_BITS32 ?
2114 BITS32 : BITS64);
2115 } else {
2116 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2117 }
2118 }
2119
2120 /* Try matching again... */
2121 for (temp = nasm_instructions[instruction->opcode];
2122 temp->opcode != I_none; temp++) {
2123 m = matches(temp, instruction, bits);
2124 if (m == MOK_JUMP) {
2125 if (jmp_match(segment, offset, bits, instruction, temp))
2126 m = MOK_GOOD;
2127 else
2128 m = MERR_INVALOP;
2129 }
2130 if (m > merr)
2131 merr = m;
2132 if (merr == MOK_GOOD)
2133 goto done;
2134 }
2135
2136 done:
2137 *tempp = temp;
2138 return merr;
2139 }
2140
2141 static uint8_t get_broadcast_num(opflags_t opflags, opflags_t brsize)
2142 {
2143 unsigned int opsize = (opflags & SIZE_MASK) >> SIZE_SHIFT;
2144 uint8_t brcast_num;
2145
2146 if (brsize > BITS64)
2147 nasm_error(ERR_FATAL,
2148 "size of broadcasting element is greater than 64 bits");
2149
2150 /*
2151 * The shift term is to take care of the extra BITS80 inserted
2152 * between BITS64 and BITS128.
2153 */
2154 brcast_num = ((opsize / (BITS64 >> SIZE_SHIFT)) * (BITS64 / brsize))
2155 >> (opsize > (BITS64 >> SIZE_SHIFT));
2156
2157 return brcast_num;
2158 }
2159
2160 static enum match_result matches(const struct itemplate *itemp,
2161 insn *instruction, int bits)
2162 {
2163 opflags_t size[MAX_OPERANDS], asize;
2164 bool opsizemissing = false;
2165 int i, oprs;
2166
2167 /*
2168 * Check the opcode
2169 */
2170 if (itemp->opcode != instruction->opcode)
2171 return MERR_INVALOP;
2172
2173 /*
2174 * Count the operands
2175 */
2176 if (itemp->operands != instruction->operands)
2177 return MERR_INVALOP;
2178
2179 /*
2180 * Is it legal?
2181 */
2182 if (!(optimizing > 0) && itemp_has(itemp, IF_OPT))
2183 return MERR_INVALOP;
2184
2185 /*
2186 * {evex} available?
2187 */
2188 switch (instruction->prefixes[PPS_VEX]) {
2189 case P_EVEX:
2190 if (!itemp_has(itemp, IF_EVEX))
2191 return MERR_ENCMISMATCH;
2192 break;
2193 case P_VEX3:
2194 case P_VEX2:
2195 if (!itemp_has(itemp, IF_VEX))
2196 return MERR_ENCMISMATCH;
2197 break;
2198 default:
2199 break;
2200 }
2201
2202 /*
2203 * Check that no spurious colons or TOs are present
2204 */
2205 for (i = 0; i < itemp->operands; i++)
2206 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2207 return MERR_INVALOP;
2208
2209 /*
2210 * Process size flags
2211 */
2212 switch (itemp_smask(itemp)) {
2213 case IF_GENBIT(IF_SB):
2214 asize = BITS8;
2215 break;
2216 case IF_GENBIT(IF_SW):
2217 asize = BITS16;
2218 break;
2219 case IF_GENBIT(IF_SD):
2220 asize = BITS32;
2221 break;
2222 case IF_GENBIT(IF_SQ):
2223 asize = BITS64;
2224 break;
2225 case IF_GENBIT(IF_SO):
2226 asize = BITS128;
2227 break;
2228 case IF_GENBIT(IF_SY):
2229 asize = BITS256;
2230 break;
2231 case IF_GENBIT(IF_SZ):
2232 asize = BITS512;
2233 break;
2234 case IF_GENBIT(IF_SIZE):
2235 switch (bits) {
2236 case 16:
2237 asize = BITS16;
2238 break;
2239 case 32:
2240 asize = BITS32;
2241 break;
2242 case 64:
2243 asize = BITS64;
2244 break;
2245 default:
2246 asize = 0;
2247 break;
2248 }
2249 break;
2250 default:
2251 asize = 0;
2252 break;
2253 }
2254
2255 if (itemp_armask(itemp)) {
2256 /* S- flags only apply to a specific operand */
2257 i = itemp_arg(itemp);
2258 memset(size, 0, sizeof size);
2259 size[i] = asize;
2260 } else {
2261 /* S- flags apply to all operands */
2262 for (i = 0; i < MAX_OPERANDS; i++)
2263 size[i] = asize;
2264 }
2265
2266 /*
2267 * Check that the operand flags all match up,
2268 * it's a bit tricky so lets be verbose:
2269 *
2270 * 1) Find out the size of operand. If instruction
2271 * doesn't have one specified -- we're trying to
2272 * guess it either from template (IF_S* flag) or
2273 * from code bits.
2274 *
2275 * 2) If template operand do not match the instruction OR
2276 * template has an operand size specified AND this size differ
2277 * from which instruction has (perhaps we got it from code bits)
2278 * we are:
2279 * a) Check that only size of instruction and operand is differ
2280 * other characteristics do match
2281 * b) Perhaps it's a register specified in instruction so
2282 * for such a case we just mark that operand as "size
2283 * missing" and this will turn on fuzzy operand size
2284 * logic facility (handled by a caller)
2285 */
2286 for (i = 0; i < itemp->operands; i++) {
2287 opflags_t type = instruction->oprs[i].type;
2288 decoflags_t deco = instruction->oprs[i].decoflags;
2289 decoflags_t ideco = itemp->deco[i];
2290 bool is_broadcast = deco & BRDCAST_MASK;
2291 uint8_t brcast_num = 0;
2292 opflags_t template_opsize, insn_opsize;
2293
2294 if (!(type & SIZE_MASK))
2295 type |= size[i];
2296
2297 insn_opsize = type & SIZE_MASK;
2298 if (!is_broadcast) {
2299 template_opsize = itemp->opd[i] & SIZE_MASK;
2300 } else {
2301 decoflags_t deco_brsize = ideco & BRSIZE_MASK;
2302
2303 if (~ideco & BRDCAST_MASK)
2304 return MERR_BRNOTHERE;
2305
2306 /*
2307 * when broadcasting, the element size depends on
2308 * the instruction type. decorator flag should match.
2309 */
2310 if (deco_brsize) {
2311 template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
2312 /* calculate the proper number : {1to<brcast_num>} */
2313 brcast_num = get_broadcast_num(itemp->opd[i], template_opsize);
2314 } else {
2315 template_opsize = 0;
2316 }
2317 }
2318
2319 if (~ideco & deco & OPMASK_MASK)
2320 return MERR_MASKNOTHERE;
2321
2322 if (~ideco & deco & (Z_MASK|STATICRND_MASK|SAE_MASK))
2323 return MERR_DECONOTHERE;
2324
2325 if (itemp->opd[i] & ~type & ~SIZE_MASK) {
2326 return MERR_INVALOP;
2327 } else if (template_opsize) {
2328 if (template_opsize != insn_opsize) {
2329 if (insn_opsize) {
2330 return MERR_INVALOP;
2331 } else if (!is_class(REGISTER, type)) {
2332 /*
2333 * Note: we don't honor extrinsic operand sizes for registers,
2334 * so "missing operand size" for a register should be
2335 * considered a wildcard match rather than an error.
2336 */
2337 opsizemissing = true;
2338 }
2339 } else if (is_broadcast &&
2340 (brcast_num !=
2341 (2U << ((deco & BRNUM_MASK) >> BRNUM_SHIFT)))) {
2342 /*
2343 * broadcasting opsize matches but the number of repeated memory
2344 * element does not match.
2345 * if 64b double precision float is broadcasted to ymm (256b),
2346 * broadcasting decorator must be {1to4}.
2347 */
2348 return MERR_BRNUMMISMATCH;
2349 }
2350 }
2351 }
2352
2353 if (opsizemissing)
2354 return MERR_OPSIZEMISSING;
2355
2356 /*
2357 * Check operand sizes
2358 */
2359 if (itemp_has(itemp, IF_SM) || itemp_has(itemp, IF_SM2)) {
2360 oprs = (itemp_has(itemp, IF_SM2) ? 2 : itemp->operands);
2361 for (i = 0; i < oprs; i++) {
2362 asize = itemp->opd[i] & SIZE_MASK;
2363 if (asize) {
2364 for (i = 0; i < oprs; i++)
2365 size[i] = asize;
2366 break;
2367 }
2368 }
2369 } else {
2370 oprs = itemp->operands;
2371 }
2372
2373 for (i = 0; i < itemp->operands; i++) {
2374 if (!(itemp->opd[i] & SIZE_MASK) &&
2375 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2376 return MERR_OPSIZEMISMATCH;
2377 }
2378
2379 /*
2380 * Check template is okay at the set cpu level
2381 */
2382 if (iflag_cmp_cpu_level(&insns_flags[itemp->iflag_idx], &cpu) > 0)
2383 return MERR_BADCPU;
2384
2385 /*
2386 * Verify the appropriate long mode flag.
2387 */
2388 if (itemp_has(itemp, (bits == 64 ? IF_NOLONG : IF_LONG)))
2389 return MERR_BADMODE;
2390
2391 /*
2392 * If we have a HLE prefix, look for the NOHLE flag
2393 */
2394 if (itemp_has(itemp, IF_NOHLE) &&
2395 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2396 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2397 return MERR_BADHLE;
2398
2399 /*
2400 * Check if special handling needed for Jumps
2401 */
2402 if ((itemp->code[0] & ~1) == 0370)
2403 return MOK_JUMP;
2404
2405 /*
2406 * Check if BND prefix is allowed.
2407 * Other 0xF2 (REPNE/REPNZ) prefix is prohibited.
2408 */
2409 if (!itemp_has(itemp, IF_BND) &&
2410 (has_prefix(instruction, PPS_REP, P_BND) ||
2411 has_prefix(instruction, PPS_REP, P_NOBND)))
2412 return MERR_BADBND;
2413 else if (itemp_has(itemp, IF_BND) &&
2414 (has_prefix(instruction, PPS_REP, P_REPNE) ||
2415 has_prefix(instruction, PPS_REP, P_REPNZ)))
2416 return MERR_BADREPNE;
2417
2418 return MOK_GOOD;
2419 }
2420
2421 /*
2422 * Check if ModR/M.mod should/can be 01.
2423 * - EAF_BYTEOFFS is set
2424 * - offset can fit in a byte when EVEX is not used
2425 * - offset can be compressed when EVEX is used
2426 */
2427 #define IS_MOD_01() (!(input->eaflags & EAF_WORDOFFS) && \
2428 (ins->rex & REX_EV ? seg == NO_SEG && !forw_ref && \
2429 is_disp8n(input, ins, &output->disp8) : \
2430 input->eaflags & EAF_BYTEOFFS || (o >= -128 && \
2431 o <= 127 && seg == NO_SEG && !forw_ref)))
2432
2433 static enum ea_type process_ea(operand *input, ea *output, int bits,
2434 int rfield, opflags_t rflags, insn *ins,
2435 const char **errmsg)
2436 {
2437 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2438 int addrbits = ins->addr_size;
2439 int eaflags = input->eaflags;
2440
2441 *errmsg = "invalid effective address"; /* Default error message */
2442
2443 output->type = EA_SCALAR;
2444 output->rip = false;
2445 output->disp8 = 0;
2446
2447 /* REX flags for the rfield operand */
2448 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2449 /* EVEX.R' flag for the REG operand */
2450 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2451
2452 if (is_class(REGISTER, input->type)) {
2453 /*
2454 * It's a direct register.
2455 */
2456 if (!is_register(input->basereg))
2457 goto err;
2458
2459 if (!is_reg_class(REG_EA, input->basereg))
2460 goto err;
2461
2462 /* broadcasting is not available with a direct register operand. */
2463 if (input->decoflags & BRDCAST_MASK) {
2464 *errmsg = "broadcast not allowed with register operand";
2465 goto err;
2466 }
2467
2468 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2469 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2470 output->sib_present = false; /* no SIB necessary */
2471 output->bytes = 0; /* no offset necessary either */
2472 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2473 } else {
2474 /*
2475 * It's a memory reference.
2476 */
2477
2478 /* Embedded rounding or SAE is not available with a mem ref operand. */
2479 if (input->decoflags & (ER | SAE)) {
2480 *errmsg = "embedded rounding is available only with "
2481 "register-register operations";
2482 goto err;
2483 }
2484
2485 if (input->basereg == -1 &&
2486 (input->indexreg == -1 || input->scale == 0)) {
2487 /*
2488 * It's a pure offset.
2489 */
2490 if (bits == 64 && ((input->type & IP_REL) == IP_REL)) {
2491 if (input->segment == NO_SEG ||
2492 (input->opflags & OPFLAG_RELATIVE)) {
2493 nasm_error(ERR_WARNING | ERR_PASS2,
2494 "absolute address can not be RIP-relative");
2495 input->type &= ~IP_REL;
2496 input->type |= MEMORY;
2497 }
2498 }
2499
2500 if (bits == 64 &&
2501 !(IP_REL & ~input->type) && (eaflags & EAF_MIB)) {
2502 *errmsg = "RIP-relative addressing is prohibited for MIB";
2503 goto err;
2504 }
2505
2506 if (eaflags & EAF_BYTEOFFS ||
2507 (eaflags & EAF_WORDOFFS &&
2508 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2509 nasm_error(ERR_WARNING | ERR_PASS1,
2510 "displacement size ignored on absolute address");
2511 }
2512
2513 if (bits == 64 && (~input->type & IP_REL)) {
2514 output->sib_present = true;
2515 output->sib = GEN_SIB(0, 4, 5);
2516 output->bytes = 4;
2517 output->modrm = GEN_MODRM(0, rfield, 4);
2518 output->rip = false;
2519 } else {
2520 output->sib_present = false;
2521 output->bytes = (addrbits != 16 ? 4 : 2);
2522 output->modrm = GEN_MODRM(0, rfield,
2523 (addrbits != 16 ? 5 : 6));
2524 output->rip = bits == 64;
2525 }
2526 } else {
2527 /*
2528 * It's an indirection.
2529 */
2530 int i = input->indexreg, b = input->basereg, s = input->scale;
2531 int32_t seg = input->segment;
2532 int hb = input->hintbase, ht = input->hinttype;
2533 int t, it, bt; /* register numbers */
2534 opflags_t x, ix, bx; /* register flags */
2535
2536 if (s == 0)
2537 i = -1; /* make this easy, at least */
2538
2539 if (is_register(i)) {
2540 it = nasm_regvals[i];
2541 ix = nasm_reg_flags[i];
2542 } else {
2543 it = -1;
2544 ix = 0;
2545 }
2546
2547 if (is_register(b)) {
2548 bt = nasm_regvals[b];
2549 bx = nasm_reg_flags[b];
2550 } else {
2551 bt = -1;
2552 bx = 0;
2553 }
2554
2555 /* if either one are a vector register... */
2556 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2557 opflags_t sok = BITS32 | BITS64;
2558 int32_t o = input->offset;
2559 int mod, scale, index, base;
2560
2561 /*
2562 * For a vector SIB, one has to be a vector and the other,
2563 * if present, a GPR. The vector must be the index operand.
2564 */
2565 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2566 if (s == 0)
2567 s = 1;
2568 else if (s != 1)
2569 goto err;
2570
2571 t = bt, bt = it, it = t;
2572 x = bx, bx = ix, ix = x;
2573 }
2574
2575 if (bt != -1) {
2576 if (REG_GPR & ~bx)
2577 goto err;
2578 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2579 sok &= bx;
2580 else
2581 goto err;
2582 }
2583
2584 /*
2585 * While we're here, ensure the user didn't specify
2586 * WORD or QWORD
2587 */
2588 if (input->disp_size == 16 || input->disp_size == 64)
2589 goto err;
2590
2591 if (addrbits == 16 ||
2592 (addrbits == 32 && !(sok & BITS32)) ||
2593 (addrbits == 64 && !(sok & BITS64)))
2594 goto err;
2595
2596 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2597 : ((ix & YMMREG & ~REG_EA)
2598 ? EA_YMMVSIB : EA_XMMVSIB));
2599
2600 output->rex |= rexflags(it, ix, REX_X);
2601 output->rex |= rexflags(bt, bx, REX_B);
2602 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2603
2604 index = it & 7; /* it is known to be != -1 */
2605
2606 switch (s) {
2607 case 1:
2608 scale = 0;
2609 break;
2610 case 2:
2611 scale = 1;
2612 break;
2613 case 4:
2614 scale = 2;
2615 break;
2616 case 8:
2617 scale = 3;
2618 break;
2619 default: /* then what the smeg is it? */
2620 goto err; /* panic */
2621 }
2622
2623 if (bt == -1) {
2624 base = 5;
2625 mod = 0;
2626 } else {
2627 base = (bt & 7);
2628 if (base != REG_NUM_EBP && o == 0 &&
2629 seg == NO_SEG && !forw_ref &&
2630 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2631 mod = 0;
2632 else if (IS_MOD_01())
2633 mod = 1;
2634 else
2635 mod = 2;
2636 }
2637
2638 output->sib_present = true;
2639 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2640 output->modrm = GEN_MODRM(mod, rfield, 4);
2641 output->sib = GEN_SIB(scale, index, base);
2642 } else if ((ix|bx) & (BITS32|BITS64)) {
2643 /*
2644 * it must be a 32/64-bit memory reference. Firstly we have
2645 * to check that all registers involved are type E/Rxx.
2646 */
2647 opflags_t sok = BITS32 | BITS64;
2648 int32_t o = input->offset;
2649
2650 if (it != -1) {
2651 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2652 sok &= ix;
2653 else
2654 goto err;
2655 }
2656
2657 if (bt != -1) {
2658 if (REG_GPR & ~bx)
2659 goto err; /* Invalid register */
2660 if (~sok & bx & SIZE_MASK)
2661 goto err; /* Invalid size */
2662 sok &= bx;
2663 }
2664
2665 /*
2666 * While we're here, ensure the user didn't specify
2667 * WORD or QWORD
2668 */
2669 if (input->disp_size == 16 || input->disp_size == 64)
2670 goto err;
2671
2672 if (addrbits == 16 ||
2673 (addrbits == 32 && !(sok & BITS32)) ||
2674 (addrbits == 64 && !(sok & BITS64)))
2675 goto err;
2676
2677 /* now reorganize base/index */
2678 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2679 ((hb == b && ht == EAH_NOTBASE) ||
2680 (hb == i && ht == EAH_MAKEBASE))) {
2681 /* swap if hints say so */
2682 t = bt, bt = it, it = t;
2683 x = bx, bx = ix, ix = x;
2684 }
2685
2686 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
2687 /* make single reg base, unless hint */
2688 bt = it, bx = ix, it = -1, ix = 0;
2689 }
2690 if (eaflags & EAF_MIB) {
2691 /* only for mib operands */
2692 if (it == -1 && (hb == b && ht == EAH_NOTBASE)) {
2693 /*
2694 * make a single reg index [reg*1].
2695 * gas uses this form for an explicit index register.
2696 */
2697 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2698 }
2699 if ((ht == EAH_SUMMED) && bt == -1) {
2700 /* separate once summed index into [base, index] */
2701 bt = it, bx = ix, s--;
2702 }
2703 } else {
2704 if (((s == 2 && it != REG_NUM_ESP &&
2705 (!(eaflags & EAF_TIMESTWO) || (ht == EAH_SUMMED))) ||
2706 s == 3 || s == 5 || s == 9) && bt == -1) {
2707 /* convert 3*EAX to EAX+2*EAX */
2708 bt = it, bx = ix, s--;
2709 }
2710 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2711 (eaflags & EAF_TIMESTWO) &&
2712 (hb == b && ht == EAH_NOTBASE)) {
2713 /*
2714 * convert [NOSPLIT EAX*1]
2715 * to sib format with 0x0 displacement - [EAX*1+0].
2716 */
2717 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2718 }
2719 }
2720 if (s == 1 && it == REG_NUM_ESP) {
2721 /* swap ESP into base if scale is 1 */
2722 t = it, it = bt, bt = t;
2723 x = ix, ix = bx, bx = x;
2724 }
2725 if (it == REG_NUM_ESP ||
2726 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2727 goto err; /* wrong, for various reasons */
2728
2729 output->rex |= rexflags(it, ix, REX_X);
2730 output->rex |= rexflags(bt, bx, REX_B);
2731
2732 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2733 /* no SIB needed */
2734 int mod, rm;
2735
2736 if (bt == -1) {
2737 rm = 5;
2738 mod = 0;
2739 } else {
2740 rm = (bt & 7);
2741 if (rm != REG_NUM_EBP && o == 0 &&
2742 seg == NO_SEG && !forw_ref &&
2743 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2744 mod = 0;
2745 else if (IS_MOD_01())
2746 mod = 1;
2747 else
2748 mod = 2;
2749 }
2750
2751 output->sib_present = false;
2752 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2753 output->modrm = GEN_MODRM(mod, rfield, rm);
2754 } else {
2755 /* we need a SIB */
2756 int mod, scale, index, base;
2757
2758 if (it == -1)
2759 index = 4, s = 1;
2760 else
2761 index = (it & 7);
2762
2763 switch (s) {
2764 case 1:
2765 scale = 0;
2766 break;
2767 case 2:
2768 scale = 1;
2769 break;
2770 case 4:
2771 scale = 2;
2772 break;
2773 case 8:
2774 scale = 3;
2775 break;
2776 default: /* then what the smeg is it? */
2777 goto err; /* panic */
2778 }
2779
2780 if (bt == -1) {
2781 base = 5;
2782 mod = 0;
2783 } else {
2784 base = (bt & 7);
2785 if (base != REG_NUM_EBP && o == 0 &&
2786 seg == NO_SEG && !forw_ref &&
2787 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2788 mod = 0;
2789 else if (IS_MOD_01())
2790 mod = 1;
2791 else
2792 mod = 2;
2793 }
2794
2795 output->sib_present = true;
2796 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2797 output->modrm = GEN_MODRM(mod, rfield, 4);
2798 output->sib = GEN_SIB(scale, index, base);
2799 }
2800 } else { /* it's 16-bit */
2801 int mod, rm;
2802 int16_t o = input->offset;
2803
2804 /* check for 64-bit long mode */
2805 if (addrbits == 64)
2806 goto err;
2807
2808 /* check all registers are BX, BP, SI or DI */
2809 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2810 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2811 goto err;
2812
2813 /* ensure the user didn't specify DWORD/QWORD */
2814 if (input->disp_size == 32 || input->disp_size == 64)
2815 goto err;
2816
2817 if (s != 1 && i != -1)
2818 goto err; /* no can do, in 16-bit EA */
2819 if (b == -1 && i != -1) {
2820 int tmp = b;
2821 b = i;
2822 i = tmp;
2823 } /* swap */
2824 if ((b == R_SI || b == R_DI) && i != -1) {
2825 int tmp = b;
2826 b = i;
2827 i = tmp;
2828 }
2829 /* have BX/BP as base, SI/DI index */
2830 if (b == i)
2831 goto err; /* shouldn't ever happen, in theory */
2832 if (i != -1 && b != -1 &&
2833 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2834 goto err; /* invalid combinations */
2835 if (b == -1) /* pure offset: handled above */
2836 goto err; /* so if it gets to here, panic! */
2837
2838 rm = -1;
2839 if (i != -1)
2840 switch (i * 256 + b) {
2841 case R_SI * 256 + R_BX:
2842 rm = 0;
2843 break;
2844 case R_DI * 256 + R_BX:
2845 rm = 1;
2846 break;
2847 case R_SI * 256 + R_BP:
2848 rm = 2;
2849 break;
2850 case R_DI * 256 + R_BP:
2851 rm = 3;
2852 break;
2853 } else
2854 switch (b) {
2855 case R_SI:
2856 rm = 4;
2857 break;
2858 case R_DI:
2859 rm = 5;
2860 break;
2861 case R_BP:
2862 rm = 6;
2863 break;
2864 case R_BX:
2865 rm = 7;
2866 break;
2867 }
2868 if (rm == -1) /* can't happen, in theory */
2869 goto err; /* so panic if it does */
2870
2871 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2872 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2873 mod = 0;
2874 else if (IS_MOD_01())
2875 mod = 1;
2876 else
2877 mod = 2;
2878
2879 output->sib_present = false; /* no SIB - it's 16-bit */
2880 output->bytes = mod; /* bytes of offset needed */
2881 output->modrm = GEN_MODRM(mod, rfield, rm);
2882 }
2883 }
2884 }
2885
2886 output->size = 1 + output->sib_present + output->bytes;
2887 return output->type;
2888
2889 err:
2890 return output->type = EA_INVALID;
2891 }
2892
2893 static void add_asp(insn *ins, int addrbits)
2894 {
2895 int j, valid;
2896 int defdisp;
2897
2898 valid = (addrbits == 64) ? 64|32 : 32|16;
2899
2900 switch (ins->prefixes[PPS_ASIZE]) {
2901 case P_A16:
2902 valid &= 16;
2903 break;
2904 case P_A32:
2905 valid &= 32;
2906 break;
2907 case P_A64:
2908 valid &= 64;
2909 break;
2910 case P_ASP:
2911 valid &= (addrbits == 32) ? 16 : 32;
2912 break;
2913 default:
2914 break;
2915 }
2916
2917 for (j = 0; j < ins->operands; j++) {
2918 if (is_class(MEMORY, ins->oprs[j].type)) {
2919 opflags_t i, b;
2920
2921 /* Verify as Register */
2922 if (!is_register(ins->oprs[j].indexreg))
2923 i = 0;
2924 else
2925 i = nasm_reg_flags[ins->oprs[j].indexreg];
2926
2927 /* Verify as Register */
2928 if (!is_register(ins->oprs[j].basereg))
2929 b = 0;
2930 else
2931 b = nasm_reg_flags[ins->oprs[j].basereg];
2932
2933 if (ins->oprs[j].scale == 0)
2934 i = 0;
2935
2936 if (!i && !b) {
2937 int ds = ins->oprs[j].disp_size;
2938 if ((addrbits != 64 && ds > 8) ||
2939 (addrbits == 64 && ds == 16))
2940 valid &= ds;
2941 } else {
2942 if (!(REG16 & ~b))
2943 valid &= 16;
2944 if (!(REG32 & ~b))
2945 valid &= 32;
2946 if (!(REG64 & ~b))
2947 valid &= 64;
2948
2949 if (!(REG16 & ~i))
2950 valid &= 16;
2951 if (!(REG32 & ~i))
2952 valid &= 32;
2953 if (!(REG64 & ~i))
2954 valid &= 64;
2955 }
2956 }
2957 }
2958
2959 if (valid & addrbits) {
2960 ins->addr_size = addrbits;
2961 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2962 /* Add an address size prefix */
2963 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2964 ins->addr_size = (addrbits == 32) ? 16 : 32;
2965 } else {
2966 /* Impossible... */
2967 nasm_error(ERR_NONFATAL, "impossible combination of address sizes");
2968 ins->addr_size = addrbits; /* Error recovery */
2969 }
2970
2971 defdisp = ins->addr_size == 16 ? 16 : 32;
2972
2973 for (j = 0; j < ins->operands; j++) {
2974 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2975 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2976 /*
2977 * mem_offs sizes must match the address size; if not,
2978 * strip the MEM_OFFS bit and match only EA instructions
2979 */
2980 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2981 }
2982 }
2983 }
The Netwide Assembler