1 /* ----------------------------------------------------------------------- *
3 * Copyright 1996-2013 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 * ----------------------------------------------------------------------- */
35 * assemble.c code generation for the Netwide Assembler
37 * the actual codes (C syntax, i.e. octal):
38 * \0 - terminates the code. (Unless it's a literal of course.)
39 * \1..\4 - that many literal bytes follow in the code stream
40 * \5 - add 4 to the primary operand number (b, low octdigit)
41 * \6 - add 4 to the secondary operand number (a, middle octdigit)
42 * \7 - add 4 to both the primary and the secondary operand number
43 * \10..\13 - a literal byte follows in the code stream, to be added
44 * to the register value of operand 0..3
45 * \14..\17 - the position of index register operand in MIB (BND insns)
46 * \20..\23 - a byte immediate operand, from operand 0..3
47 * \24..\27 - a zero-extended byte immediate operand, from operand 0..3
48 * \30..\33 - a word immediate operand, from operand 0..3
49 * \34..\37 - select between \3[0-3] and \4[0-3] depending on 16/32 bit
50 * assembly mode or the operand-size override on the operand
51 * \40..\43 - a long immediate operand, from operand 0..3
52 * \44..\47 - select between \3[0-3], \4[0-3] and \5[4-7]
53 * depending on the address size of the instruction.
54 * \50..\53 - a byte relative operand, from operand 0..3
55 * \54..\57 - a qword immediate operand, from operand 0..3
56 * \60..\63 - a word relative operand, from operand 0..3
57 * \64..\67 - select between \6[0-3] and \7[0-3] depending on 16/32 bit
58 * assembly mode or the operand-size override on the operand
59 * \70..\73 - a long relative operand, from operand 0..3
60 * \74..\77 - a word constant, from the _segment_ part of operand 0..3
61 * \1ab - a ModRM, calculated on EA in operand a, with the spare
62 * field the register value of operand b.
63 * \172\ab - the register number from operand a in bits 7..4, with
64 * the 4-bit immediate from operand b in bits 3..0.
65 * \173\xab - the register number from operand a in bits 7..4, with
66 * the value b in bits 3..0.
67 * \174..\177 - the register number from operand 0..3 in bits 7..4, and
68 * an arbitrary value in bits 3..0 (assembled as zero.)
69 * \2ab - a ModRM, calculated on EA in operand a, with the spare
70 * field equal to digit b.
72 * \240..\243 - this instruction uses EVEX rather than REX or VEX/XOP, with the
73 * V field taken from operand 0..3.
74 * \250 - this instruction uses EVEX rather than REX or VEX/XOP, with the
75 * V field set to 1111b.
76 * EVEX prefixes are followed by the sequence:
77 * \cm\wlp\tup where cm is:
79 * c = 2 for EVEX and m is the legacy escape (0f, 0f38, 0f3a)
82 * [l0] ll = 0 (.128, .lz)
85 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
87 * [w0] ww = 0 for W = 0
88 * [w1] ww = 1 for W = 1
89 * [wig] ww = 2 for W don't care (always assembled as 0)
90 * [ww] ww = 3 for W used as REX.W
92 * [p0] pp = 0 for no prefix
93 * [60] pp = 1 for legacy prefix 60
97 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
98 * (compressed displacement encoding)
100 * \254..\257 - a signed 32-bit operand to be extended to 64 bits.
101 * \260..\263 - this instruction uses VEX/XOP rather than REX, with the
102 * V field taken from operand 0..3.
103 * \270 - this instruction uses VEX/XOP rather than REX, with the
104 * V field set to 1111b.
106 * VEX/XOP prefixes are followed by the sequence:
107 * \tmm\wlp where mm is the M field; and wlp is:
109 * [l0] ll = 0 for L = 0 (.128, .lz)
110 * [l1] ll = 1 for L = 1 (.256)
111 * [lig] ll = 2 for L don't care (always assembled as 0)
113 * [w0] ww = 0 for W = 0
114 * [w1 ] ww = 1 for W = 1
115 * [wig] ww = 2 for W don't care (always assembled as 0)
116 * [ww] ww = 3 for W used as REX.W
118 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
120 * \271 - instruction takes XRELEASE (F3) with or without lock
121 * \272 - instruction takes XACQUIRE/XRELEASE with or without lock
122 * \273 - instruction takes XACQUIRE/XRELEASE with lock only
123 * \274..\277 - a byte immediate operand, from operand 0..3, sign-extended
124 * to the operand size (if o16/o32/o64 present) or the bit size
125 * \310 - indicates fixed 16-bit address size, i.e. optional 0x67.
126 * \311 - indicates fixed 32-bit address size, i.e. optional 0x67.
127 * \312 - (disassembler only) invalid with non-default address size.
128 * \313 - indicates fixed 64-bit address size, 0x67 invalid.
129 * \314 - (disassembler only) invalid with REX.B
130 * \315 - (disassembler only) invalid with REX.X
131 * \316 - (disassembler only) invalid with REX.R
132 * \317 - (disassembler only) invalid with REX.W
133 * \320 - indicates fixed 16-bit operand size, i.e. optional 0x66.
134 * \321 - indicates fixed 32-bit operand size, i.e. optional 0x66.
135 * \322 - indicates that this instruction is only valid when the
136 * operand size is the default (instruction to disassembler,
137 * generates no code in the assembler)
138 * \323 - indicates fixed 64-bit operand size, REX on extensions only.
139 * \324 - indicates 64-bit operand size requiring REX prefix.
140 * \325 - instruction which always uses spl/bpl/sil/dil
141 * \326 - instruction not valid with 0xF3 REP prefix. Hint for
142 disassembler only; for SSE instructions.
143 * \330 - a literal byte follows in the code stream, to be added
144 * to the condition code value of the instruction.
145 * \331 - instruction not valid with REP prefix. Hint for
146 * disassembler only; for SSE instructions.
147 * \332 - REP prefix (0xF2 byte) used as opcode extension.
148 * \333 - REP prefix (0xF3 byte) used as opcode extension.
149 * \334 - LOCK prefix used as REX.R (used in non-64-bit mode)
150 * \335 - disassemble a rep (0xF3 byte) prefix as repe not rep.
151 * \336 - force a REP(E) prefix (0xF3) even if not specified.
152 * \337 - force a REPNE prefix (0xF2) even if not specified.
153 * \336-\337 are still listed as prefixes in the disassembler.
154 * \340 - reserve <operand 0> bytes of uninitialized storage.
155 * Operand 0 had better be a segmentless constant.
156 * \341 - this instruction needs a WAIT "prefix"
157 * \360 - no SSE prefix (== \364\331)
158 * \361 - 66 SSE prefix (== \366\331)
159 * \364 - operand-size prefix (0x66) not permitted
160 * \365 - address-size prefix (0x67) not permitted
161 * \366 - operand-size prefix (0x66) used as opcode extension
162 * \367 - address-size prefix (0x67) used as opcode extension
163 * \370,\371 - match only if operand 0 meets byte jump criteria.
164 * 370 is used for Jcc, 371 is used for JMP.
165 * \373 - assemble 0x03 if bits==16, 0x05 if bits==32;
166 * used for conditional jump over longer jump
167 * \374 - this instruction takes an XMM VSIB memory EA
168 * \375 - this instruction takes an YMM VSIB memory EA
169 * \376 - this instruction takes an ZMM VSIB memory EA
172 #include "compiler.h"
176 #include <inttypes.h>
180 #include "assemble.h"
187 * Matching errors. These should be sorted so that more specific
188 * errors come later in the sequence.
200 * Matching success; the conditional ones first
202 MOK_JUMP
, /* Matching OK but needs jmp_match() */
203 MOK_GOOD
/* Matching unconditionally OK */
207 enum ea_type type
; /* what kind of EA is this? */
208 int sib_present
; /* is a SIB byte necessary? */
209 int bytes
; /* # of bytes of offset needed */
210 int size
; /* lazy - this is sib+bytes+1 */
211 uint8_t modrm
, sib
, rex
, rip
; /* the bytes themselves */
212 int8_t disp8
; /* compressed displacement for EVEX */
215 #define GEN_SIB(scale, index, base) \
216 (((scale) << 6) | ((index) << 3) | ((base)))
218 #define GEN_MODRM(mod, reg, rm) \
219 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
221 static iflag_t cpu
; /* cpu level received from nasm.c */
222 static efunc errfunc
;
223 static struct ofmt
*outfmt
;
224 static ListGen
*list
;
226 static int64_t calcsize(int32_t, int64_t, int, insn
*,
227 const struct itemplate
*);
228 static void gencode(int32_t segment
, int64_t offset
, int bits
,
229 insn
* ins
, const struct itemplate
*temp
,
231 static enum match_result
find_match(const struct itemplate
**tempp
,
233 int32_t segment
, int64_t offset
, int bits
);
234 static enum match_result
matches(const struct itemplate
*, insn
*, int bits
);
235 static opflags_t
regflag(const operand
*);
236 static int32_t regval(const operand
*);
237 static int rexflags(int, opflags_t
, int);
238 static int op_rexflags(const operand
*, int);
239 static int op_evexflags(const operand
*, int, uint8_t);
240 static void add_asp(insn
*, int);
242 static enum ea_type
process_ea(operand
*, ea
*, int, int, opflags_t
, insn
*);
244 static int has_prefix(insn
* ins
, enum prefix_pos pos
, int prefix
)
246 return ins
->prefixes
[pos
] == prefix
;
249 static void assert_no_prefix(insn
* ins
, enum prefix_pos pos
)
251 if (ins
->prefixes
[pos
])
252 errfunc(ERR_NONFATAL
, "invalid %s prefix",
253 prefix_name(ins
->prefixes
[pos
]));
256 static const char *size_name(int size
)
280 static void warn_overflow(int pass
, int size
)
282 errfunc(ERR_WARNING
| pass
| ERR_WARN_NOV
,
283 "%s data exceeds bounds", size_name(size
));
286 static void warn_overflow_const(int64_t data
, int size
)
288 if (overflow_general(data
, size
))
289 warn_overflow(ERR_PASS1
, size
);
292 static void warn_overflow_opd(const struct operand
*o
, int size
)
294 if (o
->wrt
== NO_SEG
&& o
->segment
== NO_SEG
) {
295 if (overflow_general(o
->offset
, size
))
296 warn_overflow(ERR_PASS2
, size
);
301 * This routine wrappers the real output format's output routine,
302 * in order to pass a copy of the data off to the listing file
303 * generator at the same time.
305 static void out(int64_t offset
, int32_t segto
, const void *data
,
306 enum out_type type
, uint64_t size
,
307 int32_t segment
, int32_t wrt
)
309 static int32_t lineno
= 0; /* static!!! */
310 static char *lnfname
= NULL
;
313 if (type
== OUT_ADDRESS
&& segment
== NO_SEG
&& wrt
== NO_SEG
) {
315 * This is a non-relocated address, and we're going to
316 * convert it into RAWDATA format.
321 errfunc(ERR_PANIC
, "OUT_ADDRESS with size > 8");
325 WRITEADDR(q
, *(int64_t *)data
, size
);
330 list
->output(offset
, data
, type
, size
);
333 * this call to src_get determines when we call the
334 * debug-format-specific "linenum" function
335 * it updates lineno and lnfname to the current values
336 * returning 0 if "same as last time", -2 if lnfname
337 * changed, and the amount by which lineno changed,
338 * if it did. thus, these variables must be static
341 if (src_get(&lineno
, &lnfname
))
342 outfmt
->current_dfmt
->linenum(lnfname
, lineno
, segto
);
344 outfmt
->output(segto
, data
, type
, size
, segment
, wrt
);
347 static void out_imm8(int64_t offset
, int32_t segment
, struct operand
*opx
)
349 if (opx
->segment
!= NO_SEG
) {
350 uint64_t data
= opx
->offset
;
351 out(offset
, segment
, &data
, OUT_ADDRESS
, 1, opx
->segment
, opx
->wrt
);
353 uint8_t byte
= opx
->offset
;
354 out(offset
, segment
, &byte
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
358 static bool jmp_match(int32_t segment
, int64_t offset
, int bits
,
359 insn
* ins
, const struct itemplate
*temp
)
362 const uint8_t *code
= temp
->code
;
366 if (((c
& ~1) != 0370) || (ins
->oprs
[0].type
& STRICT
))
370 if (optimizing
< 0 && c
== 0371)
373 isize
= calcsize(segment
, offset
, bits
, ins
, temp
);
375 if (ins
->oprs
[0].opflags
& OPFLAG_UNKNOWN
)
376 /* Be optimistic in pass 1 */
379 if (ins
->oprs
[0].segment
!= segment
)
382 isize
= ins
->oprs
[0].offset
- offset
- isize
; /* isize is delta */
383 is_byte
= (isize
>= -128 && isize
<= 127); /* is it byte size? */
385 if (is_byte
&& c
== 0371 && ins
->prefixes
[PPS_REP
] == P_BND
) {
386 /* jmp short (opcode eb) cannot be used with bnd prefix. */
387 ins
->prefixes
[PPS_REP
] = P_none
;
393 int64_t assemble(int32_t segment
, int64_t offset
, int bits
, iflag_t cp
,
394 insn
* instruction
, struct ofmt
*output
, efunc error
,
397 const struct itemplate
*temp
;
402 int64_t start
= offset
;
403 int64_t wsize
; /* size for DB etc. */
405 errfunc
= error
; /* to pass to other functions */
407 outfmt
= output
; /* likewise */
408 list
= listgen
; /* and again */
410 wsize
= idata_bytes(instruction
->opcode
);
416 int32_t t
= instruction
->times
;
419 "instruction->times < 0 (%ld) in assemble()", t
);
421 while (t
--) { /* repeat TIMES times */
422 list_for_each(e
, instruction
->eops
) {
423 if (e
->type
== EOT_DB_NUMBER
) {
425 errfunc(ERR_NONFATAL
,
426 "integer supplied to a DT, DO or DY"
429 out(offset
, segment
, &e
->offset
,
430 OUT_ADDRESS
, wsize
, e
->segment
, e
->wrt
);
433 } else if (e
->type
== EOT_DB_STRING
||
434 e
->type
== EOT_DB_STRING_FREE
) {
437 out(offset
, segment
, e
->stringval
,
438 OUT_RAWDATA
, e
->stringlen
, NO_SEG
, NO_SEG
);
439 align
= e
->stringlen
% wsize
;
442 align
= wsize
- align
;
443 out(offset
, segment
, zero_buffer
,
444 OUT_RAWDATA
, align
, NO_SEG
, NO_SEG
);
446 offset
+= e
->stringlen
+ align
;
449 if (t
> 0 && t
== instruction
->times
- 1) {
451 * Dummy call to list->output to give the offset to the
454 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
455 list
->uplevel(LIST_TIMES
);
458 if (instruction
->times
> 1)
459 list
->downlevel(LIST_TIMES
);
460 return offset
- start
;
463 if (instruction
->opcode
== I_INCBIN
) {
464 const char *fname
= instruction
->eops
->stringval
;
467 fp
= fopen(fname
, "rb");
469 error(ERR_NONFATAL
, "`incbin': unable to open file `%s'",
471 } else if (fseek(fp
, 0L, SEEK_END
) < 0) {
472 error(ERR_NONFATAL
, "`incbin': unable to seek on file `%s'",
476 static char buf
[4096];
477 size_t t
= instruction
->times
;
482 if (instruction
->eops
->next
) {
483 base
= instruction
->eops
->next
->offset
;
485 if (instruction
->eops
->next
->next
&&
486 len
> (size_t)instruction
->eops
->next
->next
->offset
)
487 len
= (size_t)instruction
->eops
->next
->next
->offset
;
490 * Dummy call to list->output to give the offset to the
493 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
494 list
->uplevel(LIST_INCBIN
);
498 fseek(fp
, base
, SEEK_SET
);
502 m
= fread(buf
, 1, l
> sizeof(buf
) ? sizeof(buf
) : l
, fp
);
505 * This shouldn't happen unless the file
506 * actually changes while we are reading
510 "`incbin': unexpected EOF while"
511 " reading file `%s'", fname
);
512 t
= 0; /* Try to exit cleanly */
515 out(offset
, segment
, buf
, OUT_RAWDATA
, m
,
520 list
->downlevel(LIST_INCBIN
);
521 if (instruction
->times
> 1) {
523 * Dummy call to list->output to give the offset to the
526 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
527 list
->uplevel(LIST_TIMES
);
528 list
->downlevel(LIST_TIMES
);
531 return instruction
->times
* len
;
533 return 0; /* if we're here, there's an error */
536 /* Check to see if we need an address-size prefix */
537 add_asp(instruction
, bits
);
539 m
= find_match(&temp
, instruction
, segment
, offset
, bits
);
543 int64_t insn_size
= calcsize(segment
, offset
, bits
, instruction
, temp
);
544 itimes
= instruction
->times
;
545 if (insn_size
< 0) /* shouldn't be, on pass two */
546 error(ERR_PANIC
, "errors made it through from pass one");
549 for (j
= 0; j
< MAXPREFIX
; j
++) {
551 switch (instruction
->prefixes
[j
]) {
572 error(ERR_WARNING
| ERR_PASS2
,
573 "cs segment base generated, but will be ignored in 64-bit mode");
579 error(ERR_WARNING
| ERR_PASS2
,
580 "ds segment base generated, but will be ignored in 64-bit mode");
586 error(ERR_WARNING
| ERR_PASS2
,
587 "es segment base generated, but will be ignored in 64-bit mode");
599 error(ERR_WARNING
| ERR_PASS2
,
600 "ss segment base generated, but will be ignored in 64-bit mode");
607 "segr6 and segr7 cannot be used as prefixes");
612 "16-bit addressing is not supported "
614 } else if (bits
!= 16)
624 "64-bit addressing is only supported "
651 error(ERR_PANIC
, "invalid instruction prefix");
654 out(offset
, segment
, &c
, OUT_RAWDATA
, 1,
659 insn_end
= offset
+ insn_size
;
660 gencode(segment
, offset
, bits
, instruction
,
663 if (itimes
> 0 && itimes
== instruction
->times
- 1) {
665 * Dummy call to list->output to give the offset to the
668 list
->output(offset
, NULL
, OUT_RAWDATA
, 0);
669 list
->uplevel(LIST_TIMES
);
672 if (instruction
->times
> 1)
673 list
->downlevel(LIST_TIMES
);
674 return offset
- start
;
678 case MERR_OPSIZEMISSING
:
679 error(ERR_NONFATAL
, "operation size not specified");
681 case MERR_OPSIZEMISMATCH
:
682 error(ERR_NONFATAL
, "mismatch in operand sizes");
684 case MERR_BRNUMMISMATCH
:
686 "mismatch in the number of broadcasting elements");
689 error(ERR_NONFATAL
, "no instruction for this cpu level");
692 error(ERR_NONFATAL
, "instruction not supported in %d-bit mode",
696 error(ERR_NONFATAL
, "bnd prefix is not allowed");
700 "invalid combination of opcode and operands");
707 int64_t insn_size(int32_t segment
, int64_t offset
, int bits
, iflag_t cp
,
708 insn
* instruction
, efunc error
)
710 const struct itemplate
*temp
;
713 errfunc
= error
; /* to pass to other functions */
716 if (instruction
->opcode
== I_none
)
719 if (instruction
->opcode
== I_DB
|| instruction
->opcode
== I_DW
||
720 instruction
->opcode
== I_DD
|| instruction
->opcode
== I_DQ
||
721 instruction
->opcode
== I_DT
|| instruction
->opcode
== I_DO
||
722 instruction
->opcode
== I_DY
) {
724 int32_t isize
, osize
, wsize
;
727 wsize
= idata_bytes(instruction
->opcode
);
729 list_for_each(e
, instruction
->eops
) {
733 if (e
->type
== EOT_DB_NUMBER
) {
735 warn_overflow_const(e
->offset
, wsize
);
736 } else if (e
->type
== EOT_DB_STRING
||
737 e
->type
== EOT_DB_STRING_FREE
)
738 osize
= e
->stringlen
;
740 align
= (-osize
) % wsize
;
743 isize
+= osize
+ align
;
745 return isize
* instruction
->times
;
748 if (instruction
->opcode
== I_INCBIN
) {
749 const char *fname
= instruction
->eops
->stringval
;
754 fp
= fopen(fname
, "rb");
756 error(ERR_NONFATAL
, "`incbin': unable to open file `%s'",
758 else if (fseek(fp
, 0L, SEEK_END
) < 0)
759 error(ERR_NONFATAL
, "`incbin': unable to seek on file `%s'",
763 if (instruction
->eops
->next
) {
764 len
-= instruction
->eops
->next
->offset
;
765 if (instruction
->eops
->next
->next
&&
766 len
> (size_t)instruction
->eops
->next
->next
->offset
) {
767 len
= (size_t)instruction
->eops
->next
->next
->offset
;
770 val
= instruction
->times
* len
;
777 /* Check to see if we need an address-size prefix */
778 add_asp(instruction
, bits
);
780 m
= find_match(&temp
, instruction
, segment
, offset
, bits
);
782 /* we've matched an instruction. */
786 isize
= calcsize(segment
, offset
, bits
, instruction
, temp
);
789 for (j
= 0; j
< MAXPREFIX
; j
++) {
790 switch (instruction
->prefixes
[j
]) {
817 return isize
* instruction
->times
;
819 return -1; /* didn't match any instruction */
823 static void bad_hle_warn(const insn
* ins
, uint8_t hleok
)
825 enum prefixes rep_pfx
= ins
->prefixes
[PPS_REP
];
826 enum whatwarn
{ w_none
, w_lock
, w_inval
} ww
;
827 static const enum whatwarn warn
[2][4] =
829 { w_inval
, w_inval
, w_none
, w_lock
}, /* XACQUIRE */
830 { w_inval
, w_none
, w_none
, w_lock
}, /* XRELEASE */
834 n
= (unsigned int)rep_pfx
- P_XACQUIRE
;
836 return; /* Not XACQUIRE/XRELEASE */
839 if (!is_class(MEMORY
, ins
->oprs
[0].type
))
840 ww
= w_inval
; /* HLE requires operand 0 to be memory */
847 if (ins
->prefixes
[PPS_LOCK
] != P_LOCK
) {
848 errfunc(ERR_WARNING
| ERR_WARN_HLE
| ERR_PASS2
,
849 "%s with this instruction requires lock",
850 prefix_name(rep_pfx
));
855 errfunc(ERR_WARNING
| ERR_WARN_HLE
| ERR_PASS2
,
856 "%s invalid with this instruction",
857 prefix_name(rep_pfx
));
862 /* Common construct */
863 #define case3(x) case (x): case (x)+1: case (x)+2
864 #define case4(x) case3(x): case (x)+3
866 static int64_t calcsize(int32_t segment
, int64_t offset
, int bits
,
867 insn
* ins
, const struct itemplate
*temp
)
869 const uint8_t *codes
= temp
->code
;
878 bool lockcheck
= true;
879 enum reg_enum mib_index
= R_none
; /* For a separate index MIB reg form */
881 ins
->rex
= 0; /* Ensure REX is reset */
882 eat
= EA_SCALAR
; /* Expect a scalar EA */
883 memset(ins
->evex_p
, 0, 3); /* Ensure EVEX is reset */
885 if (ins
->prefixes
[PPS_OSIZE
] == P_O64
)
888 (void)segment
; /* Don't warn that this parameter is unused */
889 (void)offset
; /* Don't warn that this parameter is unused */
893 op1
= (c
& 3) + ((opex
& 1) << 2);
894 op2
= ((c
>> 3) & 3) + ((opex
& 2) << 1);
895 opx
= &ins
->oprs
[op1
];
896 opex
= 0; /* For the next iteration */
900 codes
+= c
, length
+= c
;
909 op_rexflags(opx
, REX_B
|REX_H
|REX_P
|REX_W
);
914 /* this is an index reg of MIB operand */
915 mib_index
= opx
->basereg
;
928 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
929 length
+= (opx
->type
& BITS16
) ? 2 : 4;
931 length
+= (bits
== 16) ? 2 : 4;
939 length
+= ins
->addr_size
>> 3;
947 length
+= 8; /* MOV reg64/imm */
955 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
956 length
+= (opx
->type
& BITS16
) ? 2 : 4;
958 length
+= (bits
== 16) ? 2 : 4;
981 ins
->vexreg
= regval(opx
);
982 ins
->evex_p
[2] |= op_evexflags(opx
, EVEX_P2VP
, 2); /* High-16 NDS */
983 ins
->vex_cm
= *codes
++;
984 ins
->vex_wlp
= *codes
++;
985 ins
->evex_tuple
= (*codes
++ - 0300);
991 ins
->vex_cm
= *codes
++;
992 ins
->vex_wlp
= *codes
++;
993 ins
->evex_tuple
= (*codes
++ - 0300);
1002 ins
->vexreg
= regval(opx
);
1003 ins
->vex_cm
= *codes
++;
1004 ins
->vex_wlp
= *codes
++;
1010 ins
->vex_cm
= *codes
++;
1011 ins
->vex_wlp
= *codes
++;
1028 length
+= (bits
!= 16) && !has_prefix(ins
, PPS_ASIZE
, P_A16
);
1032 length
+= (bits
!= 32) && !has_prefix(ins
, PPS_ASIZE
, P_A32
);
1039 if (bits
!= 64 || has_prefix(ins
, PPS_ASIZE
, P_A16
) ||
1040 has_prefix(ins
, PPS_ASIZE
, P_A32
))
1049 enum prefixes pfx
= ins
->prefixes
[PPS_OSIZE
];
1053 errfunc(ERR_WARNING
| ERR_PASS2
, "invalid operand size prefix");
1055 ins
->prefixes
[PPS_OSIZE
] = P_O16
;
1061 enum prefixes pfx
= ins
->prefixes
[PPS_OSIZE
];
1065 errfunc(ERR_WARNING
| ERR_PASS2
, "invalid operand size prefix");
1067 ins
->prefixes
[PPS_OSIZE
] = P_O32
;
1109 if (!ins
->prefixes
[PPS_REP
])
1110 ins
->prefixes
[PPS_REP
] = P_REP
;
1114 if (!ins
->prefixes
[PPS_REP
])
1115 ins
->prefixes
[PPS_REP
] = P_REPNE
;
1119 if (ins
->oprs
[0].segment
!= NO_SEG
)
1120 errfunc(ERR_NONFATAL
, "attempt to reserve non-constant"
1121 " quantity of BSS space");
1123 length
+= ins
->oprs
[0].offset
;
1127 if (!ins
->prefixes
[PPS_WAIT
])
1128 ins
->prefixes
[PPS_WAIT
] = P_WAIT
;
1183 struct operand
*opy
= &ins
->oprs
[op2
];
1184 struct operand
*op_er_sae
;
1186 ea_data
.rex
= 0; /* Ensure ea.REX is initially 0 */
1189 /* pick rfield from operand b (opx) */
1190 rflags
= regflag(opx
);
1191 rfield
= nasm_regvals
[opx
->basereg
];
1197 /* EVEX.b1 : evex_brerop contains the operand position */
1198 op_er_sae
= (ins
->evex_brerop
>= 0 ?
1199 &ins
->oprs
[ins
->evex_brerop
] : NULL
);
1201 if (op_er_sae
&& (op_er_sae
->decoflags
& (ER
| SAE
))) {
1203 ins
->evex_p
[2] |= EVEX_P2B
;
1204 if (op_er_sae
->decoflags
& ER
) {
1205 /* set EVEX.RC (rounding control) */
1206 ins
->evex_p
[2] |= ((ins
->evex_rm
- BRC_RN
) << 5)
1210 /* set EVEX.L'L (vector length) */
1211 ins
->evex_p
[2] |= ((ins
->vex_wlp
<< (5 - 2)) & EVEX_P2LL
);
1212 ins
->evex_p
[1] |= ((ins
->vex_wlp
<< (7 - 4)) & EVEX_P1W
);
1213 if (opy
->decoflags
& BRDCAST_MASK
) {
1215 ins
->evex_p
[2] |= EVEX_P2B
;
1220 * if a separate form of MIB (ICC style) is used,
1221 * the index reg info is merged into mem operand
1223 if (mib_index
!= R_none
) {
1224 opy
->indexreg
= mib_index
;
1226 opy
->hintbase
= mib_index
;
1227 opy
->hinttype
= EAH_NOTBASE
;
1231 * only for mib operands, make a single reg index [reg*1].
1232 * gas uses this form to explicitly denote index register.
1234 if (itemp_has(temp
, IF_MIB
) &&
1235 (opy
->indexreg
== -1 && opy
->hintbase
== opy
->basereg
&&
1236 opy
->hinttype
== EAH_NOTBASE
)) {
1237 opy
->indexreg
= opy
->basereg
;
1242 if (process_ea(opy
, &ea_data
, bits
,
1243 rfield
, rflags
, ins
) != eat
) {
1244 errfunc(ERR_NONFATAL
, "invalid effective address");
1247 ins
->rex
|= ea_data
.rex
;
1248 length
+= ea_data
.size
;
1254 errfunc(ERR_PANIC
, "internal instruction table corrupt"
1255 ": instruction code \\%o (0x%02X) given", c
, c
);
1260 ins
->rex
&= rex_mask
;
1262 if (ins
->rex
& REX_NH
) {
1263 if (ins
->rex
& REX_H
) {
1264 errfunc(ERR_NONFATAL
, "instruction cannot use high registers");
1267 ins
->rex
&= ~REX_P
; /* Don't force REX prefix due to high reg */
1270 if (ins
->rex
& (REX_V
| REX_EV
)) {
1271 int bad32
= REX_R
|REX_W
|REX_X
|REX_B
;
1273 if (ins
->rex
& REX_H
) {
1274 errfunc(ERR_NONFATAL
, "cannot use high register in AVX instruction");
1277 switch (ins
->vex_wlp
& 060) {
1291 if (bits
!= 64 && ((ins
->rex
& bad32
) || ins
->vexreg
> 7)) {
1292 errfunc(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1294 } else if (!(ins
->rex
& REX_EV
) &&
1295 ((ins
->vexreg
> 15) || (ins
->evex_p
[0] & 0xf0))) {
1296 errfunc(ERR_NONFATAL
, "invalid high-16 register in non-AVX-512");
1299 if (ins
->rex
& REX_EV
)
1301 else if (ins
->vex_cm
!= 1 || (ins
->rex
& (REX_W
|REX_X
|REX_B
)))
1305 } else if (ins
->rex
& REX_REAL
) {
1306 if (ins
->rex
& REX_H
) {
1307 errfunc(ERR_NONFATAL
, "cannot use high register in rex instruction");
1309 } else if (bits
== 64) {
1311 } else if ((ins
->rex
& REX_L
) &&
1312 !(ins
->rex
& (REX_P
|REX_W
|REX_X
|REX_B
)) &&
1313 iflag_ffs(&cpu
) >= IF_X86_64
) {
1315 assert_no_prefix(ins
, PPS_LOCK
);
1316 lockcheck
= false; /* Already errored, no need for warning */
1319 errfunc(ERR_NONFATAL
, "invalid operands in non-64-bit mode");
1324 if (has_prefix(ins
, PPS_LOCK
, P_LOCK
) && lockcheck
&&
1325 (!itemp_has(temp
,IF_LOCK
) || !is_class(MEMORY
, ins
->oprs
[0].type
))) {
1326 errfunc(ERR_WARNING
| ERR_WARN_LOCK
| ERR_PASS2
,
1327 "instruction is not lockable");
1330 bad_hle_warn(ins
, hleok
);
1335 static inline unsigned int emit_rex(insn
*ins
, int32_t segment
, int64_t offset
, int bits
)
1338 if ((ins
->rex
& REX_REAL
) && !(ins
->rex
& (REX_V
| REX_EV
))) {
1339 ins
->rex
= (ins
->rex
& REX_REAL
) | REX_P
;
1340 out(offset
, segment
, &ins
->rex
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1349 static void gencode(int32_t segment
, int64_t offset
, int bits
,
1350 insn
* ins
, const struct itemplate
*temp
,
1358 struct operand
*opx
;
1359 const uint8_t *codes
= temp
->code
;
1361 enum ea_type eat
= EA_SCALAR
;
1365 op1
= (c
& 3) + ((opex
& 1) << 2);
1366 op2
= ((c
>> 3) & 3) + ((opex
& 2) << 1);
1367 opx
= &ins
->oprs
[op1
];
1368 opex
= 0; /* For the next iteration */
1375 offset
+= emit_rex(ins
, segment
, offset
, bits
);
1376 out(offset
, segment
, codes
, OUT_RAWDATA
, c
, NO_SEG
, NO_SEG
);
1388 offset
+= emit_rex(ins
, segment
, offset
, bits
);
1389 bytes
[0] = *codes
++ + (regval(opx
) & 7);
1390 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1398 if (opx
->offset
< -256 || opx
->offset
> 255) {
1399 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1400 "byte value exceeds bounds");
1402 out_imm8(offset
, segment
, opx
);
1407 if (opx
->offset
< 0 || opx
->offset
> 255)
1408 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1409 "unsigned byte value exceeds bounds");
1410 out_imm8(offset
, segment
, opx
);
1415 warn_overflow_opd(opx
, 2);
1417 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1418 opx
->segment
, opx
->wrt
);
1423 if (opx
->type
& (BITS16
| BITS32
))
1424 size
= (opx
->type
& BITS16
) ? 2 : 4;
1426 size
= (bits
== 16) ? 2 : 4;
1427 warn_overflow_opd(opx
, size
);
1429 out(offset
, segment
, &data
, OUT_ADDRESS
, size
,
1430 opx
->segment
, opx
->wrt
);
1435 warn_overflow_opd(opx
, 4);
1437 out(offset
, segment
, &data
, OUT_ADDRESS
, 4,
1438 opx
->segment
, opx
->wrt
);
1444 size
= ins
->addr_size
>> 3;
1445 warn_overflow_opd(opx
, size
);
1446 out(offset
, segment
, &data
, OUT_ADDRESS
, size
,
1447 opx
->segment
, opx
->wrt
);
1452 if (opx
->segment
!= segment
) {
1454 out(offset
, segment
, &data
,
1455 OUT_REL1ADR
, insn_end
- offset
,
1456 opx
->segment
, opx
->wrt
);
1458 data
= opx
->offset
- insn_end
;
1459 if (data
> 127 || data
< -128)
1460 errfunc(ERR_NONFATAL
, "short jump is out of range");
1461 out(offset
, segment
, &data
,
1462 OUT_ADDRESS
, 1, NO_SEG
, NO_SEG
);
1468 data
= (int64_t)opx
->offset
;
1469 out(offset
, segment
, &data
, OUT_ADDRESS
, 8,
1470 opx
->segment
, opx
->wrt
);
1475 if (opx
->segment
!= segment
) {
1477 out(offset
, segment
, &data
,
1478 OUT_REL2ADR
, insn_end
- offset
,
1479 opx
->segment
, opx
->wrt
);
1481 data
= opx
->offset
- insn_end
;
1482 out(offset
, segment
, &data
,
1483 OUT_ADDRESS
, 2, NO_SEG
, NO_SEG
);
1489 if (opx
->type
& (BITS16
| BITS32
| BITS64
))
1490 size
= (opx
->type
& BITS16
) ? 2 : 4;
1492 size
= (bits
== 16) ? 2 : 4;
1493 if (opx
->segment
!= segment
) {
1495 out(offset
, segment
, &data
,
1496 size
== 2 ? OUT_REL2ADR
: OUT_REL4ADR
,
1497 insn_end
- offset
, opx
->segment
, opx
->wrt
);
1499 data
= opx
->offset
- insn_end
;
1500 out(offset
, segment
, &data
,
1501 OUT_ADDRESS
, size
, NO_SEG
, NO_SEG
);
1507 if (opx
->segment
!= segment
) {
1509 out(offset
, segment
, &data
,
1510 OUT_REL4ADR
, insn_end
- offset
,
1511 opx
->segment
, opx
->wrt
);
1513 data
= opx
->offset
- insn_end
;
1514 out(offset
, segment
, &data
,
1515 OUT_ADDRESS
, 4, NO_SEG
, NO_SEG
);
1521 if (opx
->segment
== NO_SEG
)
1522 errfunc(ERR_NONFATAL
, "value referenced by FAR is not"
1525 out(offset
, segment
, &data
, OUT_ADDRESS
, 2,
1526 outfmt
->segbase(1 + opx
->segment
),
1533 opx
= &ins
->oprs
[c
>> 3];
1534 bytes
[0] = nasm_regvals
[opx
->basereg
] << 4;
1535 opx
= &ins
->oprs
[c
& 7];
1536 if (opx
->segment
!= NO_SEG
|| opx
->wrt
!= NO_SEG
) {
1537 errfunc(ERR_NONFATAL
,
1538 "non-absolute expression not permitted as argument %d",
1541 if (opx
->offset
& ~15) {
1542 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1543 "four-bit argument exceeds bounds");
1545 bytes
[0] |= opx
->offset
& 15;
1547 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1553 opx
= &ins
->oprs
[c
>> 4];
1554 bytes
[0] = nasm_regvals
[opx
->basereg
] << 4;
1556 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1561 bytes
[0] = nasm_regvals
[opx
->basereg
] << 4;
1562 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1568 if (opx
->wrt
== NO_SEG
&& opx
->segment
== NO_SEG
&&
1569 (int32_t)data
!= (int64_t)data
) {
1570 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1571 "signed dword immediate exceeds bounds");
1573 out(offset
, segment
, &data
, OUT_ADDRESS
, 4,
1574 opx
->segment
, opx
->wrt
);
1581 ins
->evex_p
[2] |= op_evexflags(&ins
->oprs
[0],
1582 EVEX_P2Z
| EVEX_P2AAA
, 2);
1583 ins
->evex_p
[2] ^= EVEX_P2VP
; /* 1's complement */
1585 /* EVEX.X can be set by either REX or EVEX for different reasons */
1586 bytes
[1] = ((((ins
->rex
& 7) << 5) |
1587 (ins
->evex_p
[0] & (EVEX_P0X
| EVEX_P0RP
))) ^ 0xf0) |
1589 bytes
[2] = ((ins
->rex
& REX_W
) << (7 - 3)) |
1590 ((~ins
->vexreg
& 15) << 3) |
1591 (1 << 2) | (ins
->vex_wlp
& 3);
1592 bytes
[3] = ins
->evex_p
[2];
1593 out(offset
, segment
, &bytes
, OUT_RAWDATA
, 4, NO_SEG
, NO_SEG
);
1600 if (ins
->vex_cm
!= 1 || (ins
->rex
& (REX_W
|REX_X
|REX_B
))) {
1601 bytes
[0] = (ins
->vex_cm
>> 6) ? 0x8f : 0xc4;
1602 bytes
[1] = (ins
->vex_cm
& 31) | ((~ins
->rex
& 7) << 5);
1603 bytes
[2] = ((ins
->rex
& REX_W
) << (7-3)) |
1604 ((~ins
->vexreg
& 15)<< 3) | (ins
->vex_wlp
& 07);
1605 out(offset
, segment
, &bytes
, OUT_RAWDATA
, 3, NO_SEG
, NO_SEG
);
1609 bytes
[1] = ((~ins
->rex
& REX_R
) << (7-2)) |
1610 ((~ins
->vexreg
& 15) << 3) | (ins
->vex_wlp
& 07);
1611 out(offset
, segment
, &bytes
, OUT_RAWDATA
, 2, NO_SEG
, NO_SEG
);
1626 if (ins
->rex
& REX_W
)
1628 else if (ins
->prefixes
[PPS_OSIZE
] == P_O16
)
1630 else if (ins
->prefixes
[PPS_OSIZE
] == P_O32
)
1635 um
= (uint64_t)2 << (s
-1);
1638 if (uv
> 127 && uv
< (uint64_t)-128 &&
1639 (uv
< um
-128 || uv
> um
-1)) {
1640 /* If this wasn't explicitly byte-sized, warn as though we
1641 * had fallen through to the imm16/32/64 case.
1643 errfunc(ERR_WARNING
| ERR_PASS2
| ERR_WARN_NOV
,
1644 "%s value exceeds bounds",
1645 (opx
->type
& BITS8
) ? "signed byte" :
1650 if (opx
->segment
!= NO_SEG
) {
1652 out(offset
, segment
, &data
, OUT_ADDRESS
, 1,
1653 opx
->segment
, opx
->wrt
);
1656 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
,
1667 if (bits
== 32 && !has_prefix(ins
, PPS_ASIZE
, P_A16
)) {
1669 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1676 if (bits
!= 32 && !has_prefix(ins
, PPS_ASIZE
, P_A32
)) {
1678 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1713 *bytes
= *codes
++ ^ get_cond_opcode(ins
->condition
);
1714 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1723 *bytes
= c
- 0332 + 0xF2;
1724 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1729 if (ins
->rex
& REX_R
) {
1731 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1734 ins
->rex
&= ~(REX_L
|REX_R
);
1745 if (ins
->oprs
[0].segment
!= NO_SEG
)
1746 errfunc(ERR_PANIC
, "non-constant BSS size in pass two");
1748 int64_t size
= ins
->oprs
[0].offset
;
1750 out(offset
, segment
, NULL
,
1751 OUT_RESERVE
, size
, NO_SEG
, NO_SEG
);
1764 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1774 *bytes
= c
- 0366 + 0x66;
1775 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1783 *bytes
= bits
== 16 ? 3 : 5;
1784 out(offset
, segment
, bytes
, OUT_RAWDATA
, 1, NO_SEG
, NO_SEG
);
1818 struct operand
*opy
= &ins
->oprs
[op2
];
1821 /* pick rfield from operand b (opx) */
1822 rflags
= regflag(opx
);
1823 rfield
= nasm_regvals
[opx
->basereg
];
1825 /* rfield is constant */
1830 if (process_ea(opy
, &ea_data
, bits
,
1831 rfield
, rflags
, ins
) != eat
)
1832 errfunc(ERR_NONFATAL
, "invalid effective address");
1835 *p
++ = ea_data
.modrm
;
1836 if (ea_data
.sib_present
)
1840 out(offset
, segment
, bytes
, OUT_RAWDATA
, s
, NO_SEG
, NO_SEG
);
1843 * Make sure the address gets the right offset in case
1844 * the line breaks in the .lst file (BR 1197827)
1849 switch (ea_data
.bytes
) {
1856 /* use compressed displacement, if available */
1857 data
= ea_data
.disp8
? ea_data
.disp8
: opy
->offset
;
1860 if (opy
->segment
== segment
) {
1862 if (overflow_signed(data
, ea_data
.bytes
))
1863 warn_overflow(ERR_PASS2
, ea_data
.bytes
);
1864 out(offset
, segment
, &data
, OUT_ADDRESS
,
1865 ea_data
.bytes
, NO_SEG
, NO_SEG
);
1867 /* overflow check in output/linker? */
1868 out(offset
, segment
, &data
, OUT_REL4ADR
,
1869 insn_end
- offset
, opy
->segment
, opy
->wrt
);
1872 if (overflow_general(data
, ins
->addr_size
>> 3) ||
1873 signed_bits(data
, ins
->addr_size
) !=
1874 signed_bits(data
, ea_data
.bytes
* 8))
1875 warn_overflow(ERR_PASS2
, ea_data
.bytes
);
1877 out(offset
, segment
, &data
, OUT_ADDRESS
,
1878 ea_data
.bytes
, opy
->segment
, opy
->wrt
);
1884 "Invalid amount of bytes (%d) for offset?!",
1893 errfunc(ERR_PANIC
, "internal instruction table corrupt"
1894 ": instruction code \\%o (0x%02X) given", c
, c
);
1900 static opflags_t
regflag(const operand
* o
)
1902 if (!is_register(o
->basereg
))
1903 errfunc(ERR_PANIC
, "invalid operand passed to regflag()");
1904 return nasm_reg_flags
[o
->basereg
];
1907 static int32_t regval(const operand
* o
)
1909 if (!is_register(o
->basereg
))
1910 errfunc(ERR_PANIC
, "invalid operand passed to regval()");
1911 return nasm_regvals
[o
->basereg
];
1914 static int op_rexflags(const operand
* o
, int mask
)
1919 if (!is_register(o
->basereg
))
1920 errfunc(ERR_PANIC
, "invalid operand passed to op_rexflags()");
1922 flags
= nasm_reg_flags
[o
->basereg
];
1923 val
= nasm_regvals
[o
->basereg
];
1925 return rexflags(val
, flags
, mask
);
1928 static int rexflags(int val
, opflags_t flags
, int mask
)
1932 if (val
>= 0 && (val
& 8))
1933 rex
|= REX_B
|REX_X
|REX_R
;
1936 if (!(REG_HIGH
& ~flags
)) /* AH, CH, DH, BH */
1938 else if (!(REG8
& ~flags
) && val
>= 4) /* SPL, BPL, SIL, DIL */
1944 static int evexflags(int val
, decoflags_t deco
,
1945 int mask
, uint8_t byte
)
1951 if (val
>= 0 && (val
& 16))
1952 evex
|= (EVEX_P0RP
| EVEX_P0X
);
1955 if (val
>= 0 && (val
& 16))
1959 if (deco
& OPMASK_MASK
)
1960 evex
|= deco
& EVEX_P2AAA
;
1966 static int op_evexflags(const operand
* o
, int mask
, uint8_t byte
)
1970 if (!is_register(o
->basereg
))
1971 errfunc(ERR_PANIC
, "invalid operand passed to op_evexflags()");
1973 val
= nasm_regvals
[o
->basereg
];
1975 return evexflags(val
, o
->decoflags
, mask
, byte
);
1978 static enum match_result
find_match(const struct itemplate
**tempp
,
1980 int32_t segment
, int64_t offset
, int bits
)
1982 const struct itemplate
*temp
;
1983 enum match_result m
, merr
;
1984 opflags_t xsizeflags
[MAX_OPERANDS
];
1985 bool opsizemissing
= false;
1986 int8_t broadcast
= instruction
->evex_brerop
;
1989 /* broadcasting uses a different data element size */
1990 for (i
= 0; i
< instruction
->operands
; i
++)
1992 xsizeflags
[i
] = instruction
->oprs
[i
].decoflags
& BRSIZE_MASK
;
1994 xsizeflags
[i
] = instruction
->oprs
[i
].type
& SIZE_MASK
;
1996 merr
= MERR_INVALOP
;
1998 for (temp
= nasm_instructions
[instruction
->opcode
];
1999 temp
->opcode
!= I_none
; temp
++) {
2000 m
= matches(temp
, instruction
, bits
);
2001 if (m
== MOK_JUMP
) {
2002 if (jmp_match(segment
, offset
, bits
, instruction
, temp
))
2006 } else if (m
== MERR_OPSIZEMISSING
&& !itemp_has(temp
, IF_SX
)) {
2008 * Missing operand size and a candidate for fuzzy matching...
2010 for (i
= 0; i
< temp
->operands
; i
++)
2012 xsizeflags
[i
] |= temp
->deco
[i
] & BRSIZE_MASK
;
2014 xsizeflags
[i
] |= temp
->opd
[i
] & SIZE_MASK
;
2015 opsizemissing
= true;
2019 if (merr
== MOK_GOOD
)
2023 /* No match, but see if we can get a fuzzy operand size match... */
2027 for (i
= 0; i
< instruction
->operands
; i
++) {
2029 * We ignore extrinsic operand sizes on registers, so we should
2030 * never try to fuzzy-match on them. This also resolves the case
2031 * when we have e.g. "xmmrm128" in two different positions.
2033 if (is_class(REGISTER
, instruction
->oprs
[i
].type
))
2036 /* This tests if xsizeflags[i] has more than one bit set */
2037 if ((xsizeflags
[i
] & (xsizeflags
[i
]-1)))
2038 goto done
; /* No luck */
2040 if (i
== broadcast
) {
2041 instruction
->oprs
[i
].decoflags
|= xsizeflags
[i
];
2042 instruction
->oprs
[i
].type
|= (xsizeflags
[i
] == BR_BITS32
?
2045 instruction
->oprs
[i
].type
|= xsizeflags
[i
]; /* Set the size */
2049 /* Try matching again... */
2050 for (temp
= nasm_instructions
[instruction
->opcode
];
2051 temp
->opcode
!= I_none
; temp
++) {
2052 m
= matches(temp
, instruction
, bits
);
2053 if (m
== MOK_JUMP
) {
2054 if (jmp_match(segment
, offset
, bits
, instruction
, temp
))
2061 if (merr
== MOK_GOOD
)
2070 static enum match_result
matches(const struct itemplate
*itemp
,
2071 insn
*instruction
, int bits
)
2073 opflags_t size
[MAX_OPERANDS
], asize
;
2074 bool opsizemissing
= false;
2080 if (itemp
->opcode
!= instruction
->opcode
)
2081 return MERR_INVALOP
;
2084 * Count the operands
2086 if (itemp
->operands
!= instruction
->operands
)
2087 return MERR_INVALOP
;
2092 if (!(optimizing
> 0) && itemp_has(itemp
, IF_OPT
))
2093 return MERR_INVALOP
;
2096 * Check that no spurious colons or TOs are present
2098 for (i
= 0; i
< itemp
->operands
; i
++)
2099 if (instruction
->oprs
[i
].type
& ~itemp
->opd
[i
] & (COLON
| TO
))
2100 return MERR_INVALOP
;
2103 * Process size flags
2105 switch (itemp_smask(itemp
)) {
2106 case IF_GENBIT(IF_SB
):
2109 case IF_GENBIT(IF_SW
):
2112 case IF_GENBIT(IF_SD
):
2115 case IF_GENBIT(IF_SQ
):
2118 case IF_GENBIT(IF_SO
):
2121 case IF_GENBIT(IF_SY
):
2124 case IF_GENBIT(IF_SZ
):
2127 case IF_GENBIT(IF_SIZE
):
2148 if (itemp_armask(itemp
)) {
2149 /* S- flags only apply to a specific operand */
2150 i
= itemp_arg(itemp
);
2151 memset(size
, 0, sizeof size
);
2154 /* S- flags apply to all operands */
2155 for (i
= 0; i
< MAX_OPERANDS
; i
++)
2160 * Check that the operand flags all match up,
2161 * it's a bit tricky so lets be verbose:
2163 * 1) Find out the size of operand. If instruction
2164 * doesn't have one specified -- we're trying to
2165 * guess it either from template (IF_S* flag) or
2168 * 2) If template operand do not match the instruction OR
2169 * template has an operand size specified AND this size differ
2170 * from which instruction has (perhaps we got it from code bits)
2172 * a) Check that only size of instruction and operand is differ
2173 * other characteristics do match
2174 * b) Perhaps it's a register specified in instruction so
2175 * for such a case we just mark that operand as "size
2176 * missing" and this will turn on fuzzy operand size
2177 * logic facility (handled by a caller)
2179 for (i
= 0; i
< itemp
->operands
; i
++) {
2180 opflags_t type
= instruction
->oprs
[i
].type
;
2181 decoflags_t deco
= instruction
->oprs
[i
].decoflags
;
2182 bool is_broadcast
= deco
& BRDCAST_MASK
;
2183 uint8_t brcast_num
= 0;
2184 opflags_t template_opsize
, insn_opsize
;
2186 if (!(type
& SIZE_MASK
))
2189 insn_opsize
= type
& SIZE_MASK
;
2190 if (!is_broadcast
) {
2191 template_opsize
= itemp
->opd
[i
] & SIZE_MASK
;
2193 decoflags_t deco_brsize
= itemp
->deco
[i
] & BRSIZE_MASK
;
2195 * when broadcasting, the element size depends on
2196 * the instruction type. decorator flag should match.
2200 template_opsize
= (deco_brsize
== BR_BITS32
? BITS32
: BITS64
);
2201 /* calculate the proper number : {1to<brcast_num>} */
2202 brcast_num
= (itemp
->opd
[i
] & SIZE_MASK
) / BITS128
*
2203 BITS64
/ template_opsize
* 2;
2205 template_opsize
= 0;
2209 if ((itemp
->opd
[i
] & ~type
& ~SIZE_MASK
) ||
2210 (deco
& ~itemp
->deco
[i
] & ~BRNUM_MASK
)) {
2211 return MERR_INVALOP
;
2212 } else if (template_opsize
) {
2213 if (template_opsize
!= insn_opsize
) {
2215 return MERR_INVALOP
;
2216 } else if (!is_class(REGISTER
, type
)) {
2218 * Note: we don't honor extrinsic operand sizes for registers,
2219 * so "missing operand size" for a register should be
2220 * considered a wildcard match rather than an error.
2222 opsizemissing
= true;
2224 } else if (is_broadcast
&&
2226 (8U << ((deco
& BRNUM_MASK
) >> BRNUM_SHIFT
)))) {
2228 * broadcasting opsize matches but the number of repeated memory
2229 * element does not match.
2230 * if 64b double precision float is broadcasted to zmm (512b),
2231 * broadcasting decorator must be {1to8}.
2233 return MERR_BRNUMMISMATCH
;
2235 } else if (is_register(instruction
->oprs
[i
].basereg
) &&
2236 nasm_regvals
[instruction
->oprs
[i
].basereg
] >= 16 &&
2237 !itemp_has(itemp
, IF_AVX512
)) {
2238 return MERR_ENCMISMATCH
;
2239 } else if (instruction
->prefixes
[PPS_EVEX
] &&
2240 !itemp_has(itemp
, IF_AVX512
)) {
2241 return MERR_ENCMISMATCH
;
2246 return MERR_OPSIZEMISSING
;
2249 * Check operand sizes
2251 if (itemp_has(itemp
, IF_SM
) || itemp_has(itemp
, IF_SM2
)) {
2252 oprs
= (itemp_has(itemp
, IF_SM2
) ? 2 : itemp
->operands
);
2253 for (i
= 0; i
< oprs
; i
++) {
2254 asize
= itemp
->opd
[i
] & SIZE_MASK
;
2256 for (i
= 0; i
< oprs
; i
++)
2262 oprs
= itemp
->operands
;
2265 for (i
= 0; i
< itemp
->operands
; i
++) {
2266 if (!(itemp
->opd
[i
] & SIZE_MASK
) &&
2267 (instruction
->oprs
[i
].type
& SIZE_MASK
& ~size
[i
]))
2268 return MERR_OPSIZEMISMATCH
;
2272 * Check template is okay at the set cpu level
2274 if (iflag_cmp_cpu_level(&insns_flags
[itemp
->iflag_idx
], &cpu
) > 0)
2278 * Verify the appropriate long mode flag.
2280 if (itemp_has(itemp
, (bits
== 64 ? IF_NOLONG
: IF_LONG
)))
2281 return MERR_BADMODE
;
2284 * If we have a HLE prefix, look for the NOHLE flag
2286 if (itemp_has(itemp
, IF_NOHLE
) &&
2287 (has_prefix(instruction
, PPS_REP
, P_XACQUIRE
) ||
2288 has_prefix(instruction
, PPS_REP
, P_XRELEASE
)))
2292 * Check if special handling needed for Jumps
2294 if ((itemp
->code
[0] & ~1) == 0370)
2298 * Check if BND prefix is allowed
2300 if (!itemp_has(itemp
, IF_BND
) &&
2301 has_prefix(instruction
, PPS_REP
, P_BND
))
2308 * Check if ModR/M.mod should/can be 01.
2309 * - EAF_BYTEOFFS is set
2310 * - offset can fit in a byte when EVEX is not used
2311 * - offset can be compressed when EVEX is used
2313 #define IS_MOD_01() (input->eaflags & EAF_BYTEOFFS || \
2314 (o >= -128 && o <= 127 && \
2315 seg == NO_SEG && !forw_ref && \
2316 !(input->eaflags & EAF_WORDOFFS) && \
2317 !(ins->rex & REX_EV)) || \
2318 (ins->rex & REX_EV && \
2319 is_disp8n(input, ins, &output->disp8)))
2321 static enum ea_type
process_ea(operand
*input
, ea
*output
, int bits
,
2322 int rfield
, opflags_t rflags
, insn
*ins
)
2324 bool forw_ref
= !!(input
->opflags
& OPFLAG_UNKNOWN
);
2325 int addrbits
= ins
->addr_size
;
2327 output
->type
= EA_SCALAR
;
2328 output
->rip
= false;
2331 /* REX flags for the rfield operand */
2332 output
->rex
|= rexflags(rfield
, rflags
, REX_R
| REX_P
| REX_W
| REX_H
);
2333 /* EVEX.R' flag for the REG operand */
2334 ins
->evex_p
[0] |= evexflags(rfield
, 0, EVEX_P0RP
, 0);
2336 if (is_class(REGISTER
, input
->type
)) {
2338 * It's a direct register.
2340 if (!is_register(input
->basereg
))
2343 if (!is_reg_class(REG_EA
, input
->basereg
))
2346 /* broadcasting is not available with a direct register operand. */
2347 if (input
->decoflags
& BRDCAST_MASK
) {
2348 nasm_error(ERR_NONFATAL
, "Broadcasting not allowed from a register");
2352 output
->rex
|= op_rexflags(input
, REX_B
| REX_P
| REX_W
| REX_H
);
2353 ins
->evex_p
[0] |= op_evexflags(input
, EVEX_P0X
, 0);
2354 output
->sib_present
= false; /* no SIB necessary */
2355 output
->bytes
= 0; /* no offset necessary either */
2356 output
->modrm
= GEN_MODRM(3, rfield
, nasm_regvals
[input
->basereg
]);
2359 * It's a memory reference.
2362 /* Embedded rounding or SAE is not available with a mem ref operand. */
2363 if (input
->decoflags
& (ER
| SAE
)) {
2364 nasm_error(ERR_NONFATAL
,
2365 "Embedded rounding is available only with reg-reg op.");
2369 if (input
->basereg
== -1 &&
2370 (input
->indexreg
== -1 || input
->scale
== 0)) {
2372 * It's a pure offset.
2374 if (bits
== 64 && ((input
->type
& IP_REL
) == IP_REL
) &&
2375 input
->segment
== NO_SEG
) {
2376 nasm_error(ERR_WARNING
| ERR_PASS1
, "absolute address can not be RIP-relative");
2377 input
->type
&= ~IP_REL
;
2378 input
->type
|= MEMORY
;
2381 if (input
->eaflags
& EAF_BYTEOFFS
||
2382 (input
->eaflags
& EAF_WORDOFFS
&&
2383 input
->disp_size
!= (addrbits
!= 16 ? 32 : 16))) {
2384 nasm_error(ERR_WARNING
| ERR_PASS1
, "displacement size ignored on absolute address");
2387 if (bits
== 64 && (~input
->type
& IP_REL
)) {
2388 output
->sib_present
= true;
2389 output
->sib
= GEN_SIB(0, 4, 5);
2391 output
->modrm
= GEN_MODRM(0, rfield
, 4);
2392 output
->rip
= false;
2394 output
->sib_present
= false;
2395 output
->bytes
= (addrbits
!= 16 ? 4 : 2);
2396 output
->modrm
= GEN_MODRM(0, rfield
, (addrbits
!= 16 ? 5 : 6));
2397 output
->rip
= bits
== 64;
2401 * It's an indirection.
2403 int i
= input
->indexreg
, b
= input
->basereg
, s
= input
->scale
;
2404 int32_t seg
= input
->segment
;
2405 int hb
= input
->hintbase
, ht
= input
->hinttype
;
2406 int t
, it
, bt
; /* register numbers */
2407 opflags_t x
, ix
, bx
; /* register flags */
2410 i
= -1; /* make this easy, at least */
2412 if (is_register(i
)) {
2413 it
= nasm_regvals
[i
];
2414 ix
= nasm_reg_flags
[i
];
2420 if (is_register(b
)) {
2421 bt
= nasm_regvals
[b
];
2422 bx
= nasm_reg_flags
[b
];
2428 /* if either one are a vector register... */
2429 if ((ix
|bx
) & (XMMREG
|YMMREG
|ZMMREG
) & ~REG_EA
) {
2430 opflags_t sok
= BITS32
| BITS64
;
2431 int32_t o
= input
->offset
;
2432 int mod
, scale
, index
, base
;
2435 * For a vector SIB, one has to be a vector and the other,
2436 * if present, a GPR. The vector must be the index operand.
2438 if (it
== -1 || (bx
& (XMMREG
|YMMREG
|ZMMREG
) & ~REG_EA
)) {
2444 t
= bt
, bt
= it
, it
= t
;
2445 x
= bx
, bx
= ix
, ix
= x
;
2451 if (!(REG64
& ~bx
) || !(REG32
& ~bx
))
2458 * While we're here, ensure the user didn't specify
2461 if (input
->disp_size
== 16 || input
->disp_size
== 64)
2464 if (addrbits
== 16 ||
2465 (addrbits
== 32 && !(sok
& BITS32
)) ||
2466 (addrbits
== 64 && !(sok
& BITS64
)))
2469 output
->type
= ((ix
& ZMMREG
& ~REG_EA
) ? EA_ZMMVSIB
2470 : ((ix
& YMMREG
& ~REG_EA
)
2471 ? EA_YMMVSIB
: EA_XMMVSIB
));
2473 output
->rex
|= rexflags(it
, ix
, REX_X
);
2474 output
->rex
|= rexflags(bt
, bx
, REX_B
);
2475 ins
->evex_p
[2] |= evexflags(it
, 0, EVEX_P2VP
, 2);
2477 index
= it
& 7; /* it is known to be != -1 */
2492 default: /* then what the smeg is it? */
2493 goto err
; /* panic */
2501 if (base
!= REG_NUM_EBP
&& o
== 0 &&
2502 seg
== NO_SEG
&& !forw_ref
&&
2503 !(input
->eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2505 else if (IS_MOD_01())
2511 output
->sib_present
= true;
2512 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2513 output
->modrm
= GEN_MODRM(mod
, rfield
, 4);
2514 output
->sib
= GEN_SIB(scale
, index
, base
);
2515 } else if ((ix
|bx
) & (BITS32
|BITS64
)) {
2517 * it must be a 32/64-bit memory reference. Firstly we have
2518 * to check that all registers involved are type E/Rxx.
2520 opflags_t sok
= BITS32
| BITS64
;
2521 int32_t o
= input
->offset
;
2524 if (!(REG64
& ~ix
) || !(REG32
& ~ix
))
2532 goto err
; /* Invalid register */
2533 if (~sok
& bx
& SIZE_MASK
)
2534 goto err
; /* Invalid size */
2539 * While we're here, ensure the user didn't specify
2542 if (input
->disp_size
== 16 || input
->disp_size
== 64)
2545 if (addrbits
== 16 ||
2546 (addrbits
== 32 && !(sok
& BITS32
)) ||
2547 (addrbits
== 64 && !(sok
& BITS64
)))
2550 /* now reorganize base/index */
2551 if (s
== 1 && bt
!= it
&& bt
!= -1 && it
!= -1 &&
2552 ((hb
== b
&& ht
== EAH_NOTBASE
) ||
2553 (hb
== i
&& ht
== EAH_MAKEBASE
))) {
2554 /* swap if hints say so */
2555 t
= bt
, bt
= it
, it
= t
;
2556 x
= bx
, bx
= ix
, ix
= x
;
2558 if (bt
== it
) /* convert EAX+2*EAX to 3*EAX */
2559 bt
= -1, bx
= 0, s
++;
2560 if (bt
== -1 && s
== 1 && !(hb
== i
&& ht
== EAH_NOTBASE
)) {
2561 /* make single reg base, unless hint */
2562 bt
= it
, bx
= ix
, it
= -1, ix
= 0;
2564 if (((s
== 2 && it
!= REG_NUM_ESP
&& !(input
->eaflags
& EAF_TIMESTWO
)) ||
2565 s
== 3 || s
== 5 || s
== 9) && bt
== -1)
2566 bt
= it
, bx
= ix
, s
--; /* convert 3*EAX to EAX+2*EAX */
2567 if (it
== -1 && (bt
& 7) != REG_NUM_ESP
&&
2568 (input
->eaflags
& EAF_TIMESTWO
))
2569 it
= bt
, ix
= bx
, bt
= -1, bx
= 0, s
= 1;
2570 /* convert [NOSPLIT EAX] to sib format with 0x0 displacement */
2571 if (s
== 1 && it
== REG_NUM_ESP
) {
2572 /* swap ESP into base if scale is 1 */
2573 t
= it
, it
= bt
, bt
= t
;
2574 x
= ix
, ix
= bx
, bx
= x
;
2576 if (it
== REG_NUM_ESP
||
2577 (s
!= 1 && s
!= 2 && s
!= 4 && s
!= 8 && it
!= -1))
2578 goto err
; /* wrong, for various reasons */
2580 output
->rex
|= rexflags(it
, ix
, REX_X
);
2581 output
->rex
|= rexflags(bt
, bx
, REX_B
);
2583 if (it
== -1 && (bt
& 7) != REG_NUM_ESP
) {
2592 if (rm
!= REG_NUM_EBP
&& o
== 0 &&
2593 seg
== NO_SEG
&& !forw_ref
&&
2594 !(input
->eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2596 else if (IS_MOD_01())
2602 output
->sib_present
= false;
2603 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2604 output
->modrm
= GEN_MODRM(mod
, rfield
, rm
);
2607 int mod
, scale
, index
, base
;
2627 default: /* then what the smeg is it? */
2628 goto err
; /* panic */
2636 if (base
!= REG_NUM_EBP
&& o
== 0 &&
2637 seg
== NO_SEG
&& !forw_ref
&&
2638 !(input
->eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2640 else if (IS_MOD_01())
2646 output
->sib_present
= true;
2647 output
->bytes
= (bt
== -1 || mod
== 2 ? 4 : mod
);
2648 output
->modrm
= GEN_MODRM(mod
, rfield
, 4);
2649 output
->sib
= GEN_SIB(scale
, index
, base
);
2651 } else { /* it's 16-bit */
2653 int16_t o
= input
->offset
;
2655 /* check for 64-bit long mode */
2659 /* check all registers are BX, BP, SI or DI */
2660 if ((b
!= -1 && b
!= R_BP
&& b
!= R_BX
&& b
!= R_SI
&& b
!= R_DI
) ||
2661 (i
!= -1 && i
!= R_BP
&& i
!= R_BX
&& i
!= R_SI
&& i
!= R_DI
))
2664 /* ensure the user didn't specify DWORD/QWORD */
2665 if (input
->disp_size
== 32 || input
->disp_size
== 64)
2668 if (s
!= 1 && i
!= -1)
2669 goto err
; /* no can do, in 16-bit EA */
2670 if (b
== -1 && i
!= -1) {
2675 if ((b
== R_SI
|| b
== R_DI
) && i
!= -1) {
2680 /* have BX/BP as base, SI/DI index */
2682 goto err
; /* shouldn't ever happen, in theory */
2683 if (i
!= -1 && b
!= -1 &&
2684 (i
== R_BP
|| i
== R_BX
|| b
== R_SI
|| b
== R_DI
))
2685 goto err
; /* invalid combinations */
2686 if (b
== -1) /* pure offset: handled above */
2687 goto err
; /* so if it gets to here, panic! */
2691 switch (i
* 256 + b
) {
2692 case R_SI
* 256 + R_BX
:
2695 case R_DI
* 256 + R_BX
:
2698 case R_SI
* 256 + R_BP
:
2701 case R_DI
* 256 + R_BP
:
2719 if (rm
== -1) /* can't happen, in theory */
2720 goto err
; /* so panic if it does */
2722 if (o
== 0 && seg
== NO_SEG
&& !forw_ref
&& rm
!= 6 &&
2723 !(input
->eaflags
& (EAF_BYTEOFFS
| EAF_WORDOFFS
)))
2725 else if (IS_MOD_01())
2730 output
->sib_present
= false; /* no SIB - it's 16-bit */
2731 output
->bytes
= mod
; /* bytes of offset needed */
2732 output
->modrm
= GEN_MODRM(mod
, rfield
, rm
);
2737 output
->size
= 1 + output
->sib_present
+ output
->bytes
;
2738 return output
->type
;
2741 return output
->type
= EA_INVALID
;
2744 static void add_asp(insn
*ins
, int addrbits
)
2749 valid
= (addrbits
== 64) ? 64|32 : 32|16;
2751 switch (ins
->prefixes
[PPS_ASIZE
]) {
2762 valid
&= (addrbits
== 32) ? 16 : 32;
2768 for (j
= 0; j
< ins
->operands
; j
++) {
2769 if (is_class(MEMORY
, ins
->oprs
[j
].type
)) {
2772 /* Verify as Register */
2773 if (!is_register(ins
->oprs
[j
].indexreg
))
2776 i
= nasm_reg_flags
[ins
->oprs
[j
].indexreg
];
2778 /* Verify as Register */
2779 if (!is_register(ins
->oprs
[j
].basereg
))
2782 b
= nasm_reg_flags
[ins
->oprs
[j
].basereg
];
2784 if (ins
->oprs
[j
].scale
== 0)
2788 int ds
= ins
->oprs
[j
].disp_size
;
2789 if ((addrbits
!= 64 && ds
> 8) ||
2790 (addrbits
== 64 && ds
== 16))
2810 if (valid
& addrbits
) {
2811 ins
->addr_size
= addrbits
;
2812 } else if (valid
& ((addrbits
== 32) ? 16 : 32)) {
2813 /* Add an address size prefix */
2814 ins
->prefixes
[PPS_ASIZE
] = (addrbits
== 32) ? P_A16
: P_A32
;;
2815 ins
->addr_size
= (addrbits
== 32) ? 16 : 32;
2818 errfunc(ERR_NONFATAL
, "impossible combination of address sizes");
2819 ins
->addr_size
= addrbits
; /* Error recovery */
2822 defdisp
= ins
->addr_size
== 16 ? 16 : 32;
2824 for (j
= 0; j
< ins
->operands
; j
++) {
2825 if (!(MEM_OFFS
& ~ins
->oprs
[j
].type
) &&
2826 (ins
->oprs
[j
].disp_size
? ins
->oprs
[j
].disp_size
: defdisp
) != ins
->addr_size
) {
2828 * mem_offs sizes must match the address size; if not,
2829 * strip the MEM_OFFS bit and match only EA instructions
2831 ins
->oprs
[j
].type
&= ~(MEM_OFFS
& ~MEMORY
);