disasm.c

   1 /* disasm.c   where all the _work_ gets done in the Netwide Disassembler
   2  *
   3  * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
   4  * Julian Hall. All rights reserved. The software is
   5  * redistributable under the licence given in the file "Licence"
   6  * distributed in the NASM archive.
   7  *
   8  * initial version 27/iii/95 by Simon Tatham
   9  */
  10
  11 #include <stdio.h>
  12 #include <string.h>
  13
  14 #include "nasm.h"
  15 #include "disasm.h"
  16 #include "sync.h"
  17 #include "insns.h"
  18
  19 #include "names.c"
  20
  21 extern struct itemplate **itable[];
  22
  23 /*
  24  * Flags that go into the `segment' field of `insn' structures
  25  * during disassembly.
  26  */
  27 #define SEG_RELATIVE 1
  28 #define SEG_32BIT 2
  29 #define SEG_RMREG 4
  30 #define SEG_DISP8 8
  31 #define SEG_DISP16 16
  32 #define SEG_DISP32 32
  33 #define SEG_NODISP 64
  34 #define SEG_SIGNED 128
  35
  36 static int whichreg(long regflags, int regval)
  37 {
  38     static int reg32[] = {
  39         R_EAX, R_ECX, R_EDX, R_EBX, R_ESP, R_EBP, R_ESI, R_EDI };
  40     static int reg16[] = {
  41         R_AX, R_CX, R_DX, R_BX, R_SP, R_BP, R_SI, R_DI };
  42     static int reg8[] = {
  43         R_AL, R_CL, R_DL, R_BL, R_AH, R_CH, R_DH, R_BH };
  44     static int sreg[] = {
  45         R_ES, R_CS, R_SS, R_DS, R_FS, R_GS, 0, 0 };
  46     static int creg[] = {
  47         R_CR0, 0, R_CR2, R_CR3, R_CR4, 0, 0, 0 };
  48     static int dreg[] = {
  49         R_DR0, R_DR1, R_DR2, R_DR3, 0, 0, R_DR6, R_DR7 };
  50     static int treg[] = {
  51         0, 0, 0, R_TR3, R_TR4, R_TR5, R_TR6, R_TR7 };
  52     static int fpureg[] = {
  53         R_ST0, R_ST1, R_ST2, R_ST3, R_ST4, R_ST5, R_ST6, R_ST7 };
  54     static int mmxreg[] = {
  55         R_MM0, R_MM1, R_MM2, R_MM3, R_MM4, R_MM5, R_MM6, R_MM7 };
  56
  57     if (!(REG_AL & ~regflags))
  58         return R_AL;
  59     if (!(REG_AX & ~regflags))
  60         return R_AX;
  61     if (!(REG_EAX & ~regflags))
  62         return R_EAX;
  63     if (!(REG_DX & ~regflags))
  64         return R_DX;
  65     if (!(REG_CL & ~regflags))
  66         return R_CL;
  67     if (!(REG_CX & ~regflags))
  68         return R_CX;
  69     if (!(REG_ECX & ~regflags))
  70         return R_ECX;
  71     if (!(REG_CR4 & ~regflags))
  72         return R_CR4;
  73     if (!(FPU0 & ~regflags))
  74         return R_ST0;
  75     if (!(REG_CS & ~regflags))
  76         return R_CS;
  77     if (!(REG_DESS & ~regflags))
  78         return (regval == 0 || regval == 2 || regval == 3 ? sreg[regval] : 0);
  79     if (!(REG_FSGS & ~regflags))
  80         return (regval == 4 || regval == 5 ? sreg[regval] : 0);
  81     if (!((REGMEM|BITS8) & ~regflags))
  82         return reg8[regval];
  83     if (!((REGMEM|BITS16) & ~regflags))
  84         return reg16[regval];
  85     if (!((REGMEM|BITS32) & ~regflags))
  86         return reg32[regval];
  87     if (!(REG_SREG & ~regflags))
  88         return sreg[regval];
  89     if (!(REG_CREG & ~regflags))
  90         return creg[regval];
  91     if (!(REG_DREG & ~regflags))
  92         return dreg[regval];
  93     if (!(REG_TREG & ~regflags))
  94         return treg[regval];
  95     if (!(FPUREG & ~regflags))
  96         return fpureg[regval];
  97     if (!(MMXREG & ~regflags))
  98         return mmxreg[regval];
  99     return 0;
 100 }
 101
 102 static char *whichcond(int condval)
 103 {
 104     static int conds[] = {
 105         C_O, C_NO, C_C, C_NC, C_Z, C_NZ, C_NA, C_A,
 106         C_S, C_NS, C_PE, C_PO, C_L, C_NL, C_NG, C_G
 107     };
 108     return conditions[conds[condval]];
 109 }
 110
 111 /*
 112  * Process an effective address (ModRM) specification.
 113  */
 114 static unsigned char *do_ea (unsigned char *data, int modrm, int asize,
 115                              int segsize, operand *op)
 116 {
 117     int mod, rm, scale, index, base;
 118
 119     mod = (modrm >> 6) & 03;
 120     rm = modrm & 07;
 121
 122     if (mod == 3) {                    /* pure register version */
 123         op->basereg = rm;
 124         op->segment |= SEG_RMREG;
 125         return data;
 126     }
 127
 128     op->addr_size = 0;
 129
 130     if (asize == 16) {
 131         /*
 132          * <mod> specifies the displacement size (none, byte or
 133          * word), and <rm> specifies the register combination.
 134          * Exception: mod=0,rm=6 does not specify [BP] as one might
 135          * expect, but instead specifies [disp16].
 136          */
 137         op->indexreg = op->basereg = -1;
 138         op->scale = 1;                 /* always, in 16 bits */
 139         switch (rm) {
 140           case 0: op->basereg = R_BX; op->indexreg = R_SI; break;
 141           case 1: op->basereg = R_BX; op->indexreg = R_DI; break;
 142           case 2: op->basereg = R_BP; op->indexreg = R_SI; break;
 143           case 3: op->basereg = R_BP; op->indexreg = R_DI; break;
 144           case 4: op->basereg = R_SI; break;
 145           case 5: op->basereg = R_DI; break;
 146           case 6: op->basereg = R_BP; break;
 147           case 7: op->basereg = R_BX; break;
 148         }
 149         if (rm == 6 && mod == 0) {     /* special case */
 150             op->basereg = -1;
 151             if (segsize != 16)
 152                 op->addr_size = 16;
 153             mod = 2;                   /* fake disp16 */
 154         }
 155         switch (mod) {
 156           case 0:
 157             op->segment |= SEG_NODISP;
 158             break;
 159           case 1:
 160             op->segment |= SEG_DISP8;
 161             op->offset = (signed char) *data++;
 162             break;
 163           case 2:
 164             op->segment |= SEG_DISP16;
 165             op->offset = *data++;
 166             op->offset |= (*data++) << 8;
 167             break;
 168         }
 169         return data;
 170     } else {
 171         /*
 172          * Once again, <mod> specifies displacement size (this time
 173          * none, byte or *dword*), while <rm> specifies the base
 174          * register. Again, [EBP] is missing, replaced by a pure
 175          * disp32 (this time that's mod=0,rm=*5*). However, rm=4
 176          * indicates not a single base register, but instead the
 177          * presence of a SIB byte...
 178          */
 179         op->indexreg = -1;
 180         switch (rm) {
 181           case 0: op->basereg = R_EAX; break;
 182           case 1: op->basereg = R_ECX; break;
 183           case 2: op->basereg = R_EDX; break;
 184           case 3: op->basereg = R_EBX; break;
 185           case 5: op->basereg = R_EBP; break;
 186           case 6: op->basereg = R_ESI; break;
 187           case 7: op->basereg = R_EDI; break;
 188         }
 189         if (rm == 5 && mod == 0) {
 190             op->basereg = -1;
 191             if (segsize != 32)
 192                 op->addr_size = 32;
 193             mod = 2;                   /* fake disp32 */
 194         }
 195         if (rm == 4) {                 /* process SIB */
 196             scale = (*data >> 6) & 03;
 197             index = (*data >> 3) & 07;
 198             base = *data & 07;
 199             data++;
 200
 201             op->scale = 1 << scale;
 202             switch (index) {
 203               case 0: op->indexreg = R_EAX; break;
 204               case 1: op->indexreg = R_ECX; break;
 205               case 2: op->indexreg = R_EDX; break;
 206               case 3: op->indexreg = R_EBX; break;
 207               case 4: op->indexreg = -1; break;
 208               case 5: op->indexreg = R_EBP; break;
 209               case 6: op->indexreg = R_ESI; break;
 210               case 7: op->indexreg = R_EDI; break;
 211             }
 212
 213             switch (base) {
 214               case 0: op->basereg = R_EAX; break;
 215               case 1: op->basereg = R_ECX; break;
 216               case 2: op->basereg = R_EDX; break;
 217               case 3: op->basereg = R_EBX; break;
 218               case 4: op->basereg = R_ESP; break;
 219               case 6: op->basereg = R_ESI; break;
 220               case 7: op->basereg = R_EDI; break;
 221               case 5:
 222                 if (mod == 0) {
 223                     mod = 2;
 224                     op->basereg = -1;
 225                 } else
 226                     op->basereg = R_EBP;
 227                 break;
 228             }
 229         }
 230         switch (mod) {
 231           case 0:
 232             op->segment |= SEG_NODISP;
 233             break;
 234           case 1:
 235             op->segment |= SEG_DISP8;
 236             op->offset = (signed char) *data++;
 237             break;
 238           case 2:
 239             op->segment |= SEG_DISP32;
 240             op->offset = *data++;
 241             op->offset |= (*data++) << 8;
 242             op->offset |= ((long) *data++) << 16;
 243             op->offset |= ((long) *data++) << 24;
 244             break;
 245         }
 246         return data;
 247     }
 248 }
 249
 250 /*
 251  * Determine whether the code string in r corresponds to the data
 252  * stream in data. Return the number of bytes matched if so.
 253  */
 254 static int matches (unsigned char *r, unsigned char *data, int asize,
 255                     int osize, int segsize, insn *ins)
 256 {
 257     unsigned char * origdata = data;
 258     int           a_used = FALSE, o_used = FALSE;
 259
 260     while (*r)
 261     {
 262         int c = *r++;
 263         if (c >= 01 && c <= 03) {
 264             while (c--)
 265                 if (*r++ != *data++)
 266                     return FALSE;
 267         }
 268         if (c == 04) {
 269             switch (*data++) {
 270               case 0x07: ins->oprs[0].basereg = 0; break;
 271               case 0x17: ins->oprs[0].basereg = 2; break;
 272               case 0x1F: ins->oprs[0].basereg = 3; break;
 273               default: return FALSE;
 274             }
 275         }
 276         if (c == 05) {
 277             switch (*data++) {
 278               case 0xA1: ins->oprs[0].basereg = 4; break;
 279               case 0xA9: ins->oprs[0].basereg = 5; break;
 280               default: return FALSE;
 281             }
 282         }
 283         if (c == 06) {
 284             switch (*data++) {
 285               case 0x06: ins->oprs[0].basereg = 0; break;
 286               case 0x0E: ins->oprs[0].basereg = 1; break;
 287               case 0x16: ins->oprs[0].basereg = 2; break;
 288               case 0x1E: ins->oprs[0].basereg = 3; break;
 289               default: return FALSE;
 290             }
 291         }
 292         if (c == 07) {
 293             switch (*data++) {
 294               case 0xA0: ins->oprs[0].basereg = 4; break;
 295               case 0xA8: ins->oprs[0].basereg = 5; break;
 296               default: return FALSE;
 297             }
 298         }
 299         if (c >= 010 && c <= 012) {
 300             int t = *r++, d = *data++;
 301             if (d < t || d > t+7)
 302                 return FALSE;
 303             else {
 304                 ins->oprs[c-010].basereg = d-t;
 305                 ins->oprs[c-010].segment |= SEG_RMREG;
 306             }
 307         }
 308         if (c == 017)
 309             if (*data++)
 310                 return FALSE;
 311         if (c >= 014 && c <= 016) {
 312             ins->oprs[c-014].offset = (signed char) *data++;
 313             ins->oprs[c-014].segment |= SEG_SIGNED;
 314         }
 315         if (c >= 020 && c <= 022)
 316             ins->oprs[c-020].offset = *data++;
 317         if (c >= 024 && c <= 026)
 318             ins->oprs[c-024].offset = *data++;
 319         if (c >= 030 && c <= 032) {
 320             ins->oprs[c-030].offset = *data++;
 321             ins->oprs[c-030].offset |= (*data++ << 8);
 322         }
 323         if (c >= 034 && c <= 036) {
 324             ins->oprs[c-034].offset = *data++;
 325             ins->oprs[c-034].offset |= (*data++ << 8);
 326             if (asize == 32) {
 327                 ins->oprs[c-034].offset |= (((long) *data++) << 16);
 328                 ins->oprs[c-034].offset |= (((long) *data++) << 24);
 329             }
 330             if (segsize != asize)
 331                 ins->oprs[c-034].addr_size = asize;
 332         }
 333         if (c >= 040 && c <= 042) {
 334             ins->oprs[c-040].offset = *data++;
 335             ins->oprs[c-040].offset |= (*data++ << 8);
 336             ins->oprs[c-040].offset |= (((long) *data++) << 16);
 337             ins->oprs[c-040].offset |= (((long) *data++) << 24);
 338         }
 339         if (c >= 050 && c <= 052) {
 340             ins->oprs[c-050].offset = (signed char) *data++;
 341             ins->oprs[c-050].segment |= SEG_RELATIVE;
 342         }
 343         if (c >= 060 && c <= 062) {
 344             ins->oprs[c-060].offset = *data++;
 345             ins->oprs[c-060].offset |= (*data++ << 8);
 346             ins->oprs[c-060].segment |= SEG_RELATIVE;
 347             ins->oprs[c-060].segment &= ~SEG_32BIT;
 348         }
 349         if (c >= 064 && c <= 066) {
 350             ins->oprs[c-064].offset = *data++;
 351             ins->oprs[c-064].offset |= (*data++ << 8);
 352             if (asize == 32) {
 353                 ins->oprs[c-064].offset |= (((long) *data++) << 16);
 354                 ins->oprs[c-064].offset |= (((long) *data++) << 24);
 355                 ins->oprs[c-064].segment |= SEG_32BIT;
 356             } else
 357                 ins->oprs[c-064].segment &= ~SEG_32BIT;
 358             ins->oprs[c-064].segment |= SEG_RELATIVE;
 359             if (segsize != asize)
 360                 ins->oprs[c-064].addr_size = asize;
 361         }
 362         if (c >= 070 && c <= 072) {
 363             ins->oprs[c-070].offset = *data++;
 364             ins->oprs[c-070].offset |= (*data++ << 8);
 365             ins->oprs[c-070].offset |= (((long) *data++) << 16);
 366             ins->oprs[c-070].offset |= (((long) *data++) << 24);
 367             ins->oprs[c-070].segment |= SEG_32BIT | SEG_RELATIVE;
 368         }
 369         if (c >= 0100 && c <= 0177) {
 370             int modrm = *data++;
 371             ins->oprs[c & 07].basereg = (modrm >> 3) & 07;
 372             ins->oprs[c & 07].segment |= SEG_RMREG;
 373             data = do_ea (data, modrm, asize, segsize,
 374                           &ins->oprs[(c >> 3) & 07]);
 375         }
 376         if (c >= 0200 && c <= 0277) {
 377             int modrm = *data++;
 378             if (((modrm >> 3) & 07) != (c & 07))
 379                 return FALSE;          /* spare field doesn't match up */
 380             data = do_ea (data, modrm, asize, segsize,
 381                           &ins->oprs[(c >> 3) & 07]);
 382         }
 383         if (c >= 0300 && c <= 0302) {
 384             if (asize)
 385                 ins->oprs[c-0300].segment |= SEG_32BIT;
 386             else
 387                 ins->oprs[c-0300].segment &= ~SEG_32BIT;
 388             a_used = TRUE;
 389         }
 390         if (c == 0310) {
 391             if (asize == 32)
 392                 return FALSE;
 393             else
 394                 a_used = TRUE;
 395         }
 396         if (c == 0311) {
 397             if (asize == 16)
 398                 return FALSE;
 399             else
 400                 a_used = TRUE;
 401         }
 402         if (c == 0312) {
 403             if (asize != segsize)
 404                 return FALSE;
 405             else
 406                 a_used = TRUE;
 407         }
 408         if (c == 0320) {
 409             if (osize == 32)
 410                 return FALSE;
 411             else
 412                 o_used = TRUE;
 413         }
 414         if (c == 0321) {
 415             if (osize == 16)
 416                 return FALSE;
 417             else
 418                 o_used = TRUE;
 419         }
 420         if (c == 0322) {
 421             if (osize != segsize)
 422                 return FALSE;
 423             else
 424                 o_used = TRUE;
 425         }
 426         if (c == 0330) {
 427             int t = *r++, d = *data++;
 428             if (d < t || d > t+15)
 429                 return FALSE;
 430             else
 431                 ins->condition = d - t;
 432         }
 433     }
 434
 435     /*
 436      * Check for unused a/o prefixes.
 437      */
 438     ins->nprefix = 0;
 439     if (!a_used && asize != segsize)
 440         ins->prefixes[ins->nprefix++] = (asize == 16 ? P_A16 : P_A32);
 441     if (!o_used && osize != segsize)
 442         ins->prefixes[ins->nprefix++] = (osize == 16 ? P_O16 : P_O32);
 443
 444     return data - origdata;
 445 }
 446
 447 long disasm (unsigned char *data, char *output, int segsize, long offset,
 448              int autosync)
 449 {
 450     struct itemplate **p;
 451     int length = 0;
 452     char *segover;
 453     int rep, lock, asize, osize, i, slen, colon;
 454     unsigned char *origdata;
 455     int works;
 456     insn ins;
 457
 458     /*
 459      * Scan for prefixes.
 460      */
 461     asize = osize = segsize;
 462     segover = NULL;
 463     rep = lock = 0;
 464     origdata = data;
 465     for (;;) {
 466         if (*data == 0xF3 || *data == 0xF2)
 467             rep = *data++;
 468         else if (*data == 0xF0)
 469             lock = *data++;
 470         else if (*data == 0x2E || *data == 0x36 || *data == 0x3E ||
 471                  *data == 0x26 || *data == 0x64 || *data == 0x65) {
 472             switch (*data++) {
 473               case 0x2E: segover = "cs"; break;
 474               case 0x36: segover = "ss"; break;
 475               case 0x3E: segover = "ds"; break;
 476               case 0x26: segover = "es"; break;
 477               case 0x64: segover = "fs"; break;
 478               case 0x65: segover = "gs"; break;
 479             }
 480         } else if (*data == 0x66)
 481             osize = 48 - segsize, data++;
 482         else if (*data == 0x67)
 483             asize = 48 - segsize, data++;
 484         else
 485             break;
 486     }
 487
 488     ins.oprs[0].segment = ins.oprs[1].segment = ins.oprs[2].segment =
 489     ins.oprs[0].addr_size = ins.oprs[1].addr_size = ins.oprs[2].addr_size =
 490         (segsize == 16 ? 0 : SEG_32BIT);
 491     ins.condition = -1;
 492     works = TRUE;
 493     for (p = itable[*data]; *p; p++)
 494         if ( (length = matches((unsigned char *)((*p)->code), data,
 495                                asize, osize, segsize, &ins)) )
 496         {
 497             works = TRUE;
 498             /*
 499              * Final check to make sure the types of r/m match up.
 500              */
 501             for (i = 0; i < (*p)->operands; i++)
 502                 if (
 503
 504                     /* If it's a mem-only EA but we have a register, die. */
 505                     ((ins.oprs[i].segment & SEG_RMREG) &&
 506                      !(MEMORY & ~(*p)->opd[i])) ||
 507
 508                     /* If it's a reg-only EA but we have a memory ref, die. */
 509                     (!(ins.oprs[i].segment & SEG_RMREG) &&
 510                      !(REGNORM & ~(*p)->opd[i]) &&
 511                      !((*p)->opd[i] & REG_SMASK)) ||
 512
 513                     /* Register type mismatch (eg FS vs REG_DESS): die. */
 514                     ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
 515                       (ins.oprs[i].segment & SEG_RMREG)) &&
 516                      !whichreg ((*p)->opd[i], ins.oprs[i].basereg)))
 517                 {
 518                     works = FALSE;
 519                     /*
 520                      * FIXME: can we do a break here?
 521                      */
 522                 }
 523
 524             if (works)
 525                 break;
 526         }
 527
 528     if (!length || !works)
 529         return 0;                      /* no instruction was matched */
 530
 531     slen = 0;
 532
 533     if (rep) {
 534         slen += sprintf(output+slen, "rep%s ",
 535                         (rep == 0xF2 ? "ne" :
 536                          (*p)->opcode == I_CMPSB ||
 537                          (*p)->opcode == I_CMPSW ||
 538                          (*p)->opcode == I_CMPSD ||
 539                          (*p)->opcode == I_SCASB ||
 540                          (*p)->opcode == I_SCASW ||
 541                          (*p)->opcode == I_SCASD ? "e" : ""));
 542     }
 543     if (lock)
 544         slen += sprintf(output+slen, "lock ");
 545     for (i = 0; i < ins.nprefix; i++)
 546         switch (ins.prefixes[i]) {
 547           case P_A16: slen += sprintf(output+slen, "a16 "); break;
 548           case P_A32: slen += sprintf(output+slen, "a32 "); break;
 549           case P_O16: slen += sprintf(output+slen, "o16 "); break;
 550           case P_O32: slen += sprintf(output+slen, "o32 "); break;
 551         }
 552
 553     for (i = 0; i < elements(ico); i++)
 554         if ((*p)->opcode == ico[i]) {
 555             slen += sprintf(output+slen, "%s%s", icn[i],
 556                             whichcond(ins.condition));
 557             break;
 558         }
 559     if (i >= elements(ico))
 560         slen += sprintf(output+slen, "%s", insn_names[(*p)->opcode]);
 561     colon = FALSE;
 562     length += data - origdata;         /* fix up for prefixes */
 563     for (i=0; i<(*p)->operands; i++) {
 564         output[slen++] = (colon ? ':' : i==0 ? ' ' : ',');
 565
 566         if (ins.oprs[i].segment & SEG_RELATIVE) {
 567             ins.oprs[i].offset += offset + length;
 568             /*
 569              * sort out wraparound
 570              */
 571             if (!(ins.oprs[i].segment & SEG_32BIT))
 572                 ins.oprs[i].offset &= 0xFFFF;
 573             /*
 574              * add sync marker, if autosync is on
 575              */
 576             if (autosync)
 577                 add_sync (ins.oprs[i].offset, 0L);
 578         }
 579
 580         if ((*p)->opd[i] & COLON)
 581             colon = TRUE;
 582         else
 583             colon = FALSE;
 584
 585         if (((*p)->opd[i] & (REGISTER | FPUREG)) ||
 586             (ins.oprs[i].segment & SEG_RMREG))
 587         {
 588             ins.oprs[i].basereg = whichreg ((*p)->opd[i],
 589                                             ins.oprs[i].basereg);
 590             if ( (*p)->opd[i] & TO )
 591                 slen += sprintf(output+slen, "to ");
 592             slen += sprintf(output+slen, "%s",
 593                             reg_names[ins.oprs[i].basereg-EXPR_REG_START]);
 594         } else if (!(UNITY & ~(*p)->opd[i])) {
 595             output[slen++] = '1';
 596         } else if ( (*p)->opd[i] & IMMEDIATE ) {
 597             if ( (*p)->opd[i] & BITS8 ) {
 598                 slen += sprintf(output+slen, "byte ");
 599                 if (ins.oprs[i].segment & SEG_SIGNED) {
 600                     if (ins.oprs[i].offset < 0) {
 601                         ins.oprs[i].offset *= -1;
 602                         output[slen++] = '-';
 603                     } else
 604                         output[slen++] = '+';
 605                 }
 606             } else if ( (*p)->opd[i] & BITS16 ) {
 607                 slen += sprintf(output+slen, "word ");
 608             } else if ( (*p)->opd[i] & BITS32 ) {
 609                 slen += sprintf(output+slen, "dword ");
 610             } else if ( (*p)->opd[i] & NEAR ) {
 611                 slen += sprintf(output+slen, "near ");
 612             } else if ( (*p)->opd[i] & SHORT ) {
 613                 slen += sprintf(output+slen, "short ");
 614             }
 615             slen += sprintf(output+slen, "0x%lx", ins.oprs[i].offset);
 616         } else if ( !(MEM_OFFS & ~(*p)->opd[i]) ) {
 617             slen += sprintf(output+slen, "[%s%s%s0x%lx]",
 618                             (segover ? segover : ""),
 619                             (segover ? ":" : ""),
 620                             (ins.oprs[i].addr_size == 32 ? "dword " :
 621                              ins.oprs[i].addr_size == 16 ? "word " : ""),
 622                             ins.oprs[i].offset);
 623             segover = NULL;
 624         } else if ( !(REGMEM & ~(*p)->opd[i]) ) {
 625             int started = FALSE;
 626             if ( (*p)->opd[i] & BITS8 )
 627                 slen += sprintf(output+slen, "byte ");
 628             if ( (*p)->opd[i] & BITS16 )
 629                 slen += sprintf(output+slen, "word ");
 630             if ( (*p)->opd[i] & BITS32 )
 631                 slen += sprintf(output+slen, "dword ");
 632             if ( (*p)->opd[i] & BITS64 )
 633                 slen += sprintf(output+slen, "qword ");
 634             if ( (*p)->opd[i] & BITS80 )
 635                 slen += sprintf(output+slen, "tword ");
 636             if ( (*p)->opd[i] & FAR )
 637                 slen += sprintf(output+slen, "far ");
 638             if ( (*p)->opd[i] & NEAR )
 639                 slen += sprintf(output+slen, "near ");
 640             output[slen++] = '[';
 641             if (ins.oprs[i].addr_size)
 642                 slen += sprintf(output+slen, "%s",
 643                                 (ins.oprs[i].addr_size == 32 ? "dword " :
 644                                  ins.oprs[i].addr_size == 16 ? "word " : ""));
 645             if (segover) {
 646                 slen += sprintf(output+slen, "%s:", segover);
 647                 segover = NULL;
 648             }
 649             if (ins.oprs[i].basereg != -1) {
 650                 slen += sprintf(output+slen, "%s",
 651                                 reg_names[(ins.oprs[i].basereg -
 652                                            EXPR_REG_START)]);
 653                 started = TRUE;
 654             }
 655             if (ins.oprs[i].indexreg != -1) {
 656                 if (started)
 657                     output[slen++] = '+';
 658                 slen += sprintf(output+slen, "%s",
 659                                 reg_names[(ins.oprs[i].indexreg -
 660                                            EXPR_REG_START)]);
 661                 if (ins.oprs[i].scale > 1)
 662                     slen += sprintf(output+slen, "*%d", ins.oprs[i].scale);
 663                 started = TRUE;
 664             }
 665             if (ins.oprs[i].segment & SEG_DISP8) {
 666                 int sign = '+';
 667                 if (ins.oprs[i].offset & 0x80) {
 668                     ins.oprs[i].offset = - (signed char) ins.oprs[i].offset;
 669                     sign = '-';
 670                 }
 671                 slen += sprintf(output+slen, "%c0x%lx", sign,
 672                                 ins.oprs[i].offset);
 673             } else if (ins.oprs[i].segment & SEG_DISP16) {
 674                 if (started)
 675                     output[slen++] = '+';
 676                 slen += sprintf(output+slen, "0x%lx", ins.oprs[i].offset);
 677             } else if (ins.oprs[i].segment & SEG_DISP32) {
 678                 if (started)
 679                     output[slen++] = '+';
 680                 slen += sprintf(output+slen, "0x%lx", ins.oprs[i].offset);
 681             }
 682             output[slen++] = ']';
 683         } else {
 684             slen += sprintf(output+slen, "<operand%d>", i);
 685         }
 686     }
 687     output[slen] = '\0';
 688     if (segover) {                     /* unused segment override */
 689         char *p = output;
 690         int count = slen+1;
 691         while (count--)
 692             p[count+3] = p[count];
 693         strncpy (output, segover, 2);
 694         output[2] = ' ';
 695     }
 696     return length;
 697 }
 698
 699 long eatbyte (unsigned char *data, char *output)
 700 {
 701     sprintf(output, "db 0x%02X", *data);
 702     return 1;
 703 }