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output: macho -- Avoid conversion of addresses to RAWDATA
[nasm.git] / asm / assemble.c
bloba6bb0ee559a10dfdd1c2753e81c48a2d17bf8ba2
1 /* ----------------------------------------------------------------------- *
2 *
3 * Copyright 1996-2018 The NASM Authors - All Rights Reserved
4 * See the file AUTHORS included with the NASM distribution for
5 * the specific copyright holders.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following
9 * conditions are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
19 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
20 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
29 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
30 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 * ----------------------------------------------------------------------- */
33
34 /*
35 * assemble.c code generation for the Netwide Assembler
36 *
37 * Bytecode specification
38 * ----------------------
39 *
40 *
41 * Codes Mnemonic Explanation
42 *
43 * \0 terminates the code. (Unless it's a literal of course.)
44 * \1..\4 that many literal bytes follow in the code stream
45 * \5 add 4 to the primary operand number (b, low octdigit)
46 * \6 add 4 to the secondary operand number (a, middle octdigit)
47 * \7 add 4 to both the primary and the secondary operand number
48 * \10..\13 a literal byte follows in the code stream, to be added
49 * to the register value of operand 0..3
50 * \14..\17 the position of index register operand in MIB (BND insns)
51 * \20..\23 ib a byte immediate operand, from operand 0..3
52 * \24..\27 ib,u a zero-extended byte immediate operand, from operand 0..3
53 * \30..\33 iw a word immediate operand, from operand 0..3
54 * \34..\37 iwd select between \3[0-3] and \4[0-3] depending on 16/32 bit
55 * assembly mode or the operand-size override on the operand
56 * \40..\43 id a long immediate operand, from operand 0..3
57 * \44..\47 iwdq select between \3[0-3], \4[0-3] and \5[4-7]
58 * depending on the address size of the instruction.
59 * \50..\53 rel8 a byte relative operand, from operand 0..3
60 * \54..\57 iq a qword immediate operand, from operand 0..3
61 * \60..\63 rel16 a word relative operand, from operand 0..3
62 * \64..\67 rel select between \6[0-3] and \7[0-3] depending on 16/32 bit
63 * assembly mode or the operand-size override on the operand
64 * \70..\73 rel32 a long relative operand, from operand 0..3
65 * \74..\77 seg a word constant, from the _segment_ part of operand 0..3
66 * \1ab a ModRM, calculated on EA in operand a, with the spare
67 * field the register value of operand b.
68 * \172\ab the register number from operand a in bits 7..4, with
69 * the 4-bit immediate from operand b in bits 3..0.
70 * \173\xab the register number from operand a in bits 7..4, with
71 * the value b in bits 3..0.
72 * \174..\177 the register number from operand 0..3 in bits 7..4, and
73 * an arbitrary value in bits 3..0 (assembled as zero.)
74 * \2ab a ModRM, calculated on EA in operand a, with the spare
75 * field equal to digit b.
76 *
77 * \240..\243 this instruction uses EVEX rather than REX or VEX/XOP, with the
78 * V field taken from operand 0..3.
79 * \250 this instruction uses EVEX rather than REX or VEX/XOP, with the
80 * V field set to 1111b.
81 *
82 * EVEX prefixes are followed by the sequence:
83 * \cm\wlp\tup where cm is:
84 * cc 00m mmm
85 * c = 2 for EVEX and mmmm is the M field (EVEX.P0[3:0])
86 * and wlp is:
87 * 00 wwl lpp
88 * [l0] ll = 0 (.128, .lz)
89 * [l1] ll = 1 (.256)
90 * [l2] ll = 2 (.512)
91 * [lig] ll = 3 for EVEX.L'L don't care (always assembled as 0)
92 *
93 * [w0] ww = 0 for W = 0
94 * [w1] ww = 1 for W = 1
95 * [wig] ww = 2 for W don't care (always assembled as 0)
96 * [ww] ww = 3 for W used as REX.W
97 *
98 * [p0] pp = 0 for no prefix
99 * [60] pp = 1 for legacy prefix 60
100 * [f3] pp = 2
101 * [f2] pp = 3
102 *
103 * tup is tuple type for Disp8*N from %tuple_codes in insns.pl
104 * (compressed displacement encoding)
105 *
106 * \254..\257 id,s a signed 32-bit operand to be extended to 64 bits.
107 * \260..\263 this instruction uses VEX/XOP rather than REX, with the
108 * V field taken from operand 0..3.
109 * \270 this instruction uses VEX/XOP rather than REX, with the
110 * V field set to 1111b.
111 *
112 * VEX/XOP prefixes are followed by the sequence:
113 * \tmm\wlp where mm is the M field; and wlp is:
114 * 00 wwl lpp
115 * [l0] ll = 0 for L = 0 (.128, .lz)
116 * [l1] ll = 1 for L = 1 (.256)
117 * [lig] ll = 2 for L don't care (always assembled as 0)
118 *
119 * [w0] ww = 0 for W = 0
120 * [w1 ] ww = 1 for W = 1
121 * [wig] ww = 2 for W don't care (always assembled as 0)
122 * [ww] ww = 3 for W used as REX.W
123 *
124 * t = 0 for VEX (C4/C5), t = 1 for XOP (8F).
125 *
126 * \271 hlexr instruction takes XRELEASE (F3) with or without lock
127 * \272 hlenl instruction takes XACQUIRE/XRELEASE with or without lock
128 * \273 hle instruction takes XACQUIRE/XRELEASE with lock only
129 * \274..\277 ib,s a byte immediate operand, from operand 0..3, sign-extended
130 * to the operand size (if o16/o32/o64 present) or the bit size
131 * \310 a16 indicates fixed 16-bit address size, i.e. optional 0x67.
132 * \311 a32 indicates fixed 32-bit address size, i.e. optional 0x67.
133 * \312 adf (disassembler only) invalid with non-default address size.
134 * \313 a64 indicates fixed 64-bit address size, 0x67 invalid.
135 * \314 norexb (disassembler only) invalid with REX.B
136 * \315 norexx (disassembler only) invalid with REX.X
137 * \316 norexr (disassembler only) invalid with REX.R
138 * \317 norexw (disassembler only) invalid with REX.W
139 * \320 o16 indicates fixed 16-bit operand size, i.e. optional 0x66.
140 * \321 o32 indicates fixed 32-bit operand size, i.e. optional 0x66.
141 * \322 odf indicates that this instruction is only valid when the
142 * operand size is the default (instruction to disassembler,
143 * generates no code in the assembler)
144 * \323 o64nw indicates fixed 64-bit operand size, REX on extensions only.
145 * \324 o64 indicates 64-bit operand size requiring REX prefix.
146 * \325 nohi instruction which always uses spl/bpl/sil/dil
147 * \326 nof3 instruction not valid with 0xF3 REP prefix. Hint for
148 disassembler only; for SSE instructions.
149 * \330 a literal byte follows in the code stream, to be added
150 * to the condition code value of the instruction.
151 * \331 norep instruction not valid with REP prefix. Hint for
152 * disassembler only; for SSE instructions.
153 * \332 f2i REP prefix (0xF2 byte) used as opcode extension.
154 * \333 f3i REP prefix (0xF3 byte) used as opcode extension.
155 * \334 rex.l LOCK prefix used as REX.R (used in non-64-bit mode)
156 * \335 repe disassemble a rep (0xF3 byte) prefix as repe not rep.
157 * \336 mustrep force a REP(E) prefix (0xF3) even if not specified.
158 * \337 mustrepne force a REPNE prefix (0xF2) even if not specified.
159 * \336-\337 are still listed as prefixes in the disassembler.
160 * \340 resb reserve <operand 0> bytes of uninitialized storage.
161 * Operand 0 had better be a segmentless constant.
162 * \341 wait this instruction needs a WAIT "prefix"
163 * \360 np no SSE prefix (== \364\331)
164 * \361 66 SSE prefix (== \366\331)
165 * \364 !osp operand-size prefix (0x66) not permitted
166 * \365 !asp address-size prefix (0x67) not permitted
167 * \366 operand-size prefix (0x66) used as opcode extension
168 * \367 address-size prefix (0x67) used as opcode extension
169 * \370,\371 jcc8 match only if operand 0 meets byte jump criteria.
170 * jmp8 370 is used for Jcc, 371 is used for JMP.
171 * \373 jlen assemble 0x03 if bits==16, 0x05 if bits==32;
172 * used for conditional jump over longer jump
173 * \374 vsibx|vm32x|vm64x this instruction takes an XMM VSIB memory EA
174 * \375 vsiby|vm32y|vm64y this instruction takes an YMM VSIB memory EA
175 * \376 vsibz|vm32z|vm64z this instruction takes an ZMM VSIB memory EA
176 */
177
178 #include "compiler.h"
179
180 #include <stdio.h>
181 #include <string.h>
182 #include <stdlib.h>
183
184 #include "nasm.h"
185 #include "nasmlib.h"
186 #include "error.h"
187 #include "assemble.h"
188 #include "insns.h"
189 #include "tables.h"
190 #include "disp8.h"
191 #include "listing.h"
192
193 enum match_result {
194 /*
195 * Matching errors. These should be sorted so that more specific
196 * errors come later in the sequence.
197 */
198 MERR_INVALOP,
199 MERR_OPSIZEMISSING,
200 MERR_OPSIZEMISMATCH,
201 MERR_BRNOTHERE,
202 MERR_BRNUMMISMATCH,
203 MERR_MASKNOTHERE,
204 MERR_DECONOTHERE,
205 MERR_BADCPU,
206 MERR_BADMODE,
207 MERR_BADHLE,
208 MERR_ENCMISMATCH,
209 MERR_BADBND,
210 MERR_BADREPNE,
211 /*
212 * Matching success; the conditional ones first
213 */
214 MOK_JUMP, /* Matching OK but needs jmp_match() */
215 MOK_GOOD /* Matching unconditionally OK */
216 };
217
218 typedef struct {
219 enum ea_type type; /* what kind of EA is this? */
220 int sib_present; /* is a SIB byte necessary? */
221 int bytes; /* # of bytes of offset needed */
222 int size; /* lazy - this is sib+bytes+1 */
223 uint8_t modrm, sib, rex, rip; /* the bytes themselves */
224 int8_t disp8; /* compressed displacement for EVEX */
225 } ea;
226
227 #define GEN_SIB(scale, index, base) \
228 (((scale) << 6) | ((index) << 3) | ((base)))
229
230 #define GEN_MODRM(mod, reg, rm) \
231 (((mod) << 6) | (((reg) & 7) << 3) | ((rm) & 7))
232
233 static int64_t calcsize(int32_t, int64_t, int, insn *,
234 const struct itemplate *);
235 static int emit_prefix(struct out_data *data, const int bits, insn *ins);
236 static void gencode(struct out_data *data, insn *ins);
237 static enum match_result find_match(const struct itemplate **tempp,
238 insn *instruction,
239 int32_t segment, int64_t offset, int bits);
240 static enum match_result matches(const struct itemplate *, insn *, int bits);
241 static opflags_t regflag(const operand *);
242 static int32_t regval(const operand *);
243 static int rexflags(int, opflags_t, int);
244 static int op_rexflags(const operand *, int);
245 static int op_evexflags(const operand *, int, uint8_t);
246 static void add_asp(insn *, int);
247
248 static enum ea_type process_ea(operand *, ea *, int, int,
249 opflags_t, insn *, const char **);
250
251 static inline bool absolute_op(const struct operand *o)
252 {
253 return o->segment == NO_SEG && o->wrt == NO_SEG &&
254 !(o->opflags & OPFLAG_RELATIVE);
255 }
256
257 static int has_prefix(insn * ins, enum prefix_pos pos, int prefix)
258 {
259 return ins->prefixes[pos] == prefix;
260 }
261
262 static void assert_no_prefix(insn * ins, enum prefix_pos pos)
263 {
264 if (ins->prefixes[pos])
265 nasm_error(ERR_NONFATAL, "invalid %s prefix",
266 prefix_name(ins->prefixes[pos]));
267 }
268
269 static const char *size_name(int size)
270 {
271 switch (size) {
272 case 1:
273 return "byte";
274 case 2:
275 return "word";
276 case 4:
277 return "dword";
278 case 8:
279 return "qword";
280 case 10:
281 return "tword";
282 case 16:
283 return "oword";
284 case 32:
285 return "yword";
286 case 64:
287 return "zword";
288 default:
289 return "???";
290 }
291 }
292
293 static void warn_overflow(int size)
294 {
295 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
296 "%s data exceeds bounds", size_name(size));
297 }
298
299 static void warn_overflow_const(int64_t data, int size)
300 {
301 if (overflow_general(data, size))
302 warn_overflow(size);
303 }
304
305 static void warn_overflow_out(int64_t data, int size, enum out_sign sign)
306 {
307 bool err;
308
309 switch (sign) {
310 case OUT_WRAP:
311 err = overflow_general(data, size);
312 break;
313 case OUT_SIGNED:
314 err = overflow_signed(data, size);
315 break;
316 case OUT_UNSIGNED:
317 err = overflow_unsigned(data, size);
318 break;
319 default:
320 panic();
321 break;
322 }
323
324 if (err)
325 warn_overflow(size);
326 }
327
328 /*
329 * This routine wrappers the real output format's output routine,
330 * in order to pass a copy of the data off to the listing file
331 * generator at the same time, flatten unnecessary relocations,
332 * and verify backend compatibility.
333 */
334 static void out(struct out_data *data)
335 {
336 static int32_t lineno = 0; /* static!!! */
337 static const char *lnfname = NULL;
338 union {
339 uint8_t b[8];
340 uint64_t q;
341 } xdata;
342 size_t asize, amax;
343 uint64_t zeropad = 0;
344 int64_t addrval;
345 int32_t fixseg; /* Segment for which to produce fixed data */
346
347 if (!data->size)
348 return; /* Nothing to do */
349
350 /*
351 * Convert addresses to RAWDATA if possible
352 * XXX: not all backends want this for global symbols!!!!
353 */
354 switch (data->type) {
355 case OUT_ADDRESS:
356 addrval = data->toffset;
357 fixseg = NO_SEG; /* Absolute address is fixed data */
358 goto address;
359
360 case OUT_RELADDR:
361 addrval = data->toffset - data->relbase;
362 fixseg = data->segment; /* Our own segment is fixed data */
363 goto address;
364
365 address:
366 nasm_assert(data->size <= 8);
367 asize = data->size;
368 amax = ofmt->maxbits >> 3; /* Maximum address size in bytes */
369 if ((ofmt->flags & OFMT_KEEP_ADDR) == 0 && data->tsegment == fixseg &&
370 data->twrt == NO_SEG) {
371 warn_overflow_out(addrval, asize, data->sign);
372 xdata.q = cpu_to_le64(addrval);
373 data->data = xdata.b;
374 data->type = OUT_RAWDATA;
375 asize = amax = 0; /* No longer an address */
376 }
377 break;
378
379 case OUT_SEGMENT:
380 nasm_assert(data->size <= 8);
381 asize = data->size;
382 amax = 2;
383 break;
384
385 default:
386 asize = amax = 0; /* Not an address */
387 break;
388 }
389
390 /*
391 * this call to src_get determines when we call the
392 * debug-format-specific "linenum" function
393 * it updates lineno and lnfname to the current values
394 * returning 0 if "same as last time", -2 if lnfname
395 * changed, and the amount by which lineno changed,
396 * if it did. thus, these variables must be static
397 */
398
399 if (src_get(&lineno, &lnfname))
400 dfmt->linenum(lnfname, lineno, data->segment);
401
402 if (asize > amax) {
403 if (data->type == OUT_RELADDR || data->sign == OUT_SIGNED) {
404 nasm_error(ERR_NONFATAL,
405 "%u-bit signed relocation unsupported by output format %s",
406 (unsigned int)(asize << 3), ofmt->shortname);
407 } else {
408 nasm_error(ERR_WARNING | ERR_WARN_ZEXTRELOC,
409 "%u-bit %s relocation zero-extended from %u bits",
410 (unsigned int)(asize << 3),
411 data->type == OUT_SEGMENT ? "segment" : "unsigned",
412 (unsigned int)(amax << 3));
413 }
414 zeropad = data->size - amax;
415 data->size = amax;
416 }
417 lfmt->output(data);
418 ofmt->output(data);
419 data->offset += data->size;
420 data->insoffs += data->size;
421
422 if (zeropad) {
423 data->type = OUT_ZERODATA;
424 data->size = zeropad;
425 lfmt->output(data);
426 ofmt->output(data);
427 data->offset += zeropad;
428 data->insoffs += zeropad;
429 data->size += zeropad; /* Restore original size value */
430 }
431 }
432
433 static inline void out_rawdata(struct out_data *data, const void *rawdata,
434 size_t size)
435 {
436 data->type = OUT_RAWDATA;
437 data->data = rawdata;
438 data->size = size;
439 out(data);
440 }
441
442 static void out_rawbyte(struct out_data *data, uint8_t byte)
443 {
444 data->type = OUT_RAWDATA;
445 data->data = &byte;
446 data->size = 1;
447 out(data);
448 }
449
450 static inline void out_reserve(struct out_data *data, uint64_t size)
451 {
452 data->type = OUT_RESERVE;
453 data->size = size;
454 out(data);
455 }
456
457 static void out_segment(struct out_data *data, const struct operand *opx)
458 {
459 if (opx->opflags & OPFLAG_RELATIVE)
460 nasm_error(ERR_NONFATAL, "segment references cannot be relative");
461
462 data->type = OUT_SEGMENT;
463 data->sign = OUT_UNSIGNED;
464 data->size = 2;
465 data->toffset = opx->offset;
466 data->tsegment = ofmt->segbase(opx->segment | 1);
467 data->twrt = opx->wrt;
468 out(data);
469 }
470
471 static void out_imm(struct out_data *data, const struct operand *opx,
472 int size, enum out_sign sign)
473 {
474 if (opx->segment != NO_SEG && (opx->segment & 1)) {
475 /*
476 * This is actually a segment reference, but eval() has
477 * already called ofmt->segbase() for us. Sigh.
478 */
479 if (size < 2)
480 nasm_error(ERR_NONFATAL, "segment reference must be 16 bits");
481
482 data->type = OUT_SEGMENT;
483 } else {
484 data->type = (opx->opflags & OPFLAG_RELATIVE)
485 ? OUT_RELADDR : OUT_ADDRESS;
486 }
487 data->sign = sign;
488 data->toffset = opx->offset;
489 data->tsegment = opx->segment;
490 data->twrt = opx->wrt;
491 /*
492 * XXX: improve this if at some point in the future we can
493 * distinguish the subtrahend in expressions like [foo - bar]
494 * where bar is a symbol in the current segment. However, at the
495 * current point, if OPFLAG_RELATIVE is set that subtraction has
496 * already occurred.
497 */
498 data->relbase = 0;
499 data->size = size;
500 out(data);
501 }
502
503 static void out_reladdr(struct out_data *data, const struct operand *opx,
504 int size)
505 {
506 if (opx->opflags & OPFLAG_RELATIVE)
507 nasm_error(ERR_NONFATAL, "invalid use of self-relative expression");
508
509 data->type = OUT_RELADDR;
510 data->sign = OUT_SIGNED;
511 data->size = size;
512 data->toffset = opx->offset;
513 data->tsegment = opx->segment;
514 data->twrt = opx->wrt;
515 data->relbase = data->offset + (data->inslen - data->insoffs);
516 out(data);
517 }
518
519 static bool jmp_match(int32_t segment, int64_t offset, int bits,
520 insn * ins, const struct itemplate *temp)
521 {
522 int64_t isize;
523 const uint8_t *code = temp->code;
524 uint8_t c = code[0];
525 bool is_byte;
526
527 if (((c & ~1) != 0370) || (ins->oprs[0].type & STRICT))
528 return false;
529 if (!optimizing)
530 return false;
531 if (optimizing < 0 && c == 0371)
532 return false;
533
534 isize = calcsize(segment, offset, bits, ins, temp);
535
536 if (ins->oprs[0].opflags & OPFLAG_UNKNOWN)
537 /* Be optimistic in pass 1 */
538 return true;
539
540 if (ins->oprs[0].segment != segment)
541 return false;
542
543 isize = ins->oprs[0].offset - offset - isize; /* isize is delta */
544 is_byte = (isize >= -128 && isize <= 127); /* is it byte size? */
545
546 if (is_byte && c == 0371 && ins->prefixes[PPS_REP] == P_BND) {
547 /* jmp short (opcode eb) cannot be used with bnd prefix. */
548 ins->prefixes[PPS_REP] = P_none;
549 nasm_error(ERR_WARNING | ERR_WARN_BND | ERR_PASS2 ,
550 "jmp short does not init bnd regs - bnd prefix dropped.");
551 }
552
553 return is_byte;
554 }
555
556 /* This is totally just a wild guess what is reasonable... */
557 #define INCBIN_MAX_BUF (ZERO_BUF_SIZE * 16)
558
559 int64_t assemble(int32_t segment, int64_t start, int bits, insn *instruction)
560 {
561 struct out_data data;
562 const struct itemplate *temp;
563 enum match_result m;
564 int64_t wsize; /* size for DB etc. */
565
566 nasm_zero(data);
567 data.offset = start;
568 data.segment = segment;
569 data.itemp = NULL;
570 data.bits = bits;
571
572 wsize = db_bytes(instruction->opcode);
573 if (wsize == -1)
574 return 0;
575
576 if (wsize) {
577 extop *e;
578
579 list_for_each(e, instruction->eops) {
580 if (e->type == EOT_DB_NUMBER) {
581 if (wsize > 8) {
582 nasm_error(ERR_NONFATAL,
583 "integer supplied to a DT, DO, DY or DZ"
584 " instruction");
585 } else {
586 data.insoffs = 0;
587 data.inslen = data.size = wsize;
588 data.toffset = e->offset;
589 data.twrt = e->wrt;
590 data.relbase = 0;
591 if (e->segment != NO_SEG && (e->segment & 1)) {
592 data.tsegment = e->segment;
593 data.type = OUT_SEGMENT;
594 data.sign = OUT_UNSIGNED;
595 } else {
596 data.tsegment = e->segment;
597 data.type = e->relative ? OUT_RELADDR : OUT_ADDRESS;
598 data.sign = OUT_WRAP;
599 }
600 out(&data);
601 }
602 } else if (e->type == EOT_DB_STRING ||
603 e->type == EOT_DB_STRING_FREE) {
604 int align = e->stringlen % wsize;
605 if (align)
606 align = wsize - align;
607
608 data.insoffs = 0;
609 data.inslen = e->stringlen + align;
610
611 out_rawdata(&data, e->stringval, e->stringlen);
612 out_rawdata(&data, zero_buffer, align);
613 }
614 }
615 } else if (instruction->opcode == I_INCBIN) {
616 const char *fname = instruction->eops->stringval;
617 FILE *fp;
618 size_t t = instruction->times; /* INCBIN handles TIMES by itself */
619 off_t base = 0;
620 off_t len;
621 const void *map = NULL;
622 char *buf = NULL;
623 size_t blk = 0; /* Buffered I/O block size */
624 size_t m = 0; /* Bytes last read */
625
626 if (!t)
627 goto done;
628
629 fp = nasm_open_read(fname, NF_BINARY|NF_FORMAP);
630 if (!fp) {
631 nasm_error(ERR_NONFATAL, "`incbin': unable to open file `%s'",
632 fname);
633 goto done;
634 }
635
636 len = nasm_file_size(fp);
637
638 if (len == (off_t)-1) {
639 nasm_error(ERR_NONFATAL, "`incbin': unable to get length of file `%s'",
640 fname);
641 goto close_done;
642 }
643
644 if (instruction->eops->next) {
645 base = instruction->eops->next->offset;
646 if (base >= len) {
647 len = 0;
648 } else {
649 len -= base;
650 if (instruction->eops->next->next &&
651 len > (off_t)instruction->eops->next->next->offset)
652 len = (off_t)instruction->eops->next->next->offset;
653 }
654 }
655
656 lfmt->set_offset(data.offset);
657 lfmt->uplevel(LIST_INCBIN);
658
659 if (!len)
660 goto end_incbin;
661
662 /* Try to map file data */
663 map = nasm_map_file(fp, base, len);
664 if (!map) {
665 blk = len < (off_t)INCBIN_MAX_BUF ? (size_t)len : INCBIN_MAX_BUF;
666 buf = nasm_malloc(blk);
667 }
668
669 while (t--) {
670 /*
671 * Consider these irrelevant for INCBIN, since it is fully
672 * possible that these might be (way) bigger than an int
673 * can hold; there is, however, no reason to widen these
674 * types just for INCBIN. data.inslen == 0 signals to the
675 * backend that these fields are meaningless, if at all
676 * needed.
677 */
678 data.insoffs = 0;
679 data.inslen = 0;
680
681 if (map) {
682 out_rawdata(&data, map, len);
683 } else if ((off_t)m == len) {
684 out_rawdata(&data, buf, len);
685 } else {
686 off_t l = len;
687
688 if (fseeko(fp, base, SEEK_SET) < 0 || ferror(fp)) {
689 nasm_error(ERR_NONFATAL,
690 "`incbin': unable to seek on file `%s'",
691 fname);
692 goto end_incbin;
693 }
694 while (l > 0) {
695 m = fread(buf, 1, l < (off_t)blk ? (size_t)l : blk, fp);
696 if (!m || feof(fp)) {
697 /*
698 * This shouldn't happen unless the file
699 * actually changes while we are reading
700 * it.
701 */
702 nasm_error(ERR_NONFATAL,
703 "`incbin': unexpected EOF while"
704 " reading file `%s'", fname);
705 goto end_incbin;
706 }
707 out_rawdata(&data, buf, m);
708 l -= m;
709 }
710 }
711 }
712 end_incbin:
713 lfmt->downlevel(LIST_INCBIN);
714 if (instruction->times > 1) {
715 lfmt->uplevel(LIST_TIMES);
716 lfmt->downlevel(LIST_TIMES);
717 }
718 if (ferror(fp)) {
719 nasm_error(ERR_NONFATAL,
720 "`incbin': error while"
721 " reading file `%s'", fname);
722 }
723 close_done:
724 if (buf)
725 nasm_free(buf);
726 if (map)
727 nasm_unmap_file(map, len);
728 fclose(fp);
729 done:
730 instruction->times = 1; /* Tell the upper layer not to iterate */
731 ;
732 } else {
733 /* "Real" instruction */
734
735 /* Check to see if we need an address-size prefix */
736 add_asp(instruction, bits);
737
738 m = find_match(&temp, instruction, data.segment, data.offset, bits);
739
740 if (m == MOK_GOOD) {
741 /* Matches! */
742 int64_t insn_size = calcsize(data.segment, data.offset,
743 bits, instruction, temp);
744 nasm_assert(insn_size >= 0);
745
746 data.itemp = temp;
747 data.bits = bits;
748 data.insoffs = 0;
749 data.inslen = insn_size;
750
751 gencode(&data, instruction);
752 nasm_assert(data.insoffs == insn_size);
753 } else {
754 /* No match */
755 switch (m) {
756 case MERR_OPSIZEMISSING:
757 nasm_error(ERR_NONFATAL, "operation size not specified");
758 break;
759 case MERR_OPSIZEMISMATCH:
760 nasm_error(ERR_NONFATAL, "mismatch in operand sizes");
761 break;
762 case MERR_BRNOTHERE:
763 nasm_error(ERR_NONFATAL,
764 "broadcast not permitted on this operand");
765 break;
766 case MERR_BRNUMMISMATCH:
767 nasm_error(ERR_NONFATAL,
768 "mismatch in the number of broadcasting elements");
769 break;
770 case MERR_MASKNOTHERE:
771 nasm_error(ERR_NONFATAL,
772 "mask not permitted on this operand");
773 break;
774 case MERR_DECONOTHERE:
775 nasm_error(ERR_NONFATAL, "unsupported mode decorator for instruction");
776 break;
777 case MERR_BADCPU:
778 nasm_error(ERR_NONFATAL, "no instruction for this cpu level");
779 break;
780 case MERR_BADMODE:
781 nasm_error(ERR_NONFATAL, "instruction not supported in %d-bit mode",
782 bits);
783 break;
784 case MERR_ENCMISMATCH:
785 nasm_error(ERR_NONFATAL, "specific encoding scheme not available");
786 break;
787 case MERR_BADBND:
788 nasm_error(ERR_NONFATAL, "bnd prefix is not allowed");
789 break;
790 case MERR_BADREPNE:
791 nasm_error(ERR_NONFATAL, "%s prefix is not allowed",
792 (has_prefix(instruction, PPS_REP, P_REPNE) ?
793 "repne" : "repnz"));
794 break;
795 default:
796 nasm_error(ERR_NONFATAL,
797 "invalid combination of opcode and operands");
798 break;
799 }
800
801 instruction->times = 1; /* Avoid repeated error messages */
802 }
803 }
804 return data.offset - start;
805 }
806
807 int64_t insn_size(int32_t segment, int64_t offset, int bits, insn *instruction)
808 {
809 const struct itemplate *temp;
810 enum match_result m;
811
812 if (instruction->opcode == I_none)
813 return 0;
814
815 if (opcode_is_db(instruction->opcode)) {
816 extop *e;
817 int32_t isize, osize, wsize;
818
819 isize = 0;
820 wsize = db_bytes(instruction->opcode);
821 nasm_assert(wsize > 0);
822
823 list_for_each(e, instruction->eops) {
824 int32_t align;
825
826 osize = 0;
827 if (e->type == EOT_DB_NUMBER) {
828 osize = 1;
829 warn_overflow_const(e->offset, wsize);
830 } else if (e->type == EOT_DB_STRING ||
831 e->type == EOT_DB_STRING_FREE)
832 osize = e->stringlen;
833
834 align = (-osize) % wsize;
835 if (align < 0)
836 align += wsize;
837 isize += osize + align;
838 }
839 return isize;
840 }
841
842 if (instruction->opcode == I_INCBIN) {
843 const char *fname = instruction->eops->stringval;
844 off_t len;
845
846 len = nasm_file_size_by_path(fname);
847 if (len == (off_t)-1) {
848 nasm_error(ERR_NONFATAL, "`incbin': unable to get length of file `%s'",
849 fname);
850 return 0;
851 }
852
853 if (instruction->eops->next) {
854 if (len <= (off_t)instruction->eops->next->offset) {
855 len = 0;
856 } else {
857 len -= instruction->eops->next->offset;
858 if (instruction->eops->next->next &&
859 len > (off_t)instruction->eops->next->next->offset) {
860 len = (off_t)instruction->eops->next->next->offset;
861 }
862 }
863 }
864
865 len *= instruction->times;
866 instruction->times = 1; /* Tell the upper layer to not iterate */
867
868 return len;
869 }
870
871 /* Check to see if we need an address-size prefix */
872 add_asp(instruction, bits);
873
874 m = find_match(&temp, instruction, segment, offset, bits);
875 if (m == MOK_GOOD) {
876 /* we've matched an instruction. */
877 return calcsize(segment, offset, bits, instruction, temp);
878 } else {
879 return -1; /* didn't match any instruction */
880 }
881 }
882
883 static void bad_hle_warn(const insn * ins, uint8_t hleok)
884 {
885 enum prefixes rep_pfx = ins->prefixes[PPS_REP];
886 enum whatwarn { w_none, w_lock, w_inval } ww;
887 static const enum whatwarn warn[2][4] =
888 {
889 { w_inval, w_inval, w_none, w_lock }, /* XACQUIRE */
890 { w_inval, w_none, w_none, w_lock }, /* XRELEASE */
891 };
892 unsigned int n;
893
894 n = (unsigned int)rep_pfx - P_XACQUIRE;
895 if (n > 1)
896 return; /* Not XACQUIRE/XRELEASE */
897
898 ww = warn[n][hleok];
899 if (!is_class(MEMORY, ins->oprs[0].type))
900 ww = w_inval; /* HLE requires operand 0 to be memory */
901
902 switch (ww) {
903 case w_none:
904 break;
905
906 case w_lock:
907 if (ins->prefixes[PPS_LOCK] != P_LOCK) {
908 nasm_error(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
909 "%s with this instruction requires lock",
910 prefix_name(rep_pfx));
911 }
912 break;
913
914 case w_inval:
915 nasm_error(ERR_WARNING | ERR_WARN_HLE | ERR_PASS2,
916 "%s invalid with this instruction",
917 prefix_name(rep_pfx));
918 break;
919 }
920 }
921
922 /* Common construct */
923 #define case3(x) case (x): case (x)+1: case (x)+2
924 #define case4(x) case3(x): case (x)+3
925
926 static int64_t calcsize(int32_t segment, int64_t offset, int bits,
927 insn * ins, const struct itemplate *temp)
928 {
929 const uint8_t *codes = temp->code;
930 int64_t length = 0;
931 uint8_t c;
932 int rex_mask = ~0;
933 int op1, op2;
934 struct operand *opx;
935 uint8_t opex = 0;
936 enum ea_type eat;
937 uint8_t hleok = 0;
938 bool lockcheck = true;
939 enum reg_enum mib_index = R_none; /* For a separate index MIB reg form */
940 const char *errmsg;
941
942 ins->rex = 0; /* Ensure REX is reset */
943 eat = EA_SCALAR; /* Expect a scalar EA */
944 memset(ins->evex_p, 0, 3); /* Ensure EVEX is reset */
945
946 if (ins->prefixes[PPS_OSIZE] == P_O64)
947 ins->rex |= REX_W;
948
949 (void)segment; /* Don't warn that this parameter is unused */
950 (void)offset; /* Don't warn that this parameter is unused */
951
952 while (*codes) {
953 c = *codes++;
954 op1 = (c & 3) + ((opex & 1) << 2);
955 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
956 opx = &ins->oprs[op1];
957 opex = 0; /* For the next iteration */
958
959 switch (c) {
960 case4(01):
961 codes += c, length += c;
962 break;
963
964 case3(05):
965 opex = c;
966 break;
967
968 case4(010):
969 ins->rex |=
970 op_rexflags(opx, REX_B|REX_H|REX_P|REX_W);
971 codes++, length++;
972 break;
973
974 case4(014):
975 /* this is an index reg of MIB operand */
976 mib_index = opx->basereg;
977 break;
978
979 case4(020):
980 case4(024):
981 length++;
982 break;
983
984 case4(030):
985 length += 2;
986 break;
987
988 case4(034):
989 if (opx->type & (BITS16 | BITS32 | BITS64))
990 length += (opx->type & BITS16) ? 2 : 4;
991 else
992 length += (bits == 16) ? 2 : 4;
993 break;
994
995 case4(040):
996 length += 4;
997 break;
998
999 case4(044):
1000 length += ins->addr_size >> 3;
1001 break;
1002
1003 case4(050):
1004 length++;
1005 break;
1006
1007 case4(054):
1008 length += 8; /* MOV reg64/imm */
1009 break;
1010
1011 case4(060):
1012 length += 2;
1013 break;
1014
1015 case4(064):
1016 if (opx->type & (BITS16 | BITS32 | BITS64))
1017 length += (opx->type & BITS16) ? 2 : 4;
1018 else
1019 length += (bits == 16) ? 2 : 4;
1020 break;
1021
1022 case4(070):
1023 length += 4;
1024 break;
1025
1026 case4(074):
1027 length += 2;
1028 break;
1029
1030 case 0172:
1031 case 0173:
1032 codes++;
1033 length++;
1034 break;
1035
1036 case4(0174):
1037 length++;
1038 break;
1039
1040 case4(0240):
1041 ins->rex |= REX_EV;
1042 ins->vexreg = regval(opx);
1043 ins->evex_p[2] |= op_evexflags(opx, EVEX_P2VP, 2); /* High-16 NDS */
1044 ins->vex_cm = *codes++;
1045 ins->vex_wlp = *codes++;
1046 ins->evex_tuple = (*codes++ - 0300);
1047 break;
1048
1049 case 0250:
1050 ins->rex |= REX_EV;
1051 ins->vexreg = 0;
1052 ins->vex_cm = *codes++;
1053 ins->vex_wlp = *codes++;
1054 ins->evex_tuple = (*codes++ - 0300);
1055 break;
1056
1057 case4(0254):
1058 length += 4;
1059 break;
1060
1061 case4(0260):
1062 ins->rex |= REX_V;
1063 ins->vexreg = regval(opx);
1064 ins->vex_cm = *codes++;
1065 ins->vex_wlp = *codes++;
1066 break;
1067
1068 case 0270:
1069 ins->rex |= REX_V;
1070 ins->vexreg = 0;
1071 ins->vex_cm = *codes++;
1072 ins->vex_wlp = *codes++;
1073 break;
1074
1075 case3(0271):
1076 hleok = c & 3;
1077 break;
1078
1079 case4(0274):
1080 length++;
1081 break;
1082
1083 case4(0300):
1084 break;
1085
1086 case 0310:
1087 if (bits == 64)
1088 return -1;
1089 length += (bits != 16) && !has_prefix(ins, PPS_ASIZE, P_A16);
1090 break;
1091
1092 case 0311:
1093 length += (bits != 32) && !has_prefix(ins, PPS_ASIZE, P_A32);
1094 break;
1095
1096 case 0312:
1097 break;
1098
1099 case 0313:
1100 if (bits != 64 || has_prefix(ins, PPS_ASIZE, P_A16) ||
1101 has_prefix(ins, PPS_ASIZE, P_A32))
1102 return -1;
1103 break;
1104
1105 case4(0314):
1106 break;
1107
1108 case 0320:
1109 {
1110 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1111 if (pfx == P_O16)
1112 break;
1113 if (pfx != P_none)
1114 nasm_error(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1115 else
1116 ins->prefixes[PPS_OSIZE] = P_O16;
1117 break;
1118 }
1119
1120 case 0321:
1121 {
1122 enum prefixes pfx = ins->prefixes[PPS_OSIZE];
1123 if (pfx == P_O32)
1124 break;
1125 if (pfx != P_none)
1126 nasm_error(ERR_WARNING | ERR_PASS2, "invalid operand size prefix");
1127 else
1128 ins->prefixes[PPS_OSIZE] = P_O32;
1129 break;
1130 }
1131
1132 case 0322:
1133 break;
1134
1135 case 0323:
1136 rex_mask &= ~REX_W;
1137 break;
1138
1139 case 0324:
1140 ins->rex |= REX_W;
1141 break;
1142
1143 case 0325:
1144 ins->rex |= REX_NH;
1145 break;
1146
1147 case 0326:
1148 break;
1149
1150 case 0330:
1151 codes++, length++;
1152 break;
1153
1154 case 0331:
1155 break;
1156
1157 case 0332:
1158 case 0333:
1159 length++;
1160 break;
1161
1162 case 0334:
1163 ins->rex |= REX_L;
1164 break;
1165
1166 case 0335:
1167 break;
1168
1169 case 0336:
1170 if (!ins->prefixes[PPS_REP])
1171 ins->prefixes[PPS_REP] = P_REP;
1172 break;
1173
1174 case 0337:
1175 if (!ins->prefixes[PPS_REP])
1176 ins->prefixes[PPS_REP] = P_REPNE;
1177 break;
1178
1179 case 0340:
1180 if (!absolute_op(&ins->oprs[0]))
1181 nasm_error(ERR_NONFATAL, "attempt to reserve non-constant"
1182 " quantity of BSS space");
1183 else if (ins->oprs[0].opflags & OPFLAG_FORWARD)
1184 nasm_error(ERR_WARNING | ERR_PASS1,
1185 "forward reference in RESx can have unpredictable results");
1186 else
1187 length += ins->oprs[0].offset;
1188 break;
1189
1190 case 0341:
1191 if (!ins->prefixes[PPS_WAIT])
1192 ins->prefixes[PPS_WAIT] = P_WAIT;
1193 break;
1194
1195 case 0360:
1196 break;
1197
1198 case 0361:
1199 length++;
1200 break;
1201
1202 case 0364:
1203 case 0365:
1204 break;
1205
1206 case 0366:
1207 case 0367:
1208 length++;
1209 break;
1210
1211 case 0370:
1212 case 0371:
1213 break;
1214
1215 case 0373:
1216 length++;
1217 break;
1218
1219 case 0374:
1220 eat = EA_XMMVSIB;
1221 break;
1222
1223 case 0375:
1224 eat = EA_YMMVSIB;
1225 break;
1226
1227 case 0376:
1228 eat = EA_ZMMVSIB;
1229 break;
1230
1231 case4(0100):
1232 case4(0110):
1233 case4(0120):
1234 case4(0130):
1235 case4(0200):
1236 case4(0204):
1237 case4(0210):
1238 case4(0214):
1239 case4(0220):
1240 case4(0224):
1241 case4(0230):
1242 case4(0234):
1243 {
1244 ea ea_data;
1245 int rfield;
1246 opflags_t rflags;
1247 struct operand *opy = &ins->oprs[op2];
1248 struct operand *op_er_sae;
1249
1250 ea_data.rex = 0; /* Ensure ea.REX is initially 0 */
1251
1252 if (c <= 0177) {
1253 /* pick rfield from operand b (opx) */
1254 rflags = regflag(opx);
1255 rfield = nasm_regvals[opx->basereg];
1256 } else {
1257 rflags = 0;
1258 rfield = c & 7;
1259 }
1260
1261 /* EVEX.b1 : evex_brerop contains the operand position */
1262 op_er_sae = (ins->evex_brerop >= 0 ?
1263 &ins->oprs[ins->evex_brerop] : NULL);
1264
1265 if (op_er_sae && (op_er_sae->decoflags & (ER | SAE))) {
1266 /* set EVEX.b */
1267 ins->evex_p[2] |= EVEX_P2B;
1268 if (op_er_sae->decoflags & ER) {
1269 /* set EVEX.RC (rounding control) */
1270 ins->evex_p[2] |= ((ins->evex_rm - BRC_RN) << 5)
1271 & EVEX_P2RC;
1272 }
1273 } else {
1274 /* set EVEX.L'L (vector length) */
1275 ins->evex_p[2] |= ((ins->vex_wlp << (5 - 2)) & EVEX_P2LL);
1276 ins->evex_p[1] |= ((ins->vex_wlp << (7 - 4)) & EVEX_P1W);
1277 if (opy->decoflags & BRDCAST_MASK) {
1278 /* set EVEX.b */
1279 ins->evex_p[2] |= EVEX_P2B;
1280 }
1281 }
1282
1283 if (itemp_has(temp, IF_MIB)) {
1284 opy->eaflags |= EAF_MIB;
1285 /*
1286 * if a separate form of MIB (ICC style) is used,
1287 * the index reg info is merged into mem operand
1288 */
1289 if (mib_index != R_none) {
1290 opy->indexreg = mib_index;
1291 opy->scale = 1;
1292 opy->hintbase = mib_index;
1293 opy->hinttype = EAH_NOTBASE;
1294 }
1295 }
1296
1297 if (process_ea(opy, &ea_data, bits,
1298 rfield, rflags, ins, &errmsg) != eat) {
1299 nasm_error(ERR_NONFATAL, "%s", errmsg);
1300 return -1;
1301 } else {
1302 ins->rex |= ea_data.rex;
1303 length += ea_data.size;
1304 }
1305 }
1306 break;
1307
1308 default:
1309 nasm_panic(0, "internal instruction table corrupt"
1310 ": instruction code \\%o (0x%02X) given", c, c);
1311 break;
1312 }
1313 }
1314
1315 ins->rex &= rex_mask;
1316
1317 if (ins->rex & REX_NH) {
1318 if (ins->rex & REX_H) {
1319 nasm_error(ERR_NONFATAL, "instruction cannot use high registers");
1320 return -1;
1321 }
1322 ins->rex &= ~REX_P; /* Don't force REX prefix due to high reg */
1323 }
1324
1325 switch (ins->prefixes[PPS_VEX]) {
1326 case P_EVEX:
1327 if (!(ins->rex & REX_EV))
1328 return -1;
1329 break;
1330 case P_VEX3:
1331 case P_VEX2:
1332 if (!(ins->rex & REX_V))
1333 return -1;
1334 break;
1335 default:
1336 break;
1337 }
1338
1339 if (ins->rex & (REX_V | REX_EV)) {
1340 int bad32 = REX_R|REX_W|REX_X|REX_B;
1341
1342 if (ins->rex & REX_H) {
1343 nasm_error(ERR_NONFATAL, "cannot use high register in AVX instruction");
1344 return -1;
1345 }
1346 switch (ins->vex_wlp & 060) {
1347 case 000:
1348 case 040:
1349 ins->rex &= ~REX_W;
1350 break;
1351 case 020:
1352 ins->rex |= REX_W;
1353 bad32 &= ~REX_W;
1354 break;
1355 case 060:
1356 /* Follow REX_W */
1357 break;
1358 }
1359
1360 if (bits != 64 && ((ins->rex & bad32) || ins->vexreg > 7)) {
1361 nasm_error(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1362 return -1;
1363 } else if (!(ins->rex & REX_EV) &&
1364 ((ins->vexreg > 15) || (ins->evex_p[0] & 0xf0))) {
1365 nasm_error(ERR_NONFATAL, "invalid high-16 register in non-AVX-512");
1366 return -1;
1367 }
1368 if (ins->rex & REX_EV)
1369 length += 4;
1370 else if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1371 ins->prefixes[PPS_VEX] == P_VEX3)
1372 length += 3;
1373 else
1374 length += 2;
1375 } else if (ins->rex & REX_MASK) {
1376 if (ins->rex & REX_H) {
1377 nasm_error(ERR_NONFATAL, "cannot use high register in rex instruction");
1378 return -1;
1379 } else if (bits == 64) {
1380 length++;
1381 } else if ((ins->rex & REX_L) &&
1382 !(ins->rex & (REX_P|REX_W|REX_X|REX_B)) &&
1383 iflag_cpu_level_ok(&cpu, IF_X86_64)) {
1384 /* LOCK-as-REX.R */
1385 assert_no_prefix(ins, PPS_LOCK);
1386 lockcheck = false; /* Already errored, no need for warning */
1387 length++;
1388 } else {
1389 nasm_error(ERR_NONFATAL, "invalid operands in non-64-bit mode");
1390 return -1;
1391 }
1392 }
1393
1394 if (has_prefix(ins, PPS_LOCK, P_LOCK) && lockcheck &&
1395 (!itemp_has(temp,IF_LOCK) || !is_class(MEMORY, ins->oprs[0].type))) {
1396 nasm_error(ERR_WARNING | ERR_WARN_LOCK | ERR_PASS2 ,
1397 "instruction is not lockable");
1398 }
1399
1400 bad_hle_warn(ins, hleok);
1401
1402 /*
1403 * when BND prefix is set by DEFAULT directive,
1404 * BND prefix is added to every appropriate instruction line
1405 * unless it is overridden by NOBND prefix.
1406 */
1407 if (globalbnd &&
1408 (itemp_has(temp, IF_BND) && !has_prefix(ins, PPS_REP, P_NOBND)))
1409 ins->prefixes[PPS_REP] = P_BND;
1410
1411 /*
1412 * Add length of legacy prefixes
1413 */
1414 length += emit_prefix(NULL, bits, ins);
1415
1416 return length;
1417 }
1418
1419 static inline void emit_rex(struct out_data *data, insn *ins)
1420 {
1421 if (data->bits == 64) {
1422 if ((ins->rex & REX_MASK) &&
1423 !(ins->rex & (REX_V | REX_EV)) &&
1424 !ins->rex_done) {
1425 uint8_t rex = (ins->rex & REX_MASK) | REX_P;
1426 out_rawbyte(data, rex);
1427 ins->rex_done = true;
1428 }
1429 }
1430 }
1431
1432 static int emit_prefix(struct out_data *data, const int bits, insn *ins)
1433 {
1434 int bytes = 0;
1435 int j;
1436
1437 for (j = 0; j < MAXPREFIX; j++) {
1438 uint8_t c = 0;
1439 switch (ins->prefixes[j]) {
1440 case P_WAIT:
1441 c = 0x9B;
1442 break;
1443 case P_LOCK:
1444 c = 0xF0;
1445 break;
1446 case P_REPNE:
1447 case P_REPNZ:
1448 case P_XACQUIRE:
1449 case P_BND:
1450 c = 0xF2;
1451 break;
1452 case P_REPE:
1453 case P_REPZ:
1454 case P_REP:
1455 case P_XRELEASE:
1456 c = 0xF3;
1457 break;
1458 case R_CS:
1459 if (bits == 64) {
1460 nasm_error(ERR_WARNING | ERR_PASS2,
1461 "cs segment base generated, but will be ignored in 64-bit mode");
1462 }
1463 c = 0x2E;
1464 break;
1465 case R_DS:
1466 if (bits == 64) {
1467 nasm_error(ERR_WARNING | ERR_PASS2,
1468 "ds segment base generated, but will be ignored in 64-bit mode");
1469 }
1470 c = 0x3E;
1471 break;
1472 case R_ES:
1473 if (bits == 64) {
1474 nasm_error(ERR_WARNING | ERR_PASS2,
1475 "es segment base generated, but will be ignored in 64-bit mode");
1476 }
1477 c = 0x26;
1478 break;
1479 case R_FS:
1480 c = 0x64;
1481 break;
1482 case R_GS:
1483 c = 0x65;
1484 break;
1485 case R_SS:
1486 if (bits == 64) {
1487 nasm_error(ERR_WARNING | ERR_PASS2,
1488 "ss segment base generated, but will be ignored in 64-bit mode");
1489 }
1490 c = 0x36;
1491 break;
1492 case R_SEGR6:
1493 case R_SEGR7:
1494 nasm_error(ERR_NONFATAL,
1495 "segr6 and segr7 cannot be used as prefixes");
1496 break;
1497 case P_A16:
1498 if (bits == 64) {
1499 nasm_error(ERR_NONFATAL,
1500 "16-bit addressing is not supported "
1501 "in 64-bit mode");
1502 } else if (bits != 16)
1503 c = 0x67;
1504 break;
1505 case P_A32:
1506 if (bits != 32)
1507 c = 0x67;
1508 break;
1509 case P_A64:
1510 if (bits != 64) {
1511 nasm_error(ERR_NONFATAL,
1512 "64-bit addressing is only supported "
1513 "in 64-bit mode");
1514 }
1515 break;
1516 case P_ASP:
1517 c = 0x67;
1518 break;
1519 case P_O16:
1520 if (bits != 16)
1521 c = 0x66;
1522 break;
1523 case P_O32:
1524 if (bits == 16)
1525 c = 0x66;
1526 break;
1527 case P_O64:
1528 /* REX.W */
1529 break;
1530 case P_OSP:
1531 c = 0x66;
1532 break;
1533 case P_EVEX:
1534 case P_VEX3:
1535 case P_VEX2:
1536 case P_NOBND:
1537 case P_none:
1538 break;
1539 default:
1540 nasm_panic(0, "invalid instruction prefix");
1541 }
1542 if (c) {
1543 if (data)
1544 out_rawbyte(data, c);
1545 bytes++;
1546 }
1547 }
1548 return bytes;
1549 }
1550
1551 static void gencode(struct out_data *data, insn *ins)
1552 {
1553 uint8_t c;
1554 uint8_t bytes[4];
1555 int64_t size;
1556 int op1, op2;
1557 struct operand *opx;
1558 const uint8_t *codes = data->itemp->code;
1559 uint8_t opex = 0;
1560 enum ea_type eat = EA_SCALAR;
1561 int r;
1562 const int bits = data->bits;
1563 const char *errmsg;
1564
1565 ins->rex_done = false;
1566
1567 emit_prefix(data, bits, ins);
1568
1569 while (*codes) {
1570 c = *codes++;
1571 op1 = (c & 3) + ((opex & 1) << 2);
1572 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
1573 opx = &ins->oprs[op1];
1574 opex = 0; /* For the next iteration */
1575
1576
1577 switch (c) {
1578 case 01:
1579 case 02:
1580 case 03:
1581 case 04:
1582 emit_rex(data, ins);
1583 out_rawdata(data, codes, c);
1584 codes += c;
1585 break;
1586
1587 case 05:
1588 case 06:
1589 case 07:
1590 opex = c;
1591 break;
1592
1593 case4(010):
1594 emit_rex(data, ins);
1595 out_rawbyte(data, *codes++ + (regval(opx) & 7));
1596 break;
1597
1598 case4(014):
1599 break;
1600
1601 case4(020):
1602 out_imm(data, opx, 1, OUT_WRAP);
1603 break;
1604
1605 case4(024):
1606 out_imm(data, opx, 1, OUT_UNSIGNED);
1607 break;
1608
1609 case4(030):
1610 out_imm(data, opx, 2, OUT_WRAP);
1611 break;
1612
1613 case4(034):
1614 if (opx->type & (BITS16 | BITS32))
1615 size = (opx->type & BITS16) ? 2 : 4;
1616 else
1617 size = (bits == 16) ? 2 : 4;
1618 out_imm(data, opx, size, OUT_WRAP);
1619 break;
1620
1621 case4(040):
1622 out_imm(data, opx, 4, OUT_WRAP);
1623 break;
1624
1625 case4(044):
1626 size = ins->addr_size >> 3;
1627 out_imm(data, opx, size, OUT_WRAP);
1628 break;
1629
1630 case4(050):
1631 if (opx->segment == data->segment) {
1632 int64_t delta = opx->offset - data->offset
1633 - (data->inslen - data->insoffs);
1634 if (delta > 127 || delta < -128)
1635 nasm_error(ERR_NONFATAL, "short jump is out of range");
1636 }
1637 out_reladdr(data, opx, 1);
1638 break;
1639
1640 case4(054):
1641 out_imm(data, opx, 8, OUT_WRAP);
1642 break;
1643
1644 case4(060):
1645 out_reladdr(data, opx, 2);
1646 break;
1647
1648 case4(064):
1649 if (opx->type & (BITS16 | BITS32 | BITS64))
1650 size = (opx->type & BITS16) ? 2 : 4;
1651 else
1652 size = (bits == 16) ? 2 : 4;
1653
1654 out_reladdr(data, opx, size);
1655 break;
1656
1657 case4(070):
1658 out_reladdr(data, opx, 4);
1659 break;
1660
1661 case4(074):
1662 if (opx->segment == NO_SEG)
1663 nasm_error(ERR_NONFATAL, "value referenced by FAR is not"
1664 " relocatable");
1665 out_segment(data, opx);
1666 break;
1667
1668 case 0172:
1669 {
1670 int mask = ins->prefixes[PPS_VEX] == P_EVEX ? 7 : 15;
1671 const struct operand *opy;
1672
1673 c = *codes++;
1674 opx = &ins->oprs[c >> 3];
1675 opy = &ins->oprs[c & 7];
1676 if (!absolute_op(opy)) {
1677 nasm_error(ERR_NONFATAL,
1678 "non-absolute expression not permitted as argument %d",
1679 c & 7);
1680 } else if (opy->offset & ~mask) {
1681 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1682 "is4 argument exceeds bounds");
1683 }
1684 c = opy->offset & mask;
1685 goto emit_is4;
1686 }
1687
1688 case 0173:
1689 c = *codes++;
1690 opx = &ins->oprs[c >> 4];
1691 c &= 15;
1692 goto emit_is4;
1693
1694 case4(0174):
1695 c = 0;
1696 emit_is4:
1697 r = nasm_regvals[opx->basereg];
1698 out_rawbyte(data, (r << 4) | ((r & 0x10) >> 1) | c);
1699 break;
1700
1701 case4(0254):
1702 if (absolute_op(opx) &&
1703 (int32_t)opx->offset != (int64_t)opx->offset) {
1704 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1705 "signed dword immediate exceeds bounds");
1706 }
1707 out_imm(data, opx, 4, OUT_SIGNED);
1708 break;
1709
1710 case4(0240):
1711 case 0250:
1712 codes += 3;
1713 ins->evex_p[2] |= op_evexflags(&ins->oprs[0],
1714 EVEX_P2Z | EVEX_P2AAA, 2);
1715 ins->evex_p[2] ^= EVEX_P2VP; /* 1's complement */
1716 bytes[0] = 0x62;
1717 /* EVEX.X can be set by either REX or EVEX for different reasons */
1718 bytes[1] = ((((ins->rex & 7) << 5) |
1719 (ins->evex_p[0] & (EVEX_P0X | EVEX_P0RP))) ^ 0xf0) |
1720 (ins->vex_cm & EVEX_P0MM);
1721 bytes[2] = ((ins->rex & REX_W) << (7 - 3)) |
1722 ((~ins->vexreg & 15) << 3) |
1723 (1 << 2) | (ins->vex_wlp & 3);
1724 bytes[3] = ins->evex_p[2];
1725 out_rawdata(data, bytes, 4);
1726 break;
1727
1728 case4(0260):
1729 case 0270:
1730 codes += 2;
1731 if (ins->vex_cm != 1 || (ins->rex & (REX_W|REX_X|REX_B)) ||
1732 ins->prefixes[PPS_VEX] == P_VEX3) {
1733 bytes[0] = (ins->vex_cm >> 6) ? 0x8f : 0xc4;
1734 bytes[1] = (ins->vex_cm & 31) | ((~ins->rex & 7) << 5);
1735 bytes[2] = ((ins->rex & REX_W) << (7-3)) |
1736 ((~ins->vexreg & 15)<< 3) | (ins->vex_wlp & 07);
1737 out_rawdata(data, bytes, 3);
1738 } else {
1739 bytes[0] = 0xc5;
1740 bytes[1] = ((~ins->rex & REX_R) << (7-2)) |
1741 ((~ins->vexreg & 15) << 3) | (ins->vex_wlp & 07);
1742 out_rawdata(data, bytes, 2);
1743 }
1744 break;
1745
1746 case 0271:
1747 case 0272:
1748 case 0273:
1749 break;
1750
1751 case4(0274):
1752 {
1753 uint64_t uv, um;
1754 int s;
1755
1756 if (absolute_op(opx)) {
1757 if (ins->rex & REX_W)
1758 s = 64;
1759 else if (ins->prefixes[PPS_OSIZE] == P_O16)
1760 s = 16;
1761 else if (ins->prefixes[PPS_OSIZE] == P_O32)
1762 s = 32;
1763 else
1764 s = bits;
1765
1766 um = (uint64_t)2 << (s-1);
1767 uv = opx->offset;
1768
1769 if (uv > 127 && uv < (uint64_t)-128 &&
1770 (uv < um-128 || uv > um-1)) {
1771 /* If this wasn't explicitly byte-sized, warn as though we
1772 * had fallen through to the imm16/32/64 case.
1773 */
1774 nasm_error(ERR_WARNING | ERR_PASS2 | ERR_WARN_NOV,
1775 "%s value exceeds bounds",
1776 (opx->type & BITS8) ? "signed byte" :
1777 s == 16 ? "word" :
1778 s == 32 ? "dword" :
1779 "signed dword");
1780 }
1781
1782 /* Output as a raw byte to avoid byte overflow check */
1783 out_rawbyte(data, (uint8_t)uv);
1784 } else {
1785 out_imm(data, opx, 1, OUT_WRAP); /* XXX: OUT_SIGNED? */
1786 }
1787 break;
1788 }
1789
1790 case4(0300):
1791 break;
1792
1793 case 0310:
1794 if (bits == 32 && !has_prefix(ins, PPS_ASIZE, P_A16))
1795 out_rawbyte(data, 0x67);
1796 break;
1797
1798 case 0311:
1799 if (bits != 32 && !has_prefix(ins, PPS_ASIZE, P_A32))
1800 out_rawbyte(data, 0x67);
1801 break;
1802
1803 case 0312:
1804 break;
1805
1806 case 0313:
1807 ins->rex = 0;
1808 break;
1809
1810 case4(0314):
1811 break;
1812
1813 case 0320:
1814 case 0321:
1815 break;
1816
1817 case 0322:
1818 case 0323:
1819 break;
1820
1821 case 0324:
1822 ins->rex |= REX_W;
1823 break;
1824
1825 case 0325:
1826 break;
1827
1828 case 0326:
1829 break;
1830
1831 case 0330:
1832 out_rawbyte(data, *codes++ ^ get_cond_opcode(ins->condition));
1833 break;
1834
1835 case 0331:
1836 break;
1837
1838 case 0332:
1839 case 0333:
1840 out_rawbyte(data, c - 0332 + 0xF2);
1841 break;
1842
1843 case 0334:
1844 if (ins->rex & REX_R)
1845 out_rawbyte(data, 0xF0);
1846 ins->rex &= ~(REX_L|REX_R);
1847 break;
1848
1849 case 0335:
1850 break;
1851
1852 case 0336:
1853 case 0337:
1854 break;
1855
1856 case 0340:
1857 if (ins->oprs[0].segment != NO_SEG)
1858 nasm_panic(0, "non-constant BSS size in pass two");
1859
1860 out_reserve(data, ins->oprs[0].offset);
1861 break;
1862
1863 case 0341:
1864 break;
1865
1866 case 0360:
1867 break;
1868
1869 case 0361:
1870 out_rawbyte(data, 0x66);
1871 break;
1872
1873 case 0364:
1874 case 0365:
1875 break;
1876
1877 case 0366:
1878 case 0367:
1879 out_rawbyte(data, c - 0366 + 0x66);
1880 break;
1881
1882 case3(0370):
1883 break;
1884
1885 case 0373:
1886 out_rawbyte(data, bits == 16 ? 3 : 5);
1887 break;
1888
1889 case 0374:
1890 eat = EA_XMMVSIB;
1891 break;
1892
1893 case 0375:
1894 eat = EA_YMMVSIB;
1895 break;
1896
1897 case 0376:
1898 eat = EA_ZMMVSIB;
1899 break;
1900
1901 case4(0100):
1902 case4(0110):
1903 case4(0120):
1904 case4(0130):
1905 case4(0200):
1906 case4(0204):
1907 case4(0210):
1908 case4(0214):
1909 case4(0220):
1910 case4(0224):
1911 case4(0230):
1912 case4(0234):
1913 {
1914 ea ea_data;
1915 int rfield;
1916 opflags_t rflags;
1917 uint8_t *p;
1918 struct operand *opy = &ins->oprs[op2];
1919
1920 if (c <= 0177) {
1921 /* pick rfield from operand b (opx) */
1922 rflags = regflag(opx);
1923 rfield = nasm_regvals[opx->basereg];
1924 } else {
1925 /* rfield is constant */
1926 rflags = 0;
1927 rfield = c & 7;
1928 }
1929
1930 if (process_ea(opy, &ea_data, bits,
1931 rfield, rflags, ins, &errmsg) != eat)
1932 nasm_error(ERR_NONFATAL, "%s", errmsg);
1933
1934 p = bytes;
1935 *p++ = ea_data.modrm;
1936 if (ea_data.sib_present)
1937 *p++ = ea_data.sib;
1938 out_rawdata(data, bytes, p - bytes);
1939
1940 /*
1941 * Make sure the address gets the right offset in case
1942 * the line breaks in the .lst file (BR 1197827)
1943 */
1944
1945 if (ea_data.bytes) {
1946 /* use compressed displacement, if available */
1947 if (ea_data.disp8) {
1948 out_rawbyte(data, ea_data.disp8);
1949 } else if (ea_data.rip) {
1950 out_reladdr(data, opy, ea_data.bytes);
1951 } else {
1952 int asize = ins->addr_size >> 3;
1953
1954 if (overflow_general(opy->offset, asize) ||
1955 signed_bits(opy->offset, ins->addr_size) !=
1956 signed_bits(opy->offset, ea_data.bytes << 3))
1957 warn_overflow(ea_data.bytes);
1958
1959 out_imm(data, opy, ea_data.bytes,
1960 (asize > ea_data.bytes)
1961 ? OUT_SIGNED : OUT_WRAP);
1962 }
1963 }
1964 }
1965 break;
1966
1967 default:
1968 nasm_panic(0, "internal instruction table corrupt"
1969 ": instruction code \\%o (0x%02X) given", c, c);
1970 break;
1971 }
1972 }
1973 }
1974
1975 static opflags_t regflag(const operand * o)
1976 {
1977 if (!is_register(o->basereg))
1978 nasm_panic(0, "invalid operand passed to regflag()");
1979 return nasm_reg_flags[o->basereg];
1980 }
1981
1982 static int32_t regval(const operand * o)
1983 {
1984 if (!is_register(o->basereg))
1985 nasm_panic(0, "invalid operand passed to regval()");
1986 return nasm_regvals[o->basereg];
1987 }
1988
1989 static int op_rexflags(const operand * o, int mask)
1990 {
1991 opflags_t flags;
1992 int val;
1993
1994 if (!is_register(o->basereg))
1995 nasm_panic(0, "invalid operand passed to op_rexflags()");
1996
1997 flags = nasm_reg_flags[o->basereg];
1998 val = nasm_regvals[o->basereg];
1999
2000 return rexflags(val, flags, mask);
2001 }
2002
2003 static int rexflags(int val, opflags_t flags, int mask)
2004 {
2005 int rex = 0;
2006
2007 if (val >= 0 && (val & 8))
2008 rex |= REX_B|REX_X|REX_R;
2009 if (flags & BITS64)
2010 rex |= REX_W;
2011 if (!(REG_HIGH & ~flags)) /* AH, CH, DH, BH */
2012 rex |= REX_H;
2013 else if (!(REG8 & ~flags) && val >= 4) /* SPL, BPL, SIL, DIL */
2014 rex |= REX_P;
2015
2016 return rex & mask;
2017 }
2018
2019 static int evexflags(int val, decoflags_t deco,
2020 int mask, uint8_t byte)
2021 {
2022 int evex = 0;
2023
2024 switch (byte) {
2025 case 0:
2026 if (val >= 0 && (val & 16))
2027 evex |= (EVEX_P0RP | EVEX_P0X);
2028 break;
2029 case 2:
2030 if (val >= 0 && (val & 16))
2031 evex |= EVEX_P2VP;
2032 if (deco & Z)
2033 evex |= EVEX_P2Z;
2034 if (deco & OPMASK_MASK)
2035 evex |= deco & EVEX_P2AAA;
2036 break;
2037 }
2038 return evex & mask;
2039 }
2040
2041 static int op_evexflags(const operand * o, int mask, uint8_t byte)
2042 {
2043 int val;
2044
2045 val = nasm_regvals[o->basereg];
2046
2047 return evexflags(val, o->decoflags, mask, byte);
2048 }
2049
2050 static enum match_result find_match(const struct itemplate **tempp,
2051 insn *instruction,
2052 int32_t segment, int64_t offset, int bits)
2053 {
2054 const struct itemplate *temp;
2055 enum match_result m, merr;
2056 opflags_t xsizeflags[MAX_OPERANDS];
2057 bool opsizemissing = false;
2058 int8_t broadcast = instruction->evex_brerop;
2059 int i;
2060
2061 /* broadcasting uses a different data element size */
2062 for (i = 0; i < instruction->operands; i++)
2063 if (i == broadcast)
2064 xsizeflags[i] = instruction->oprs[i].decoflags & BRSIZE_MASK;
2065 else
2066 xsizeflags[i] = instruction->oprs[i].type & SIZE_MASK;
2067
2068 merr = MERR_INVALOP;
2069
2070 for (temp = nasm_instructions[instruction->opcode];
2071 temp->opcode != I_none; temp++) {
2072 m = matches(temp, instruction, bits);
2073 if (m == MOK_JUMP) {
2074 if (jmp_match(segment, offset, bits, instruction, temp))
2075 m = MOK_GOOD;
2076 else
2077 m = MERR_INVALOP;
2078 } else if (m == MERR_OPSIZEMISSING && !itemp_has(temp, IF_SX)) {
2079 /*
2080 * Missing operand size and a candidate for fuzzy matching...
2081 */
2082 for (i = 0; i < temp->operands; i++)
2083 if (i == broadcast)
2084 xsizeflags[i] |= temp->deco[i] & BRSIZE_MASK;
2085 else
2086 xsizeflags[i] |= temp->opd[i] & SIZE_MASK;
2087 opsizemissing = true;
2088 }
2089 if (m > merr)
2090 merr = m;
2091 if (merr == MOK_GOOD)
2092 goto done;
2093 }
2094
2095 /* No match, but see if we can get a fuzzy operand size match... */
2096 if (!opsizemissing)
2097 goto done;
2098
2099 for (i = 0; i < instruction->operands; i++) {
2100 /*
2101 * We ignore extrinsic operand sizes on registers, so we should
2102 * never try to fuzzy-match on them. This also resolves the case
2103 * when we have e.g. "xmmrm128" in two different positions.
2104 */
2105 if (is_class(REGISTER, instruction->oprs[i].type))
2106 continue;
2107
2108 /* This tests if xsizeflags[i] has more than one bit set */
2109 if ((xsizeflags[i] & (xsizeflags[i]-1)))
2110 goto done; /* No luck */
2111
2112 if (i == broadcast) {
2113 instruction->oprs[i].decoflags |= xsizeflags[i];
2114 instruction->oprs[i].type |= (xsizeflags[i] == BR_BITS32 ?
2115 BITS32 : BITS64);
2116 } else {
2117 instruction->oprs[i].type |= xsizeflags[i]; /* Set the size */
2118 }
2119 }
2120
2121 /* Try matching again... */
2122 for (temp = nasm_instructions[instruction->opcode];
2123 temp->opcode != I_none; temp++) {
2124 m = matches(temp, instruction, bits);
2125 if (m == MOK_JUMP) {
2126 if (jmp_match(segment, offset, bits, instruction, temp))
2127 m = MOK_GOOD;
2128 else
2129 m = MERR_INVALOP;
2130 }
2131 if (m > merr)
2132 merr = m;
2133 if (merr == MOK_GOOD)
2134 goto done;
2135 }
2136
2137 done:
2138 *tempp = temp;
2139 return merr;
2140 }
2141
2142 static uint8_t get_broadcast_num(opflags_t opflags, opflags_t brsize)
2143 {
2144 unsigned int opsize = (opflags & SIZE_MASK) >> SIZE_SHIFT;
2145 uint8_t brcast_num;
2146
2147 if (brsize > BITS64)
2148 nasm_error(ERR_FATAL,
2149 "size of broadcasting element is greater than 64 bits");
2150
2151 /*
2152 * The shift term is to take care of the extra BITS80 inserted
2153 * between BITS64 and BITS128.
2154 */
2155 brcast_num = ((opsize / (BITS64 >> SIZE_SHIFT)) * (BITS64 / brsize))
2156 >> (opsize > (BITS64 >> SIZE_SHIFT));
2157
2158 return brcast_num;
2159 }
2160
2161 static enum match_result matches(const struct itemplate *itemp,
2162 insn *instruction, int bits)
2163 {
2164 opflags_t size[MAX_OPERANDS], asize;
2165 bool opsizemissing = false;
2166 int i, oprs;
2167
2168 /*
2169 * Check the opcode
2170 */
2171 if (itemp->opcode != instruction->opcode)
2172 return MERR_INVALOP;
2173
2174 /*
2175 * Count the operands
2176 */
2177 if (itemp->operands != instruction->operands)
2178 return MERR_INVALOP;
2179
2180 /*
2181 * Is it legal?
2182 */
2183 if (!(optimizing > 0) && itemp_has(itemp, IF_OPT))
2184 return MERR_INVALOP;
2185
2186 /*
2187 * {evex} available?
2188 */
2189 switch (instruction->prefixes[PPS_VEX]) {
2190 case P_EVEX:
2191 if (!itemp_has(itemp, IF_EVEX))
2192 return MERR_ENCMISMATCH;
2193 break;
2194 case P_VEX3:
2195 case P_VEX2:
2196 if (!itemp_has(itemp, IF_VEX))
2197 return MERR_ENCMISMATCH;
2198 break;
2199 default:
2200 break;
2201 }
2202
2203 /*
2204 * Check that no spurious colons or TOs are present
2205 */
2206 for (i = 0; i < itemp->operands; i++)
2207 if (instruction->oprs[i].type & ~itemp->opd[i] & (COLON | TO))
2208 return MERR_INVALOP;
2209
2210 /*
2211 * Process size flags
2212 */
2213 switch (itemp_smask(itemp)) {
2214 case IF_GENBIT(IF_SB):
2215 asize = BITS8;
2216 break;
2217 case IF_GENBIT(IF_SW):
2218 asize = BITS16;
2219 break;
2220 case IF_GENBIT(IF_SD):
2221 asize = BITS32;
2222 break;
2223 case IF_GENBIT(IF_SQ):
2224 asize = BITS64;
2225 break;
2226 case IF_GENBIT(IF_SO):
2227 asize = BITS128;
2228 break;
2229 case IF_GENBIT(IF_SY):
2230 asize = BITS256;
2231 break;
2232 case IF_GENBIT(IF_SZ):
2233 asize = BITS512;
2234 break;
2235 case IF_GENBIT(IF_SIZE):
2236 switch (bits) {
2237 case 16:
2238 asize = BITS16;
2239 break;
2240 case 32:
2241 asize = BITS32;
2242 break;
2243 case 64:
2244 asize = BITS64;
2245 break;
2246 default:
2247 asize = 0;
2248 break;
2249 }
2250 break;
2251 default:
2252 asize = 0;
2253 break;
2254 }
2255
2256 if (itemp_armask(itemp)) {
2257 /* S- flags only apply to a specific operand */
2258 i = itemp_arg(itemp);
2259 memset(size, 0, sizeof size);
2260 size[i] = asize;
2261 } else {
2262 /* S- flags apply to all operands */
2263 for (i = 0; i < MAX_OPERANDS; i++)
2264 size[i] = asize;
2265 }
2266
2267 /*
2268 * Check that the operand flags all match up,
2269 * it's a bit tricky so lets be verbose:
2270 *
2271 * 1) Find out the size of operand. If instruction
2272 * doesn't have one specified -- we're trying to
2273 * guess it either from template (IF_S* flag) or
2274 * from code bits.
2275 *
2276 * 2) If template operand do not match the instruction OR
2277 * template has an operand size specified AND this size differ
2278 * from which instruction has (perhaps we got it from code bits)
2279 * we are:
2280 * a) Check that only size of instruction and operand is differ
2281 * other characteristics do match
2282 * b) Perhaps it's a register specified in instruction so
2283 * for such a case we just mark that operand as "size
2284 * missing" and this will turn on fuzzy operand size
2285 * logic facility (handled by a caller)
2286 */
2287 for (i = 0; i < itemp->operands; i++) {
2288 opflags_t type = instruction->oprs[i].type;
2289 decoflags_t deco = instruction->oprs[i].decoflags;
2290 decoflags_t ideco = itemp->deco[i];
2291 bool is_broadcast = deco & BRDCAST_MASK;
2292 uint8_t brcast_num = 0;
2293 opflags_t template_opsize, insn_opsize;
2294
2295 if (!(type & SIZE_MASK))
2296 type |= size[i];
2297
2298 insn_opsize = type & SIZE_MASK;
2299 if (!is_broadcast) {
2300 template_opsize = itemp->opd[i] & SIZE_MASK;
2301 } else {
2302 decoflags_t deco_brsize = ideco & BRSIZE_MASK;
2303
2304 if (~ideco & BRDCAST_MASK)
2305 return MERR_BRNOTHERE;
2306
2307 /*
2308 * when broadcasting, the element size depends on
2309 * the instruction type. decorator flag should match.
2310 */
2311 if (deco_brsize) {
2312 template_opsize = (deco_brsize == BR_BITS32 ? BITS32 : BITS64);
2313 /* calculate the proper number : {1to<brcast_num>} */
2314 brcast_num = get_broadcast_num(itemp->opd[i], template_opsize);
2315 } else {
2316 template_opsize = 0;
2317 }
2318 }
2319
2320 if (~ideco & deco & OPMASK_MASK)
2321 return MERR_MASKNOTHERE;
2322
2323 if (~ideco & deco & (Z_MASK|STATICRND_MASK|SAE_MASK))
2324 return MERR_DECONOTHERE;
2325
2326 if (itemp->opd[i] & ~type & ~SIZE_MASK) {
2327 return MERR_INVALOP;
2328 } else if (template_opsize) {
2329 if (template_opsize != insn_opsize) {
2330 if (insn_opsize) {
2331 return MERR_INVALOP;
2332 } else if (!is_class(REGISTER, type)) {
2333 /*
2334 * Note: we don't honor extrinsic operand sizes for registers,
2335 * so "missing operand size" for a register should be
2336 * considered a wildcard match rather than an error.
2337 */
2338 opsizemissing = true;
2339 }
2340 } else if (is_broadcast &&
2341 (brcast_num !=
2342 (2U << ((deco & BRNUM_MASK) >> BRNUM_SHIFT)))) {
2343 /*
2344 * broadcasting opsize matches but the number of repeated memory
2345 * element does not match.
2346 * if 64b double precision float is broadcasted to ymm (256b),
2347 * broadcasting decorator must be {1to4}.
2348 */
2349 return MERR_BRNUMMISMATCH;
2350 }
2351 }
2352 }
2353
2354 if (opsizemissing)
2355 return MERR_OPSIZEMISSING;
2356
2357 /*
2358 * Check operand sizes
2359 */
2360 if (itemp_has(itemp, IF_SM) || itemp_has(itemp, IF_SM2)) {
2361 oprs = (itemp_has(itemp, IF_SM2) ? 2 : itemp->operands);
2362 for (i = 0; i < oprs; i++) {
2363 asize = itemp->opd[i] & SIZE_MASK;
2364 if (asize) {
2365 for (i = 0; i < oprs; i++)
2366 size[i] = asize;
2367 break;
2368 }
2369 }
2370 } else {
2371 oprs = itemp->operands;
2372 }
2373
2374 for (i = 0; i < itemp->operands; i++) {
2375 if (!(itemp->opd[i] & SIZE_MASK) &&
2376 (instruction->oprs[i].type & SIZE_MASK & ~size[i]))
2377 return MERR_OPSIZEMISMATCH;
2378 }
2379
2380 /*
2381 * Check template is okay at the set cpu level
2382 */
2383 if (iflag_cmp_cpu_level(&insns_flags[itemp->iflag_idx], &cpu) > 0)
2384 return MERR_BADCPU;
2385
2386 /*
2387 * Verify the appropriate long mode flag.
2388 */
2389 if (itemp_has(itemp, (bits == 64 ? IF_NOLONG : IF_LONG)))
2390 return MERR_BADMODE;
2391
2392 /*
2393 * If we have a HLE prefix, look for the NOHLE flag
2394 */
2395 if (itemp_has(itemp, IF_NOHLE) &&
2396 (has_prefix(instruction, PPS_REP, P_XACQUIRE) ||
2397 has_prefix(instruction, PPS_REP, P_XRELEASE)))
2398 return MERR_BADHLE;
2399
2400 /*
2401 * Check if special handling needed for Jumps
2402 */
2403 if ((itemp->code[0] & ~1) == 0370)
2404 return MOK_JUMP;
2405
2406 /*
2407 * Check if BND prefix is allowed.
2408 * Other 0xF2 (REPNE/REPNZ) prefix is prohibited.
2409 */
2410 if (!itemp_has(itemp, IF_BND) &&
2411 (has_prefix(instruction, PPS_REP, P_BND) ||
2412 has_prefix(instruction, PPS_REP, P_NOBND)))
2413 return MERR_BADBND;
2414 else if (itemp_has(itemp, IF_BND) &&
2415 (has_prefix(instruction, PPS_REP, P_REPNE) ||
2416 has_prefix(instruction, PPS_REP, P_REPNZ)))
2417 return MERR_BADREPNE;
2418
2419 return MOK_GOOD;
2420 }
2421
2422 /*
2423 * Check if ModR/M.mod should/can be 01.
2424 * - EAF_BYTEOFFS is set
2425 * - offset can fit in a byte when EVEX is not used
2426 * - offset can be compressed when EVEX is used
2427 */
2428 #define IS_MOD_01() (!(input->eaflags & EAF_WORDOFFS) && \
2429 (ins->rex & REX_EV ? seg == NO_SEG && !forw_ref && \
2430 is_disp8n(input, ins, &output->disp8) : \
2431 input->eaflags & EAF_BYTEOFFS || (o >= -128 && \
2432 o <= 127 && seg == NO_SEG && !forw_ref)))
2433
2434 static enum ea_type process_ea(operand *input, ea *output, int bits,
2435 int rfield, opflags_t rflags, insn *ins,
2436 const char **errmsg)
2437 {
2438 bool forw_ref = !!(input->opflags & OPFLAG_UNKNOWN);
2439 int addrbits = ins->addr_size;
2440 int eaflags = input->eaflags;
2441
2442 *errmsg = "invalid effective address"; /* Default error message */
2443
2444 output->type = EA_SCALAR;
2445 output->rip = false;
2446 output->disp8 = 0;
2447
2448 /* REX flags for the rfield operand */
2449 output->rex |= rexflags(rfield, rflags, REX_R | REX_P | REX_W | REX_H);
2450 /* EVEX.R' flag for the REG operand */
2451 ins->evex_p[0] |= evexflags(rfield, 0, EVEX_P0RP, 0);
2452
2453 if (is_class(REGISTER, input->type)) {
2454 /*
2455 * It's a direct register.
2456 */
2457 if (!is_register(input->basereg))
2458 goto err;
2459
2460 if (!is_reg_class(REG_EA, input->basereg))
2461 goto err;
2462
2463 /* broadcasting is not available with a direct register operand. */
2464 if (input->decoflags & BRDCAST_MASK) {
2465 *errmsg = "broadcast not allowed with register operand";
2466 goto err;
2467 }
2468
2469 output->rex |= op_rexflags(input, REX_B | REX_P | REX_W | REX_H);
2470 ins->evex_p[0] |= op_evexflags(input, EVEX_P0X, 0);
2471 output->sib_present = false; /* no SIB necessary */
2472 output->bytes = 0; /* no offset necessary either */
2473 output->modrm = GEN_MODRM(3, rfield, nasm_regvals[input->basereg]);
2474 } else {
2475 /*
2476 * It's a memory reference.
2477 */
2478
2479 /* Embedded rounding or SAE is not available with a mem ref operand. */
2480 if (input->decoflags & (ER | SAE)) {
2481 *errmsg = "embedded rounding is available only with "
2482 "register-register operations";
2483 goto err;
2484 }
2485
2486 if (input->basereg == -1 &&
2487 (input->indexreg == -1 || input->scale == 0)) {
2488 /*
2489 * It's a pure offset.
2490 */
2491 if (bits == 64 && ((input->type & IP_REL) == IP_REL)) {
2492 if (input->segment == NO_SEG ||
2493 (input->opflags & OPFLAG_RELATIVE)) {
2494 nasm_error(ERR_WARNING | ERR_PASS2,
2495 "absolute address can not be RIP-relative");
2496 input->type &= ~IP_REL;
2497 input->type |= MEMORY;
2498 }
2499 }
2500
2501 if (bits == 64 &&
2502 !(IP_REL & ~input->type) && (eaflags & EAF_MIB)) {
2503 *errmsg = "RIP-relative addressing is prohibited for MIB";
2504 goto err;
2505 }
2506
2507 if (eaflags & EAF_BYTEOFFS ||
2508 (eaflags & EAF_WORDOFFS &&
2509 input->disp_size != (addrbits != 16 ? 32 : 16))) {
2510 nasm_error(ERR_WARNING | ERR_PASS1,
2511 "displacement size ignored on absolute address");
2512 }
2513
2514 if (bits == 64 && (~input->type & IP_REL)) {
2515 output->sib_present = true;
2516 output->sib = GEN_SIB(0, 4, 5);
2517 output->bytes = 4;
2518 output->modrm = GEN_MODRM(0, rfield, 4);
2519 output->rip = false;
2520 } else {
2521 output->sib_present = false;
2522 output->bytes = (addrbits != 16 ? 4 : 2);
2523 output->modrm = GEN_MODRM(0, rfield,
2524 (addrbits != 16 ? 5 : 6));
2525 output->rip = bits == 64;
2526 }
2527 } else {
2528 /*
2529 * It's an indirection.
2530 */
2531 int i = input->indexreg, b = input->basereg, s = input->scale;
2532 int32_t seg = input->segment;
2533 int hb = input->hintbase, ht = input->hinttype;
2534 int t, it, bt; /* register numbers */
2535 opflags_t x, ix, bx; /* register flags */
2536
2537 if (s == 0)
2538 i = -1; /* make this easy, at least */
2539
2540 if (is_register(i)) {
2541 it = nasm_regvals[i];
2542 ix = nasm_reg_flags[i];
2543 } else {
2544 it = -1;
2545 ix = 0;
2546 }
2547
2548 if (is_register(b)) {
2549 bt = nasm_regvals[b];
2550 bx = nasm_reg_flags[b];
2551 } else {
2552 bt = -1;
2553 bx = 0;
2554 }
2555
2556 /* if either one are a vector register... */
2557 if ((ix|bx) & (XMMREG|YMMREG|ZMMREG) & ~REG_EA) {
2558 opflags_t sok = BITS32 | BITS64;
2559 int32_t o = input->offset;
2560 int mod, scale, index, base;
2561
2562 /*
2563 * For a vector SIB, one has to be a vector and the other,
2564 * if present, a GPR. The vector must be the index operand.
2565 */
2566 if (it == -1 || (bx & (XMMREG|YMMREG|ZMMREG) & ~REG_EA)) {
2567 if (s == 0)
2568 s = 1;
2569 else if (s != 1)
2570 goto err;
2571
2572 t = bt, bt = it, it = t;
2573 x = bx, bx = ix, ix = x;
2574 }
2575
2576 if (bt != -1) {
2577 if (REG_GPR & ~bx)
2578 goto err;
2579 if (!(REG64 & ~bx) || !(REG32 & ~bx))
2580 sok &= bx;
2581 else
2582 goto err;
2583 }
2584
2585 /*
2586 * While we're here, ensure the user didn't specify
2587 * WORD or QWORD
2588 */
2589 if (input->disp_size == 16 || input->disp_size == 64)
2590 goto err;
2591
2592 if (addrbits == 16 ||
2593 (addrbits == 32 && !(sok & BITS32)) ||
2594 (addrbits == 64 && !(sok & BITS64)))
2595 goto err;
2596
2597 output->type = ((ix & ZMMREG & ~REG_EA) ? EA_ZMMVSIB
2598 : ((ix & YMMREG & ~REG_EA)
2599 ? EA_YMMVSIB : EA_XMMVSIB));
2600
2601 output->rex |= rexflags(it, ix, REX_X);
2602 output->rex |= rexflags(bt, bx, REX_B);
2603 ins->evex_p[2] |= evexflags(it, 0, EVEX_P2VP, 2);
2604
2605 index = it & 7; /* it is known to be != -1 */
2606
2607 switch (s) {
2608 case 1:
2609 scale = 0;
2610 break;
2611 case 2:
2612 scale = 1;
2613 break;
2614 case 4:
2615 scale = 2;
2616 break;
2617 case 8:
2618 scale = 3;
2619 break;
2620 default: /* then what the smeg is it? */
2621 goto err; /* panic */
2622 }
2623
2624 if (bt == -1) {
2625 base = 5;
2626 mod = 0;
2627 } else {
2628 base = (bt & 7);
2629 if (base != REG_NUM_EBP && o == 0 &&
2630 seg == NO_SEG && !forw_ref &&
2631 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2632 mod = 0;
2633 else if (IS_MOD_01())
2634 mod = 1;
2635 else
2636 mod = 2;
2637 }
2638
2639 output->sib_present = true;
2640 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2641 output->modrm = GEN_MODRM(mod, rfield, 4);
2642 output->sib = GEN_SIB(scale, index, base);
2643 } else if ((ix|bx) & (BITS32|BITS64)) {
2644 /*
2645 * it must be a 32/64-bit memory reference. Firstly we have
2646 * to check that all registers involved are type E/Rxx.
2647 */
2648 opflags_t sok = BITS32 | BITS64;
2649 int32_t o = input->offset;
2650
2651 if (it != -1) {
2652 if (!(REG64 & ~ix) || !(REG32 & ~ix))
2653 sok &= ix;
2654 else
2655 goto err;
2656 }
2657
2658 if (bt != -1) {
2659 if (REG_GPR & ~bx)
2660 goto err; /* Invalid register */
2661 if (~sok & bx & SIZE_MASK)
2662 goto err; /* Invalid size */
2663 sok &= bx;
2664 }
2665
2666 /*
2667 * While we're here, ensure the user didn't specify
2668 * WORD or QWORD
2669 */
2670 if (input->disp_size == 16 || input->disp_size == 64)
2671 goto err;
2672
2673 if (addrbits == 16 ||
2674 (addrbits == 32 && !(sok & BITS32)) ||
2675 (addrbits == 64 && !(sok & BITS64)))
2676 goto err;
2677
2678 /* now reorganize base/index */
2679 if (s == 1 && bt != it && bt != -1 && it != -1 &&
2680 ((hb == b && ht == EAH_NOTBASE) ||
2681 (hb == i && ht == EAH_MAKEBASE))) {
2682 /* swap if hints say so */
2683 t = bt, bt = it, it = t;
2684 x = bx, bx = ix, ix = x;
2685 }
2686
2687 if (bt == -1 && s == 1 && !(hb == i && ht == EAH_NOTBASE)) {
2688 /* make single reg base, unless hint */
2689 bt = it, bx = ix, it = -1, ix = 0;
2690 }
2691 if (eaflags & EAF_MIB) {
2692 /* only for mib operands */
2693 if (it == -1 && (hb == b && ht == EAH_NOTBASE)) {
2694 /*
2695 * make a single reg index [reg*1].
2696 * gas uses this form for an explicit index register.
2697 */
2698 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2699 }
2700 if ((ht == EAH_SUMMED) && bt == -1) {
2701 /* separate once summed index into [base, index] */
2702 bt = it, bx = ix, s--;
2703 }
2704 } else {
2705 if (((s == 2 && it != REG_NUM_ESP &&
2706 (!(eaflags & EAF_TIMESTWO) || (ht == EAH_SUMMED))) ||
2707 s == 3 || s == 5 || s == 9) && bt == -1) {
2708 /* convert 3*EAX to EAX+2*EAX */
2709 bt = it, bx = ix, s--;
2710 }
2711 if (it == -1 && (bt & 7) != REG_NUM_ESP &&
2712 (eaflags & EAF_TIMESTWO) &&
2713 (hb == b && ht == EAH_NOTBASE)) {
2714 /*
2715 * convert [NOSPLIT EAX*1]
2716 * to sib format with 0x0 displacement - [EAX*1+0].
2717 */
2718 it = bt, ix = bx, bt = -1, bx = 0, s = 1;
2719 }
2720 }
2721 if (s == 1 && it == REG_NUM_ESP) {
2722 /* swap ESP into base if scale is 1 */
2723 t = it, it = bt, bt = t;
2724 x = ix, ix = bx, bx = x;
2725 }
2726 if (it == REG_NUM_ESP ||
2727 (s != 1 && s != 2 && s != 4 && s != 8 && it != -1))
2728 goto err; /* wrong, for various reasons */
2729
2730 output->rex |= rexflags(it, ix, REX_X);
2731 output->rex |= rexflags(bt, bx, REX_B);
2732
2733 if (it == -1 && (bt & 7) != REG_NUM_ESP) {
2734 /* no SIB needed */
2735 int mod, rm;
2736
2737 if (bt == -1) {
2738 rm = 5;
2739 mod = 0;
2740 } else {
2741 rm = (bt & 7);
2742 if (rm != REG_NUM_EBP && o == 0 &&
2743 seg == NO_SEG && !forw_ref &&
2744 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2745 mod = 0;
2746 else if (IS_MOD_01())
2747 mod = 1;
2748 else
2749 mod = 2;
2750 }
2751
2752 output->sib_present = false;
2753 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2754 output->modrm = GEN_MODRM(mod, rfield, rm);
2755 } else {
2756 /* we need a SIB */
2757 int mod, scale, index, base;
2758
2759 if (it == -1)
2760 index = 4, s = 1;
2761 else
2762 index = (it & 7);
2763
2764 switch (s) {
2765 case 1:
2766 scale = 0;
2767 break;
2768 case 2:
2769 scale = 1;
2770 break;
2771 case 4:
2772 scale = 2;
2773 break;
2774 case 8:
2775 scale = 3;
2776 break;
2777 default: /* then what the smeg is it? */
2778 goto err; /* panic */
2779 }
2780
2781 if (bt == -1) {
2782 base = 5;
2783 mod = 0;
2784 } else {
2785 base = (bt & 7);
2786 if (base != REG_NUM_EBP && o == 0 &&
2787 seg == NO_SEG && !forw_ref &&
2788 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2789 mod = 0;
2790 else if (IS_MOD_01())
2791 mod = 1;
2792 else
2793 mod = 2;
2794 }
2795
2796 output->sib_present = true;
2797 output->bytes = (bt == -1 || mod == 2 ? 4 : mod);
2798 output->modrm = GEN_MODRM(mod, rfield, 4);
2799 output->sib = GEN_SIB(scale, index, base);
2800 }
2801 } else { /* it's 16-bit */
2802 int mod, rm;
2803 int16_t o = input->offset;
2804
2805 /* check for 64-bit long mode */
2806 if (addrbits == 64)
2807 goto err;
2808
2809 /* check all registers are BX, BP, SI or DI */
2810 if ((b != -1 && b != R_BP && b != R_BX && b != R_SI && b != R_DI) ||
2811 (i != -1 && i != R_BP && i != R_BX && i != R_SI && i != R_DI))
2812 goto err;
2813
2814 /* ensure the user didn't specify DWORD/QWORD */
2815 if (input->disp_size == 32 || input->disp_size == 64)
2816 goto err;
2817
2818 if (s != 1 && i != -1)
2819 goto err; /* no can do, in 16-bit EA */
2820 if (b == -1 && i != -1) {
2821 int tmp = b;
2822 b = i;
2823 i = tmp;
2824 } /* swap */
2825 if ((b == R_SI || b == R_DI) && i != -1) {
2826 int tmp = b;
2827 b = i;
2828 i = tmp;
2829 }
2830 /* have BX/BP as base, SI/DI index */
2831 if (b == i)
2832 goto err; /* shouldn't ever happen, in theory */
2833 if (i != -1 && b != -1 &&
2834 (i == R_BP || i == R_BX || b == R_SI || b == R_DI))
2835 goto err; /* invalid combinations */
2836 if (b == -1) /* pure offset: handled above */
2837 goto err; /* so if it gets to here, panic! */
2838
2839 rm = -1;
2840 if (i != -1)
2841 switch (i * 256 + b) {
2842 case R_SI * 256 + R_BX:
2843 rm = 0;
2844 break;
2845 case R_DI * 256 + R_BX:
2846 rm = 1;
2847 break;
2848 case R_SI * 256 + R_BP:
2849 rm = 2;
2850 break;
2851 case R_DI * 256 + R_BP:
2852 rm = 3;
2853 break;
2854 } else
2855 switch (b) {
2856 case R_SI:
2857 rm = 4;
2858 break;
2859 case R_DI:
2860 rm = 5;
2861 break;
2862 case R_BP:
2863 rm = 6;
2864 break;
2865 case R_BX:
2866 rm = 7;
2867 break;
2868 }
2869 if (rm == -1) /* can't happen, in theory */
2870 goto err; /* so panic if it does */
2871
2872 if (o == 0 && seg == NO_SEG && !forw_ref && rm != 6 &&
2873 !(eaflags & (EAF_BYTEOFFS | EAF_WORDOFFS)))
2874 mod = 0;
2875 else if (IS_MOD_01())
2876 mod = 1;
2877 else
2878 mod = 2;
2879
2880 output->sib_present = false; /* no SIB - it's 16-bit */
2881 output->bytes = mod; /* bytes of offset needed */
2882 output->modrm = GEN_MODRM(mod, rfield, rm);
2883 }
2884 }
2885 }
2886
2887 output->size = 1 + output->sib_present + output->bytes;
2888 return output->type;
2889
2890 err:
2891 return output->type = EA_INVALID;
2892 }
2893
2894 static void add_asp(insn *ins, int addrbits)
2895 {
2896 int j, valid;
2897 int defdisp;
2898
2899 valid = (addrbits == 64) ? 64|32 : 32|16;
2900
2901 switch (ins->prefixes[PPS_ASIZE]) {
2902 case P_A16:
2903 valid &= 16;
2904 break;
2905 case P_A32:
2906 valid &= 32;
2907 break;
2908 case P_A64:
2909 valid &= 64;
2910 break;
2911 case P_ASP:
2912 valid &= (addrbits == 32) ? 16 : 32;
2913 break;
2914 default:
2915 break;
2916 }
2917
2918 for (j = 0; j < ins->operands; j++) {
2919 if (is_class(MEMORY, ins->oprs[j].type)) {
2920 opflags_t i, b;
2921
2922 /* Verify as Register */
2923 if (!is_register(ins->oprs[j].indexreg))
2924 i = 0;
2925 else
2926 i = nasm_reg_flags[ins->oprs[j].indexreg];
2927
2928 /* Verify as Register */
2929 if (!is_register(ins->oprs[j].basereg))
2930 b = 0;
2931 else
2932 b = nasm_reg_flags[ins->oprs[j].basereg];
2933
2934 if (ins->oprs[j].scale == 0)
2935 i = 0;
2936
2937 if (!i && !b) {
2938 int ds = ins->oprs[j].disp_size;
2939 if ((addrbits != 64 && ds > 8) ||
2940 (addrbits == 64 && ds == 16))
2941 valid &= ds;
2942 } else {
2943 if (!(REG16 & ~b))
2944 valid &= 16;
2945 if (!(REG32 & ~b))
2946 valid &= 32;
2947 if (!(REG64 & ~b))
2948 valid &= 64;
2949
2950 if (!(REG16 & ~i))
2951 valid &= 16;
2952 if (!(REG32 & ~i))
2953 valid &= 32;
2954 if (!(REG64 & ~i))
2955 valid &= 64;
2956 }
2957 }
2958 }
2959
2960 if (valid & addrbits) {
2961 ins->addr_size = addrbits;
2962 } else if (valid & ((addrbits == 32) ? 16 : 32)) {
2963 /* Add an address size prefix */
2964 ins->prefixes[PPS_ASIZE] = (addrbits == 32) ? P_A16 : P_A32;;
2965 ins->addr_size = (addrbits == 32) ? 16 : 32;
2966 } else {
2967 /* Impossible... */
2968 nasm_error(ERR_NONFATAL, "impossible combination of address sizes");
2969 ins->addr_size = addrbits; /* Error recovery */
2970 }
2971
2972 defdisp = ins->addr_size == 16 ? 16 : 32;
2973
2974 for (j = 0; j < ins->operands; j++) {
2975 if (!(MEM_OFFS & ~ins->oprs[j].type) &&
2976 (ins->oprs[j].disp_size ? ins->oprs[j].disp_size : defdisp) != ins->addr_size) {
2977 /*
2978 * mem_offs sizes must match the address size; if not,
2979 * strip the MEM_OFFS bit and match only EA instructions
2980 */
2981 ins->oprs[j].type &= ~(MEM_OFFS & ~MEMORY);
2982 }
2983 }
2984 }
The Netwide Assembler