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insns.pl: allow relaxed forms to be created without duplication
[nasm.git] / disasm.c
bloba48a015340b990bc292512dbfdfc661448489729
1 /* disasm.c where all the _work_ gets done in the Netwide Disassembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
7 *
8 * initial version 27/iii/95 by Simon Tatham
9 */
10
11 #include "compiler.h"
12
13 #include <stdio.h>
14 #include <string.h>
15 #include <limits.h>
16 #include <inttypes.h>
17
18 #include "nasm.h"
19 #include "disasm.h"
20 #include "sync.h"
21 #include "insns.h"
22 #include "tables.h"
23 #include "regdis.h"
24
25 /*
26 * Flags that go into the `segment' field of `insn' structures
27 * during disassembly.
28 */
29 #define SEG_RELATIVE 1
30 #define SEG_32BIT 2
31 #define SEG_RMREG 4
32 #define SEG_DISP8 8
33 #define SEG_DISP16 16
34 #define SEG_DISP32 32
35 #define SEG_NODISP 64
36 #define SEG_SIGNED 128
37 #define SEG_64BIT 256
38
39 /*
40 * Prefix information
41 */
42 struct prefix_info {
43 uint8_t osize; /* Operand size */
44 uint8_t asize; /* Address size */
45 uint8_t osp; /* Operand size prefix present */
46 uint8_t asp; /* Address size prefix present */
47 uint8_t rep; /* Rep prefix present */
48 uint8_t seg; /* Segment override prefix present */
49 uint8_t wait; /* WAIT "prefix" present */
50 uint8_t lock; /* Lock prefix present */
51 uint8_t vex[3]; /* VEX prefix present */
52 uint8_t vex_c; /* VEX "class" (VEX, XOP, ...) */
53 uint8_t vex_m; /* VEX.M field */
54 uint8_t vex_v;
55 uint8_t vex_lp; /* VEX.LP fields */
56 uint32_t rex; /* REX prefix present */
57 };
58
59 #define getu8(x) (*(uint8_t *)(x))
60 #if X86_MEMORY
61 /* Littleendian CPU which can handle unaligned references */
62 #define getu16(x) (*(uint16_t *)(x))
63 #define getu32(x) (*(uint32_t *)(x))
64 #define getu64(x) (*(uint64_t *)(x))
65 #else
66 static uint16_t getu16(uint8_t *data)
67 {
68 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
69 }
70 static uint32_t getu32(uint8_t *data)
71 {
72 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
73 }
74 static uint64_t getu64(uint8_t *data)
75 {
76 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
77 }
78 #endif
79
80 #define gets8(x) ((int8_t)getu8(x))
81 #define gets16(x) ((int16_t)getu16(x))
82 #define gets32(x) ((int32_t)getu32(x))
83 #define gets64(x) ((int64_t)getu64(x))
84
85 /* Important: regval must already have been adjusted for rex extensions */
86 static enum reg_enum whichreg(int32_t regflags, int regval, int rex)
87 {
88 if (!(regflags & (REGISTER|REGMEM)))
89 return 0; /* Registers not permissible?! */
90
91 regflags |= REGISTER;
92
93 if (!(REG_AL & ~regflags))
94 return R_AL;
95 if (!(REG_AX & ~regflags))
96 return R_AX;
97 if (!(REG_EAX & ~regflags))
98 return R_EAX;
99 if (!(REG_RAX & ~regflags))
100 return R_RAX;
101 if (!(REG_DL & ~regflags))
102 return R_DL;
103 if (!(REG_DX & ~regflags))
104 return R_DX;
105 if (!(REG_EDX & ~regflags))
106 return R_EDX;
107 if (!(REG_RDX & ~regflags))
108 return R_RDX;
109 if (!(REG_CL & ~regflags))
110 return R_CL;
111 if (!(REG_CX & ~regflags))
112 return R_CX;
113 if (!(REG_ECX & ~regflags))
114 return R_ECX;
115 if (!(REG_RCX & ~regflags))
116 return R_RCX;
117 if (!(FPU0 & ~regflags))
118 return R_ST0;
119 if (!(XMM0 & ~regflags))
120 return R_XMM0;
121 if (!(YMM0 & ~regflags))
122 return R_YMM0;
123 if (!(REG_CS & ~regflags))
124 return (regval == 1) ? R_CS : 0;
125 if (!(REG_DESS & ~regflags))
126 return (regval == 0 || regval == 2
127 || regval == 3 ? nasm_rd_sreg[regval] : 0);
128 if (!(REG_FSGS & ~regflags))
129 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
130 if (!(REG_SEG67 & ~regflags))
131 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
132
133 /* All the entries below look up regval in an 16-entry array */
134 if (regval < 0 || regval > 15)
135 return 0;
136
137 if (!(REG8 & ~regflags)) {
138 if (rex & REX_P)
139 return nasm_rd_reg8_rex[regval];
140 else
141 return nasm_rd_reg8[regval];
142 }
143 if (!(REG16 & ~regflags))
144 return nasm_rd_reg16[regval];
145 if (!(REG32 & ~regflags))
146 return nasm_rd_reg32[regval];
147 if (!(REG64 & ~regflags))
148 return nasm_rd_reg64[regval];
149 if (!(REG_SREG & ~regflags))
150 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
151 if (!(REG_CREG & ~regflags))
152 return nasm_rd_creg[regval];
153 if (!(REG_DREG & ~regflags))
154 return nasm_rd_dreg[regval];
155 if (!(REG_TREG & ~regflags)) {
156 if (rex & REX_P)
157 return 0; /* TR registers are ill-defined with rex */
158 return nasm_rd_treg[regval];
159 }
160 if (!(FPUREG & ~regflags))
161 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
162 if (!(MMXREG & ~regflags))
163 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
164 if (!(XMMREG & ~regflags))
165 return nasm_rd_xmmreg[regval];
166 if (!(YMMREG & ~regflags))
167 return nasm_rd_ymmreg[regval];
168
169 return 0;
170 }
171
172 /*
173 * Process a DREX suffix
174 */
175 static uint8_t *do_drex(uint8_t *data, insn *ins)
176 {
177 uint8_t drex = *data++;
178 operand *dst = &ins->oprs[ins->drexdst];
179
180 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
181 return NULL; /* OC0 mismatch */
182 ins->rex = (ins->rex & ~7) | (drex & 7);
183
184 dst->segment = SEG_RMREG;
185 dst->basereg = drex >> 4;
186 return data;
187 }
188
189
190 /*
191 * Process an effective address (ModRM) specification.
192 */
193 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
194 int segsize, operand * op, insn *ins)
195 {
196 int mod, rm, scale, index, base;
197 int rex;
198 uint8_t sib = 0;
199
200 mod = (modrm >> 6) & 03;
201 rm = modrm & 07;
202
203 if (mod != 3 && rm == 4 && asize != 16)
204 sib = *data++;
205
206 if (ins->rex & REX_D) {
207 data = do_drex(data, ins);
208 if (!data)
209 return NULL;
210 }
211 rex = ins->rex;
212
213 if (mod == 3) { /* pure register version */
214 op->basereg = rm+(rex & REX_B ? 8 : 0);
215 op->segment |= SEG_RMREG;
216 return data;
217 }
218
219 op->disp_size = 0;
220 op->eaflags = 0;
221
222 if (asize == 16) {
223 /*
224 * <mod> specifies the displacement size (none, byte or
225 * word), and <rm> specifies the register combination.
226 * Exception: mod=0,rm=6 does not specify [BP] as one might
227 * expect, but instead specifies [disp16].
228 */
229 op->indexreg = op->basereg = -1;
230 op->scale = 1; /* always, in 16 bits */
231 switch (rm) {
232 case 0:
233 op->basereg = R_BX;
234 op->indexreg = R_SI;
235 break;
236 case 1:
237 op->basereg = R_BX;
238 op->indexreg = R_DI;
239 break;
240 case 2:
241 op->basereg = R_BP;
242 op->indexreg = R_SI;
243 break;
244 case 3:
245 op->basereg = R_BP;
246 op->indexreg = R_DI;
247 break;
248 case 4:
249 op->basereg = R_SI;
250 break;
251 case 5:
252 op->basereg = R_DI;
253 break;
254 case 6:
255 op->basereg = R_BP;
256 break;
257 case 7:
258 op->basereg = R_BX;
259 break;
260 }
261 if (rm == 6 && mod == 0) { /* special case */
262 op->basereg = -1;
263 if (segsize != 16)
264 op->disp_size = 16;
265 mod = 2; /* fake disp16 */
266 }
267 switch (mod) {
268 case 0:
269 op->segment |= SEG_NODISP;
270 break;
271 case 1:
272 op->segment |= SEG_DISP8;
273 op->offset = (int8_t)*data++;
274 break;
275 case 2:
276 op->segment |= SEG_DISP16;
277 op->offset = *data++;
278 op->offset |= ((unsigned)*data++) << 8;
279 break;
280 }
281 return data;
282 } else {
283 /*
284 * Once again, <mod> specifies displacement size (this time
285 * none, byte or *dword*), while <rm> specifies the base
286 * register. Again, [EBP] is missing, replaced by a pure
287 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
288 * and RIP-relative addressing in 64-bit mode.
289 *
290 * However, rm=4
291 * indicates not a single base register, but instead the
292 * presence of a SIB byte...
293 */
294 int a64 = asize == 64;
295
296 op->indexreg = -1;
297
298 if (a64)
299 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
300 else
301 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
302
303 if (rm == 5 && mod == 0) {
304 if (segsize == 64) {
305 op->eaflags |= EAF_REL;
306 op->segment |= SEG_RELATIVE;
307 mod = 2; /* fake disp32 */
308 }
309
310 if (asize != 64)
311 op->disp_size = asize;
312
313 op->basereg = -1;
314 mod = 2; /* fake disp32 */
315 }
316
317 if (rm == 4) { /* process SIB */
318 scale = (sib >> 6) & 03;
319 index = (sib >> 3) & 07;
320 base = sib & 07;
321
322 op->scale = 1 << scale;
323
324 if (index == 4 && !(rex & REX_X))
325 op->indexreg = -1; /* ESP/RSP cannot be an index */
326 else if (a64)
327 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
328 else
329 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
330
331 if (base == 5 && mod == 0) {
332 op->basereg = -1;
333 mod = 2; /* Fake disp32 */
334 } else if (a64)
335 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
336 else
337 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
338
339 if (segsize == 16)
340 op->disp_size = 32;
341 }
342
343 switch (mod) {
344 case 0:
345 op->segment |= SEG_NODISP;
346 break;
347 case 1:
348 op->segment |= SEG_DISP8;
349 op->offset = gets8(data);
350 data++;
351 break;
352 case 2:
353 op->segment |= SEG_DISP32;
354 op->offset = gets32(data);
355 data += 4;
356 break;
357 }
358 return data;
359 }
360 }
361
362 /*
363 * Determine whether the instruction template in t corresponds to the data
364 * stream in data. Return the number of bytes matched if so.
365 */
366 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
367
368 static int matches(const struct itemplate *t, uint8_t *data,
369 const struct prefix_info *prefix, int segsize, insn *ins)
370 {
371 uint8_t *r = (uint8_t *)(t->code);
372 uint8_t *origdata = data;
373 bool a_used = false, o_used = false;
374 enum prefixes drep = 0;
375 enum prefixes dwait = 0;
376 uint8_t lock = prefix->lock;
377 int osize = prefix->osize;
378 int asize = prefix->asize;
379 int i, c;
380 int op1, op2;
381 struct operand *opx, *opy;
382 uint8_t opex = 0;
383 int s_field_for = -1; /* No 144/154 series code encountered */
384 bool vex_ok = false;
385 int regmask = (segsize == 64) ? 15 : 7;
386
387 for (i = 0; i < MAX_OPERANDS; i++) {
388 ins->oprs[i].segment = ins->oprs[i].disp_size =
389 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
390 }
391 ins->condition = -1;
392 ins->rex = prefix->rex;
393 memset(ins->prefixes, 0, sizeof ins->prefixes);
394
395 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
396 return false;
397
398 if (prefix->rep == 0xF2)
399 drep = P_REPNE;
400 else if (prefix->rep == 0xF3)
401 drep = P_REP;
402
403 dwait = prefix->wait ? P_WAIT : 0;
404
405 while ((c = *r++) != 0) {
406 op1 = (c & 3) + ((opex & 1) << 2);
407 op2 = ((c >> 3) & 3) + ((opex & 2) << 1);
408 opx = &ins->oprs[op1];
409 opy = &ins->oprs[op2];
410 opex = 0;
411
412 switch (c) {
413 case 01:
414 case 02:
415 case 03:
416 case 04:
417 while (c--)
418 if (*r++ != *data++)
419 return false;
420 break;
421
422 case 05:
423 case 06:
424 case 07:
425 opex = c;
426 break;
427
428 case4(010):
429 {
430 int t = *r++, d = *data++;
431 if (d < t || d > t + 7)
432 return false;
433 else {
434 opx->basereg = (d-t)+
435 (ins->rex & REX_B ? 8 : 0);
436 opx->segment |= SEG_RMREG;
437 }
438 break;
439 }
440
441 case4(014):
442 case4(0274):
443 opx->offset = (int8_t)*data++;
444 opx->segment |= SEG_SIGNED;
445 break;
446
447 case4(020):
448 opx->offset = *data++;
449 break;
450
451 case4(024):
452 opx->offset = *data++;
453 break;
454
455 case4(030):
456 opx->offset = getu16(data);
457 data += 2;
458 break;
459
460 case4(034):
461 if (osize == 32) {
462 opx->offset = getu32(data);
463 data += 4;
464 } else {
465 opx->offset = getu16(data);
466 data += 2;
467 }
468 if (segsize != asize)
469 opx->disp_size = asize;
470 break;
471
472 case4(040):
473 case4(0254):
474 opx->offset = getu32(data);
475 data += 4;
476 break;
477
478 case4(044):
479 switch (asize) {
480 case 16:
481 opx->offset = getu16(data);
482 data += 2;
483 if (segsize != 16)
484 opx->disp_size = 16;
485 break;
486 case 32:
487 opx->offset = getu32(data);
488 data += 4;
489 if (segsize == 16)
490 opx->disp_size = 32;
491 break;
492 case 64:
493 opx->offset = getu64(data);
494 opx->disp_size = 64;
495 data += 8;
496 break;
497 }
498 break;
499
500 case4(050):
501 opx->offset = gets8(data++);
502 opx->segment |= SEG_RELATIVE;
503 break;
504
505 case4(054):
506 opx->offset = getu64(data);
507 data += 8;
508 break;
509
510 case4(060):
511 opx->offset = gets16(data);
512 data += 2;
513 opx->segment |= SEG_RELATIVE;
514 opx->segment &= ~SEG_32BIT;
515 break;
516
517 case4(064):
518 opx->segment |= SEG_RELATIVE;
519 if (osize == 16) {
520 opx->offset = gets16(data);
521 data += 2;
522 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
523 } else if (osize == 32) {
524 opx->offset = gets32(data);
525 data += 4;
526 opx->segment &= ~SEG_64BIT;
527 opx->segment |= SEG_32BIT;
528 }
529 if (segsize != osize) {
530 opx->type =
531 (opx->type & ~SIZE_MASK)
532 | ((osize == 16) ? BITS16 : BITS32);
533 }
534 break;
535
536 case4(070):
537 opx->offset = gets32(data);
538 data += 4;
539 opx->segment |= SEG_32BIT | SEG_RELATIVE;
540 break;
541
542 case4(0100):
543 case4(0110):
544 case4(0120):
545 case4(0130):
546 {
547 int modrm = *data++;
548 opx->segment |= SEG_RMREG;
549 data = do_ea(data, modrm, asize, segsize, opy, ins);
550 if (!data)
551 return false;
552 opx->basereg = ((modrm >> 3) & 7) + (ins->rex & REX_R ? 8 : 0);
553 break;
554 }
555
556 case4(0140):
557 if (s_field_for == op1) {
558 opx->offset = gets8(data);
559 data++;
560 } else {
561 opx->offset = getu16(data);
562 data += 2;
563 }
564 break;
565
566 case4(0144):
567 case4(0154):
568 s_field_for = (*data & 0x02) ? op1 : -1;
569 if ((*data++ & ~0x02) != *r++)
570 return false;
571 break;
572
573 case4(0150):
574 if (s_field_for == op1) {
575 opx->offset = gets8(data);
576 data++;
577 } else {
578 opx->offset = getu32(data);
579 data += 4;
580 }
581 break;
582
583 case4(0160):
584 ins->rex |= REX_D;
585 ins->drexdst = op1;
586 break;
587
588 case4(0164):
589 ins->rex |= REX_D|REX_OC;
590 ins->drexdst = op1;
591 break;
592
593 case 0171:
594 data = do_drex(data, ins);
595 if (!data)
596 return false;
597 break;
598
599 case 0172:
600 {
601 uint8_t ximm = *data++;
602 c = *r++;
603 ins->oprs[c >> 3].basereg = (ximm >> 4) & regmask;
604 ins->oprs[c >> 3].segment |= SEG_RMREG;
605 ins->oprs[c & 7].offset = ximm & 15;
606 }
607 break;
608
609 case 0173:
610 {
611 uint8_t ximm = *data++;
612 c = *r++;
613
614 if ((c ^ ximm) & 15)
615 return false;
616
617 ins->oprs[c >> 4].basereg = (ximm >> 4) & regmask;
618 ins->oprs[c >> 4].segment |= SEG_RMREG;
619 }
620 break;
621
622 case 0174:
623 {
624 uint8_t ximm = *data++;
625 c = *r++;
626
627 ins->oprs[c].basereg = (ximm >> 4) & regmask;
628 ins->oprs[c].segment |= SEG_RMREG;
629 }
630 break;
631
632 case4(0200):
633 case4(0204):
634 case4(0210):
635 case4(0214):
636 case4(0220):
637 case4(0224):
638 case4(0230):
639 case4(0234):
640 {
641 int modrm = *data++;
642 if (((modrm >> 3) & 07) != (c & 07))
643 return false; /* spare field doesn't match up */
644 data = do_ea(data, modrm, asize, segsize, opy, ins);
645 if (!data)
646 return false;
647 break;
648 }
649
650 case4(0260):
651 {
652 int vexm = *r++;
653 int vexwlp = *r++;
654 ins->rex |= REX_V;
655 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
656 return false;
657
658 if ((vexm & 0x1f) != prefix->vex_m)
659 return false;
660
661 switch (vexwlp & 030) {
662 case 000:
663 if (prefix->rex & REX_W)
664 return false;
665 break;
666 case 010:
667 if (!(prefix->rex & REX_W))
668 return false;
669 ins->rex &= ~REX_W;
670 break;
671 case 020: /* VEX.W is a don't care */
672 ins->rex &= ~REX_W;
673 break;
674 case 030:
675 break;
676 }
677
678 if ((vexwlp & 007) != prefix->vex_lp)
679 return false;
680
681 opx->segment |= SEG_RMREG;
682 opx->basereg = prefix->vex_v;
683 vex_ok = true;
684 break;
685 }
686
687 case 0270:
688 {
689 int vexm = *r++;
690 int vexwlp = *r++;
691 ins->rex |= REX_V;
692 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
693 return false;
694
695 if ((vexm & 0x1f) != prefix->vex_m)
696 return false;
697
698 switch (vexwlp & 030) {
699 case 000:
700 if (ins->rex & REX_W)
701 return false;
702 break;
703 case 010:
704 if (!(ins->rex & REX_W))
705 return false;
706 break;
707 default:
708 break; /* Need to do anything special here? */
709 }
710
711 if ((vexwlp & 007) != prefix->vex_lp)
712 return false;
713
714 if (prefix->vex_v != 0)
715 return false;
716
717 vex_ok = true;
718 break;
719 }
720
721 case 0310:
722 if (asize != 16)
723 return false;
724 else
725 a_used = true;
726 break;
727
728 case 0311:
729 if (asize == 16)
730 return false;
731 else
732 a_used = true;
733 break;
734
735 case 0312:
736 if (asize != segsize)
737 return false;
738 else
739 a_used = true;
740 break;
741
742 case 0313:
743 if (asize != 64)
744 return false;
745 else
746 a_used = true;
747 break;
748
749 case 0314:
750 if (prefix->rex & REX_B)
751 return false;
752 break;
753
754 case 0315:
755 if (prefix->rex & REX_X)
756 return false;
757 break;
758
759 case 0316:
760 if (prefix->rex & REX_R)
761 return false;
762 break;
763
764 case 0317:
765 if (prefix->rex & REX_W)
766 return false;
767 break;
768
769 case 0320:
770 if (osize != 16)
771 return false;
772 else
773 o_used = true;
774 break;
775
776 case 0321:
777 if (osize != 32)
778 return false;
779 else
780 o_used = true;
781 break;
782
783 case 0322:
784 if (osize != (segsize == 16) ? 16 : 32)
785 return false;
786 else
787 o_used = true;
788 break;
789
790 case 0323:
791 ins->rex |= REX_W; /* 64-bit only instruction */
792 osize = 64;
793 o_used = true;
794 break;
795
796 case 0324:
797 if (!(ins->rex & (REX_P|REX_W)) || osize != 64)
798 return false;
799 o_used = true;
800 break;
801
802 case 0330:
803 {
804 int t = *r++, d = *data++;
805 if (d < t || d > t + 15)
806 return false;
807 else
808 ins->condition = d - t;
809 break;
810 }
811
812 case 0331:
813 if (prefix->rep)
814 return false;
815 break;
816
817 case 0332:
818 if (prefix->rep != 0xF2)
819 return false;
820 drep = 0;
821 break;
822
823 case 0333:
824 if (prefix->rep != 0xF3)
825 return false;
826 drep = 0;
827 break;
828
829 case 0334:
830 if (lock) {
831 ins->rex |= REX_R;
832 lock = 0;
833 }
834 break;
835
836 case 0335:
837 if (drep == P_REP)
838 drep = P_REPE;
839 break;
840
841 case 0336:
842 case 0337:
843 break;
844
845 case 0340:
846 return false;
847
848 case 0341:
849 if (prefix->wait != 0x9B)
850 return false;
851 dwait = 0;
852 break;
853
854 case4(0344):
855 ins->oprs[0].basereg = (*data++ >> 3) & 7;
856 break;
857
858 case 0360:
859 if (prefix->osp || prefix->rep)
860 return false;
861 break;
862
863 case 0361:
864 if (!prefix->osp || prefix->rep)
865 return false;
866 o_used = true;
867 break;
868
869 case 0362:
870 if (prefix->osp || prefix->rep != 0xf2)
871 return false;
872 drep = 0;
873 break;
874
875 case 0363:
876 if (prefix->osp || prefix->rep != 0xf3)
877 return false;
878 drep = 0;
879 break;
880
881 case 0364:
882 if (prefix->osp)
883 return false;
884 break;
885
886 case 0365:
887 if (prefix->asp)
888 return false;
889 break;
890
891 case 0366:
892 if (!prefix->osp)
893 return false;
894 o_used = true;
895 break;
896
897 case 0367:
898 if (!prefix->asp)
899 return false;
900 a_used = true;
901 break;
902
903 default:
904 return false; /* Unknown code */
905 }
906 }
907
908 if (!vex_ok && (ins->rex & REX_V))
909 return false;
910
911 /* REX cannot be combined with DREX or VEX */
912 if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
913 return false;
914
915 /*
916 * Check for unused rep or a/o prefixes.
917 */
918 for (i = 0; i < t->operands; i++) {
919 if (ins->oprs[i].segment != SEG_RMREG)
920 a_used = true;
921 }
922
923 if (lock) {
924 if (ins->prefixes[PPS_LREP])
925 return false;
926 ins->prefixes[PPS_LREP] = P_LOCK;
927 }
928 if (drep) {
929 if (ins->prefixes[PPS_LREP])
930 return false;
931 ins->prefixes[PPS_LREP] = drep;
932 }
933 ins->prefixes[PPS_WAIT] = dwait;
934 if (!o_used) {
935 if (osize != ((segsize == 16) ? 16 : 32)) {
936 enum prefixes pfx = 0;
937
938 switch (osize) {
939 case 16:
940 pfx = P_O16;
941 break;
942 case 32:
943 pfx = P_O32;
944 break;
945 case 64:
946 pfx = P_O64;
947 break;
948 }
949
950 if (ins->prefixes[PPS_OSIZE])
951 return false;
952 ins->prefixes[PPS_OSIZE] = pfx;
953 }
954 }
955 if (!a_used && asize != segsize) {
956 if (ins->prefixes[PPS_ASIZE])
957 return false;
958 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
959 }
960
961 /* Fix: check for redundant REX prefixes */
962
963 return data - origdata;
964 }
965
966 /* Condition names for disassembly, sorted by x86 code */
967 static const char * const condition_name[16] = {
968 "o", "no", "c", "nc", "z", "nz", "na", "a",
969 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
970 };
971
972 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
973 int32_t offset, int autosync, uint32_t prefer)
974 {
975 const struct itemplate * const *p, * const *best_p;
976 const struct disasm_index *ix;
977 uint8_t *dp;
978 int length, best_length = 0;
979 char *segover;
980 int i, slen, colon, n;
981 uint8_t *origdata;
982 int works;
983 insn tmp_ins, ins;
984 uint32_t goodness, best;
985 int best_pref;
986 struct prefix_info prefix;
987 bool end_prefix;
988
989 memset(&ins, 0, sizeof ins);
990
991 /*
992 * Scan for prefixes.
993 */
994 memset(&prefix, 0, sizeof prefix);
995 prefix.asize = segsize;
996 prefix.osize = (segsize == 64) ? 32 : segsize;
997 segover = NULL;
998 origdata = data;
999
1000 ix = itable;
1001
1002 end_prefix = false;
1003 while (!end_prefix) {
1004 switch (*data) {
1005 case 0xF2:
1006 case 0xF3:
1007 prefix.rep = *data++;
1008 break;
1009
1010 case 0x9B:
1011 prefix.wait = *data++;
1012 break;
1013
1014 case 0xF0:
1015 prefix.lock = *data++;
1016 break;
1017
1018 case 0x2E:
1019 segover = "cs", prefix.seg = *data++;
1020 break;
1021 case 0x36:
1022 segover = "ss", prefix.seg = *data++;
1023 break;
1024 case 0x3E:
1025 segover = "ds", prefix.seg = *data++;
1026 break;
1027 case 0x26:
1028 segover = "es", prefix.seg = *data++;
1029 break;
1030 case 0x64:
1031 segover = "fs", prefix.seg = *data++;
1032 break;
1033 case 0x65:
1034 segover = "gs", prefix.seg = *data++;
1035 break;
1036
1037 case 0x66:
1038 prefix.osize = (segsize == 16) ? 32 : 16;
1039 prefix.osp = *data++;
1040 break;
1041 case 0x67:
1042 prefix.asize = (segsize == 32) ? 16 : 32;
1043 prefix.asp = *data++;
1044 break;
1045
1046 case 0xC4:
1047 case 0xC5:
1048 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1049 prefix.vex[0] = *data++;
1050 prefix.vex[1] = *data++;
1051
1052 prefix.rex = REX_V;
1053 prefix.vex_c = RV_VEX;
1054
1055 if (prefix.vex[0] == 0xc4) {
1056 prefix.vex[2] = *data++;
1057 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1058 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1059 prefix.vex_m = prefix.vex[1] & 0x1f;
1060 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1061 prefix.vex_lp = prefix.vex[2] & 7;
1062 } else {
1063 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1064 prefix.vex_m = 1;
1065 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1066 prefix.vex_lp = prefix.vex[1] & 7;
1067 }
1068
1069 ix = itable_vex[RV_VEX][prefix.vex_m][prefix.vex_lp];
1070 }
1071 end_prefix = true;
1072 break;
1073
1074 case 0x8F:
1075 if ((data[1] & 030) != 0 &&
1076 (segsize == 64 || (data[1] & 0xc0) == 0xc0)) {
1077 prefix.vex[0] = *data++;
1078 prefix.vex[1] = *data++;
1079 prefix.vex[2] = *data++;
1080
1081 prefix.rex = REX_V;
1082 prefix.vex_c = RV_XOP;
1083
1084 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1085 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1086 prefix.vex_m = prefix.vex[1] & 0x1f;
1087 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1088 prefix.vex_lp = prefix.vex[2] & 7;
1089
1090 ix = itable_vex[RV_XOP][prefix.vex_m][prefix.vex_lp];
1091 }
1092 end_prefix = true;
1093 break;
1094
1095 case REX_P + 0x0:
1096 case REX_P + 0x1:
1097 case REX_P + 0x2:
1098 case REX_P + 0x3:
1099 case REX_P + 0x4:
1100 case REX_P + 0x5:
1101 case REX_P + 0x6:
1102 case REX_P + 0x7:
1103 case REX_P + 0x8:
1104 case REX_P + 0x9:
1105 case REX_P + 0xA:
1106 case REX_P + 0xB:
1107 case REX_P + 0xC:
1108 case REX_P + 0xD:
1109 case REX_P + 0xE:
1110 case REX_P + 0xF:
1111 if (segsize == 64) {
1112 prefix.rex = *data++;
1113 if (prefix.rex & REX_W)
1114 prefix.osize = 64;
1115 }
1116 end_prefix = true;
1117 break;
1118
1119 default:
1120 end_prefix = true;
1121 break;
1122 }
1123 }
1124
1125 best = -1; /* Worst possible */
1126 best_p = NULL;
1127 best_pref = INT_MAX;
1128
1129 if (!ix)
1130 return 0; /* No instruction table at all... */
1131
1132 dp = data;
1133 ix += *dp++;
1134 while (ix->n == -1) {
1135 ix = (const struct disasm_index *)ix->p + *dp++;
1136 }
1137
1138 p = (const struct itemplate * const *)ix->p;
1139 for (n = ix->n; n; n--, p++) {
1140 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1141 works = true;
1142 /*
1143 * Final check to make sure the types of r/m match up.
1144 * XXX: Need to make sure this is actually correct.
1145 */
1146 for (i = 0; i < (*p)->operands; i++) {
1147 if (!((*p)->opd[i] & SAME_AS) &&
1148 (
1149 /* If it's a mem-only EA but we have a
1150 register, die. */
1151 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1152 !(MEMORY & ~(*p)->opd[i])) ||
1153 /* If it's a reg-only EA but we have a memory
1154 ref, die. */
1155 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1156 !(REG_EA & ~(*p)->opd[i]) &&
1157 !((*p)->opd[i] & REG_SMASK)) ||
1158 /* Register type mismatch (eg FS vs REG_DESS):
1159 die. */
1160 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1161 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1162 !whichreg((*p)->opd[i],
1163 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1164 )) {
1165 works = false;
1166 break;
1167 }
1168 }
1169
1170 /*
1171 * Note: we always prefer instructions which incorporate
1172 * prefixes in the instructions themselves. This is to allow
1173 * e.g. PAUSE to be preferred to REP NOP, and deal with
1174 * MMX/SSE instructions where prefixes are used to select
1175 * between MMX and SSE register sets or outright opcode
1176 * selection.
1177 */
1178 if (works) {
1179 int i, nprefix;
1180 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1181 nprefix = 0;
1182 for (i = 0; i < MAXPREFIX; i++)
1183 if (tmp_ins.prefixes[i])
1184 nprefix++;
1185 if (nprefix < best_pref ||
1186 (nprefix == best_pref && goodness < best)) {
1187 /* This is the best one found so far */
1188 best = goodness;
1189 best_p = p;
1190 best_pref = nprefix;
1191 best_length = length;
1192 ins = tmp_ins;
1193 }
1194 }
1195 }
1196 }
1197
1198 if (!best_p)
1199 return 0; /* no instruction was matched */
1200
1201 /* Pick the best match */
1202 p = best_p;
1203 length = best_length;
1204
1205 slen = 0;
1206
1207 /* TODO: snprintf returns the value that the string would have if
1208 * the buffer were long enough, and not the actual length of
1209 * the returned string, so each instance of using the return
1210 * value of snprintf should actually be checked to assure that
1211 * the return value is "sane." Maybe a macro wrapper could
1212 * be used for that purpose.
1213 */
1214 for (i = 0; i < MAXPREFIX; i++) {
1215 const char *prefix = prefix_name(ins.prefixes[i]);
1216 if (prefix)
1217 slen += snprintf(output+slen, outbufsize-slen, "%s ", prefix);
1218 }
1219
1220 i = (*p)->opcode;
1221 if (i >= FIRST_COND_OPCODE)
1222 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1223 nasm_insn_names[i], condition_name[ins.condition]);
1224 else
1225 slen += snprintf(output + slen, outbufsize - slen, "%s",
1226 nasm_insn_names[i]);
1227
1228 colon = false;
1229 length += data - origdata; /* fix up for prefixes */
1230 for (i = 0; i < (*p)->operands; i++) {
1231 opflags_t t = (*p)->opd[i];
1232 const operand *o = &ins.oprs[i];
1233 int64_t offs;
1234
1235 if (t & SAME_AS) {
1236 o = &ins.oprs[t & ~SAME_AS];
1237 t = (*p)->opd[t & ~SAME_AS];
1238 }
1239
1240 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1241
1242 offs = o->offset;
1243 if (o->segment & SEG_RELATIVE) {
1244 offs += offset + length;
1245 /*
1246 * sort out wraparound
1247 */
1248 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1249 offs &= 0xffff;
1250 else if (segsize != 64)
1251 offs &= 0xffffffff;
1252
1253 /*
1254 * add sync marker, if autosync is on
1255 */
1256 if (autosync)
1257 add_sync(offs, 0L);
1258 }
1259
1260 if (t & COLON)
1261 colon = true;
1262 else
1263 colon = false;
1264
1265 if ((t & (REGISTER | FPUREG)) ||
1266 (o->segment & SEG_RMREG)) {
1267 enum reg_enum reg;
1268 reg = whichreg(t, o->basereg, ins.rex);
1269 if (t & TO)
1270 slen += snprintf(output + slen, outbufsize - slen, "to ");
1271 slen += snprintf(output + slen, outbufsize - slen, "%s",
1272 nasm_reg_names[reg-EXPR_REG_START]);
1273 } else if (!(UNITY & ~t)) {
1274 output[slen++] = '1';
1275 } else if (t & IMMEDIATE) {
1276 if (t & BITS8) {
1277 slen +=
1278 snprintf(output + slen, outbufsize - slen, "byte ");
1279 if (o->segment & SEG_SIGNED) {
1280 if (offs < 0) {
1281 offs *= -1;
1282 output[slen++] = '-';
1283 } else
1284 output[slen++] = '+';
1285 }
1286 } else if (t & BITS16) {
1287 slen +=
1288 snprintf(output + slen, outbufsize - slen, "word ");
1289 } else if (t & BITS32) {
1290 slen +=
1291 snprintf(output + slen, outbufsize - slen, "dword ");
1292 } else if (t & BITS64) {
1293 slen +=
1294 snprintf(output + slen, outbufsize - slen, "qword ");
1295 } else if (t & NEAR) {
1296 slen +=
1297 snprintf(output + slen, outbufsize - slen, "near ");
1298 } else if (t & SHORT) {
1299 slen +=
1300 snprintf(output + slen, outbufsize - slen, "short ");
1301 }
1302 slen +=
1303 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1304 offs);
1305 } else if (!(MEM_OFFS & ~t)) {
1306 slen +=
1307 snprintf(output + slen, outbufsize - slen,
1308 "[%s%s%s0x%"PRIx64"]",
1309 (segover ? segover : ""),
1310 (segover ? ":" : ""),
1311 (o->disp_size == 64 ? "qword " :
1312 o->disp_size == 32 ? "dword " :
1313 o->disp_size == 16 ? "word " : ""), offs);
1314 segover = NULL;
1315 } else if (!(REGMEM & ~t)) {
1316 int started = false;
1317 if (t & BITS8)
1318 slen +=
1319 snprintf(output + slen, outbufsize - slen, "byte ");
1320 if (t & BITS16)
1321 slen +=
1322 snprintf(output + slen, outbufsize - slen, "word ");
1323 if (t & BITS32)
1324 slen +=
1325 snprintf(output + slen, outbufsize - slen, "dword ");
1326 if (t & BITS64)
1327 slen +=
1328 snprintf(output + slen, outbufsize - slen, "qword ");
1329 if (t & BITS80)
1330 slen +=
1331 snprintf(output + slen, outbufsize - slen, "tword ");
1332 if (t & BITS128)
1333 slen +=
1334 snprintf(output + slen, outbufsize - slen, "oword ");
1335 if (t & BITS256)
1336 slen +=
1337 snprintf(output + slen, outbufsize - slen, "yword ");
1338 if (t & FAR)
1339 slen += snprintf(output + slen, outbufsize - slen, "far ");
1340 if (t & NEAR)
1341 slen +=
1342 snprintf(output + slen, outbufsize - slen, "near ");
1343 output[slen++] = '[';
1344 if (o->disp_size)
1345 slen += snprintf(output + slen, outbufsize - slen, "%s",
1346 (o->disp_size == 64 ? "qword " :
1347 o->disp_size == 32 ? "dword " :
1348 o->disp_size == 16 ? "word " :
1349 ""));
1350 if (o->eaflags & EAF_REL)
1351 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1352 if (segover) {
1353 slen +=
1354 snprintf(output + slen, outbufsize - slen, "%s:",
1355 segover);
1356 segover = NULL;
1357 }
1358 if (o->basereg != -1) {
1359 slen += snprintf(output + slen, outbufsize - slen, "%s",
1360 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1361 started = true;
1362 }
1363 if (o->indexreg != -1) {
1364 if (started)
1365 output[slen++] = '+';
1366 slen += snprintf(output + slen, outbufsize - slen, "%s",
1367 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1368 if (o->scale > 1)
1369 slen +=
1370 snprintf(output + slen, outbufsize - slen, "*%d",
1371 o->scale);
1372 started = true;
1373 }
1374
1375
1376 if (o->segment & SEG_DISP8) {
1377 const char *prefix;
1378 uint8_t offset = offs;
1379 if ((int8_t)offset < 0) {
1380 prefix = "-";
1381 offset = -offset;
1382 } else {
1383 prefix = "+";
1384 }
1385 slen +=
1386 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1387 prefix, offset);
1388 } else if (o->segment & SEG_DISP16) {
1389 const char *prefix;
1390 uint16_t offset = offs;
1391 if ((int16_t)offset < 0 && started) {
1392 offset = -offset;
1393 prefix = "-";
1394 } else {
1395 prefix = started ? "+" : "";
1396 }
1397 slen +=
1398 snprintf(output + slen, outbufsize - slen,
1399 "%s0x%"PRIx16"", prefix, offset);
1400 } else if (o->segment & SEG_DISP32) {
1401 if (prefix.asize == 64) {
1402 const char *prefix;
1403 uint64_t offset = (int64_t)(int32_t)offs;
1404 if ((int32_t)offs < 0 && started) {
1405 offset = -offset;
1406 prefix = "-";
1407 } else {
1408 prefix = started ? "+" : "";
1409 }
1410 slen +=
1411 snprintf(output + slen, outbufsize - slen,
1412 "%s0x%"PRIx64"", prefix, offset);
1413 } else {
1414 const char *prefix;
1415 uint32_t offset = offs;
1416 if ((int32_t) offset < 0 && started) {
1417 offset = -offset;
1418 prefix = "-";
1419 } else {
1420 prefix = started ? "+" : "";
1421 }
1422 slen +=
1423 snprintf(output + slen, outbufsize - slen,
1424 "%s0x%"PRIx32"", prefix, offset);
1425 }
1426 }
1427 output[slen++] = ']';
1428 } else {
1429 slen +=
1430 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1431 i);
1432 }
1433 }
1434 output[slen] = '\0';
1435 if (segover) { /* unused segment override */
1436 char *p = output;
1437 int count = slen + 1;
1438 while (count--)
1439 p[count + 3] = p[count];
1440 strncpy(output, segover, 2);
1441 output[2] = ' ';
1442 }
1443 return length;
1444 }
1445
1446 /*
1447 * This is called when we don't have a complete instruction. If it
1448 * is a standalone *single-byte* prefix show it as such, otherwise
1449 * print it as a literal.
1450 */
1451 int32_t eatbyte(uint8_t *data, char *output, int outbufsize, int segsize)
1452 {
1453 uint8_t byte = *data;
1454 const char *str = NULL;
1455
1456 switch (byte) {
1457 case 0xF2:
1458 str = "repne";
1459 break;
1460 case 0xF3:
1461 str = "rep";
1462 break;
1463 case 0x9B:
1464 str = "wait";
1465 break;
1466 case 0xF0:
1467 str = "lock";
1468 break;
1469 case 0x2E:
1470 str = "cs";
1471 break;
1472 case 0x36:
1473 str = "ss";
1474 break;
1475 case 0x3E:
1476 str = "ss";
1477 break;
1478 case 0x26:
1479 str = "es";
1480 break;
1481 case 0x64:
1482 str = "fs";
1483 break;
1484 case 0x65:
1485 str = "gs";
1486 break;
1487 case 0x66:
1488 str = (segsize == 16) ? "o32" : "o16";
1489 break;
1490 case 0x67:
1491 str = (segsize == 32) ? "a16" : "a32";
1492 break;
1493 case REX_P + 0x0:
1494 case REX_P + 0x1:
1495 case REX_P + 0x2:
1496 case REX_P + 0x3:
1497 case REX_P + 0x4:
1498 case REX_P + 0x5:
1499 case REX_P + 0x6:
1500 case REX_P + 0x7:
1501 case REX_P + 0x8:
1502 case REX_P + 0x9:
1503 case REX_P + 0xA:
1504 case REX_P + 0xB:
1505 case REX_P + 0xC:
1506 case REX_P + 0xD:
1507 case REX_P + 0xE:
1508 case REX_P + 0xF:
1509 if (segsize == 64) {
1510 snprintf(output, outbufsize, "rex%s%s%s%s%s",
1511 (byte == REX_P) ? "" : ".",
1512 (byte & REX_W) ? "w" : "",
1513 (byte & REX_R) ? "r" : "",
1514 (byte & REX_X) ? "x" : "",
1515 (byte & REX_B) ? "b" : "");
1516 break;
1517 }
1518 /* else fall through */
1519 default:
1520 snprintf(output, outbufsize, "db 0x%02x", byte);
1521 break;
1522 }
1523
1524 if (str)
1525 strcpy(output, str);
1526
1527 return 1;
1528 }
The Netwide Assembler