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insns.pl: readabilty improvements for isnsnd.c
[nasm.git] / disasm.c
blobf4cc6c6843138e260f7d77647151a7ae19ed9b1d
1 /* disasm.c where all the _work_ gets done in the Netwide Disassembler
2 *
3 * The Netwide Assembler is copyright (C) 1996 Simon Tatham and
4 * Julian Hall. All rights reserved. The software is
5 * redistributable under the license given in the file "LICENSE"
6 * distributed in the NASM archive.
7 *
8 * initial version 27/iii/95 by Simon Tatham
9 */
10
11 #include "compiler.h"
12
13 #include <stdio.h>
14 #include <string.h>
15 #include <limits.h>
16 #include <inttypes.h>
17
18 #include "nasm.h"
19 #include "disasm.h"
20 #include "sync.h"
21 #include "insns.h"
22 #include "tables.h"
23 #include "regdis.h"
24
25 /*
26 * Flags that go into the `segment' field of `insn' structures
27 * during disassembly.
28 */
29 #define SEG_RELATIVE 1
30 #define SEG_32BIT 2
31 #define SEG_RMREG 4
32 #define SEG_DISP8 8
33 #define SEG_DISP16 16
34 #define SEG_DISP32 32
35 #define SEG_NODISP 64
36 #define SEG_SIGNED 128
37 #define SEG_64BIT 256
38
39 /*
40 * Prefix information
41 */
42 struct prefix_info {
43 uint8_t osize; /* Operand size */
44 uint8_t asize; /* Address size */
45 uint8_t osp; /* Operand size prefix present */
46 uint8_t asp; /* Address size prefix present */
47 uint8_t rep; /* Rep prefix present */
48 uint8_t seg; /* Segment override prefix present */
49 uint8_t lock; /* Lock prefix present */
50 uint8_t vex[3]; /* VEX prefix present */
51 uint8_t vex_m; /* VEX.M field */
52 uint8_t vex_v;
53 uint8_t vex_lp; /* VEX.LP fields */
54 uint32_t rex; /* REX prefix present */
55 };
56
57 #define getu8(x) (*(uint8_t *)(x))
58 #if X86_MEMORY
59 /* Littleendian CPU which can handle unaligned references */
60 #define getu16(x) (*(uint16_t *)(x))
61 #define getu32(x) (*(uint32_t *)(x))
62 #define getu64(x) (*(uint64_t *)(x))
63 #else
64 static uint16_t getu16(uint8_t *data)
65 {
66 return (uint16_t)data[0] + ((uint16_t)data[1] << 8);
67 }
68 static uint32_t getu32(uint8_t *data)
69 {
70 return (uint32_t)getu16(data) + ((uint32_t)getu16(data+2) << 16);
71 }
72 static uint64_t getu64(uint8_t *data)
73 {
74 return (uint64_t)getu32(data) + ((uint64_t)getu32(data+4) << 32);
75 }
76 #endif
77
78 #define gets8(x) ((int8_t)getu8(x))
79 #define gets16(x) ((int16_t)getu16(x))
80 #define gets32(x) ((int32_t)getu32(x))
81 #define gets64(x) ((int64_t)getu64(x))
82
83 /* Important: regval must already have been adjusted for rex extensions */
84 static enum reg_enum whichreg(int32_t regflags, int regval, int rex)
85 {
86 if (!(regflags & (REGISTER|REGMEM)))
87 return 0; /* Registers not permissible?! */
88
89 regflags |= REGISTER;
90
91 if (!(REG_AL & ~regflags))
92 return R_AL;
93 if (!(REG_AX & ~regflags))
94 return R_AX;
95 if (!(REG_EAX & ~regflags))
96 return R_EAX;
97 if (!(REG_RAX & ~regflags))
98 return R_RAX;
99 if (!(REG_DL & ~regflags))
100 return R_DL;
101 if (!(REG_DX & ~regflags))
102 return R_DX;
103 if (!(REG_EDX & ~regflags))
104 return R_EDX;
105 if (!(REG_RDX & ~regflags))
106 return R_RDX;
107 if (!(REG_CL & ~regflags))
108 return R_CL;
109 if (!(REG_CX & ~regflags))
110 return R_CX;
111 if (!(REG_ECX & ~regflags))
112 return R_ECX;
113 if (!(REG_RCX & ~regflags))
114 return R_RCX;
115 if (!(FPU0 & ~regflags))
116 return R_ST0;
117 if (!(XMM0 & ~regflags))
118 return R_XMM0;
119 if (!(YMM0 & ~regflags))
120 return R_YMM0;
121 if (!(REG_CS & ~regflags))
122 return (regval == 1) ? R_CS : 0;
123 if (!(REG_DESS & ~regflags))
124 return (regval == 0 || regval == 2
125 || regval == 3 ? nasm_rd_sreg[regval] : 0);
126 if (!(REG_FSGS & ~regflags))
127 return (regval == 4 || regval == 5 ? nasm_rd_sreg[regval] : 0);
128 if (!(REG_SEG67 & ~regflags))
129 return (regval == 6 || regval == 7 ? nasm_rd_sreg[regval] : 0);
130
131 /* All the entries below look up regval in an 16-entry array */
132 if (regval < 0 || regval > 15)
133 return 0;
134
135 if (!(REG8 & ~regflags)) {
136 if (rex & REX_P)
137 return nasm_rd_reg8_rex[regval];
138 else
139 return nasm_rd_reg8[regval];
140 }
141 if (!(REG16 & ~regflags))
142 return nasm_rd_reg16[regval];
143 if (!(REG32 & ~regflags))
144 return nasm_rd_reg32[regval];
145 if (!(REG64 & ~regflags))
146 return nasm_rd_reg64[regval];
147 if (!(REG_SREG & ~regflags))
148 return nasm_rd_sreg[regval & 7]; /* Ignore REX */
149 if (!(REG_CREG & ~regflags))
150 return nasm_rd_creg[regval];
151 if (!(REG_DREG & ~regflags))
152 return nasm_rd_dreg[regval];
153 if (!(REG_TREG & ~regflags)) {
154 if (rex & REX_P)
155 return 0; /* TR registers are ill-defined with rex */
156 return nasm_rd_treg[regval];
157 }
158 if (!(FPUREG & ~regflags))
159 return nasm_rd_fpureg[regval & 7]; /* Ignore REX */
160 if (!(MMXREG & ~regflags))
161 return nasm_rd_mmxreg[regval & 7]; /* Ignore REX */
162 if (!(XMMREG & ~regflags))
163 return nasm_rd_xmmreg[regval];
164 if (!(YMMREG & ~regflags))
165 return nasm_rd_ymmreg[regval];
166
167 return 0;
168 }
169
170 /*
171 * Process a DREX suffix
172 */
173 static uint8_t *do_drex(uint8_t *data, insn *ins)
174 {
175 uint8_t drex = *data++;
176 operand *dst = &ins->oprs[ins->drexdst];
177
178 if ((drex & 8) != ((ins->rex & REX_OC) ? 8 : 0))
179 return NULL; /* OC0 mismatch */
180 ins->rex = (ins->rex & ~7) | (drex & 7);
181
182 dst->segment = SEG_RMREG;
183 dst->basereg = drex >> 4;
184 return data;
185 }
186
187
188 /*
189 * Process an effective address (ModRM) specification.
190 */
191 static uint8_t *do_ea(uint8_t *data, int modrm, int asize,
192 int segsize, operand * op, insn *ins)
193 {
194 int mod, rm, scale, index, base;
195 int rex;
196 uint8_t sib = 0;
197
198 mod = (modrm >> 6) & 03;
199 rm = modrm & 07;
200
201 if (mod != 3 && rm == 4 && asize != 16)
202 sib = *data++;
203
204 if (ins->rex & REX_D) {
205 data = do_drex(data, ins);
206 if (!data)
207 return NULL;
208 }
209 rex = ins->rex;
210
211 if (mod == 3) { /* pure register version */
212 op->basereg = rm+(rex & REX_B ? 8 : 0);
213 op->segment |= SEG_RMREG;
214 return data;
215 }
216
217 op->disp_size = 0;
218 op->eaflags = 0;
219
220 if (asize == 16) {
221 /*
222 * <mod> specifies the displacement size (none, byte or
223 * word), and <rm> specifies the register combination.
224 * Exception: mod=0,rm=6 does not specify [BP] as one might
225 * expect, but instead specifies [disp16].
226 */
227 op->indexreg = op->basereg = -1;
228 op->scale = 1; /* always, in 16 bits */
229 switch (rm) {
230 case 0:
231 op->basereg = R_BX;
232 op->indexreg = R_SI;
233 break;
234 case 1:
235 op->basereg = R_BX;
236 op->indexreg = R_DI;
237 break;
238 case 2:
239 op->basereg = R_BP;
240 op->indexreg = R_SI;
241 break;
242 case 3:
243 op->basereg = R_BP;
244 op->indexreg = R_DI;
245 break;
246 case 4:
247 op->basereg = R_SI;
248 break;
249 case 5:
250 op->basereg = R_DI;
251 break;
252 case 6:
253 op->basereg = R_BP;
254 break;
255 case 7:
256 op->basereg = R_BX;
257 break;
258 }
259 if (rm == 6 && mod == 0) { /* special case */
260 op->basereg = -1;
261 if (segsize != 16)
262 op->disp_size = 16;
263 mod = 2; /* fake disp16 */
264 }
265 switch (mod) {
266 case 0:
267 op->segment |= SEG_NODISP;
268 break;
269 case 1:
270 op->segment |= SEG_DISP8;
271 op->offset = (int8_t)*data++;
272 break;
273 case 2:
274 op->segment |= SEG_DISP16;
275 op->offset = *data++;
276 op->offset |= ((unsigned)*data++) << 8;
277 break;
278 }
279 return data;
280 } else {
281 /*
282 * Once again, <mod> specifies displacement size (this time
283 * none, byte or *dword*), while <rm> specifies the base
284 * register. Again, [EBP] is missing, replaced by a pure
285 * disp32 (this time that's mod=0,rm=*5*) in 32-bit mode,
286 * and RIP-relative addressing in 64-bit mode.
287 *
288 * However, rm=4
289 * indicates not a single base register, but instead the
290 * presence of a SIB byte...
291 */
292 int a64 = asize == 64;
293
294 op->indexreg = -1;
295
296 if (a64)
297 op->basereg = nasm_rd_reg64[rm | ((rex & REX_B) ? 8 : 0)];
298 else
299 op->basereg = nasm_rd_reg32[rm | ((rex & REX_B) ? 8 : 0)];
300
301 if (rm == 5 && mod == 0) {
302 if (segsize == 64) {
303 op->eaflags |= EAF_REL;
304 op->segment |= SEG_RELATIVE;
305 mod = 2; /* fake disp32 */
306 }
307
308 if (asize != 64)
309 op->disp_size = asize;
310
311 op->basereg = -1;
312 mod = 2; /* fake disp32 */
313 }
314
315 if (rm == 4) { /* process SIB */
316 scale = (sib >> 6) & 03;
317 index = (sib >> 3) & 07;
318 base = sib & 07;
319
320 op->scale = 1 << scale;
321
322 if (index == 4)
323 op->indexreg = -1; /* ESP/RSP/R12 cannot be an index */
324 else if (a64)
325 op->indexreg = nasm_rd_reg64[index | ((rex & REX_X) ? 8 : 0)];
326 else
327 op->indexreg = nasm_rd_reg32[index | ((rex & REX_X) ? 8 : 0)];
328
329 if (base == 5 && mod == 0) {
330 op->basereg = -1;
331 mod = 2; /* Fake disp32 */
332 } else if (a64)
333 op->basereg = nasm_rd_reg64[base | ((rex & REX_B) ? 8 : 0)];
334 else
335 op->basereg = nasm_rd_reg32[base | ((rex & REX_B) ? 8 : 0)];
336
337 if (segsize == 16)
338 op->disp_size = 32;
339 }
340
341 switch (mod) {
342 case 0:
343 op->segment |= SEG_NODISP;
344 break;
345 case 1:
346 op->segment |= SEG_DISP8;
347 op->offset = gets8(data);
348 data++;
349 break;
350 case 2:
351 op->segment |= SEG_DISP32;
352 op->offset = gets32(data);
353 data += 4;
354 break;
355 }
356 return data;
357 }
358 }
359
360 /*
361 * Determine whether the instruction template in t corresponds to the data
362 * stream in data. Return the number of bytes matched if so.
363 */
364 #define case4(x) case (x): case (x)+1: case (x)+2: case (x)+3
365
366 static int matches(const struct itemplate *t, uint8_t *data,
367 const struct prefix_info *prefix, int segsize, insn *ins)
368 {
369 uint8_t *r = (uint8_t *)(t->code);
370 uint8_t *origdata = data;
371 bool a_used = false, o_used = false;
372 enum prefixes drep = 0;
373 uint8_t lock = prefix->lock;
374 int osize = prefix->osize;
375 int asize = prefix->asize;
376 int i, c;
377 struct operand *opx;
378 int s_field_for = -1; /* No 144/154 series code encountered */
379 bool vex_ok = false;
380
381 for (i = 0; i < MAX_OPERANDS; i++) {
382 ins->oprs[i].segment = ins->oprs[i].disp_size =
383 (segsize == 64 ? SEG_64BIT : segsize == 32 ? SEG_32BIT : 0);
384 }
385 ins->condition = -1;
386 ins->rex = prefix->rex;
387 memset(ins->prefixes, 0, sizeof ins->prefixes);
388
389 if (t->flags & (segsize == 64 ? IF_NOLONG : IF_LONG))
390 return false;
391
392 if (prefix->rep == 0xF2)
393 drep = P_REPNE;
394 else if (prefix->rep == 0xF3)
395 drep = P_REP;
396
397 while ((c = *r++) != 0) {
398 opx = &ins->oprs[c & 3];
399
400 switch (c) {
401 case 01:
402 case 02:
403 case 03:
404 while (c--)
405 if (*r++ != *data++)
406 return false;
407 break;
408
409 case 04:
410 switch (*data++) {
411 case 0x07:
412 ins->oprs[0].basereg = 0;
413 break;
414 case 0x17:
415 ins->oprs[0].basereg = 2;
416 break;
417 case 0x1F:
418 ins->oprs[0].basereg = 3;
419 break;
420 default:
421 return false;
422 }
423 break;
424
425 case 05:
426 switch (*data++) {
427 case 0xA1:
428 ins->oprs[0].basereg = 4;
429 break;
430 case 0xA9:
431 ins->oprs[0].basereg = 5;
432 break;
433 default:
434 return false;
435 }
436 break;
437
438 case 06:
439 switch (*data++) {
440 case 0x06:
441 ins->oprs[0].basereg = 0;
442 break;
443 case 0x0E:
444 ins->oprs[0].basereg = 1;
445 break;
446 case 0x16:
447 ins->oprs[0].basereg = 2;
448 break;
449 case 0x1E:
450 ins->oprs[0].basereg = 3;
451 break;
452 default:
453 return false;
454 }
455 break;
456
457 case 07:
458 switch (*data++) {
459 case 0xA0:
460 ins->oprs[0].basereg = 4;
461 break;
462 case 0xA8:
463 ins->oprs[0].basereg = 5;
464 break;
465 default:
466 return false;
467 }
468 break;
469
470 case4(010):
471 {
472 int t = *r++, d = *data++;
473 if (d < t || d > t + 7)
474 return false;
475 else {
476 opx->basereg = (d-t)+
477 (ins->rex & REX_B ? 8 : 0);
478 opx->segment |= SEG_RMREG;
479 }
480 break;
481 }
482
483 case4(014):
484 opx->offset = (int8_t)*data++;
485 opx->segment |= SEG_SIGNED;
486 break;
487
488 case4(020):
489 opx->offset = *data++;
490 break;
491
492 case4(024):
493 opx->offset = *data++;
494 break;
495
496 case4(030):
497 opx->offset = getu16(data);
498 data += 2;
499 break;
500
501 case4(034):
502 if (osize == 32) {
503 opx->offset = getu32(data);
504 data += 4;
505 } else {
506 opx->offset = getu16(data);
507 data += 2;
508 }
509 if (segsize != asize)
510 opx->disp_size = asize;
511 break;
512
513 case4(040):
514 opx->offset = getu32(data);
515 data += 4;
516 break;
517
518 case4(044):
519 switch (asize) {
520 case 16:
521 opx->offset = getu16(data);
522 data += 2;
523 if (segsize != 16)
524 opx->disp_size = 16;
525 break;
526 case 32:
527 opx->offset = getu32(data);
528 data += 4;
529 if (segsize == 16)
530 opx->disp_size = 32;
531 break;
532 case 64:
533 opx->offset = getu64(data);
534 opx->disp_size = 64;
535 data += 8;
536 break;
537 }
538 break;
539
540 case4(050):
541 opx->offset = gets8(data++);
542 opx->segment |= SEG_RELATIVE;
543 break;
544
545 case4(054):
546 opx->offset = getu64(data);
547 data += 8;
548 break;
549
550 case4(060):
551 opx->offset = gets16(data);
552 data += 2;
553 opx->segment |= SEG_RELATIVE;
554 opx->segment &= ~SEG_32BIT;
555 break;
556
557 case4(064):
558 opx->segment |= SEG_RELATIVE;
559 if (osize == 16) {
560 opx->offset = gets16(data);
561 data += 2;
562 opx->segment &= ~(SEG_32BIT|SEG_64BIT);
563 } else if (osize == 32) {
564 opx->offset = gets32(data);
565 data += 4;
566 opx->segment &= ~SEG_64BIT;
567 opx->segment |= SEG_32BIT;
568 }
569 if (segsize != osize) {
570 opx->type =
571 (opx->type & ~SIZE_MASK)
572 | ((osize == 16) ? BITS16 : BITS32);
573 }
574 break;
575
576 case4(070):
577 opx->offset = gets32(data);
578 data += 4;
579 opx->segment |= SEG_32BIT | SEG_RELATIVE;
580 break;
581
582 case4(0100):
583 case4(0110):
584 case4(0120):
585 case4(0130):
586 {
587 int modrm = *data++;
588 opx->segment |= SEG_RMREG;
589 data = do_ea(data, modrm, asize, segsize,
590 &ins->oprs[(c >> 3) & 3], ins);
591 if (!data)
592 return false;
593 opx->basereg = ((modrm >> 3)&7)+
594 (ins->rex & REX_R ? 8 : 0);
595 break;
596 }
597
598 case4(0140):
599 if (s_field_for == (c & 3)) {
600 opx->offset = gets8(data);
601 data++;
602 } else {
603 opx->offset = getu16(data);
604 data += 2;
605 }
606 break;
607
608 case4(0144):
609 case4(0154):
610 s_field_for = (*data & 0x02) ? c & 3 : -1;
611 if ((*data++ & ~0x02) != *r++)
612 return false;
613 break;
614
615 case4(0150):
616 if (s_field_for == (c & 3)) {
617 opx->offset = gets8(data);
618 data++;
619 } else {
620 opx->offset = getu32(data);
621 data += 4;
622 }
623 break;
624
625 case4(0160):
626 ins->rex |= REX_D;
627 ins->drexdst = c & 3;
628 break;
629
630 case4(0164):
631 ins->rex |= REX_D|REX_OC;
632 ins->drexdst = c & 3;
633 break;
634
635 case 0171:
636 data = do_drex(data, ins);
637 if (!data)
638 return false;
639 break;
640
641 case 0172:
642 {
643 uint8_t ximm = *data++;
644 c = *r++;
645 ins->oprs[c >> 3].basereg = ximm >> 4;
646 ins->oprs[c >> 3].segment |= SEG_RMREG;
647 ins->oprs[c & 7].offset = ximm & 15;
648 }
649 break;
650
651 case 0173:
652 {
653 uint8_t ximm = *data++;
654 c = *r++;
655
656 if ((c ^ ximm) & 15)
657 return false;
658
659 ins->oprs[c >> 4].basereg = ximm >> 4;
660 ins->oprs[c >> 4].segment |= SEG_RMREG;
661 }
662 break;
663
664 case 0174:
665 {
666 uint8_t ximm = *data++;
667 c = *r++;
668
669 ins->oprs[c].basereg = ximm >> 4;
670 ins->oprs[c].segment |= SEG_RMREG;
671 }
672 break;
673
674 case4(0200):
675 case4(0204):
676 case4(0210):
677 case4(0214):
678 case4(0220):
679 case4(0224):
680 case4(0230):
681 case4(0234):
682 {
683 int modrm = *data++;
684 if (((modrm >> 3) & 07) != (c & 07))
685 return false; /* spare field doesn't match up */
686 data = do_ea(data, modrm, asize, segsize,
687 &ins->oprs[(c >> 3) & 07], ins);
688 if (!data)
689 return false;
690 break;
691 }
692
693 case4(0260):
694 {
695 int vexm = *r++;
696 int vexwlp = *r++;
697 ins->rex |= REX_V;
698 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
699 return false;
700
701 if ((vexm & 0x1f) != prefix->vex_m)
702 return false;
703
704 switch (vexwlp & 030) {
705 case 000:
706 if (prefix->rex & REX_W)
707 return false;
708 break;
709 case 010:
710 if (!(prefix->rex & REX_W))
711 return false;
712 break;
713 default:
714 break; /* XXX: Need to do anything special here? */
715 }
716
717 if ((vexwlp & 007) != prefix->vex_lp)
718 return false;
719
720 opx->segment |= SEG_RMREG;
721 opx->basereg = prefix->vex_v;
722 vex_ok = true;
723 break;
724 }
725
726 case 0270:
727 {
728 int vexm = *r++;
729 int vexwlp = *r++;
730 ins->rex |= REX_V;
731 if ((prefix->rex & (REX_V|REX_D|REX_P)) != REX_V)
732 return false;
733
734 if ((vexm & 0x1f) != prefix->vex_m)
735 return false;
736
737 switch (vexwlp & 030) {
738 case 000:
739 if (ins->rex & REX_W)
740 return false;
741 break;
742 case 010:
743 if (!(ins->rex & REX_W))
744 return false;
745 break;
746 default:
747 break; /* Need to do anything special here? */
748 }
749
750 if ((vexwlp & 007) != prefix->vex_lp)
751 return false;
752
753 if (prefix->vex_v != 0)
754 return false;
755
756 vex_ok = true;
757 break;
758 }
759
760 case 0310:
761 if (asize != 16)
762 return false;
763 else
764 a_used = true;
765 break;
766
767 case 0311:
768 if (asize == 16)
769 return false;
770 else
771 a_used = true;
772 break;
773
774 case 0312:
775 if (asize != segsize)
776 return false;
777 else
778 a_used = true;
779 break;
780
781 case 0313:
782 if (asize != 64)
783 return false;
784 else
785 a_used = true;
786 break;
787
788 case 0314:
789 if (prefix->rex & REX_B)
790 return false;
791 break;
792
793 case 0315:
794 if (prefix->rex & REX_X)
795 return false;
796 break;
797
798 case 0316:
799 if (prefix->rex & REX_R)
800 return false;
801 break;
802
803 case 0317:
804 if (prefix->rex & REX_W)
805 return false;
806 break;
807
808 case 0320:
809 if (osize != 16)
810 return false;
811 else
812 o_used = true;
813 break;
814
815 case 0321:
816 if (osize != 32)
817 return false;
818 else
819 o_used = true;
820 break;
821
822 case 0322:
823 if (osize != (segsize == 16) ? 16 : 32)
824 return false;
825 else
826 o_used = true;
827 break;
828
829 case 0323:
830 ins->rex |= REX_W; /* 64-bit only instruction */
831 osize = 64;
832 o_used = true;
833 break;
834
835 case 0324:
836 if (!(ins->rex & (REX_P|REX_W)) || osize != 64)
837 return false;
838 o_used = true;
839 break;
840
841 case 0330:
842 {
843 int t = *r++, d = *data++;
844 if (d < t || d > t + 15)
845 return false;
846 else
847 ins->condition = d - t;
848 break;
849 }
850
851 case 0331:
852 if (prefix->rep)
853 return false;
854 break;
855
856 case 0332:
857 if (prefix->rep != 0xF2)
858 return false;
859 drep = 0;
860 break;
861
862 case 0333:
863 if (prefix->rep != 0xF3)
864 return false;
865 drep = 0;
866 break;
867
868 case 0334:
869 if (lock) {
870 ins->rex |= REX_R;
871 lock = 0;
872 }
873 break;
874
875 case 0335:
876 if (drep == P_REP)
877 drep = P_REPE;
878 break;
879
880 case 0340:
881 return false;
882
883 case 0360:
884 if (prefix->osp || prefix->rep)
885 return false;
886 break;
887
888 case 0361:
889 if (!prefix->osp || prefix->rep)
890 return false;
891 o_used = true;
892 break;
893
894 case 0362:
895 if (prefix->osp || prefix->rep != 0xf2)
896 return false;
897 drep = 0;
898 break;
899
900 case 0363:
901 if (prefix->osp || prefix->rep != 0xf3)
902 return false;
903 drep = 0;
904 break;
905
906 case 0364:
907 if (prefix->osp)
908 return false;
909 break;
910
911 case 0365:
912 if (prefix->asp)
913 return false;
914 break;
915
916 case 0366:
917 if (!prefix->osp)
918 return false;
919 o_used = true;
920 break;
921
922 case 0367:
923 if (!prefix->asp)
924 return false;
925 a_used = true;
926 break;
927
928 default:
929 return false; /* Unknown code */
930 }
931 }
932
933 if (!vex_ok && (ins->rex & REX_V))
934 return false;
935
936 /* REX cannot be combined with DREX or VEX */
937 if ((ins->rex & (REX_D|REX_V)) && (prefix->rex & REX_P))
938 return false;
939
940 /*
941 * Check for unused rep or a/o prefixes.
942 */
943 for (i = 0; i < t->operands; i++) {
944 if (ins->oprs[i].segment != SEG_RMREG)
945 a_used = true;
946 }
947
948 if (lock) {
949 if (ins->prefixes[PPS_LREP])
950 return false;
951 ins->prefixes[PPS_LREP] = P_LOCK;
952 }
953 if (drep) {
954 if (ins->prefixes[PPS_LREP])
955 return false;
956 ins->prefixes[PPS_LREP] = drep;
957 }
958 if (!o_used) {
959 if (osize != ((segsize == 16) ? 16 : 32)) {
960 enum prefixes pfx = 0;
961
962 switch (osize) {
963 case 16:
964 pfx = P_O16;
965 break;
966 case 32:
967 pfx = P_O32;
968 break;
969 case 64:
970 pfx = P_O64;
971 break;
972 }
973
974 if (ins->prefixes[PPS_OSIZE])
975 return false;
976 ins->prefixes[PPS_OSIZE] = pfx;
977 }
978 }
979 if (!a_used && asize != segsize) {
980 if (ins->prefixes[PPS_ASIZE])
981 return false;
982 ins->prefixes[PPS_ASIZE] = asize == 16 ? P_A16 : P_A32;
983 }
984
985 /* Fix: check for redundant REX prefixes */
986
987 return data - origdata;
988 }
989
990 /* Condition names for disassembly, sorted by x86 code */
991 static const char * const condition_name[16] = {
992 "o", "no", "c", "nc", "z", "nz", "na", "a",
993 "s", "ns", "pe", "po", "l", "nl", "ng", "g"
994 };
995
996 int32_t disasm(uint8_t *data, char *output, int outbufsize, int segsize,
997 int32_t offset, int autosync, uint32_t prefer)
998 {
999 const struct itemplate * const *p, * const *best_p;
1000 const struct disasm_index *ix;
1001 uint8_t *dp;
1002 int length, best_length = 0;
1003 char *segover;
1004 int i, slen, colon, n;
1005 uint8_t *origdata;
1006 int works;
1007 insn tmp_ins, ins;
1008 uint32_t goodness, best;
1009 int best_pref;
1010 struct prefix_info prefix;
1011 bool end_prefix;
1012
1013 memset(&ins, 0, sizeof ins);
1014
1015 /*
1016 * Scan for prefixes.
1017 */
1018 memset(&prefix, 0, sizeof prefix);
1019 prefix.asize = segsize;
1020 prefix.osize = (segsize == 64) ? 32 : segsize;
1021 segover = NULL;
1022 origdata = data;
1023
1024 ix = itable;
1025
1026 end_prefix = false;
1027 while (!end_prefix) {
1028 switch (*data) {
1029 case 0xF2:
1030 case 0xF3:
1031 prefix.rep = *data++;
1032 break;
1033
1034 case 0xF0:
1035 prefix.lock = *data++;
1036 break;
1037
1038 case 0x2E:
1039 segover = "cs", prefix.seg = *data++;
1040 break;
1041 case 0x36:
1042 segover = "ss", prefix.seg = *data++;
1043 break;
1044 case 0x3E:
1045 segover = "ds", prefix.seg = *data++;
1046 break;
1047 case 0x26:
1048 segover = "es", prefix.seg = *data++;
1049 break;
1050 case 0x64:
1051 segover = "fs", prefix.seg = *data++;
1052 break;
1053 case 0x65:
1054 segover = "gs", prefix.seg = *data++;
1055 break;
1056
1057 case 0x66:
1058 prefix.osize = (segsize == 16) ? 32 : 16;
1059 prefix.osp = *data++;
1060 break;
1061 case 0x67:
1062 prefix.asize = (segsize == 32) ? 16 : 32;
1063 prefix.asp = *data++;
1064 break;
1065
1066 case 0xC4:
1067 case 0xC5:
1068 if (segsize == 64 || (data[1] & 0xc0) == 0xc0) {
1069 prefix.vex[0] = *data++;
1070 prefix.vex[1] = *data++;
1071 if (prefix.vex[0] == 0xc4)
1072 prefix.vex[2] = *data++;
1073 }
1074 prefix.rex = REX_V;
1075 if (prefix.vex[0] == 0xc4) {
1076 prefix.rex |= (~prefix.vex[1] >> 5) & 7; /* REX_RXB */
1077 prefix.rex |= (prefix.vex[2] >> (7-3)) & REX_W;
1078 prefix.vex_m = prefix.vex[1] & 0x1f;
1079 prefix.vex_v = (~prefix.vex[2] >> 3) & 15;
1080 prefix.vex_lp = prefix.vex[2] & 7;
1081 } else {
1082 prefix.rex |= (~prefix.vex[1] >> (7-2)) & REX_R;
1083 prefix.vex_m = 1;
1084 prefix.vex_v = (~prefix.vex[1] >> 3) & 15;
1085 prefix.vex_lp = prefix.vex[1] & 7;
1086 }
1087
1088 ix = itable_VEX[prefix.vex_m][prefix.vex_lp];
1089 end_prefix = true;
1090 break;
1091
1092 case REX_P + 0x0:
1093 case REX_P + 0x1:
1094 case REX_P + 0x2:
1095 case REX_P + 0x3:
1096 case REX_P + 0x4:
1097 case REX_P + 0x5:
1098 case REX_P + 0x6:
1099 case REX_P + 0x7:
1100 case REX_P + 0x8:
1101 case REX_P + 0x9:
1102 case REX_P + 0xA:
1103 case REX_P + 0xB:
1104 case REX_P + 0xC:
1105 case REX_P + 0xD:
1106 case REX_P + 0xE:
1107 case REX_P + 0xF:
1108 if (segsize == 64) {
1109 prefix.rex = *data++;
1110 if (prefix.rex & REX_W)
1111 prefix.osize = 64;
1112 }
1113 end_prefix = true;
1114 break;
1115
1116 default:
1117 end_prefix = true;
1118 break;
1119 }
1120 }
1121
1122 best = -1; /* Worst possible */
1123 best_p = NULL;
1124 best_pref = INT_MAX;
1125
1126 if (!ix)
1127 return 0; /* No instruction table at all... */
1128
1129 dp = data;
1130 ix += *dp++;
1131 while (ix->n == -1) {
1132 ix = (const struct disasm_index *)ix->p + *dp++;
1133 }
1134
1135 p = (const struct itemplate * const *)ix->p;
1136 for (n = ix->n; n; n--, p++) {
1137 if ((length = matches(*p, data, &prefix, segsize, &tmp_ins))) {
1138 works = true;
1139 /*
1140 * Final check to make sure the types of r/m match up.
1141 * XXX: Need to make sure this is actually correct.
1142 */
1143 for (i = 0; i < (*p)->operands; i++) {
1144 if (!((*p)->opd[i] & SAME_AS) &&
1145 (
1146 /* If it's a mem-only EA but we have a
1147 register, die. */
1148 ((tmp_ins.oprs[i].segment & SEG_RMREG) &&
1149 !(MEMORY & ~(*p)->opd[i])) ||
1150 /* If it's a reg-only EA but we have a memory
1151 ref, die. */
1152 (!(tmp_ins.oprs[i].segment & SEG_RMREG) &&
1153 !(REG_EA & ~(*p)->opd[i]) &&
1154 !((*p)->opd[i] & REG_SMASK)) ||
1155 /* Register type mismatch (eg FS vs REG_DESS):
1156 die. */
1157 ((((*p)->opd[i] & (REGISTER | FPUREG)) ||
1158 (tmp_ins.oprs[i].segment & SEG_RMREG)) &&
1159 !whichreg((*p)->opd[i],
1160 tmp_ins.oprs[i].basereg, tmp_ins.rex))
1161 )) {
1162 works = false;
1163 break;
1164 }
1165 }
1166
1167 /*
1168 * Note: we always prefer instructions which incorporate
1169 * prefixes in the instructions themselves. This is to allow
1170 * e.g. PAUSE to be preferred to REP NOP, and deal with
1171 * MMX/SSE instructions where prefixes are used to select
1172 * between MMX and SSE register sets or outright opcode
1173 * selection.
1174 */
1175 if (works) {
1176 int i, nprefix;
1177 goodness = ((*p)->flags & IF_PFMASK) ^ prefer;
1178 nprefix = 0;
1179 for (i = 0; i < MAXPREFIX; i++)
1180 if (tmp_ins.prefixes[i])
1181 nprefix++;
1182 if (nprefix < best_pref ||
1183 (nprefix == best_pref && goodness < best)) {
1184 /* This is the best one found so far */
1185 best = goodness;
1186 best_p = p;
1187 best_pref = nprefix;
1188 best_length = length;
1189 ins = tmp_ins;
1190 }
1191 }
1192 }
1193 }
1194
1195 if (!best_p)
1196 return 0; /* no instruction was matched */
1197
1198 /* Pick the best match */
1199 p = best_p;
1200 length = best_length;
1201
1202 slen = 0;
1203
1204 /* TODO: snprintf returns the value that the string would have if
1205 * the buffer were long enough, and not the actual length of
1206 * the returned string, so each instance of using the return
1207 * value of snprintf should actually be checked to assure that
1208 * the return value is "sane." Maybe a macro wrapper could
1209 * be used for that purpose.
1210 */
1211 for (i = 0; i < MAXPREFIX; i++)
1212 switch (ins.prefixes[i]) {
1213 case P_LOCK:
1214 slen += snprintf(output + slen, outbufsize - slen, "lock ");
1215 break;
1216 case P_REP:
1217 slen += snprintf(output + slen, outbufsize - slen, "rep ");
1218 break;
1219 case P_REPE:
1220 slen += snprintf(output + slen, outbufsize - slen, "repe ");
1221 break;
1222 case P_REPNE:
1223 slen += snprintf(output + slen, outbufsize - slen, "repne ");
1224 break;
1225 case P_A16:
1226 slen += snprintf(output + slen, outbufsize - slen, "a16 ");
1227 break;
1228 case P_A32:
1229 slen += snprintf(output + slen, outbufsize - slen, "a32 ");
1230 break;
1231 case P_A64:
1232 slen += snprintf(output + slen, outbufsize - slen, "a64 ");
1233 break;
1234 case P_O16:
1235 slen += snprintf(output + slen, outbufsize - slen, "o16 ");
1236 break;
1237 case P_O32:
1238 slen += snprintf(output + slen, outbufsize - slen, "o32 ");
1239 break;
1240 case P_O64:
1241 slen += snprintf(output + slen, outbufsize - slen, "o64 ");
1242 break;
1243 default:
1244 break;
1245 }
1246
1247 i = (*p)->opcode;
1248 if (i >= FIRST_COND_OPCODE) {
1249 slen += snprintf(output + slen, outbufsize - slen, "%s%s",
1250 nasm_cond_insn_names[i-FIRST_COND_OPCODE],
1251 condition_name[ins.condition]);
1252 } else {
1253 slen += snprintf(output + slen, outbufsize - slen, "%s",
1254 nasm_insn_names[i]);
1255 }
1256 colon = false;
1257 length += data - origdata; /* fix up for prefixes */
1258 for (i = 0; i < (*p)->operands; i++) {
1259 opflags_t t = (*p)->opd[i];
1260 const operand *o = &ins.oprs[i];
1261 int64_t offs;
1262
1263 if (t & SAME_AS) {
1264 o = &ins.oprs[t & ~SAME_AS];
1265 t = (*p)->opd[t & ~SAME_AS];
1266 }
1267
1268 output[slen++] = (colon ? ':' : i == 0 ? ' ' : ',');
1269
1270 offs = o->offset;
1271 if (o->segment & SEG_RELATIVE) {
1272 offs += offset + length;
1273 /*
1274 * sort out wraparound
1275 */
1276 if (!(o->segment & (SEG_32BIT|SEG_64BIT)))
1277 offs &= 0xffff;
1278 else if (segsize != 64)
1279 offs &= 0xffffffff;
1280
1281 /*
1282 * add sync marker, if autosync is on
1283 */
1284 if (autosync)
1285 add_sync(offs, 0L);
1286 }
1287
1288 if (t & COLON)
1289 colon = true;
1290 else
1291 colon = false;
1292
1293 if ((t & (REGISTER | FPUREG)) ||
1294 (o->segment & SEG_RMREG)) {
1295 enum reg_enum reg;
1296 reg = whichreg(t, o->basereg, ins.rex);
1297 if (t & TO)
1298 slen += snprintf(output + slen, outbufsize - slen, "to ");
1299 slen += snprintf(output + slen, outbufsize - slen, "%s",
1300 nasm_reg_names[reg-EXPR_REG_START]);
1301 } else if (!(UNITY & ~t)) {
1302 output[slen++] = '1';
1303 } else if (t & IMMEDIATE) {
1304 if (t & BITS8) {
1305 slen +=
1306 snprintf(output + slen, outbufsize - slen, "byte ");
1307 if (o->segment & SEG_SIGNED) {
1308 if (offs < 0) {
1309 offs *= -1;
1310 output[slen++] = '-';
1311 } else
1312 output[slen++] = '+';
1313 }
1314 } else if (t & BITS16) {
1315 slen +=
1316 snprintf(output + slen, outbufsize - slen, "word ");
1317 } else if (t & BITS32) {
1318 slen +=
1319 snprintf(output + slen, outbufsize - slen, "dword ");
1320 } else if (t & BITS64) {
1321 slen +=
1322 snprintf(output + slen, outbufsize - slen, "qword ");
1323 } else if (t & NEAR) {
1324 slen +=
1325 snprintf(output + slen, outbufsize - slen, "near ");
1326 } else if (t & SHORT) {
1327 slen +=
1328 snprintf(output + slen, outbufsize - slen, "short ");
1329 }
1330 slen +=
1331 snprintf(output + slen, outbufsize - slen, "0x%"PRIx64"",
1332 offs);
1333 } else if (!(MEM_OFFS & ~t)) {
1334 slen +=
1335 snprintf(output + slen, outbufsize - slen,
1336 "[%s%s%s0x%"PRIx64"]",
1337 (segover ? segover : ""),
1338 (segover ? ":" : ""),
1339 (o->disp_size == 64 ? "qword " :
1340 o->disp_size == 32 ? "dword " :
1341 o->disp_size == 16 ? "word " : ""), offs);
1342 segover = NULL;
1343 } else if (!(REGMEM & ~t)) {
1344 int started = false;
1345 if (t & BITS8)
1346 slen +=
1347 snprintf(output + slen, outbufsize - slen, "byte ");
1348 if (t & BITS16)
1349 slen +=
1350 snprintf(output + slen, outbufsize - slen, "word ");
1351 if (t & BITS32)
1352 slen +=
1353 snprintf(output + slen, outbufsize - slen, "dword ");
1354 if (t & BITS64)
1355 slen +=
1356 snprintf(output + slen, outbufsize - slen, "qword ");
1357 if (t & BITS80)
1358 slen +=
1359 snprintf(output + slen, outbufsize - slen, "tword ");
1360 if (t & BITS128)
1361 slen +=
1362 snprintf(output + slen, outbufsize - slen, "oword ");
1363 if (t & BITS256)
1364 slen +=
1365 snprintf(output + slen, outbufsize - slen, "yword ");
1366 if (t & FAR)
1367 slen += snprintf(output + slen, outbufsize - slen, "far ");
1368 if (t & NEAR)
1369 slen +=
1370 snprintf(output + slen, outbufsize - slen, "near ");
1371 output[slen++] = '[';
1372 if (o->disp_size)
1373 slen += snprintf(output + slen, outbufsize - slen, "%s",
1374 (o->disp_size == 64 ? "qword " :
1375 o->disp_size == 32 ? "dword " :
1376 o->disp_size == 16 ? "word " :
1377 ""));
1378 if (o->eaflags & EAF_REL)
1379 slen += snprintf(output + slen, outbufsize - slen, "rel ");
1380 if (segover) {
1381 slen +=
1382 snprintf(output + slen, outbufsize - slen, "%s:",
1383 segover);
1384 segover = NULL;
1385 }
1386 if (o->basereg != -1) {
1387 slen += snprintf(output + slen, outbufsize - slen, "%s",
1388 nasm_reg_names[(o->basereg-EXPR_REG_START)]);
1389 started = true;
1390 }
1391 if (o->indexreg != -1) {
1392 if (started)
1393 output[slen++] = '+';
1394 slen += snprintf(output + slen, outbufsize - slen, "%s",
1395 nasm_reg_names[(o->indexreg-EXPR_REG_START)]);
1396 if (o->scale > 1)
1397 slen +=
1398 snprintf(output + slen, outbufsize - slen, "*%d",
1399 o->scale);
1400 started = true;
1401 }
1402
1403
1404 if (o->segment & SEG_DISP8) {
1405 const char *prefix;
1406 uint8_t offset = offs;
1407 if ((int8_t)offset < 0) {
1408 prefix = "-";
1409 offset = -offset;
1410 } else {
1411 prefix = "+";
1412 }
1413 slen +=
1414 snprintf(output + slen, outbufsize - slen, "%s0x%"PRIx8"",
1415 prefix, offset);
1416 } else if (o->segment & SEG_DISP16) {
1417 const char *prefix;
1418 uint16_t offset = offs;
1419 if ((int16_t)offset < 0 && started) {
1420 offset = -offset;
1421 prefix = "-";
1422 } else {
1423 prefix = started ? "+" : "";
1424 }
1425 slen +=
1426 snprintf(output + slen, outbufsize - slen,
1427 "%s0x%"PRIx16"", prefix, offset);
1428 } else if (o->segment & SEG_DISP32) {
1429 if (prefix.asize == 64) {
1430 const char *prefix;
1431 uint64_t offset = (int64_t)(int32_t)offs;
1432 if ((int32_t)offs < 0 && started) {
1433 offset = -offset;
1434 prefix = "-";
1435 } else {
1436 prefix = started ? "+" : "";
1437 }
1438 slen +=
1439 snprintf(output + slen, outbufsize - slen,
1440 "%s0x%"PRIx64"", prefix, offset);
1441 } else {
1442 const char *prefix;
1443 uint32_t offset = offs;
1444 if ((int32_t) offset < 0 && started) {
1445 offset = -offset;
1446 prefix = "-";
1447 } else {
1448 prefix = started ? "+" : "";
1449 }
1450 slen +=
1451 snprintf(output + slen, outbufsize - slen,
1452 "%s0x%"PRIx32"", prefix, offset);
1453 }
1454 }
1455 output[slen++] = ']';
1456 } else {
1457 slen +=
1458 snprintf(output + slen, outbufsize - slen, "<operand%d>",
1459 i);
1460 }
1461 }
1462 output[slen] = '\0';
1463 if (segover) { /* unused segment override */
1464 char *p = output;
1465 int count = slen + 1;
1466 while (count--)
1467 p[count + 3] = p[count];
1468 strncpy(output, segover, 2);
1469 output[2] = ' ';
1470 }
1471 return length;
1472 }
1473
1474 int32_t eatbyte(uint8_t *data, char *output, int outbufsize)
1475 {
1476 snprintf(output, outbufsize, "db 0x%02X", *data);
1477 return 1;
1478 }
The Netwide Assembler